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caab277b | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
4f04d8f0 CM |
2 | /* |
3 | * Copyright (C) 2012 ARM Ltd. | |
4f04d8f0 CM |
4 | */ |
5 | #ifndef __ASM_PGTABLE_H | |
6 | #define __ASM_PGTABLE_H | |
7 | ||
2f4b829c | 8 | #include <asm/bug.h> |
4f04d8f0 CM |
9 | #include <asm/proc-fns.h> |
10 | ||
11 | #include <asm/memory.h> | |
34bfeea4 | 12 | #include <asm/mte.h> |
4f04d8f0 | 13 | #include <asm/pgtable-hwdef.h> |
3eca86e7 | 14 | #include <asm/pgtable-prot.h> |
3403e56b | 15 | #include <asm/tlbflush.h> |
4f04d8f0 CM |
16 | |
17 | /* | |
3e1907d5 | 18 | * VMALLOC range. |
08375198 | 19 | * |
f9040773 | 20 | * VMALLOC_START: beginning of the kernel vmalloc space |
a5315819 | 21 | * VMALLOC_END: extends to the available space below vmemmap, PCI I/O space |
3e1907d5 | 22 | * and fixed mappings |
4f04d8f0 | 23 | */ |
f9040773 | 24 | #define VMALLOC_START (MODULES_END) |
9ad7c6d5 | 25 | #define VMALLOC_END (VMEMMAP_START - SZ_256M) |
4f04d8f0 | 26 | |
7bc1a0f9 AB |
27 | #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) |
28 | ||
4f04d8f0 | 29 | #ifndef __ASSEMBLY__ |
2f4b829c | 30 | |
3bbf7157 | 31 | #include <asm/cmpxchg.h> |
961faac1 | 32 | #include <asm/fixmap.h> |
2f4b829c | 33 | #include <linux/mmdebug.h> |
86c9e812 WD |
34 | #include <linux/mm_types.h> |
35 | #include <linux/sched.h> | |
42b25471 | 36 | #include <linux/page_table_check.h> |
2f4b829c | 37 | |
a7ac1cfa ZY |
38 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
39 | #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE | |
40 | ||
41 | /* Set stride and tlb_level in flush_*_tlb_range */ | |
42 | #define flush_pmd_tlb_range(vma, addr, end) \ | |
43 | __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2) | |
44 | #define flush_pud_tlb_range(vma, addr, end) \ | |
45 | __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) | |
46 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
47 | ||
6a1bdb17 WD |
48 | /* |
49 | * Outside of a few very special situations (e.g. hibernation), we always | |
50 | * use broadcast TLB invalidation instructions, therefore a spurious page | |
51 | * fault on one CPU which has been handled concurrently by another CPU | |
52 | * does not need to perform additional invalidation. | |
53 | */ | |
54 | #define flush_tlb_fix_spurious_fault(vma, address) do { } while (0) | |
55 | ||
4f04d8f0 CM |
56 | /* |
57 | * ZERO_PAGE is a global shared page that is always zero: used | |
58 | * for zero-mapped memory areas etc.. | |
59 | */ | |
5227cfa7 | 60 | extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; |
2077be67 | 61 | #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) |
4f04d8f0 | 62 | |
2cf660eb GS |
63 | #define pte_ERROR(e) \ |
64 | pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e)) | |
7078db46 | 65 | |
75387b92 KM |
66 | /* |
67 | * Macros to convert between a physical address and its placement in a | |
68 | * page table entry, taking care of 52-bit addresses. | |
69 | */ | |
70 | #ifdef CONFIG_ARM64_PA_BITS_52 | |
c7c386fb AB |
71 | static inline phys_addr_t __pte_to_phys(pte_t pte) |
72 | { | |
73 | return (pte_val(pte) & PTE_ADDR_LOW) | | |
74 | ((pte_val(pte) & PTE_ADDR_HIGH) << 36); | |
75 | } | |
76 | static inline pteval_t __phys_to_pte_val(phys_addr_t phys) | |
77 | { | |
78 | return (phys | (phys >> 36)) & PTE_ADDR_MASK; | |
79 | } | |
75387b92 KM |
80 | #else |
81 | #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK) | |
82 | #define __phys_to_pte_val(phys) (phys) | |
83 | #endif | |
4f04d8f0 | 84 | |
75387b92 KM |
85 | #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) |
86 | #define pfn_pte(pfn,prot) \ | |
87 | __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) | |
4f04d8f0 CM |
88 | |
89 | #define pte_none(pte) (!pte_val(pte)) | |
90 | #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) | |
91 | #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) | |
7078db46 | 92 | |
4f04d8f0 CM |
93 | /* |
94 | * The following only work if pte_present(). Undefined behaviour otherwise. | |
95 | */ | |
84fe6826 | 96 | #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) |
84fe6826 SC |
97 | #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) |
98 | #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) | |
99 | #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) | |
42b25471 | 100 | #define pte_user(pte) (!!(pte_val(pte) & PTE_USER)) |
ec663d96 | 101 | #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) |
93ef666a | 102 | #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) |
73b20c84 | 103 | #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) |
34bfeea4 CM |
104 | #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \ |
105 | PTE_ATTRINDX(MT_NORMAL_TAGGED)) | |
4f04d8f0 | 106 | |
d27cfa1f AB |
107 | #define pte_cont_addr_end(addr, end) \ |
108 | ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ | |
109 | (__boundary - 1 < (end) - 1) ? __boundary : (end); \ | |
110 | }) | |
111 | ||
112 | #define pmd_cont_addr_end(addr, end) \ | |
113 | ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ | |
114 | (__boundary - 1 < (end) - 1) ? __boundary : (end); \ | |
115 | }) | |
116 | ||
b847415c | 117 | #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) |
2f4b829c CM |
118 | #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) |
119 | #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) | |
120 | ||
766ffb69 | 121 | #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) |
18107f8a VM |
122 | /* |
123 | * Execute-only user mappings do not have the PTE_USER bit set. All valid | |
124 | * kernel mappings have the PTE_UXN bit set. | |
125 | */ | |
ec663d96 | 126 | #define pte_valid_not_user(pte) \ |
18107f8a | 127 | ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) |
76c714be WD |
128 | /* |
129 | * Could the pte be present in the TLB? We must check mm_tlb_flush_pending | |
130 | * so that we don't erroneously return false for pages that have been | |
131 | * remapped as PROT_NONE but are yet to be flushed from the TLB. | |
07509e10 WD |
132 | * Note that we can't make any assumptions based on the state of the access |
133 | * flag, since ptep_clear_flush_young() elides a DSB when invalidating the | |
134 | * TLB. | |
76c714be WD |
135 | */ |
136 | #define pte_accessible(mm, pte) \ | |
07509e10 | 137 | (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte)) |
4f04d8f0 | 138 | |
6218f96c | 139 | /* |
18107f8a VM |
140 | * p??_access_permitted() is true for valid user mappings (PTE_USER |
141 | * bit set, subject to the write permission check). For execute-only | |
142 | * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits | |
143 | * not set) must return false. PROT_NONE mappings do not have the | |
144 | * PTE_VALID bit set. | |
6218f96c CM |
145 | */ |
146 | #define pte_access_permitted(pte, write) \ | |
18107f8a | 147 | (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte))) |
6218f96c CM |
148 | #define pmd_access_permitted(pmd, write) \ |
149 | (pte_access_permitted(pmd_pte(pmd), (write))) | |
150 | #define pud_access_permitted(pud, write) \ | |
151 | (pte_access_permitted(pud_pte(pud), (write))) | |
152 | ||
b6d4f280 | 153 | static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) |
44b6dfc5 | 154 | { |
b6d4f280 | 155 | pte_val(pte) &= ~pgprot_val(prot); |
44b6dfc5 SC |
156 | return pte; |
157 | } | |
158 | ||
b6d4f280 | 159 | static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) |
44b6dfc5 | 160 | { |
b6d4f280 | 161 | pte_val(pte) |= pgprot_val(prot); |
44b6dfc5 SC |
162 | return pte; |
163 | } | |
164 | ||
b65399f6 AK |
165 | static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) |
166 | { | |
167 | pmd_val(pmd) &= ~pgprot_val(prot); | |
168 | return pmd; | |
169 | } | |
170 | ||
171 | static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) | |
172 | { | |
173 | pmd_val(pmd) |= pgprot_val(prot); | |
174 | return pmd; | |
175 | } | |
176 | ||
b6d4f280 LA |
177 | static inline pte_t pte_mkwrite(pte_t pte) |
178 | { | |
73e86cb0 CM |
179 | pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); |
180 | pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); | |
181 | return pte; | |
b6d4f280 LA |
182 | } |
183 | ||
44b6dfc5 SC |
184 | static inline pte_t pte_mkclean(pte_t pte) |
185 | { | |
8781bcbc SC |
186 | pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); |
187 | pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); | |
188 | ||
189 | return pte; | |
44b6dfc5 SC |
190 | } |
191 | ||
192 | static inline pte_t pte_mkdirty(pte_t pte) | |
193 | { | |
8781bcbc SC |
194 | pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); |
195 | ||
196 | if (pte_write(pte)) | |
197 | pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); | |
198 | ||
199 | return pte; | |
44b6dfc5 SC |
200 | } |
201 | ||
ff1712f9 WD |
202 | static inline pte_t pte_wrprotect(pte_t pte) |
203 | { | |
204 | /* | |
205 | * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY | |
206 | * clear), set the PTE_DIRTY bit. | |
207 | */ | |
208 | if (pte_hw_dirty(pte)) | |
209 | pte = pte_mkdirty(pte); | |
210 | ||
211 | pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); | |
212 | pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); | |
213 | return pte; | |
214 | } | |
215 | ||
44b6dfc5 SC |
216 | static inline pte_t pte_mkold(pte_t pte) |
217 | { | |
b6d4f280 | 218 | return clear_pte_bit(pte, __pgprot(PTE_AF)); |
44b6dfc5 SC |
219 | } |
220 | ||
221 | static inline pte_t pte_mkyoung(pte_t pte) | |
222 | { | |
b6d4f280 | 223 | return set_pte_bit(pte, __pgprot(PTE_AF)); |
44b6dfc5 SC |
224 | } |
225 | ||
226 | static inline pte_t pte_mkspecial(pte_t pte) | |
227 | { | |
b6d4f280 | 228 | return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); |
44b6dfc5 | 229 | } |
4f04d8f0 | 230 | |
93ef666a JL |
231 | static inline pte_t pte_mkcont(pte_t pte) |
232 | { | |
66b3923a DW |
233 | pte = set_pte_bit(pte, __pgprot(PTE_CONT)); |
234 | return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); | |
93ef666a JL |
235 | } |
236 | ||
237 | static inline pte_t pte_mknoncont(pte_t pte) | |
238 | { | |
239 | return clear_pte_bit(pte, __pgprot(PTE_CONT)); | |
240 | } | |
241 | ||
5ebe3a44 JM |
242 | static inline pte_t pte_mkpresent(pte_t pte) |
243 | { | |
244 | return set_pte_bit(pte, __pgprot(PTE_VALID)); | |
245 | } | |
246 | ||
66b3923a DW |
247 | static inline pmd_t pmd_mkcont(pmd_t pmd) |
248 | { | |
249 | return __pmd(pmd_val(pmd) | PMD_SECT_CONT); | |
250 | } | |
251 | ||
73b20c84 RM |
252 | static inline pte_t pte_mkdevmap(pte_t pte) |
253 | { | |
30e23538 | 254 | return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); |
73b20c84 RM |
255 | } |
256 | ||
4f04d8f0 CM |
257 | static inline void set_pte(pte_t *ptep, pte_t pte) |
258 | { | |
20a004e7 | 259 | WRITE_ONCE(*ptep, pte); |
7f0b1bf0 CM |
260 | |
261 | /* | |
262 | * Only if the new pte is valid and kernel, otherwise TLB maintenance | |
263 | * or update_mmu_cache() have the necessary barriers. | |
264 | */ | |
d0b7a302 | 265 | if (pte_valid_not_user(pte)) { |
7f0b1bf0 | 266 | dsb(ishst); |
d0b7a302 WD |
267 | isb(); |
268 | } | |
4f04d8f0 CM |
269 | } |
270 | ||
907e21c1 | 271 | extern void __sync_icache_dcache(pte_t pteval); |
4f04d8f0 | 272 | |
2f4b829c CM |
273 | /* |
274 | * PTE bits configuration in the presence of hardware Dirty Bit Management | |
275 | * (PTE_WRITE == PTE_DBM): | |
276 | * | |
277 | * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) | |
278 | * 0 0 | 1 0 0 | |
279 | * 0 1 | 1 1 0 | |
280 | * 1 0 | 1 0 1 | |
281 | * 1 1 | 0 1 x | |
282 | * | |
283 | * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via | |
284 | * the page fault mechanism. Checking the dirty status of a pte becomes: | |
285 | * | |
b847415c | 286 | * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) |
2f4b829c | 287 | */ |
9b604722 MR |
288 | |
289 | static inline void __check_racy_pte_update(struct mm_struct *mm, pte_t *ptep, | |
290 | pte_t pte) | |
4f04d8f0 | 291 | { |
20a004e7 WD |
292 | pte_t old_pte; |
293 | ||
9b604722 MR |
294 | if (!IS_ENABLED(CONFIG_DEBUG_VM)) |
295 | return; | |
296 | ||
297 | old_pte = READ_ONCE(*ptep); | |
298 | ||
299 | if (!pte_valid(old_pte) || !pte_valid(pte)) | |
300 | return; | |
301 | if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) | |
302 | return; | |
02522463 | 303 | |
2f4b829c | 304 | /* |
9b604722 MR |
305 | * Check for potential race with hardware updates of the pte |
306 | * (ptep_set_access_flags safely changes valid ptes without going | |
307 | * through an invalid entry). | |
2f4b829c | 308 | */ |
9b604722 MR |
309 | VM_WARN_ONCE(!pte_young(pte), |
310 | "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", | |
311 | __func__, pte_val(old_pte), pte_val(pte)); | |
312 | VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), | |
313 | "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", | |
314 | __func__, pte_val(old_pte), pte_val(pte)); | |
315 | } | |
316 | ||
42b25471 KW |
317 | static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, |
318 | pte_t *ptep, pte_t pte) | |
9b604722 MR |
319 | { |
320 | if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) | |
321 | __sync_icache_dcache(pte); | |
322 | ||
69e3b846 SP |
323 | /* |
324 | * If the PTE would provide user space access to the tags associated | |
325 | * with it then ensure that the MTE tags are synchronised. Although | |
326 | * pte_access_permitted() returns false for exec only mappings, they | |
327 | * don't expose tags (instruction fetches don't check tags). | |
328 | */ | |
329 | if (system_supports_mte() && pte_access_permitted(pte, false) && | |
330 | !pte_special(pte)) { | |
331 | pte_t old_pte = READ_ONCE(*ptep); | |
332 | /* | |
333 | * We only need to synchronise if the new PTE has tags enabled | |
334 | * or if swapping in (in which case another mapping may have | |
335 | * set tags in the past even if this PTE isn't tagged). | |
336 | * (!pte_none() && !pte_present()) is an open coded version of | |
337 | * is_swap_pte() | |
338 | */ | |
339 | if (pte_tagged(pte) || (!pte_none(old_pte) && !pte_present(old_pte))) | |
340 | mte_sync_tags(old_pte, pte); | |
341 | } | |
34bfeea4 | 342 | |
9b604722 | 343 | __check_racy_pte_update(mm, ptep, pte); |
2f4b829c | 344 | |
4f04d8f0 CM |
345 | set_pte(ptep, pte); |
346 | } | |
347 | ||
42b25471 KW |
348 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, |
349 | pte_t *ptep, pte_t pte) | |
350 | { | |
351 | page_table_check_pte_set(mm, addr, ptep, pte); | |
352 | return __set_pte_at(mm, addr, ptep, pte); | |
353 | } | |
354 | ||
4f04d8f0 CM |
355 | /* |
356 | * Huge pte definitions. | |
357 | */ | |
084bd298 SC |
358 | #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) |
359 | ||
360 | /* | |
361 | * Hugetlb definitions. | |
362 | */ | |
66b3923a | 363 | #define HUGE_MAX_HSTATE 4 |
084bd298 SC |
364 | #define HPAGE_SHIFT PMD_SHIFT |
365 | #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) | |
366 | #define HPAGE_MASK (~(HPAGE_SIZE - 1)) | |
367 | #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) | |
4f04d8f0 | 368 | |
75387b92 KM |
369 | static inline pte_t pgd_pte(pgd_t pgd) |
370 | { | |
371 | return __pte(pgd_val(pgd)); | |
372 | } | |
373 | ||
e9f63768 MR |
374 | static inline pte_t p4d_pte(p4d_t p4d) |
375 | { | |
376 | return __pte(p4d_val(p4d)); | |
377 | } | |
378 | ||
29e56940 SC |
379 | static inline pte_t pud_pte(pud_t pud) |
380 | { | |
381 | return __pte(pud_val(pud)); | |
382 | } | |
383 | ||
eb3f0624 PA |
384 | static inline pud_t pte_pud(pte_t pte) |
385 | { | |
386 | return __pud(pte_val(pte)); | |
387 | } | |
388 | ||
29e56940 SC |
389 | static inline pmd_t pud_pmd(pud_t pud) |
390 | { | |
391 | return __pmd(pud_val(pud)); | |
392 | } | |
393 | ||
9c7e535f SC |
394 | static inline pte_t pmd_pte(pmd_t pmd) |
395 | { | |
396 | return __pte(pmd_val(pmd)); | |
397 | } | |
af074848 | 398 | |
9c7e535f SC |
399 | static inline pmd_t pte_pmd(pte_t pte) |
400 | { | |
401 | return __pmd(pte_val(pte)); | |
402 | } | |
af074848 | 403 | |
f7f0097a | 404 | static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) |
8ce837ce | 405 | { |
f7f0097a AK |
406 | return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT); |
407 | } | |
408 | ||
409 | static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) | |
8ce837ce | 410 | { |
f7f0097a | 411 | return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); |
8ce837ce AB |
412 | } |
413 | ||
570ef363 DH |
414 | #define __HAVE_ARCH_PTE_SWP_EXCLUSIVE |
415 | static inline pte_t pte_swp_mkexclusive(pte_t pte) | |
416 | { | |
417 | return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); | |
418 | } | |
419 | ||
420 | static inline int pte_swp_exclusive(pte_t pte) | |
421 | { | |
422 | return pte_val(pte) & PTE_SWP_EXCLUSIVE; | |
423 | } | |
424 | ||
425 | static inline pte_t pte_swp_clear_exclusive(pte_t pte) | |
426 | { | |
427 | return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); | |
428 | } | |
429 | ||
56166230 GK |
430 | #ifdef CONFIG_NUMA_BALANCING |
431 | /* | |
ca5999fd | 432 | * See the comment in include/linux/pgtable.h |
56166230 GK |
433 | */ |
434 | static inline int pte_protnone(pte_t pte) | |
435 | { | |
436 | return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE; | |
437 | } | |
438 | ||
439 | static inline int pmd_protnone(pmd_t pmd) | |
440 | { | |
441 | return pte_protnone(pmd_pte(pmd)); | |
442 | } | |
443 | #endif | |
444 | ||
b65399f6 AK |
445 | #define pmd_present_invalid(pmd) (!!(pmd_val(pmd) & PMD_PRESENT_INVALID)) |
446 | ||
447 | static inline int pmd_present(pmd_t pmd) | |
448 | { | |
449 | return pte_present(pmd_pte(pmd)) || pmd_present_invalid(pmd); | |
450 | } | |
451 | ||
af074848 SC |
452 | /* |
453 | * THP definitions. | |
454 | */ | |
af074848 SC |
455 | |
456 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
b65399f6 AK |
457 | static inline int pmd_trans_huge(pmd_t pmd) |
458 | { | |
459 | return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT); | |
460 | } | |
29e56940 | 461 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
af074848 | 462 | |
c164e038 | 463 | #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) |
9c7e535f | 464 | #define pmd_young(pmd) pte_young(pmd_pte(pmd)) |
0795edaf | 465 | #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) |
42b25471 KW |
466 | #define pmd_user(pmd) pte_user(pmd_pte(pmd)) |
467 | #define pmd_user_exec(pmd) pte_user_exec(pmd_pte(pmd)) | |
d55863db | 468 | #define pmd_cont(pmd) pte_cont(pmd_pte(pmd)) |
9c7e535f | 469 | #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) |
9c7e535f SC |
470 | #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) |
471 | #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) | |
ab4db1f2 | 472 | #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) |
9c7e535f SC |
473 | #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) |
474 | #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) | |
b65399f6 AK |
475 | |
476 | static inline pmd_t pmd_mkinvalid(pmd_t pmd) | |
477 | { | |
478 | pmd = set_pmd_bit(pmd, __pgprot(PMD_PRESENT_INVALID)); | |
479 | pmd = clear_pmd_bit(pmd, __pgprot(PMD_SECT_VALID)); | |
480 | ||
481 | return pmd; | |
482 | } | |
af074848 | 483 | |
0dbd3b18 SP |
484 | #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) |
485 | ||
9c7e535f | 486 | #define pmd_write(pmd) pte_write(pmd_pte(pmd)) |
af074848 SC |
487 | |
488 | #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) | |
489 | ||
73b20c84 RM |
490 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
491 | #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) | |
492 | #endif | |
30e23538 JH |
493 | static inline pmd_t pmd_mkdevmap(pmd_t pmd) |
494 | { | |
495 | return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); | |
496 | } | |
73b20c84 | 497 | |
75387b92 KM |
498 | #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) |
499 | #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) | |
500 | #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) | |
501 | #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) | |
af074848 SC |
502 | #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) |
503 | ||
35a63966 | 504 | #define pud_young(pud) pte_young(pud_pte(pud)) |
eb3f0624 | 505 | #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) |
29e56940 | 506 | #define pud_write(pud) pte_write(pud_pte(pud)) |
75387b92 | 507 | |
b8e0ba7c PA |
508 | #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) |
509 | ||
75387b92 KM |
510 | #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) |
511 | #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) | |
512 | #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) | |
513 | #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) | |
af074848 | 514 | |
42b25471 KW |
515 | static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, |
516 | pmd_t *pmdp, pmd_t pmd) | |
517 | { | |
518 | page_table_check_pmd_set(mm, addr, pmdp, pmd); | |
519 | return __set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)); | |
520 | } | |
521 | ||
522 | static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, | |
523 | pud_t *pudp, pud_t pud) | |
524 | { | |
525 | page_table_check_pud_set(mm, addr, pudp, pud); | |
526 | return __set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud)); | |
527 | } | |
af074848 | 528 | |
e9f63768 MR |
529 | #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d)) |
530 | #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys) | |
531 | ||
75387b92 KM |
532 | #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) |
533 | #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) | |
534 | ||
a501e324 CM |
535 | #define __pgprot_modify(prot,mask,bits) \ |
536 | __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) | |
537 | ||
cca98e9f | 538 | #define pgprot_nx(prot) \ |
034aa9cd | 539 | __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN) |
cca98e9f | 540 | |
4f04d8f0 CM |
541 | /* |
542 | * Mark the prot value as uncacheable and unbufferable. | |
543 | */ | |
544 | #define pgprot_noncached(prot) \ | |
de2db743 | 545 | __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) |
4f04d8f0 | 546 | #define pgprot_writecombine(prot) \ |
de2db743 | 547 | __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) |
d1e6dc91 LD |
548 | #define pgprot_device(prot) \ |
549 | __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) | |
d15dfd31 CM |
550 | #define pgprot_tagged(prot) \ |
551 | __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED)) | |
552 | #define pgprot_mhp pgprot_tagged | |
3e4e1d3f CH |
553 | /* |
554 | * DMA allocations for non-coherent devices use what the Arm architecture calls | |
555 | * "Normal non-cacheable" memory, which permits speculation, unaligned accesses | |
556 | * and merging of writes. This is different from "Device-nGnR[nE]" memory which | |
557 | * is intended for MMIO and thus forbids speculation, preserves access size, | |
558 | * requires strict alignment and can also force write responses to come from the | |
559 | * endpoint. | |
560 | */ | |
419e2f18 CH |
561 | #define pgprot_dmacoherent(prot) \ |
562 | __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ | |
563 | PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) | |
564 | ||
4f04d8f0 CM |
565 | #define __HAVE_PHYS_MEM_ACCESS_PROT |
566 | struct file; | |
567 | extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, | |
568 | unsigned long size, pgprot_t vma_prot); | |
569 | ||
570 | #define pmd_none(pmd) (!pmd_val(pmd)) | |
4f04d8f0 | 571 | |
36311607 MZ |
572 | #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ |
573 | PMD_TYPE_TABLE) | |
574 | #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ | |
575 | PMD_TYPE_SECT) | |
23bc8f69 | 576 | #define pmd_leaf(pmd) (pmd_present(pmd) && !pmd_table(pmd)) |
e377ab82 | 577 | #define pmd_bad(pmd) (!pmd_table(pmd)) |
36311607 | 578 | |
d55863db PZ |
579 | #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE) |
580 | #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE) | |
581 | ||
cac4b8cd | 582 | #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 |
7d4e2dcf QC |
583 | static inline bool pud_sect(pud_t pud) { return false; } |
584 | static inline bool pud_table(pud_t pud) { return true; } | |
206a2a73 SC |
585 | #else |
586 | #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ | |
587 | PUD_TYPE_SECT) | |
523d6e9f | 588 | #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ |
589 | PUD_TYPE_TABLE) | |
206a2a73 | 590 | #endif |
36311607 | 591 | |
2330b7ca JY |
592 | extern pgd_t init_pg_dir[PTRS_PER_PGD]; |
593 | extern pgd_t init_pg_end[]; | |
594 | extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; | |
595 | extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; | |
9d2d75ed | 596 | extern pgd_t idmap_pg_end[]; |
2330b7ca | 597 | extern pgd_t tramp_pg_dir[PTRS_PER_PGD]; |
833be850 | 598 | extern pgd_t reserved_pg_dir[PTRS_PER_PGD]; |
2330b7ca JY |
599 | |
600 | extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); | |
601 | ||
602 | static inline bool in_swapper_pgdir(void *addr) | |
603 | { | |
604 | return ((unsigned long)addr & PAGE_MASK) == | |
605 | ((unsigned long)swapper_pg_dir & PAGE_MASK); | |
606 | } | |
607 | ||
4f04d8f0 CM |
608 | static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) |
609 | { | |
e9ed821b JM |
610 | #ifdef __PAGETABLE_PMD_FOLDED |
611 | if (in_swapper_pgdir(pmdp)) { | |
2330b7ca JY |
612 | set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); |
613 | return; | |
614 | } | |
e9ed821b | 615 | #endif /* __PAGETABLE_PMD_FOLDED */ |
2330b7ca | 616 | |
20a004e7 | 617 | WRITE_ONCE(*pmdp, pmd); |
0795edaf | 618 | |
d0b7a302 | 619 | if (pmd_valid(pmd)) { |
0795edaf | 620 | dsb(ishst); |
d0b7a302 WD |
621 | isb(); |
622 | } | |
4f04d8f0 CM |
623 | } |
624 | ||
625 | static inline void pmd_clear(pmd_t *pmdp) | |
626 | { | |
627 | set_pmd(pmdp, __pmd(0)); | |
628 | } | |
629 | ||
dca56dca | 630 | static inline phys_addr_t pmd_page_paddr(pmd_t pmd) |
4f04d8f0 | 631 | { |
75387b92 | 632 | return __pmd_to_phys(pmd); |
4f04d8f0 CM |
633 | } |
634 | ||
974b9b2c MR |
635 | static inline unsigned long pmd_page_vaddr(pmd_t pmd) |
636 | { | |
637 | return (unsigned long)__va(pmd_page_paddr(pmd)); | |
638 | } | |
74dd022f | 639 | |
053520f7 | 640 | /* Find an entry in the third-level page table. */ |
f069faba | 641 | #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) |
053520f7 | 642 | |
961faac1 MR |
643 | #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) |
644 | #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) | |
645 | #define pte_clear_fixmap() clear_fixmap(FIX_PTE) | |
646 | ||
68ecabd0 | 647 | #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd)) |
4f04d8f0 | 648 | |
6533945a AB |
649 | /* use ONLY for statically allocated translation tables */ |
650 | #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) | |
651 | ||
4f04d8f0 CM |
652 | /* |
653 | * Conversion functions: convert a page and protection to a page entry, | |
654 | * and a page entry and page directory to the page they refer to. | |
655 | */ | |
656 | #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) | |
657 | ||
9f25e6ad | 658 | #if CONFIG_PGTABLE_LEVELS > 2 |
4f04d8f0 | 659 | |
2cf660eb GS |
660 | #define pmd_ERROR(e) \ |
661 | pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e)) | |
7078db46 | 662 | |
4f04d8f0 | 663 | #define pud_none(pud) (!pud_val(pud)) |
e377ab82 | 664 | #define pud_bad(pud) (!pud_table(pud)) |
f02ab08a | 665 | #define pud_present(pud) pte_present(pud_pte(pud)) |
23bc8f69 | 666 | #define pud_leaf(pud) (pud_present(pud) && !pud_table(pud)) |
0795edaf | 667 | #define pud_valid(pud) pte_valid(pud_pte(pud)) |
42b25471 KW |
668 | #define pud_user(pud) pte_user(pud_pte(pud)) |
669 | ||
670 | #ifdef CONFIG_PAGE_TABLE_CHECK | |
671 | static inline bool pte_user_accessible_page(pte_t pte) | |
672 | { | |
673 | return pte_present(pte) && (pte_user(pte) || pte_user_exec(pte)); | |
674 | } | |
675 | ||
676 | static inline bool pmd_user_accessible_page(pmd_t pmd) | |
677 | { | |
678 | return pmd_present(pmd) && (pmd_user(pmd) || pmd_user_exec(pmd)); | |
679 | } | |
680 | ||
681 | static inline bool pud_user_accessible_page(pud_t pud) | |
682 | { | |
683 | return pud_present(pud) && pud_user(pud); | |
684 | } | |
685 | #endif | |
4f04d8f0 CM |
686 | |
687 | static inline void set_pud(pud_t *pudp, pud_t pud) | |
688 | { | |
e9ed821b JM |
689 | #ifdef __PAGETABLE_PUD_FOLDED |
690 | if (in_swapper_pgdir(pudp)) { | |
2330b7ca JY |
691 | set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); |
692 | return; | |
693 | } | |
e9ed821b | 694 | #endif /* __PAGETABLE_PUD_FOLDED */ |
2330b7ca | 695 | |
20a004e7 | 696 | WRITE_ONCE(*pudp, pud); |
0795edaf | 697 | |
d0b7a302 | 698 | if (pud_valid(pud)) { |
0795edaf | 699 | dsb(ishst); |
d0b7a302 WD |
700 | isb(); |
701 | } | |
4f04d8f0 CM |
702 | } |
703 | ||
704 | static inline void pud_clear(pud_t *pudp) | |
705 | { | |
706 | set_pud(pudp, __pud(0)); | |
707 | } | |
708 | ||
dca56dca | 709 | static inline phys_addr_t pud_page_paddr(pud_t pud) |
4f04d8f0 | 710 | { |
75387b92 | 711 | return __pud_to_phys(pud); |
4f04d8f0 CM |
712 | } |
713 | ||
9cf6fa24 | 714 | static inline pmd_t *pud_pgtable(pud_t pud) |
974b9b2c | 715 | { |
9cf6fa24 | 716 | return (pmd_t *)__va(pud_page_paddr(pud)); |
974b9b2c | 717 | } |
7078db46 | 718 | |
974b9b2c | 719 | /* Find an entry in the second-level page table. */ |
20a004e7 | 720 | #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) |
7078db46 | 721 | |
961faac1 MR |
722 | #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) |
723 | #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) | |
724 | #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) | |
7078db46 | 725 | |
68ecabd0 | 726 | #define pud_page(pud) phys_to_page(__pud_to_phys(pud)) |
29e56940 | 727 | |
6533945a AB |
728 | /* use ONLY for statically allocated translation tables */ |
729 | #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) | |
730 | ||
dca56dca MR |
731 | #else |
732 | ||
733 | #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) | |
734 | ||
961faac1 MR |
735 | /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ |
736 | #define pmd_set_fixmap(addr) NULL | |
737 | #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) | |
738 | #define pmd_clear_fixmap() | |
739 | ||
6533945a AB |
740 | #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) |
741 | ||
9f25e6ad | 742 | #endif /* CONFIG_PGTABLE_LEVELS > 2 */ |
4f04d8f0 | 743 | |
9f25e6ad | 744 | #if CONFIG_PGTABLE_LEVELS > 3 |
c79b954b | 745 | |
2cf660eb GS |
746 | #define pud_ERROR(e) \ |
747 | pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e)) | |
7078db46 | 748 | |
e9f63768 MR |
749 | #define p4d_none(p4d) (!p4d_val(p4d)) |
750 | #define p4d_bad(p4d) (!(p4d_val(p4d) & 2)) | |
751 | #define p4d_present(p4d) (p4d_val(p4d)) | |
c79b954b | 752 | |
e9f63768 | 753 | static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) |
c79b954b | 754 | { |
e9f63768 MR |
755 | if (in_swapper_pgdir(p4dp)) { |
756 | set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d))); | |
2330b7ca JY |
757 | return; |
758 | } | |
759 | ||
e9f63768 | 760 | WRITE_ONCE(*p4dp, p4d); |
c79b954b | 761 | dsb(ishst); |
eb6a4dcc | 762 | isb(); |
c79b954b JL |
763 | } |
764 | ||
e9f63768 | 765 | static inline void p4d_clear(p4d_t *p4dp) |
c79b954b | 766 | { |
e9f63768 | 767 | set_p4d(p4dp, __p4d(0)); |
c79b954b JL |
768 | } |
769 | ||
e9f63768 | 770 | static inline phys_addr_t p4d_page_paddr(p4d_t p4d) |
c79b954b | 771 | { |
e9f63768 | 772 | return __p4d_to_phys(p4d); |
c79b954b JL |
773 | } |
774 | ||
dc4875f0 | 775 | static inline pud_t *p4d_pgtable(p4d_t p4d) |
974b9b2c | 776 | { |
dc4875f0 | 777 | return (pud_t *)__va(p4d_page_paddr(p4d)); |
974b9b2c | 778 | } |
7078db46 | 779 | |
5845e703 | 780 | /* Find an entry in the first-level page table. */ |
e9f63768 | 781 | #define pud_offset_phys(dir, addr) (p4d_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t)) |
7078db46 | 782 | |
961faac1 | 783 | #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr)) |
e9f63768 | 784 | #define pud_set_fixmap_offset(p4d, addr) pud_set_fixmap(pud_offset_phys(p4d, addr)) |
961faac1 | 785 | #define pud_clear_fixmap() clear_fixmap(FIX_PUD) |
7078db46 | 786 | |
e9f63768 | 787 | #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d))) |
5d96e0cb | 788 | |
6533945a AB |
789 | /* use ONLY for statically allocated translation tables */ |
790 | #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr)))) | |
791 | ||
dca56dca MR |
792 | #else |
793 | ||
e9f63768 | 794 | #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;}) |
dca56dca MR |
795 | #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;}) |
796 | ||
961faac1 MR |
797 | /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ |
798 | #define pud_set_fixmap(addr) NULL | |
799 | #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) | |
800 | #define pud_clear_fixmap() | |
801 | ||
6533945a AB |
802 | #define pud_offset_kimg(dir,addr) ((pud_t *)dir) |
803 | ||
9f25e6ad | 804 | #endif /* CONFIG_PGTABLE_LEVELS > 3 */ |
c79b954b | 805 | |
2cf660eb GS |
806 | #define pgd_ERROR(e) \ |
807 | pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e)) | |
7078db46 | 808 | |
961faac1 MR |
809 | #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) |
810 | #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) | |
811 | ||
4f04d8f0 CM |
812 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) |
813 | { | |
9f341931 CM |
814 | /* |
815 | * Normal and Normal-Tagged are two different memory types and indices | |
816 | * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK. | |
817 | */ | |
a6fadf7e | 818 | const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | |
9f341931 CM |
819 | PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP | |
820 | PTE_ATTRINDX_MASK; | |
2f4b829c CM |
821 | /* preserve the hardware dirty information */ |
822 | if (pte_hw_dirty(pte)) | |
62d96c71 | 823 | pte = pte_mkdirty(pte); |
4f04d8f0 CM |
824 | pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); |
825 | return pte; | |
826 | } | |
827 | ||
9c7e535f SC |
828 | static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) |
829 | { | |
830 | return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); | |
831 | } | |
832 | ||
66dbd6e6 CM |
833 | #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS |
834 | extern int ptep_set_access_flags(struct vm_area_struct *vma, | |
835 | unsigned long address, pte_t *ptep, | |
836 | pte_t entry, int dirty); | |
837 | ||
282aa705 CM |
838 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
839 | #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS | |
840 | static inline int pmdp_set_access_flags(struct vm_area_struct *vma, | |
841 | unsigned long address, pmd_t *pmdp, | |
842 | pmd_t entry, int dirty) | |
843 | { | |
844 | return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); | |
845 | } | |
73b20c84 RM |
846 | |
847 | static inline int pud_devmap(pud_t pud) | |
848 | { | |
849 | return 0; | |
850 | } | |
851 | ||
852 | static inline int pgd_devmap(pgd_t pgd) | |
853 | { | |
854 | return 0; | |
855 | } | |
282aa705 CM |
856 | #endif |
857 | ||
2f4b829c CM |
858 | /* |
859 | * Atomic pte/pmd modifications. | |
860 | */ | |
861 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG | |
06485053 | 862 | static inline int __ptep_test_and_clear_young(pte_t *ptep) |
2f4b829c | 863 | { |
3bbf7157 | 864 | pte_t old_pte, pte; |
2f4b829c | 865 | |
3bbf7157 CM |
866 | pte = READ_ONCE(*ptep); |
867 | do { | |
868 | old_pte = pte; | |
869 | pte = pte_mkold(pte); | |
870 | pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), | |
871 | pte_val(old_pte), pte_val(pte)); | |
872 | } while (pte_val(pte) != pte_val(old_pte)); | |
2f4b829c | 873 | |
3bbf7157 | 874 | return pte_young(pte); |
2f4b829c CM |
875 | } |
876 | ||
06485053 CM |
877 | static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, |
878 | unsigned long address, | |
879 | pte_t *ptep) | |
880 | { | |
881 | return __ptep_test_and_clear_young(ptep); | |
882 | } | |
883 | ||
3403e56b AVB |
884 | #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH |
885 | static inline int ptep_clear_flush_young(struct vm_area_struct *vma, | |
886 | unsigned long address, pte_t *ptep) | |
887 | { | |
888 | int young = ptep_test_and_clear_young(vma, address, ptep); | |
889 | ||
890 | if (young) { | |
891 | /* | |
892 | * We can elide the trailing DSB here since the worst that can | |
893 | * happen is that a CPU continues to use the young entry in its | |
894 | * TLB and we mistakenly reclaim the associated page. The | |
895 | * window for such an event is bounded by the next | |
896 | * context-switch, which provides a DSB to complete the TLB | |
897 | * invalidation. | |
898 | */ | |
899 | flush_tlb_page_nosync(vma, address); | |
900 | } | |
901 | ||
902 | return young; | |
903 | } | |
904 | ||
2f4b829c CM |
905 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
906 | #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG | |
907 | static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, | |
908 | unsigned long address, | |
909 | pmd_t *pmdp) | |
910 | { | |
911 | return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); | |
912 | } | |
913 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
914 | ||
915 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR | |
916 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, | |
917 | unsigned long address, pte_t *ptep) | |
918 | { | |
42b25471 KW |
919 | pte_t pte = __pte(xchg_relaxed(&pte_val(*ptep), 0)); |
920 | ||
921 | page_table_check_pte_clear(mm, address, pte); | |
922 | ||
923 | return pte; | |
2f4b829c CM |
924 | } |
925 | ||
926 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
911f56ee CM |
927 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR |
928 | static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, | |
929 | unsigned long address, pmd_t *pmdp) | |
2f4b829c | 930 | { |
42b25471 KW |
931 | pmd_t pmd = __pmd(xchg_relaxed(&pmd_val(*pmdp), 0)); |
932 | ||
933 | page_table_check_pmd_clear(mm, address, pmd); | |
934 | ||
935 | return pmd; | |
2f4b829c CM |
936 | } |
937 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
938 | ||
939 | /* | |
8781bcbc SC |
940 | * ptep_set_wrprotect - mark read-only while trasferring potential hardware |
941 | * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. | |
2f4b829c CM |
942 | */ |
943 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT | |
944 | static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) | |
945 | { | |
3bbf7157 CM |
946 | pte_t old_pte, pte; |
947 | ||
948 | pte = READ_ONCE(*ptep); | |
949 | do { | |
950 | old_pte = pte; | |
3bbf7157 CM |
951 | pte = pte_wrprotect(pte); |
952 | pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), | |
953 | pte_val(old_pte), pte_val(pte)); | |
954 | } while (pte_val(pte) != pte_val(old_pte)); | |
2f4b829c CM |
955 | } |
956 | ||
957 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
958 | #define __HAVE_ARCH_PMDP_SET_WRPROTECT | |
959 | static inline void pmdp_set_wrprotect(struct mm_struct *mm, | |
960 | unsigned long address, pmd_t *pmdp) | |
961 | { | |
962 | ptep_set_wrprotect(mm, address, (pte_t *)pmdp); | |
963 | } | |
1d78a62c CM |
964 | |
965 | #define pmdp_establish pmdp_establish | |
966 | static inline pmd_t pmdp_establish(struct vm_area_struct *vma, | |
967 | unsigned long address, pmd_t *pmdp, pmd_t pmd) | |
968 | { | |
42b25471 | 969 | page_table_check_pmd_set(vma->vm_mm, address, pmdp, pmd); |
1d78a62c CM |
970 | return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); |
971 | } | |
2f4b829c | 972 | #endif |
2f4b829c | 973 | |
4f04d8f0 CM |
974 | /* |
975 | * Encode and decode a swap entry: | |
3676f9ef | 976 | * bits 0-1: present (must be zero) |
570ef363 DH |
977 | * bits 2: remember PG_anon_exclusive |
978 | * bits 3-7: swap type | |
9b3e661e | 979 | * bits 8-57: swap offset |
fdc69e7d | 980 | * bit 58: PTE_PROT_NONE (must be zero) |
4f04d8f0 | 981 | */ |
570ef363 DH |
982 | #define __SWP_TYPE_SHIFT 3 |
983 | #define __SWP_TYPE_BITS 5 | |
9b3e661e | 984 | #define __SWP_OFFSET_BITS 50 |
4f04d8f0 CM |
985 | #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) |
986 | #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) | |
3676f9ef | 987 | #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) |
4f04d8f0 CM |
988 | |
989 | #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) | |
3676f9ef | 990 | #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) |
4f04d8f0 CM |
991 | #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) |
992 | ||
993 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | |
994 | #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) | |
995 | ||
53fa117b AK |
996 | #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION |
997 | #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) | |
998 | #define __swp_entry_to_pmd(swp) __pmd((swp).val) | |
999 | #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ | |
1000 | ||
4f04d8f0 CM |
1001 | /* |
1002 | * Ensure that there are not more swap files than can be encoded in the kernel | |
aad9061b | 1003 | * PTEs. |
4f04d8f0 CM |
1004 | */ |
1005 | #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) | |
1006 | ||
4f04d8f0 CM |
1007 | extern int kern_addr_valid(unsigned long addr); |
1008 | ||
36943aba SP |
1009 | #ifdef CONFIG_ARM64_MTE |
1010 | ||
1011 | #define __HAVE_ARCH_PREPARE_TO_SWAP | |
1012 | static inline int arch_prepare_to_swap(struct page *page) | |
1013 | { | |
1014 | if (system_supports_mte()) | |
1015 | return mte_save_tags(page); | |
1016 | return 0; | |
1017 | } | |
1018 | ||
1019 | #define __HAVE_ARCH_SWAP_INVALIDATE | |
1020 | static inline void arch_swap_invalidate_page(int type, pgoff_t offset) | |
1021 | { | |
1022 | if (system_supports_mte()) | |
1023 | mte_invalidate_tags(type, offset); | |
1024 | } | |
1025 | ||
1026 | static inline void arch_swap_invalidate_area(int type) | |
1027 | { | |
1028 | if (system_supports_mte()) | |
1029 | mte_invalidate_tags_area(type); | |
1030 | } | |
1031 | ||
1032 | #define __HAVE_ARCH_SWAP_RESTORE | |
da08e9b7 | 1033 | static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio) |
36943aba | 1034 | { |
da08e9b7 MWO |
1035 | if (system_supports_mte() && mte_restore_tags(entry, &folio->page)) |
1036 | set_bit(PG_mte_tagged, &folio->flags); | |
36943aba SP |
1037 | } |
1038 | ||
1039 | #endif /* CONFIG_ARM64_MTE */ | |
1040 | ||
cba3574f WD |
1041 | /* |
1042 | * On AArch64, the cache coherency is handled via the set_pte_at() function. | |
1043 | */ | |
1044 | static inline void update_mmu_cache(struct vm_area_struct *vma, | |
1045 | unsigned long addr, pte_t *ptep) | |
1046 | { | |
1047 | /* | |
120798d2 WD |
1048 | * We don't do anything here, so there's a very small chance of |
1049 | * us retaking a user fault which we just fixed up. The alternative | |
1050 | * is doing a dsb(ishst), but that penalises the fastpath. | |
cba3574f | 1051 | */ |
cba3574f WD |
1052 | } |
1053 | ||
1054 | #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) | |
1055 | ||
529c4b05 KM |
1056 | #ifdef CONFIG_ARM64_PA_BITS_52 |
1057 | #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) | |
1058 | #else | |
1059 | #define phys_to_ttbr(addr) (addr) | |
1060 | #endif | |
1061 | ||
6af31226 JH |
1062 | /* |
1063 | * On arm64 without hardware Access Flag, copying from user will fail because | |
1064 | * the pte is old and cannot be marked young. So we always end up with zeroed | |
1065 | * page after fork() + CoW for pfn mappings. We don't always have a | |
1066 | * hardware-managed access flag on arm64. | |
1067 | */ | |
1068 | static inline bool arch_faults_on_old_pte(void) | |
1069 | { | |
1070 | WARN_ON(preemptible()); | |
1071 | ||
1072 | return !cpu_has_hw_af(); | |
1073 | } | |
0388f9c7 WD |
1074 | #define arch_faults_on_old_pte arch_faults_on_old_pte |
1075 | ||
1076 | /* | |
1077 | * Experimentally, it's cheap to set the access flag in hardware and we | |
1078 | * benefit from prefaulting mappings as 'old' to start with. | |
1079 | */ | |
1080 | static inline bool arch_wants_old_prefaulted_pte(void) | |
1081 | { | |
1082 | return !arch_faults_on_old_pte(); | |
1083 | } | |
1084 | #define arch_wants_old_prefaulted_pte arch_wants_old_prefaulted_pte | |
6af31226 | 1085 | |
f8b46c4b AK |
1086 | static inline bool pud_sect_supported(void) |
1087 | { | |
1088 | return PAGE_SIZE == SZ_4K; | |
1089 | } | |
1090 | ||
18107f8a | 1091 | |
4f04d8f0 CM |
1092 | #endif /* !__ASSEMBLY__ */ |
1093 | ||
1094 | #endif /* __ASM_PGTABLE_H */ |