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4f04d8f0 CM |
1 | /* |
2 | * Copyright (C) 2012 ARM Ltd. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | #ifndef __ASM_PGTABLE_H | |
17 | #define __ASM_PGTABLE_H | |
18 | ||
2f4b829c | 19 | #include <asm/bug.h> |
4f04d8f0 CM |
20 | #include <asm/proc-fns.h> |
21 | ||
22 | #include <asm/memory.h> | |
23 | #include <asm/pgtable-hwdef.h> | |
24 | ||
25 | /* | |
26 | * Software defined PTE bits definition. | |
27 | */ | |
a6fadf7e | 28 | #define PTE_VALID (_AT(pteval_t, 1) << 0) |
bf950040 | 29 | #define PTE_WRITE (PTE_DBM) /* same as DBM (51) */ |
4f04d8f0 CM |
30 | #define PTE_DIRTY (_AT(pteval_t, 1) << 55) |
31 | #define PTE_SPECIAL (_AT(pteval_t, 1) << 56) | |
3676f9ef | 32 | #define PTE_PROT_NONE (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */ |
4f04d8f0 CM |
33 | |
34 | /* | |
35 | * VMALLOC and SPARSEMEM_VMEMMAP ranges. | |
08375198 CM |
36 | * |
37 | * VMEMAP_SIZE: allows the whole VA space to be covered by a struct page array | |
38 | * (rounded up to PUD_SIZE). | |
39 | * VMALLOC_START: beginning of the kernel VA space | |
40 | * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space, | |
41 | * fixed mappings and modules | |
4f04d8f0 | 42 | */ |
08375198 | 43 | #define VMEMMAP_SIZE ALIGN((1UL << (VA_BITS - PAGE_SHIFT)) * sizeof(struct page), PUD_SIZE) |
39d114dd AR |
44 | |
45 | #ifndef CONFIG_KASAN | |
127db024 | 46 | #define VMALLOC_START (VA_START) |
39d114dd AR |
47 | #else |
48 | #include <asm/kasan.h> | |
49 | #define VMALLOC_START (KASAN_SHADOW_END + SZ_64K) | |
50 | #endif | |
51 | ||
08375198 | 52 | #define VMALLOC_END (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K) |
4f04d8f0 CM |
53 | |
54 | #define vmemmap ((struct page *)(VMALLOC_END + SZ_64K)) | |
55 | ||
d016bf7e | 56 | #define FIRST_USER_ADDRESS 0UL |
4f04d8f0 CM |
57 | |
58 | #ifndef __ASSEMBLY__ | |
2f4b829c | 59 | |
961faac1 | 60 | #include <asm/fixmap.h> |
2f4b829c CM |
61 | #include <linux/mmdebug.h> |
62 | ||
4f04d8f0 CM |
63 | extern void __pte_error(const char *file, int line, unsigned long val); |
64 | extern void __pmd_error(const char *file, int line, unsigned long val); | |
c79b954b | 65 | extern void __pud_error(const char *file, int line, unsigned long val); |
4f04d8f0 CM |
66 | extern void __pgd_error(const char *file, int line, unsigned long val); |
67 | ||
a501e324 CM |
68 | #define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED) |
69 | #define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S) | |
4f04d8f0 | 70 | |
ac15bd63 CM |
71 | #define PROT_DEVICE_nGnRnE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE)) |
72 | #define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE)) | |
73 | #define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC)) | |
74 | #define PROT_NORMAL_WT (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT)) | |
75 | #define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL)) | |
4f04d8f0 | 76 | |
a501e324 CM |
77 | #define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE)) |
78 | #define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL)) | |
79 | #define PROT_SECT_NORMAL_EXEC (PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL)) | |
a6fadf7e | 80 | |
a501e324 | 81 | #define _PAGE_DEFAULT (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL)) |
4f04d8f0 | 82 | |
a501e324 | 83 | #define PAGE_KERNEL __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE) |
fb226c3d | 84 | #define PAGE_KERNEL_RO __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_RDONLY) |
ac15bd63 | 85 | #define PAGE_KERNEL_ROX __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_RDONLY) |
a501e324 | 86 | #define PAGE_KERNEL_EXEC __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE) |
06f90d25 | 87 | #define PAGE_KERNEL_EXEC_CONT __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_CONT) |
8e620b04 | 88 | |
a501e324 | 89 | #define PAGE_HYP __pgprot(_PAGE_DEFAULT | PTE_HYP) |
36311607 MZ |
90 | #define PAGE_HYP_DEVICE __pgprot(PROT_DEVICE_nGnRE | PTE_HYP) |
91 | ||
a501e324 | 92 | #define PAGE_S2 __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY) |
4a513fb0 | 93 | #define PAGE_S2_DEVICE __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_UXN) |
36311607 | 94 | |
1a541b4e | 95 | #define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_PXN | PTE_UXN) |
a501e324 CM |
96 | #define PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE) |
97 | #define PAGE_SHARED_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE) | |
98 | #define PAGE_COPY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN) | |
99 | #define PAGE_COPY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN) | |
100 | #define PAGE_READONLY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN) | |
101 | #define PAGE_READONLY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN) | |
a501e324 CM |
102 | |
103 | #define __P000 PAGE_NONE | |
104 | #define __P001 PAGE_READONLY | |
105 | #define __P010 PAGE_COPY | |
106 | #define __P011 PAGE_COPY | |
5a0fdfad | 107 | #define __P100 PAGE_READONLY_EXEC |
a501e324 CM |
108 | #define __P101 PAGE_READONLY_EXEC |
109 | #define __P110 PAGE_COPY_EXEC | |
110 | #define __P111 PAGE_COPY_EXEC | |
111 | ||
112 | #define __S000 PAGE_NONE | |
113 | #define __S001 PAGE_READONLY | |
114 | #define __S010 PAGE_SHARED | |
115 | #define __S011 PAGE_SHARED | |
5a0fdfad | 116 | #define __S100 PAGE_READONLY_EXEC |
a501e324 CM |
117 | #define __S101 PAGE_READONLY_EXEC |
118 | #define __S110 PAGE_SHARED_EXEC | |
119 | #define __S111 PAGE_SHARED_EXEC | |
4f04d8f0 | 120 | |
4f04d8f0 CM |
121 | /* |
122 | * ZERO_PAGE is a global shared page that is always zero: used | |
123 | * for zero-mapped memory areas etc.. | |
124 | */ | |
5227cfa7 MR |
125 | extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; |
126 | #define ZERO_PAGE(vaddr) virt_to_page(empty_zero_page) | |
4f04d8f0 | 127 | |
7078db46 CM |
128 | #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) |
129 | ||
4f04d8f0 CM |
130 | #define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT) |
131 | ||
132 | #define pfn_pte(pfn,prot) (__pte(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))) | |
133 | ||
134 | #define pte_none(pte) (!pte_val(pte)) | |
135 | #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) | |
136 | #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) | |
7078db46 | 137 | |
4f04d8f0 CM |
138 | /* |
139 | * The following only work if pte_present(). Undefined behaviour otherwise. | |
140 | */ | |
84fe6826 | 141 | #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) |
84fe6826 SC |
142 | #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) |
143 | #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) | |
144 | #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) | |
8e620b04 | 145 | #define pte_exec(pte) (!(pte_val(pte) & PTE_UXN)) |
93ef666a | 146 | #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) |
ac15bd63 | 147 | #define pte_user(pte) (!!(pte_val(pte) & PTE_USER)) |
4f04d8f0 | 148 | |
2f4b829c | 149 | #ifdef CONFIG_ARM64_HW_AFDBM |
b847415c | 150 | #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) |
2f4b829c CM |
151 | #else |
152 | #define pte_hw_dirty(pte) (0) | |
153 | #endif | |
154 | #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) | |
155 | #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) | |
156 | ||
766ffb69 | 157 | #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) |
7f0b1bf0 CM |
158 | #define pte_valid_not_user(pte) \ |
159 | ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID) | |
76c714be WD |
160 | #define pte_valid_young(pte) \ |
161 | ((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF)) | |
162 | ||
163 | /* | |
164 | * Could the pte be present in the TLB? We must check mm_tlb_flush_pending | |
165 | * so that we don't erroneously return false for pages that have been | |
166 | * remapped as PROT_NONE but are yet to be flushed from the TLB. | |
167 | */ | |
168 | #define pte_accessible(mm, pte) \ | |
169 | (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte)) | |
4f04d8f0 | 170 | |
b6d4f280 | 171 | static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) |
44b6dfc5 | 172 | { |
b6d4f280 | 173 | pte_val(pte) &= ~pgprot_val(prot); |
44b6dfc5 SC |
174 | return pte; |
175 | } | |
176 | ||
b6d4f280 | 177 | static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) |
44b6dfc5 | 178 | { |
b6d4f280 | 179 | pte_val(pte) |= pgprot_val(prot); |
44b6dfc5 SC |
180 | return pte; |
181 | } | |
182 | ||
b6d4f280 LA |
183 | static inline pte_t pte_wrprotect(pte_t pte) |
184 | { | |
185 | return clear_pte_bit(pte, __pgprot(PTE_WRITE)); | |
186 | } | |
187 | ||
188 | static inline pte_t pte_mkwrite(pte_t pte) | |
189 | { | |
190 | return set_pte_bit(pte, __pgprot(PTE_WRITE)); | |
191 | } | |
192 | ||
44b6dfc5 SC |
193 | static inline pte_t pte_mkclean(pte_t pte) |
194 | { | |
b6d4f280 | 195 | return clear_pte_bit(pte, __pgprot(PTE_DIRTY)); |
44b6dfc5 SC |
196 | } |
197 | ||
198 | static inline pte_t pte_mkdirty(pte_t pte) | |
199 | { | |
b6d4f280 | 200 | return set_pte_bit(pte, __pgprot(PTE_DIRTY)); |
44b6dfc5 SC |
201 | } |
202 | ||
203 | static inline pte_t pte_mkold(pte_t pte) | |
204 | { | |
b6d4f280 | 205 | return clear_pte_bit(pte, __pgprot(PTE_AF)); |
44b6dfc5 SC |
206 | } |
207 | ||
208 | static inline pte_t pte_mkyoung(pte_t pte) | |
209 | { | |
b6d4f280 | 210 | return set_pte_bit(pte, __pgprot(PTE_AF)); |
44b6dfc5 SC |
211 | } |
212 | ||
213 | static inline pte_t pte_mkspecial(pte_t pte) | |
214 | { | |
b6d4f280 | 215 | return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); |
44b6dfc5 | 216 | } |
4f04d8f0 | 217 | |
93ef666a JL |
218 | static inline pte_t pte_mkcont(pte_t pte) |
219 | { | |
66b3923a DW |
220 | pte = set_pte_bit(pte, __pgprot(PTE_CONT)); |
221 | return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); | |
93ef666a JL |
222 | } |
223 | ||
224 | static inline pte_t pte_mknoncont(pte_t pte) | |
225 | { | |
226 | return clear_pte_bit(pte, __pgprot(PTE_CONT)); | |
227 | } | |
228 | ||
66b3923a DW |
229 | static inline pmd_t pmd_mkcont(pmd_t pmd) |
230 | { | |
231 | return __pmd(pmd_val(pmd) | PMD_SECT_CONT); | |
232 | } | |
233 | ||
4f04d8f0 CM |
234 | static inline void set_pte(pte_t *ptep, pte_t pte) |
235 | { | |
236 | *ptep = pte; | |
7f0b1bf0 CM |
237 | |
238 | /* | |
239 | * Only if the new pte is valid and kernel, otherwise TLB maintenance | |
240 | * or update_mmu_cache() have the necessary barriers. | |
241 | */ | |
242 | if (pte_valid_not_user(pte)) { | |
243 | dsb(ishst); | |
244 | isb(); | |
245 | } | |
4f04d8f0 CM |
246 | } |
247 | ||
2f4b829c CM |
248 | struct mm_struct; |
249 | struct vm_area_struct; | |
250 | ||
4f04d8f0 CM |
251 | extern void __sync_icache_dcache(pte_t pteval, unsigned long addr); |
252 | ||
2f4b829c CM |
253 | /* |
254 | * PTE bits configuration in the presence of hardware Dirty Bit Management | |
255 | * (PTE_WRITE == PTE_DBM): | |
256 | * | |
257 | * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) | |
258 | * 0 0 | 1 0 0 | |
259 | * 0 1 | 1 1 0 | |
260 | * 1 0 | 1 0 1 | |
261 | * 1 1 | 0 1 x | |
262 | * | |
263 | * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via | |
264 | * the page fault mechanism. Checking the dirty status of a pte becomes: | |
265 | * | |
b847415c | 266 | * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) |
2f4b829c | 267 | */ |
4f04d8f0 CM |
268 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, |
269 | pte_t *ptep, pte_t pte) | |
270 | { | |
ac15bd63 | 271 | if (pte_valid(pte)) { |
2f4b829c | 272 | if (pte_sw_dirty(pte) && pte_write(pte)) |
c2c93e5b SC |
273 | pte_val(pte) &= ~PTE_RDONLY; |
274 | else | |
275 | pte_val(pte) |= PTE_RDONLY; | |
ac15bd63 CM |
276 | if (pte_user(pte) && pte_exec(pte) && !pte_special(pte)) |
277 | __sync_icache_dcache(pte, addr); | |
02522463 WD |
278 | } |
279 | ||
2f4b829c CM |
280 | /* |
281 | * If the existing pte is valid, check for potential race with | |
282 | * hardware updates of the pte (ptep_set_access_flags safely changes | |
283 | * valid ptes without going through an invalid entry). | |
284 | */ | |
82d34008 CM |
285 | if (IS_ENABLED(CONFIG_ARM64_HW_AFDBM) && |
286 | pte_valid(*ptep) && pte_valid(pte)) { | |
287 | VM_WARN_ONCE(!pte_young(pte), | |
288 | "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", | |
289 | __func__, pte_val(*ptep), pte_val(pte)); | |
290 | VM_WARN_ONCE(pte_write(*ptep) && !pte_dirty(pte), | |
291 | "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", | |
292 | __func__, pte_val(*ptep), pte_val(pte)); | |
2f4b829c CM |
293 | } |
294 | ||
4f04d8f0 CM |
295 | set_pte(ptep, pte); |
296 | } | |
297 | ||
298 | /* | |
299 | * Huge pte definitions. | |
300 | */ | |
084bd298 SC |
301 | #define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT)) |
302 | #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) | |
303 | ||
304 | /* | |
305 | * Hugetlb definitions. | |
306 | */ | |
66b3923a | 307 | #define HUGE_MAX_HSTATE 4 |
084bd298 SC |
308 | #define HPAGE_SHIFT PMD_SHIFT |
309 | #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) | |
310 | #define HPAGE_MASK (~(HPAGE_SIZE - 1)) | |
311 | #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) | |
4f04d8f0 | 312 | |
4f04d8f0 CM |
313 | #define __HAVE_ARCH_PTE_SPECIAL |
314 | ||
29e56940 SC |
315 | static inline pte_t pud_pte(pud_t pud) |
316 | { | |
317 | return __pte(pud_val(pud)); | |
318 | } | |
319 | ||
320 | static inline pmd_t pud_pmd(pud_t pud) | |
321 | { | |
322 | return __pmd(pud_val(pud)); | |
323 | } | |
324 | ||
9c7e535f SC |
325 | static inline pte_t pmd_pte(pmd_t pmd) |
326 | { | |
327 | return __pte(pmd_val(pmd)); | |
328 | } | |
af074848 | 329 | |
9c7e535f SC |
330 | static inline pmd_t pte_pmd(pte_t pte) |
331 | { | |
332 | return __pmd(pte_val(pte)); | |
333 | } | |
af074848 | 334 | |
8ce837ce AB |
335 | static inline pgprot_t mk_sect_prot(pgprot_t prot) |
336 | { | |
337 | return __pgprot(pgprot_val(prot) & ~PTE_TABLE_BIT); | |
338 | } | |
339 | ||
af074848 SC |
340 | /* |
341 | * THP definitions. | |
342 | */ | |
af074848 SC |
343 | |
344 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
345 | #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT)) | |
29e56940 | 346 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
af074848 | 347 | |
c164e038 | 348 | #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) |
9c7e535f SC |
349 | #define pmd_young(pmd) pte_young(pmd_pte(pmd)) |
350 | #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) | |
9c7e535f SC |
351 | #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) |
352 | #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) | |
05ee26d9 | 353 | #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) |
9c7e535f SC |
354 | #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) |
355 | #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) | |
e3a920af | 356 | #define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_TYPE_MASK)) |
af074848 | 357 | |
9c7e535f SC |
358 | #define __HAVE_ARCH_PMD_WRITE |
359 | #define pmd_write(pmd) pte_write(pmd_pte(pmd)) | |
af074848 SC |
360 | |
361 | #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) | |
362 | ||
363 | #define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT) | |
364 | #define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))) | |
365 | #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) | |
366 | ||
29e56940 | 367 | #define pud_write(pud) pte_write(pud_pte(pud)) |
206a2a73 | 368 | #define pud_pfn(pud) (((pud_val(pud) & PUD_MASK) & PHYS_MASK) >> PAGE_SHIFT) |
af074848 | 369 | |
ceb21835 | 370 | #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)) |
af074848 SC |
371 | |
372 | static inline int has_transparent_hugepage(void) | |
373 | { | |
374 | return 1; | |
375 | } | |
376 | ||
a501e324 CM |
377 | #define __pgprot_modify(prot,mask,bits) \ |
378 | __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) | |
379 | ||
4f04d8f0 CM |
380 | /* |
381 | * Mark the prot value as uncacheable and unbufferable. | |
382 | */ | |
383 | #define pgprot_noncached(prot) \ | |
de2db743 | 384 | __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) |
4f04d8f0 | 385 | #define pgprot_writecombine(prot) \ |
de2db743 | 386 | __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) |
d1e6dc91 LD |
387 | #define pgprot_device(prot) \ |
388 | __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) | |
4f04d8f0 CM |
389 | #define __HAVE_PHYS_MEM_ACCESS_PROT |
390 | struct file; | |
391 | extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, | |
392 | unsigned long size, pgprot_t vma_prot); | |
393 | ||
394 | #define pmd_none(pmd) (!pmd_val(pmd)) | |
395 | #define pmd_present(pmd) (pmd_val(pmd)) | |
396 | ||
397 | #define pmd_bad(pmd) (!(pmd_val(pmd) & 2)) | |
398 | ||
36311607 MZ |
399 | #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ |
400 | PMD_TYPE_TABLE) | |
401 | #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ | |
402 | PMD_TYPE_SECT) | |
403 | ||
f3b766a2 | 404 | #ifdef CONFIG_ARM64_64K_PAGES |
206a2a73 | 405 | #define pud_sect(pud) (0) |
523d6e9f | 406 | #define pud_table(pud) (1) |
206a2a73 SC |
407 | #else |
408 | #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ | |
409 | PUD_TYPE_SECT) | |
523d6e9f | 410 | #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ |
411 | PUD_TYPE_TABLE) | |
206a2a73 | 412 | #endif |
36311607 | 413 | |
4f04d8f0 CM |
414 | static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) |
415 | { | |
416 | *pmdp = pmd; | |
98f7685e | 417 | dsb(ishst); |
7f0b1bf0 | 418 | isb(); |
4f04d8f0 CM |
419 | } |
420 | ||
421 | static inline void pmd_clear(pmd_t *pmdp) | |
422 | { | |
423 | set_pmd(pmdp, __pmd(0)); | |
424 | } | |
425 | ||
dca56dca | 426 | static inline phys_addr_t pmd_page_paddr(pmd_t pmd) |
4f04d8f0 | 427 | { |
dca56dca | 428 | return pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK; |
4f04d8f0 CM |
429 | } |
430 | ||
053520f7 MR |
431 | /* Find an entry in the third-level page table. */ |
432 | #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) | |
433 | ||
dca56dca MR |
434 | #define pte_offset_phys(dir,addr) (pmd_page_paddr(*(dir)) + pte_index(addr) * sizeof(pte_t)) |
435 | #define pte_offset_kernel(dir,addr) ((pte_t *)__va(pte_offset_phys((dir), (addr)))) | |
053520f7 MR |
436 | |
437 | #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) | |
438 | #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr)) | |
439 | #define pte_unmap(pte) do { } while (0) | |
440 | #define pte_unmap_nested(pte) do { } while (0) | |
441 | ||
961faac1 MR |
442 | #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) |
443 | #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) | |
444 | #define pte_clear_fixmap() clear_fixmap(FIX_PTE) | |
445 | ||
4f04d8f0 CM |
446 | #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK)) |
447 | ||
448 | /* | |
449 | * Conversion functions: convert a page and protection to a page entry, | |
450 | * and a page entry and page directory to the page they refer to. | |
451 | */ | |
452 | #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) | |
453 | ||
9f25e6ad | 454 | #if CONFIG_PGTABLE_LEVELS > 2 |
4f04d8f0 | 455 | |
7078db46 CM |
456 | #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd)) |
457 | ||
4f04d8f0 CM |
458 | #define pud_none(pud) (!pud_val(pud)) |
459 | #define pud_bad(pud) (!(pud_val(pud) & 2)) | |
460 | #define pud_present(pud) (pud_val(pud)) | |
461 | ||
462 | static inline void set_pud(pud_t *pudp, pud_t pud) | |
463 | { | |
464 | *pudp = pud; | |
98f7685e | 465 | dsb(ishst); |
7f0b1bf0 | 466 | isb(); |
4f04d8f0 CM |
467 | } |
468 | ||
469 | static inline void pud_clear(pud_t *pudp) | |
470 | { | |
471 | set_pud(pudp, __pud(0)); | |
472 | } | |
473 | ||
dca56dca | 474 | static inline phys_addr_t pud_page_paddr(pud_t pud) |
4f04d8f0 | 475 | { |
dca56dca | 476 | return pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK; |
4f04d8f0 CM |
477 | } |
478 | ||
7078db46 CM |
479 | /* Find an entry in the second-level page table. */ |
480 | #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) | |
481 | ||
dca56dca MR |
482 | #define pmd_offset_phys(dir, addr) (pud_page_paddr(*(dir)) + pmd_index(addr) * sizeof(pmd_t)) |
483 | #define pmd_offset(dir, addr) ((pmd_t *)__va(pmd_offset_phys((dir), (addr)))) | |
7078db46 | 484 | |
961faac1 MR |
485 | #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) |
486 | #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) | |
487 | #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) | |
488 | ||
5d96e0cb | 489 | #define pud_page(pud) pfn_to_page(__phys_to_pfn(pud_val(pud) & PHYS_MASK)) |
29e56940 | 490 | |
dca56dca MR |
491 | #else |
492 | ||
493 | #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) | |
494 | ||
961faac1 MR |
495 | /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ |
496 | #define pmd_set_fixmap(addr) NULL | |
497 | #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) | |
498 | #define pmd_clear_fixmap() | |
499 | ||
9f25e6ad | 500 | #endif /* CONFIG_PGTABLE_LEVELS > 2 */ |
4f04d8f0 | 501 | |
9f25e6ad | 502 | #if CONFIG_PGTABLE_LEVELS > 3 |
c79b954b | 503 | |
7078db46 CM |
504 | #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud)) |
505 | ||
c79b954b JL |
506 | #define pgd_none(pgd) (!pgd_val(pgd)) |
507 | #define pgd_bad(pgd) (!(pgd_val(pgd) & 2)) | |
508 | #define pgd_present(pgd) (pgd_val(pgd)) | |
509 | ||
510 | static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) | |
511 | { | |
512 | *pgdp = pgd; | |
513 | dsb(ishst); | |
514 | } | |
515 | ||
516 | static inline void pgd_clear(pgd_t *pgdp) | |
517 | { | |
518 | set_pgd(pgdp, __pgd(0)); | |
519 | } | |
520 | ||
dca56dca | 521 | static inline phys_addr_t pgd_page_paddr(pgd_t pgd) |
c79b954b | 522 | { |
dca56dca | 523 | return pgd_val(pgd) & PHYS_MASK & (s32)PAGE_MASK; |
c79b954b JL |
524 | } |
525 | ||
7078db46 CM |
526 | /* Find an entry in the frst-level page table. */ |
527 | #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) | |
528 | ||
dca56dca MR |
529 | #define pud_offset_phys(dir, addr) (pgd_page_paddr(*(dir)) + pud_index(addr) * sizeof(pud_t)) |
530 | #define pud_offset(dir, addr) ((pud_t *)__va(pud_offset_phys((dir), (addr)))) | |
7078db46 | 531 | |
961faac1 MR |
532 | #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr)) |
533 | #define pud_set_fixmap_offset(pgd, addr) pud_set_fixmap(pud_offset_phys(pgd, addr)) | |
534 | #define pud_clear_fixmap() clear_fixmap(FIX_PUD) | |
535 | ||
5d96e0cb JL |
536 | #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(pgd_val(pgd) & PHYS_MASK)) |
537 | ||
dca56dca MR |
538 | #else |
539 | ||
540 | #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;}) | |
541 | ||
961faac1 MR |
542 | /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ |
543 | #define pud_set_fixmap(addr) NULL | |
544 | #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) | |
545 | #define pud_clear_fixmap() | |
546 | ||
9f25e6ad | 547 | #endif /* CONFIG_PGTABLE_LEVELS > 3 */ |
c79b954b | 548 | |
7078db46 CM |
549 | #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) |
550 | ||
4f04d8f0 CM |
551 | /* to find an entry in a page-table-directory */ |
552 | #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) | |
553 | ||
dca56dca MR |
554 | #define pgd_offset_raw(pgd, addr) ((pgd) + pgd_index(addr)) |
555 | ||
556 | #define pgd_offset(mm, addr) (pgd_offset_raw((mm)->pgd, (addr))) | |
4f04d8f0 CM |
557 | |
558 | /* to find an entry in a kernel page-table-directory */ | |
559 | #define pgd_offset_k(addr) pgd_offset(&init_mm, addr) | |
560 | ||
961faac1 MR |
561 | #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) |
562 | #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) | |
563 | ||
4f04d8f0 CM |
564 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) |
565 | { | |
a6fadf7e | 566 | const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | |
1a541b4e | 567 | PTE_PROT_NONE | PTE_VALID | PTE_WRITE; |
2f4b829c CM |
568 | /* preserve the hardware dirty information */ |
569 | if (pte_hw_dirty(pte)) | |
62d96c71 | 570 | pte = pte_mkdirty(pte); |
4f04d8f0 CM |
571 | pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); |
572 | return pte; | |
573 | } | |
574 | ||
9c7e535f SC |
575 | static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) |
576 | { | |
577 | return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); | |
578 | } | |
579 | ||
2f4b829c CM |
580 | #ifdef CONFIG_ARM64_HW_AFDBM |
581 | /* | |
582 | * Atomic pte/pmd modifications. | |
583 | */ | |
584 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG | |
585 | static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, | |
586 | unsigned long address, | |
587 | pte_t *ptep) | |
588 | { | |
589 | pteval_t pteval; | |
590 | unsigned int tmp, res; | |
591 | ||
592 | asm volatile("// ptep_test_and_clear_young\n" | |
593 | " prfm pstl1strm, %2\n" | |
594 | "1: ldxr %0, %2\n" | |
595 | " ubfx %w3, %w0, %5, #1 // extract PTE_AF (young)\n" | |
596 | " and %0, %0, %4 // clear PTE_AF\n" | |
597 | " stxr %w1, %0, %2\n" | |
598 | " cbnz %w1, 1b\n" | |
599 | : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)), "=&r" (res) | |
600 | : "L" (~PTE_AF), "I" (ilog2(PTE_AF))); | |
601 | ||
602 | return res; | |
603 | } | |
604 | ||
605 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
606 | #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG | |
607 | static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, | |
608 | unsigned long address, | |
609 | pmd_t *pmdp) | |
610 | { | |
611 | return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); | |
612 | } | |
613 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
614 | ||
615 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR | |
616 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, | |
617 | unsigned long address, pte_t *ptep) | |
618 | { | |
619 | pteval_t old_pteval; | |
620 | unsigned int tmp; | |
621 | ||
622 | asm volatile("// ptep_get_and_clear\n" | |
623 | " prfm pstl1strm, %2\n" | |
624 | "1: ldxr %0, %2\n" | |
625 | " stxr %w1, xzr, %2\n" | |
626 | " cbnz %w1, 1b\n" | |
627 | : "=&r" (old_pteval), "=&r" (tmp), "+Q" (pte_val(*ptep))); | |
628 | ||
629 | return __pte(old_pteval); | |
630 | } | |
631 | ||
632 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
633 | #define __HAVE_ARCH_PMDP_GET_AND_CLEAR | |
634 | static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm, | |
635 | unsigned long address, pmd_t *pmdp) | |
636 | { | |
637 | return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); | |
638 | } | |
639 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
640 | ||
641 | /* | |
642 | * ptep_set_wrprotect - mark read-only while trasferring potential hardware | |
643 | * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. | |
644 | */ | |
645 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT | |
646 | static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) | |
647 | { | |
648 | pteval_t pteval; | |
649 | unsigned long tmp; | |
650 | ||
651 | asm volatile("// ptep_set_wrprotect\n" | |
652 | " prfm pstl1strm, %2\n" | |
653 | "1: ldxr %0, %2\n" | |
654 | " tst %0, %4 // check for hw dirty (!PTE_RDONLY)\n" | |
655 | " csel %1, %3, xzr, eq // set PTE_DIRTY|PTE_RDONLY if dirty\n" | |
656 | " orr %0, %0, %1 // if !dirty, PTE_RDONLY is already set\n" | |
657 | " and %0, %0, %5 // clear PTE_WRITE/PTE_DBM\n" | |
658 | " stxr %w1, %0, %2\n" | |
659 | " cbnz %w1, 1b\n" | |
660 | : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)) | |
661 | : "r" (PTE_DIRTY|PTE_RDONLY), "L" (PTE_RDONLY), "L" (~PTE_WRITE) | |
662 | : "cc"); | |
663 | } | |
664 | ||
665 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
666 | #define __HAVE_ARCH_PMDP_SET_WRPROTECT | |
667 | static inline void pmdp_set_wrprotect(struct mm_struct *mm, | |
668 | unsigned long address, pmd_t *pmdp) | |
669 | { | |
670 | ptep_set_wrprotect(mm, address, (pte_t *)pmdp); | |
671 | } | |
672 | #endif | |
673 | #endif /* CONFIG_ARM64_HW_AFDBM */ | |
674 | ||
4f04d8f0 CM |
675 | extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; |
676 | extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; | |
677 | ||
4f04d8f0 CM |
678 | /* |
679 | * Encode and decode a swap entry: | |
3676f9ef | 680 | * bits 0-1: present (must be zero) |
9b3e661e KS |
681 | * bits 2-7: swap type |
682 | * bits 8-57: swap offset | |
4f04d8f0 | 683 | */ |
9b3e661e | 684 | #define __SWP_TYPE_SHIFT 2 |
4f04d8f0 | 685 | #define __SWP_TYPE_BITS 6 |
9b3e661e | 686 | #define __SWP_OFFSET_BITS 50 |
4f04d8f0 CM |
687 | #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) |
688 | #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) | |
3676f9ef | 689 | #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) |
4f04d8f0 CM |
690 | |
691 | #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) | |
3676f9ef | 692 | #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) |
4f04d8f0 CM |
693 | #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) |
694 | ||
695 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | |
696 | #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) | |
697 | ||
698 | /* | |
699 | * Ensure that there are not more swap files than can be encoded in the kernel | |
aad9061b | 700 | * PTEs. |
4f04d8f0 CM |
701 | */ |
702 | #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) | |
703 | ||
4f04d8f0 CM |
704 | extern int kern_addr_valid(unsigned long addr); |
705 | ||
706 | #include <asm-generic/pgtable.h> | |
707 | ||
39b5be9b WD |
708 | void pgd_cache_init(void); |
709 | #define pgtable_cache_init pgd_cache_init | |
4f04d8f0 | 710 | |
cba3574f WD |
711 | /* |
712 | * On AArch64, the cache coherency is handled via the set_pte_at() function. | |
713 | */ | |
714 | static inline void update_mmu_cache(struct vm_area_struct *vma, | |
715 | unsigned long addr, pte_t *ptep) | |
716 | { | |
717 | /* | |
120798d2 WD |
718 | * We don't do anything here, so there's a very small chance of |
719 | * us retaking a user fault which we just fixed up. The alternative | |
720 | * is doing a dsb(ishst), but that penalises the fastpath. | |
cba3574f | 721 | */ |
cba3574f WD |
722 | } |
723 | ||
724 | #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) | |
725 | ||
7db743c6 CM |
726 | #define kc_vaddr_to_offset(v) ((v) & ~VA_START) |
727 | #define kc_offset_to_vaddr(o) ((o) | VA_START) | |
728 | ||
4f04d8f0 CM |
729 | #endif /* !__ASSEMBLY__ */ |
730 | ||
731 | #endif /* __ASM_PGTABLE_H */ |