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4f04d8f0 CM |
1 | /* |
2 | * Copyright (C) 2012 ARM Ltd. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | #ifndef __ASM_PGTABLE_H | |
17 | #define __ASM_PGTABLE_H | |
18 | ||
2f4b829c | 19 | #include <asm/bug.h> |
4f04d8f0 CM |
20 | #include <asm/proc-fns.h> |
21 | ||
22 | #include <asm/memory.h> | |
23 | #include <asm/pgtable-hwdef.h> | |
3eca86e7 | 24 | #include <asm/pgtable-prot.h> |
4f04d8f0 CM |
25 | |
26 | /* | |
3e1907d5 | 27 | * VMALLOC range. |
08375198 | 28 | * |
f9040773 | 29 | * VMALLOC_START: beginning of the kernel vmalloc space |
3e1907d5 AB |
30 | * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space |
31 | * and fixed mappings | |
4f04d8f0 | 32 | */ |
f9040773 | 33 | #define VMALLOC_START (MODULES_END) |
08375198 | 34 | #define VMALLOC_END (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K) |
4f04d8f0 | 35 | |
3bab79ed | 36 | #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) |
4f04d8f0 | 37 | |
d016bf7e | 38 | #define FIRST_USER_ADDRESS 0UL |
4f04d8f0 CM |
39 | |
40 | #ifndef __ASSEMBLY__ | |
2f4b829c | 41 | |
3bbf7157 | 42 | #include <asm/cmpxchg.h> |
961faac1 | 43 | #include <asm/fixmap.h> |
2f4b829c | 44 | #include <linux/mmdebug.h> |
86c9e812 WD |
45 | #include <linux/mm_types.h> |
46 | #include <linux/sched.h> | |
2f4b829c | 47 | |
4f04d8f0 CM |
48 | extern void __pte_error(const char *file, int line, unsigned long val); |
49 | extern void __pmd_error(const char *file, int line, unsigned long val); | |
c79b954b | 50 | extern void __pud_error(const char *file, int line, unsigned long val); |
4f04d8f0 CM |
51 | extern void __pgd_error(const char *file, int line, unsigned long val); |
52 | ||
4f04d8f0 CM |
53 | /* |
54 | * ZERO_PAGE is a global shared page that is always zero: used | |
55 | * for zero-mapped memory areas etc.. | |
56 | */ | |
5227cfa7 | 57 | extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; |
2077be67 | 58 | #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) |
4f04d8f0 | 59 | |
7078db46 CM |
60 | #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) |
61 | ||
75387b92 KM |
62 | /* |
63 | * Macros to convert between a physical address and its placement in a | |
64 | * page table entry, taking care of 52-bit addresses. | |
65 | */ | |
66 | #ifdef CONFIG_ARM64_PA_BITS_52 | |
67 | #define __pte_to_phys(pte) \ | |
68 | ((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36)) | |
69 | #define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK) | |
70 | #else | |
71 | #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK) | |
72 | #define __phys_to_pte_val(phys) (phys) | |
73 | #endif | |
4f04d8f0 | 74 | |
75387b92 KM |
75 | #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) |
76 | #define pfn_pte(pfn,prot) \ | |
77 | __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) | |
4f04d8f0 CM |
78 | |
79 | #define pte_none(pte) (!pte_val(pte)) | |
80 | #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) | |
81 | #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) | |
7078db46 | 82 | |
4f04d8f0 CM |
83 | /* |
84 | * The following only work if pte_present(). Undefined behaviour otherwise. | |
85 | */ | |
84fe6826 | 86 | #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) |
84fe6826 SC |
87 | #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) |
88 | #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) | |
89 | #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) | |
ec663d96 | 90 | #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) |
93ef666a | 91 | #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) |
4f04d8f0 | 92 | |
d27cfa1f AB |
93 | #define pte_cont_addr_end(addr, end) \ |
94 | ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ | |
95 | (__boundary - 1 < (end) - 1) ? __boundary : (end); \ | |
96 | }) | |
97 | ||
98 | #define pmd_cont_addr_end(addr, end) \ | |
99 | ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ | |
100 | (__boundary - 1 < (end) - 1) ? __boundary : (end); \ | |
101 | }) | |
102 | ||
b847415c | 103 | #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) |
2f4b829c CM |
104 | #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) |
105 | #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) | |
106 | ||
766ffb69 | 107 | #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) |
ec663d96 CM |
108 | /* |
109 | * Execute-only user mappings do not have the PTE_USER bit set. All valid | |
110 | * kernel mappings have the PTE_UXN bit set. | |
111 | */ | |
112 | #define pte_valid_not_user(pte) \ | |
113 | ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) | |
76c714be WD |
114 | #define pte_valid_young(pte) \ |
115 | ((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF)) | |
6218f96c CM |
116 | #define pte_valid_user(pte) \ |
117 | ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) | |
76c714be WD |
118 | |
119 | /* | |
120 | * Could the pte be present in the TLB? We must check mm_tlb_flush_pending | |
121 | * so that we don't erroneously return false for pages that have been | |
122 | * remapped as PROT_NONE but are yet to be flushed from the TLB. | |
123 | */ | |
124 | #define pte_accessible(mm, pte) \ | |
125 | (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte)) | |
4f04d8f0 | 126 | |
6218f96c CM |
127 | /* |
128 | * p??_access_permitted() is true for valid user mappings (subject to the | |
129 | * write permission check) other than user execute-only which do not have the | |
130 | * PTE_USER bit set. PROT_NONE mappings do not have the PTE_VALID bit set. | |
131 | */ | |
132 | #define pte_access_permitted(pte, write) \ | |
133 | (pte_valid_user(pte) && (!(write) || pte_write(pte))) | |
134 | #define pmd_access_permitted(pmd, write) \ | |
135 | (pte_access_permitted(pmd_pte(pmd), (write))) | |
136 | #define pud_access_permitted(pud, write) \ | |
137 | (pte_access_permitted(pud_pte(pud), (write))) | |
138 | ||
b6d4f280 | 139 | static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) |
44b6dfc5 | 140 | { |
b6d4f280 | 141 | pte_val(pte) &= ~pgprot_val(prot); |
44b6dfc5 SC |
142 | return pte; |
143 | } | |
144 | ||
b6d4f280 | 145 | static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) |
44b6dfc5 | 146 | { |
b6d4f280 | 147 | pte_val(pte) |= pgprot_val(prot); |
44b6dfc5 SC |
148 | return pte; |
149 | } | |
150 | ||
b6d4f280 LA |
151 | static inline pte_t pte_wrprotect(pte_t pte) |
152 | { | |
73e86cb0 CM |
153 | pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); |
154 | pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); | |
155 | return pte; | |
b6d4f280 LA |
156 | } |
157 | ||
158 | static inline pte_t pte_mkwrite(pte_t pte) | |
159 | { | |
73e86cb0 CM |
160 | pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); |
161 | pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); | |
162 | return pte; | |
b6d4f280 LA |
163 | } |
164 | ||
44b6dfc5 SC |
165 | static inline pte_t pte_mkclean(pte_t pte) |
166 | { | |
8781bcbc SC |
167 | pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); |
168 | pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); | |
169 | ||
170 | return pte; | |
44b6dfc5 SC |
171 | } |
172 | ||
173 | static inline pte_t pte_mkdirty(pte_t pte) | |
174 | { | |
8781bcbc SC |
175 | pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); |
176 | ||
177 | if (pte_write(pte)) | |
178 | pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); | |
179 | ||
180 | return pte; | |
44b6dfc5 SC |
181 | } |
182 | ||
183 | static inline pte_t pte_mkold(pte_t pte) | |
184 | { | |
b6d4f280 | 185 | return clear_pte_bit(pte, __pgprot(PTE_AF)); |
44b6dfc5 SC |
186 | } |
187 | ||
188 | static inline pte_t pte_mkyoung(pte_t pte) | |
189 | { | |
b6d4f280 | 190 | return set_pte_bit(pte, __pgprot(PTE_AF)); |
44b6dfc5 SC |
191 | } |
192 | ||
193 | static inline pte_t pte_mkspecial(pte_t pte) | |
194 | { | |
b6d4f280 | 195 | return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); |
44b6dfc5 | 196 | } |
4f04d8f0 | 197 | |
93ef666a JL |
198 | static inline pte_t pte_mkcont(pte_t pte) |
199 | { | |
66b3923a DW |
200 | pte = set_pte_bit(pte, __pgprot(PTE_CONT)); |
201 | return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); | |
93ef666a JL |
202 | } |
203 | ||
204 | static inline pte_t pte_mknoncont(pte_t pte) | |
205 | { | |
206 | return clear_pte_bit(pte, __pgprot(PTE_CONT)); | |
207 | } | |
208 | ||
5ebe3a44 JM |
209 | static inline pte_t pte_mkpresent(pte_t pte) |
210 | { | |
211 | return set_pte_bit(pte, __pgprot(PTE_VALID)); | |
212 | } | |
213 | ||
66b3923a DW |
214 | static inline pmd_t pmd_mkcont(pmd_t pmd) |
215 | { | |
216 | return __pmd(pmd_val(pmd) | PMD_SECT_CONT); | |
217 | } | |
218 | ||
4f04d8f0 CM |
219 | static inline void set_pte(pte_t *ptep, pte_t pte) |
220 | { | |
20a004e7 | 221 | WRITE_ONCE(*ptep, pte); |
7f0b1bf0 CM |
222 | |
223 | /* | |
224 | * Only if the new pte is valid and kernel, otherwise TLB maintenance | |
225 | * or update_mmu_cache() have the necessary barriers. | |
226 | */ | |
24fe1b0e | 227 | if (pte_valid_not_user(pte)) |
7f0b1bf0 | 228 | dsb(ishst); |
4f04d8f0 CM |
229 | } |
230 | ||
907e21c1 | 231 | extern void __sync_icache_dcache(pte_t pteval); |
4f04d8f0 | 232 | |
2f4b829c CM |
233 | /* |
234 | * PTE bits configuration in the presence of hardware Dirty Bit Management | |
235 | * (PTE_WRITE == PTE_DBM): | |
236 | * | |
237 | * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) | |
238 | * 0 0 | 1 0 0 | |
239 | * 0 1 | 1 1 0 | |
240 | * 1 0 | 1 0 1 | |
241 | * 1 1 | 0 1 x | |
242 | * | |
243 | * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via | |
244 | * the page fault mechanism. Checking the dirty status of a pte becomes: | |
245 | * | |
b847415c | 246 | * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) |
2f4b829c | 247 | */ |
4f04d8f0 CM |
248 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, |
249 | pte_t *ptep, pte_t pte) | |
250 | { | |
20a004e7 WD |
251 | pte_t old_pte; |
252 | ||
73e86cb0 | 253 | if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) |
907e21c1 | 254 | __sync_icache_dcache(pte); |
02522463 | 255 | |
2f4b829c CM |
256 | /* |
257 | * If the existing pte is valid, check for potential race with | |
258 | * hardware updates of the pte (ptep_set_access_flags safely changes | |
259 | * valid ptes without going through an invalid entry). | |
260 | */ | |
20a004e7 WD |
261 | old_pte = READ_ONCE(*ptep); |
262 | if (IS_ENABLED(CONFIG_DEBUG_VM) && pte_valid(old_pte) && pte_valid(pte) && | |
86c9e812 | 263 | (mm == current->active_mm || atomic_read(&mm->mm_users) > 1)) { |
82d34008 CM |
264 | VM_WARN_ONCE(!pte_young(pte), |
265 | "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", | |
20a004e7 WD |
266 | __func__, pte_val(old_pte), pte_val(pte)); |
267 | VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), | |
82d34008 | 268 | "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", |
20a004e7 | 269 | __func__, pte_val(old_pte), pte_val(pte)); |
2f4b829c CM |
270 | } |
271 | ||
4f04d8f0 CM |
272 | set_pte(ptep, pte); |
273 | } | |
274 | ||
747a70e6 SC |
275 | #define __HAVE_ARCH_PTE_SAME |
276 | static inline int pte_same(pte_t pte_a, pte_t pte_b) | |
277 | { | |
278 | pteval_t lhs, rhs; | |
279 | ||
280 | lhs = pte_val(pte_a); | |
281 | rhs = pte_val(pte_b); | |
282 | ||
283 | if (pte_present(pte_a)) | |
284 | lhs &= ~PTE_RDONLY; | |
285 | ||
286 | if (pte_present(pte_b)) | |
287 | rhs &= ~PTE_RDONLY; | |
288 | ||
289 | return (lhs == rhs); | |
290 | } | |
291 | ||
4f04d8f0 CM |
292 | /* |
293 | * Huge pte definitions. | |
294 | */ | |
084bd298 SC |
295 | #define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT)) |
296 | #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) | |
297 | ||
298 | /* | |
299 | * Hugetlb definitions. | |
300 | */ | |
66b3923a | 301 | #define HUGE_MAX_HSTATE 4 |
084bd298 SC |
302 | #define HPAGE_SHIFT PMD_SHIFT |
303 | #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) | |
304 | #define HPAGE_MASK (~(HPAGE_SIZE - 1)) | |
305 | #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) | |
4f04d8f0 | 306 | |
75387b92 KM |
307 | static inline pte_t pgd_pte(pgd_t pgd) |
308 | { | |
309 | return __pte(pgd_val(pgd)); | |
310 | } | |
311 | ||
29e56940 SC |
312 | static inline pte_t pud_pte(pud_t pud) |
313 | { | |
314 | return __pte(pud_val(pud)); | |
315 | } | |
316 | ||
317 | static inline pmd_t pud_pmd(pud_t pud) | |
318 | { | |
319 | return __pmd(pud_val(pud)); | |
320 | } | |
321 | ||
9c7e535f SC |
322 | static inline pte_t pmd_pte(pmd_t pmd) |
323 | { | |
324 | return __pte(pmd_val(pmd)); | |
325 | } | |
af074848 | 326 | |
9c7e535f SC |
327 | static inline pmd_t pte_pmd(pte_t pte) |
328 | { | |
329 | return __pmd(pte_val(pte)); | |
330 | } | |
af074848 | 331 | |
8ce837ce AB |
332 | static inline pgprot_t mk_sect_prot(pgprot_t prot) |
333 | { | |
334 | return __pgprot(pgprot_val(prot) & ~PTE_TABLE_BIT); | |
335 | } | |
336 | ||
56166230 GK |
337 | #ifdef CONFIG_NUMA_BALANCING |
338 | /* | |
339 | * See the comment in include/asm-generic/pgtable.h | |
340 | */ | |
341 | static inline int pte_protnone(pte_t pte) | |
342 | { | |
343 | return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE; | |
344 | } | |
345 | ||
346 | static inline int pmd_protnone(pmd_t pmd) | |
347 | { | |
348 | return pte_protnone(pmd_pte(pmd)); | |
349 | } | |
350 | #endif | |
351 | ||
af074848 SC |
352 | /* |
353 | * THP definitions. | |
354 | */ | |
af074848 SC |
355 | |
356 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
357 | #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT)) | |
29e56940 | 358 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
af074848 | 359 | |
5bb1cc0f | 360 | #define pmd_present(pmd) pte_present(pmd_pte(pmd)) |
c164e038 | 361 | #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) |
9c7e535f | 362 | #define pmd_young(pmd) pte_young(pmd_pte(pmd)) |
0795edaf | 363 | #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) |
9c7e535f | 364 | #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) |
9c7e535f SC |
365 | #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) |
366 | #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) | |
ab4db1f2 | 367 | #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) |
9c7e535f SC |
368 | #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) |
369 | #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) | |
5bb1cc0f | 370 | #define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_SECT_VALID)) |
af074848 | 371 | |
0dbd3b18 SP |
372 | #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) |
373 | ||
9c7e535f | 374 | #define pmd_write(pmd) pte_write(pmd_pte(pmd)) |
af074848 SC |
375 | |
376 | #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) | |
377 | ||
75387b92 KM |
378 | #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) |
379 | #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) | |
380 | #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) | |
381 | #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) | |
af074848 SC |
382 | #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) |
383 | ||
29e56940 | 384 | #define pud_write(pud) pte_write(pud_pte(pud)) |
75387b92 KM |
385 | |
386 | #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) | |
387 | #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) | |
388 | #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) | |
389 | #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) | |
af074848 | 390 | |
ceb21835 | 391 | #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)) |
af074848 | 392 | |
75387b92 KM |
393 | #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) |
394 | #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) | |
395 | ||
a501e324 CM |
396 | #define __pgprot_modify(prot,mask,bits) \ |
397 | __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) | |
398 | ||
4f04d8f0 CM |
399 | /* |
400 | * Mark the prot value as uncacheable and unbufferable. | |
401 | */ | |
402 | #define pgprot_noncached(prot) \ | |
de2db743 | 403 | __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) |
4f04d8f0 | 404 | #define pgprot_writecombine(prot) \ |
de2db743 | 405 | __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) |
d1e6dc91 LD |
406 | #define pgprot_device(prot) \ |
407 | __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) | |
4f04d8f0 CM |
408 | #define __HAVE_PHYS_MEM_ACCESS_PROT |
409 | struct file; | |
410 | extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, | |
411 | unsigned long size, pgprot_t vma_prot); | |
412 | ||
413 | #define pmd_none(pmd) (!pmd_val(pmd)) | |
4f04d8f0 | 414 | |
ab4db1f2 | 415 | #define pmd_bad(pmd) (!(pmd_val(pmd) & PMD_TABLE_BIT)) |
4f04d8f0 | 416 | |
36311607 MZ |
417 | #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ |
418 | PMD_TYPE_TABLE) | |
419 | #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ | |
420 | PMD_TYPE_SECT) | |
421 | ||
cac4b8cd | 422 | #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 |
206a2a73 | 423 | #define pud_sect(pud) (0) |
523d6e9f | 424 | #define pud_table(pud) (1) |
206a2a73 SC |
425 | #else |
426 | #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ | |
427 | PUD_TYPE_SECT) | |
523d6e9f | 428 | #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ |
429 | PUD_TYPE_TABLE) | |
206a2a73 | 430 | #endif |
36311607 | 431 | |
2330b7ca JY |
432 | extern pgd_t init_pg_dir[PTRS_PER_PGD]; |
433 | extern pgd_t init_pg_end[]; | |
434 | extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; | |
435 | extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; | |
436 | extern pgd_t tramp_pg_dir[PTRS_PER_PGD]; | |
437 | ||
438 | extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); | |
439 | ||
440 | static inline bool in_swapper_pgdir(void *addr) | |
441 | { | |
442 | return ((unsigned long)addr & PAGE_MASK) == | |
443 | ((unsigned long)swapper_pg_dir & PAGE_MASK); | |
444 | } | |
445 | ||
4f04d8f0 CM |
446 | static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) |
447 | { | |
e9ed821b JM |
448 | #ifdef __PAGETABLE_PMD_FOLDED |
449 | if (in_swapper_pgdir(pmdp)) { | |
2330b7ca JY |
450 | set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); |
451 | return; | |
452 | } | |
e9ed821b | 453 | #endif /* __PAGETABLE_PMD_FOLDED */ |
2330b7ca | 454 | |
20a004e7 | 455 | WRITE_ONCE(*pmdp, pmd); |
0795edaf WD |
456 | |
457 | if (pmd_valid(pmd)) | |
458 | dsb(ishst); | |
4f04d8f0 CM |
459 | } |
460 | ||
461 | static inline void pmd_clear(pmd_t *pmdp) | |
462 | { | |
463 | set_pmd(pmdp, __pmd(0)); | |
464 | } | |
465 | ||
dca56dca | 466 | static inline phys_addr_t pmd_page_paddr(pmd_t pmd) |
4f04d8f0 | 467 | { |
75387b92 | 468 | return __pmd_to_phys(pmd); |
4f04d8f0 CM |
469 | } |
470 | ||
053520f7 MR |
471 | /* Find an entry in the third-level page table. */ |
472 | #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) | |
473 | ||
f069faba | 474 | #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) |
dca56dca | 475 | #define pte_offset_kernel(dir,addr) ((pte_t *)__va(pte_offset_phys((dir), (addr)))) |
053520f7 MR |
476 | |
477 | #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) | |
478 | #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr)) | |
479 | #define pte_unmap(pte) do { } while (0) | |
480 | #define pte_unmap_nested(pte) do { } while (0) | |
481 | ||
961faac1 MR |
482 | #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) |
483 | #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) | |
484 | #define pte_clear_fixmap() clear_fixmap(FIX_PTE) | |
485 | ||
75387b92 | 486 | #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(__pmd_to_phys(pmd))) |
4f04d8f0 | 487 | |
6533945a AB |
488 | /* use ONLY for statically allocated translation tables */ |
489 | #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) | |
490 | ||
4f04d8f0 CM |
491 | /* |
492 | * Conversion functions: convert a page and protection to a page entry, | |
493 | * and a page entry and page directory to the page they refer to. | |
494 | */ | |
495 | #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) | |
496 | ||
9f25e6ad | 497 | #if CONFIG_PGTABLE_LEVELS > 2 |
4f04d8f0 | 498 | |
7078db46 CM |
499 | #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd)) |
500 | ||
4f04d8f0 | 501 | #define pud_none(pud) (!pud_val(pud)) |
ab4db1f2 | 502 | #define pud_bad(pud) (!(pud_val(pud) & PUD_TABLE_BIT)) |
f02ab08a | 503 | #define pud_present(pud) pte_present(pud_pte(pud)) |
0795edaf | 504 | #define pud_valid(pud) pte_valid(pud_pte(pud)) |
4f04d8f0 CM |
505 | |
506 | static inline void set_pud(pud_t *pudp, pud_t pud) | |
507 | { | |
e9ed821b JM |
508 | #ifdef __PAGETABLE_PUD_FOLDED |
509 | if (in_swapper_pgdir(pudp)) { | |
2330b7ca JY |
510 | set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); |
511 | return; | |
512 | } | |
e9ed821b | 513 | #endif /* __PAGETABLE_PUD_FOLDED */ |
2330b7ca | 514 | |
20a004e7 | 515 | WRITE_ONCE(*pudp, pud); |
0795edaf WD |
516 | |
517 | if (pud_valid(pud)) | |
518 | dsb(ishst); | |
4f04d8f0 CM |
519 | } |
520 | ||
521 | static inline void pud_clear(pud_t *pudp) | |
522 | { | |
523 | set_pud(pudp, __pud(0)); | |
524 | } | |
525 | ||
dca56dca | 526 | static inline phys_addr_t pud_page_paddr(pud_t pud) |
4f04d8f0 | 527 | { |
75387b92 | 528 | return __pud_to_phys(pud); |
4f04d8f0 CM |
529 | } |
530 | ||
7078db46 CM |
531 | /* Find an entry in the second-level page table. */ |
532 | #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) | |
533 | ||
20a004e7 | 534 | #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) |
dca56dca | 535 | #define pmd_offset(dir, addr) ((pmd_t *)__va(pmd_offset_phys((dir), (addr)))) |
7078db46 | 536 | |
961faac1 MR |
537 | #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) |
538 | #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) | |
539 | #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) | |
7078db46 | 540 | |
75387b92 | 541 | #define pud_page(pud) pfn_to_page(__phys_to_pfn(__pud_to_phys(pud))) |
29e56940 | 542 | |
6533945a AB |
543 | /* use ONLY for statically allocated translation tables */ |
544 | #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) | |
545 | ||
dca56dca MR |
546 | #else |
547 | ||
548 | #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) | |
549 | ||
961faac1 MR |
550 | /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ |
551 | #define pmd_set_fixmap(addr) NULL | |
552 | #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) | |
553 | #define pmd_clear_fixmap() | |
554 | ||
6533945a AB |
555 | #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) |
556 | ||
9f25e6ad | 557 | #endif /* CONFIG_PGTABLE_LEVELS > 2 */ |
4f04d8f0 | 558 | |
9f25e6ad | 559 | #if CONFIG_PGTABLE_LEVELS > 3 |
c79b954b | 560 | |
7078db46 CM |
561 | #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud)) |
562 | ||
c79b954b JL |
563 | #define pgd_none(pgd) (!pgd_val(pgd)) |
564 | #define pgd_bad(pgd) (!(pgd_val(pgd) & 2)) | |
565 | #define pgd_present(pgd) (pgd_val(pgd)) | |
566 | ||
567 | static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) | |
568 | { | |
2330b7ca JY |
569 | if (in_swapper_pgdir(pgdp)) { |
570 | set_swapper_pgd(pgdp, pgd); | |
571 | return; | |
572 | } | |
573 | ||
20a004e7 | 574 | WRITE_ONCE(*pgdp, pgd); |
c79b954b JL |
575 | dsb(ishst); |
576 | } | |
577 | ||
578 | static inline void pgd_clear(pgd_t *pgdp) | |
579 | { | |
580 | set_pgd(pgdp, __pgd(0)); | |
581 | } | |
582 | ||
dca56dca | 583 | static inline phys_addr_t pgd_page_paddr(pgd_t pgd) |
c79b954b | 584 | { |
75387b92 | 585 | return __pgd_to_phys(pgd); |
c79b954b JL |
586 | } |
587 | ||
7078db46 CM |
588 | /* Find an entry in the frst-level page table. */ |
589 | #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) | |
590 | ||
20a004e7 | 591 | #define pud_offset_phys(dir, addr) (pgd_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t)) |
dca56dca | 592 | #define pud_offset(dir, addr) ((pud_t *)__va(pud_offset_phys((dir), (addr)))) |
7078db46 | 593 | |
961faac1 MR |
594 | #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr)) |
595 | #define pud_set_fixmap_offset(pgd, addr) pud_set_fixmap(pud_offset_phys(pgd, addr)) | |
596 | #define pud_clear_fixmap() clear_fixmap(FIX_PUD) | |
7078db46 | 597 | |
75387b92 | 598 | #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(__pgd_to_phys(pgd))) |
5d96e0cb | 599 | |
6533945a AB |
600 | /* use ONLY for statically allocated translation tables */ |
601 | #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr)))) | |
602 | ||
dca56dca MR |
603 | #else |
604 | ||
605 | #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;}) | |
606 | ||
961faac1 MR |
607 | /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ |
608 | #define pud_set_fixmap(addr) NULL | |
609 | #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) | |
610 | #define pud_clear_fixmap() | |
611 | ||
6533945a AB |
612 | #define pud_offset_kimg(dir,addr) ((pud_t *)dir) |
613 | ||
9f25e6ad | 614 | #endif /* CONFIG_PGTABLE_LEVELS > 3 */ |
c79b954b | 615 | |
7078db46 CM |
616 | #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) |
617 | ||
4f04d8f0 CM |
618 | /* to find an entry in a page-table-directory */ |
619 | #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) | |
620 | ||
dca56dca MR |
621 | #define pgd_offset_raw(pgd, addr) ((pgd) + pgd_index(addr)) |
622 | ||
623 | #define pgd_offset(mm, addr) (pgd_offset_raw((mm)->pgd, (addr))) | |
4f04d8f0 CM |
624 | |
625 | /* to find an entry in a kernel page-table-directory */ | |
626 | #define pgd_offset_k(addr) pgd_offset(&init_mm, addr) | |
627 | ||
961faac1 MR |
628 | #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) |
629 | #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) | |
630 | ||
4f04d8f0 CM |
631 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) |
632 | { | |
a6fadf7e | 633 | const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | |
1a541b4e | 634 | PTE_PROT_NONE | PTE_VALID | PTE_WRITE; |
2f4b829c CM |
635 | /* preserve the hardware dirty information */ |
636 | if (pte_hw_dirty(pte)) | |
62d96c71 | 637 | pte = pte_mkdirty(pte); |
4f04d8f0 CM |
638 | pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); |
639 | return pte; | |
640 | } | |
641 | ||
9c7e535f SC |
642 | static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) |
643 | { | |
644 | return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); | |
645 | } | |
646 | ||
66dbd6e6 CM |
647 | #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS |
648 | extern int ptep_set_access_flags(struct vm_area_struct *vma, | |
649 | unsigned long address, pte_t *ptep, | |
650 | pte_t entry, int dirty); | |
651 | ||
282aa705 CM |
652 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
653 | #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS | |
654 | static inline int pmdp_set_access_flags(struct vm_area_struct *vma, | |
655 | unsigned long address, pmd_t *pmdp, | |
656 | pmd_t entry, int dirty) | |
657 | { | |
658 | return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); | |
659 | } | |
660 | #endif | |
661 | ||
2f4b829c CM |
662 | /* |
663 | * Atomic pte/pmd modifications. | |
664 | */ | |
665 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG | |
06485053 | 666 | static inline int __ptep_test_and_clear_young(pte_t *ptep) |
2f4b829c | 667 | { |
3bbf7157 | 668 | pte_t old_pte, pte; |
2f4b829c | 669 | |
3bbf7157 CM |
670 | pte = READ_ONCE(*ptep); |
671 | do { | |
672 | old_pte = pte; | |
673 | pte = pte_mkold(pte); | |
674 | pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), | |
675 | pte_val(old_pte), pte_val(pte)); | |
676 | } while (pte_val(pte) != pte_val(old_pte)); | |
2f4b829c | 677 | |
3bbf7157 | 678 | return pte_young(pte); |
2f4b829c CM |
679 | } |
680 | ||
06485053 CM |
681 | static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, |
682 | unsigned long address, | |
683 | pte_t *ptep) | |
684 | { | |
685 | return __ptep_test_and_clear_young(ptep); | |
686 | } | |
687 | ||
2f4b829c CM |
688 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
689 | #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG | |
690 | static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, | |
691 | unsigned long address, | |
692 | pmd_t *pmdp) | |
693 | { | |
694 | return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); | |
695 | } | |
696 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
697 | ||
698 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR | |
699 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, | |
700 | unsigned long address, pte_t *ptep) | |
701 | { | |
3bbf7157 | 702 | return __pte(xchg_relaxed(&pte_val(*ptep), 0)); |
2f4b829c CM |
703 | } |
704 | ||
705 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
911f56ee CM |
706 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR |
707 | static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, | |
708 | unsigned long address, pmd_t *pmdp) | |
2f4b829c CM |
709 | { |
710 | return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); | |
711 | } | |
712 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
713 | ||
714 | /* | |
8781bcbc SC |
715 | * ptep_set_wrprotect - mark read-only while trasferring potential hardware |
716 | * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. | |
2f4b829c CM |
717 | */ |
718 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT | |
719 | static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) | |
720 | { | |
3bbf7157 CM |
721 | pte_t old_pte, pte; |
722 | ||
723 | pte = READ_ONCE(*ptep); | |
724 | do { | |
725 | old_pte = pte; | |
8781bcbc SC |
726 | /* |
727 | * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY | |
728 | * clear), set the PTE_DIRTY bit. | |
729 | */ | |
730 | if (pte_hw_dirty(pte)) | |
731 | pte = pte_mkdirty(pte); | |
3bbf7157 CM |
732 | pte = pte_wrprotect(pte); |
733 | pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), | |
734 | pte_val(old_pte), pte_val(pte)); | |
735 | } while (pte_val(pte) != pte_val(old_pte)); | |
2f4b829c CM |
736 | } |
737 | ||
738 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
739 | #define __HAVE_ARCH_PMDP_SET_WRPROTECT | |
740 | static inline void pmdp_set_wrprotect(struct mm_struct *mm, | |
741 | unsigned long address, pmd_t *pmdp) | |
742 | { | |
743 | ptep_set_wrprotect(mm, address, (pte_t *)pmdp); | |
744 | } | |
1d78a62c CM |
745 | |
746 | #define pmdp_establish pmdp_establish | |
747 | static inline pmd_t pmdp_establish(struct vm_area_struct *vma, | |
748 | unsigned long address, pmd_t *pmdp, pmd_t pmd) | |
749 | { | |
750 | return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); | |
751 | } | |
2f4b829c | 752 | #endif |
2f4b829c | 753 | |
4f04d8f0 CM |
754 | /* |
755 | * Encode and decode a swap entry: | |
3676f9ef | 756 | * bits 0-1: present (must be zero) |
9b3e661e KS |
757 | * bits 2-7: swap type |
758 | * bits 8-57: swap offset | |
fdc69e7d | 759 | * bit 58: PTE_PROT_NONE (must be zero) |
4f04d8f0 | 760 | */ |
9b3e661e | 761 | #define __SWP_TYPE_SHIFT 2 |
4f04d8f0 | 762 | #define __SWP_TYPE_BITS 6 |
9b3e661e | 763 | #define __SWP_OFFSET_BITS 50 |
4f04d8f0 CM |
764 | #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) |
765 | #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) | |
3676f9ef | 766 | #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) |
4f04d8f0 CM |
767 | |
768 | #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) | |
3676f9ef | 769 | #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) |
4f04d8f0 CM |
770 | #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) |
771 | ||
772 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | |
773 | #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) | |
774 | ||
775 | /* | |
776 | * Ensure that there are not more swap files than can be encoded in the kernel | |
aad9061b | 777 | * PTEs. |
4f04d8f0 CM |
778 | */ |
779 | #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) | |
780 | ||
4f04d8f0 CM |
781 | extern int kern_addr_valid(unsigned long addr); |
782 | ||
783 | #include <asm-generic/pgtable.h> | |
784 | ||
39b5be9b WD |
785 | void pgd_cache_init(void); |
786 | #define pgtable_cache_init pgd_cache_init | |
4f04d8f0 | 787 | |
cba3574f WD |
788 | /* |
789 | * On AArch64, the cache coherency is handled via the set_pte_at() function. | |
790 | */ | |
791 | static inline void update_mmu_cache(struct vm_area_struct *vma, | |
792 | unsigned long addr, pte_t *ptep) | |
793 | { | |
794 | /* | |
120798d2 WD |
795 | * We don't do anything here, so there's a very small chance of |
796 | * us retaking a user fault which we just fixed up. The alternative | |
797 | * is doing a dsb(ishst), but that penalises the fastpath. | |
cba3574f | 798 | */ |
cba3574f WD |
799 | } |
800 | ||
801 | #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) | |
802 | ||
7db743c6 CM |
803 | #define kc_vaddr_to_offset(v) ((v) & ~VA_START) |
804 | #define kc_offset_to_vaddr(o) ((o) | VA_START) | |
805 | ||
529c4b05 KM |
806 | #ifdef CONFIG_ARM64_PA_BITS_52 |
807 | #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) | |
808 | #else | |
809 | #define phys_to_ttbr(addr) (addr) | |
810 | #endif | |
811 | ||
4f04d8f0 CM |
812 | #endif /* !__ASSEMBLY__ */ |
813 | ||
814 | #endif /* __ASM_PGTABLE_H */ |