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caab277b | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
4f04d8f0 CM |
2 | /* |
3 | * Copyright (C) 2012 ARM Ltd. | |
4f04d8f0 CM |
4 | */ |
5 | #ifndef __ASM_PGTABLE_H | |
6 | #define __ASM_PGTABLE_H | |
7 | ||
2f4b829c | 8 | #include <asm/bug.h> |
4f04d8f0 CM |
9 | #include <asm/proc-fns.h> |
10 | ||
11 | #include <asm/memory.h> | |
12 | #include <asm/pgtable-hwdef.h> | |
3eca86e7 | 13 | #include <asm/pgtable-prot.h> |
3403e56b | 14 | #include <asm/tlbflush.h> |
4f04d8f0 CM |
15 | |
16 | /* | |
3e1907d5 | 17 | * VMALLOC range. |
08375198 | 18 | * |
f9040773 | 19 | * VMALLOC_START: beginning of the kernel vmalloc space |
3e1907d5 AB |
20 | * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space |
21 | * and fixed mappings | |
4f04d8f0 | 22 | */ |
f9040773 | 23 | #define VMALLOC_START (MODULES_END) |
08375198 | 24 | #define VMALLOC_END (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K) |
4f04d8f0 | 25 | |
3bab79ed | 26 | #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) |
4f04d8f0 | 27 | |
d016bf7e | 28 | #define FIRST_USER_ADDRESS 0UL |
4f04d8f0 CM |
29 | |
30 | #ifndef __ASSEMBLY__ | |
2f4b829c | 31 | |
3bbf7157 | 32 | #include <asm/cmpxchg.h> |
961faac1 | 33 | #include <asm/fixmap.h> |
2f4b829c | 34 | #include <linux/mmdebug.h> |
86c9e812 WD |
35 | #include <linux/mm_types.h> |
36 | #include <linux/sched.h> | |
2f4b829c | 37 | |
4f04d8f0 CM |
38 | extern void __pte_error(const char *file, int line, unsigned long val); |
39 | extern void __pmd_error(const char *file, int line, unsigned long val); | |
c79b954b | 40 | extern void __pud_error(const char *file, int line, unsigned long val); |
4f04d8f0 CM |
41 | extern void __pgd_error(const char *file, int line, unsigned long val); |
42 | ||
4f04d8f0 CM |
43 | /* |
44 | * ZERO_PAGE is a global shared page that is always zero: used | |
45 | * for zero-mapped memory areas etc.. | |
46 | */ | |
5227cfa7 | 47 | extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; |
2077be67 | 48 | #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) |
4f04d8f0 | 49 | |
7078db46 CM |
50 | #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) |
51 | ||
75387b92 KM |
52 | /* |
53 | * Macros to convert between a physical address and its placement in a | |
54 | * page table entry, taking care of 52-bit addresses. | |
55 | */ | |
56 | #ifdef CONFIG_ARM64_PA_BITS_52 | |
57 | #define __pte_to_phys(pte) \ | |
58 | ((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36)) | |
59 | #define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK) | |
60 | #else | |
61 | #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK) | |
62 | #define __phys_to_pte_val(phys) (phys) | |
63 | #endif | |
4f04d8f0 | 64 | |
75387b92 KM |
65 | #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) |
66 | #define pfn_pte(pfn,prot) \ | |
67 | __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) | |
4f04d8f0 CM |
68 | |
69 | #define pte_none(pte) (!pte_val(pte)) | |
70 | #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) | |
71 | #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) | |
7078db46 | 72 | |
4f04d8f0 CM |
73 | /* |
74 | * The following only work if pte_present(). Undefined behaviour otherwise. | |
75 | */ | |
84fe6826 | 76 | #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) |
84fe6826 SC |
77 | #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) |
78 | #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) | |
79 | #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) | |
ec663d96 | 80 | #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) |
93ef666a | 81 | #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) |
73b20c84 | 82 | #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) |
4f04d8f0 | 83 | |
d27cfa1f AB |
84 | #define pte_cont_addr_end(addr, end) \ |
85 | ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ | |
86 | (__boundary - 1 < (end) - 1) ? __boundary : (end); \ | |
87 | }) | |
88 | ||
89 | #define pmd_cont_addr_end(addr, end) \ | |
90 | ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ | |
91 | (__boundary - 1 < (end) - 1) ? __boundary : (end); \ | |
92 | }) | |
93 | ||
b847415c | 94 | #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) |
2f4b829c CM |
95 | #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) |
96 | #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) | |
97 | ||
766ffb69 | 98 | #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) |
ec663d96 | 99 | #define pte_valid_not_user(pte) \ |
bb2c329a | 100 | ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID) |
76c714be WD |
101 | #define pte_valid_young(pte) \ |
102 | ((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF)) | |
6218f96c CM |
103 | #define pte_valid_user(pte) \ |
104 | ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) | |
76c714be WD |
105 | |
106 | /* | |
107 | * Could the pte be present in the TLB? We must check mm_tlb_flush_pending | |
108 | * so that we don't erroneously return false for pages that have been | |
109 | * remapped as PROT_NONE but are yet to be flushed from the TLB. | |
110 | */ | |
111 | #define pte_accessible(mm, pte) \ | |
112 | (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte)) | |
4f04d8f0 | 113 | |
6218f96c CM |
114 | /* |
115 | * p??_access_permitted() is true for valid user mappings (subject to the | |
bb2c329a CM |
116 | * write permission check). PROT_NONE mappings do not have the PTE_VALID bit |
117 | * set. | |
6218f96c CM |
118 | */ |
119 | #define pte_access_permitted(pte, write) \ | |
120 | (pte_valid_user(pte) && (!(write) || pte_write(pte))) | |
121 | #define pmd_access_permitted(pmd, write) \ | |
122 | (pte_access_permitted(pmd_pte(pmd), (write))) | |
123 | #define pud_access_permitted(pud, write) \ | |
124 | (pte_access_permitted(pud_pte(pud), (write))) | |
125 | ||
b6d4f280 | 126 | static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) |
44b6dfc5 | 127 | { |
b6d4f280 | 128 | pte_val(pte) &= ~pgprot_val(prot); |
44b6dfc5 SC |
129 | return pte; |
130 | } | |
131 | ||
b6d4f280 | 132 | static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) |
44b6dfc5 | 133 | { |
b6d4f280 | 134 | pte_val(pte) |= pgprot_val(prot); |
44b6dfc5 SC |
135 | return pte; |
136 | } | |
137 | ||
b6d4f280 LA |
138 | static inline pte_t pte_wrprotect(pte_t pte) |
139 | { | |
73e86cb0 CM |
140 | pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); |
141 | pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); | |
142 | return pte; | |
b6d4f280 LA |
143 | } |
144 | ||
145 | static inline pte_t pte_mkwrite(pte_t pte) | |
146 | { | |
73e86cb0 CM |
147 | pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); |
148 | pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); | |
149 | return pte; | |
b6d4f280 LA |
150 | } |
151 | ||
44b6dfc5 SC |
152 | static inline pte_t pte_mkclean(pte_t pte) |
153 | { | |
8781bcbc SC |
154 | pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); |
155 | pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); | |
156 | ||
157 | return pte; | |
44b6dfc5 SC |
158 | } |
159 | ||
160 | static inline pte_t pte_mkdirty(pte_t pte) | |
161 | { | |
8781bcbc SC |
162 | pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); |
163 | ||
164 | if (pte_write(pte)) | |
165 | pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); | |
166 | ||
167 | return pte; | |
44b6dfc5 SC |
168 | } |
169 | ||
170 | static inline pte_t pte_mkold(pte_t pte) | |
171 | { | |
b6d4f280 | 172 | return clear_pte_bit(pte, __pgprot(PTE_AF)); |
44b6dfc5 SC |
173 | } |
174 | ||
175 | static inline pte_t pte_mkyoung(pte_t pte) | |
176 | { | |
b6d4f280 | 177 | return set_pte_bit(pte, __pgprot(PTE_AF)); |
44b6dfc5 SC |
178 | } |
179 | ||
180 | static inline pte_t pte_mkspecial(pte_t pte) | |
181 | { | |
b6d4f280 | 182 | return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); |
44b6dfc5 | 183 | } |
4f04d8f0 | 184 | |
93ef666a JL |
185 | static inline pte_t pte_mkcont(pte_t pte) |
186 | { | |
66b3923a DW |
187 | pte = set_pte_bit(pte, __pgprot(PTE_CONT)); |
188 | return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); | |
93ef666a JL |
189 | } |
190 | ||
191 | static inline pte_t pte_mknoncont(pte_t pte) | |
192 | { | |
193 | return clear_pte_bit(pte, __pgprot(PTE_CONT)); | |
194 | } | |
195 | ||
5ebe3a44 JM |
196 | static inline pte_t pte_mkpresent(pte_t pte) |
197 | { | |
198 | return set_pte_bit(pte, __pgprot(PTE_VALID)); | |
199 | } | |
200 | ||
66b3923a DW |
201 | static inline pmd_t pmd_mkcont(pmd_t pmd) |
202 | { | |
203 | return __pmd(pmd_val(pmd) | PMD_SECT_CONT); | |
204 | } | |
205 | ||
73b20c84 RM |
206 | static inline pte_t pte_mkdevmap(pte_t pte) |
207 | { | |
30e23538 | 208 | return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); |
73b20c84 RM |
209 | } |
210 | ||
4f04d8f0 CM |
211 | static inline void set_pte(pte_t *ptep, pte_t pte) |
212 | { | |
20a004e7 | 213 | WRITE_ONCE(*ptep, pte); |
7f0b1bf0 CM |
214 | |
215 | /* | |
216 | * Only if the new pte is valid and kernel, otherwise TLB maintenance | |
217 | * or update_mmu_cache() have the necessary barriers. | |
218 | */ | |
205546bf | 219 | if (pte_valid_not_user(pte)) { |
7f0b1bf0 | 220 | dsb(ishst); |
205546bf WD |
221 | isb(); |
222 | } | |
4f04d8f0 CM |
223 | } |
224 | ||
907e21c1 | 225 | extern void __sync_icache_dcache(pte_t pteval); |
4f04d8f0 | 226 | |
2f4b829c CM |
227 | /* |
228 | * PTE bits configuration in the presence of hardware Dirty Bit Management | |
229 | * (PTE_WRITE == PTE_DBM): | |
230 | * | |
231 | * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) | |
232 | * 0 0 | 1 0 0 | |
233 | * 0 1 | 1 1 0 | |
234 | * 1 0 | 1 0 1 | |
235 | * 1 1 | 0 1 x | |
236 | * | |
237 | * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via | |
238 | * the page fault mechanism. Checking the dirty status of a pte becomes: | |
239 | * | |
b847415c | 240 | * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) |
2f4b829c | 241 | */ |
9b604722 MR |
242 | |
243 | static inline void __check_racy_pte_update(struct mm_struct *mm, pte_t *ptep, | |
244 | pte_t pte) | |
4f04d8f0 | 245 | { |
20a004e7 WD |
246 | pte_t old_pte; |
247 | ||
9b604722 MR |
248 | if (!IS_ENABLED(CONFIG_DEBUG_VM)) |
249 | return; | |
250 | ||
251 | old_pte = READ_ONCE(*ptep); | |
252 | ||
253 | if (!pte_valid(old_pte) || !pte_valid(pte)) | |
254 | return; | |
255 | if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) | |
256 | return; | |
02522463 | 257 | |
2f4b829c | 258 | /* |
9b604722 MR |
259 | * Check for potential race with hardware updates of the pte |
260 | * (ptep_set_access_flags safely changes valid ptes without going | |
261 | * through an invalid entry). | |
2f4b829c | 262 | */ |
9b604722 MR |
263 | VM_WARN_ONCE(!pte_young(pte), |
264 | "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", | |
265 | __func__, pte_val(old_pte), pte_val(pte)); | |
266 | VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), | |
267 | "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", | |
268 | __func__, pte_val(old_pte), pte_val(pte)); | |
269 | } | |
270 | ||
271 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, | |
272 | pte_t *ptep, pte_t pte) | |
273 | { | |
274 | if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) | |
275 | __sync_icache_dcache(pte); | |
276 | ||
277 | __check_racy_pte_update(mm, ptep, pte); | |
2f4b829c | 278 | |
4f04d8f0 CM |
279 | set_pte(ptep, pte); |
280 | } | |
281 | ||
282 | /* | |
283 | * Huge pte definitions. | |
284 | */ | |
084bd298 SC |
285 | #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) |
286 | ||
287 | /* | |
288 | * Hugetlb definitions. | |
289 | */ | |
66b3923a | 290 | #define HUGE_MAX_HSTATE 4 |
084bd298 SC |
291 | #define HPAGE_SHIFT PMD_SHIFT |
292 | #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) | |
293 | #define HPAGE_MASK (~(HPAGE_SIZE - 1)) | |
294 | #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) | |
4f04d8f0 | 295 | |
75387b92 KM |
296 | static inline pte_t pgd_pte(pgd_t pgd) |
297 | { | |
298 | return __pte(pgd_val(pgd)); | |
299 | } | |
300 | ||
29e56940 SC |
301 | static inline pte_t pud_pte(pud_t pud) |
302 | { | |
303 | return __pte(pud_val(pud)); | |
304 | } | |
305 | ||
eb3f0624 PA |
306 | static inline pud_t pte_pud(pte_t pte) |
307 | { | |
308 | return __pud(pte_val(pte)); | |
309 | } | |
310 | ||
29e56940 SC |
311 | static inline pmd_t pud_pmd(pud_t pud) |
312 | { | |
313 | return __pmd(pud_val(pud)); | |
314 | } | |
315 | ||
9c7e535f SC |
316 | static inline pte_t pmd_pte(pmd_t pmd) |
317 | { | |
318 | return __pte(pmd_val(pmd)); | |
319 | } | |
af074848 | 320 | |
9c7e535f SC |
321 | static inline pmd_t pte_pmd(pte_t pte) |
322 | { | |
323 | return __pmd(pte_val(pte)); | |
324 | } | |
af074848 | 325 | |
f7f0097a | 326 | static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) |
8ce837ce | 327 | { |
f7f0097a AK |
328 | return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT); |
329 | } | |
330 | ||
331 | static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) | |
8ce837ce | 332 | { |
f7f0097a | 333 | return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); |
8ce837ce AB |
334 | } |
335 | ||
56166230 GK |
336 | #ifdef CONFIG_NUMA_BALANCING |
337 | /* | |
338 | * See the comment in include/asm-generic/pgtable.h | |
339 | */ | |
340 | static inline int pte_protnone(pte_t pte) | |
341 | { | |
342 | return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE; | |
343 | } | |
344 | ||
345 | static inline int pmd_protnone(pmd_t pmd) | |
346 | { | |
347 | return pte_protnone(pmd_pte(pmd)); | |
348 | } | |
349 | #endif | |
350 | ||
af074848 SC |
351 | /* |
352 | * THP definitions. | |
353 | */ | |
af074848 SC |
354 | |
355 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
356 | #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT)) | |
29e56940 | 357 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
af074848 | 358 | |
5bb1cc0f | 359 | #define pmd_present(pmd) pte_present(pmd_pte(pmd)) |
c164e038 | 360 | #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) |
9c7e535f | 361 | #define pmd_young(pmd) pte_young(pmd_pte(pmd)) |
0795edaf | 362 | #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) |
9c7e535f | 363 | #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) |
9c7e535f SC |
364 | #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) |
365 | #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) | |
ab4db1f2 | 366 | #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) |
9c7e535f SC |
367 | #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) |
368 | #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) | |
5bb1cc0f | 369 | #define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_SECT_VALID)) |
af074848 | 370 | |
0dbd3b18 SP |
371 | #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) |
372 | ||
9c7e535f | 373 | #define pmd_write(pmd) pte_write(pmd_pte(pmd)) |
af074848 SC |
374 | |
375 | #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) | |
376 | ||
73b20c84 RM |
377 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
378 | #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) | |
379 | #endif | |
30e23538 JH |
380 | static inline pmd_t pmd_mkdevmap(pmd_t pmd) |
381 | { | |
382 | return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); | |
383 | } | |
73b20c84 | 384 | |
75387b92 KM |
385 | #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) |
386 | #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) | |
387 | #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) | |
388 | #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) | |
af074848 SC |
389 | #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) |
390 | ||
35a63966 | 391 | #define pud_young(pud) pte_young(pud_pte(pud)) |
eb3f0624 | 392 | #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) |
29e56940 | 393 | #define pud_write(pud) pte_write(pud_pte(pud)) |
75387b92 | 394 | |
b8e0ba7c PA |
395 | #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) |
396 | ||
75387b92 KM |
397 | #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) |
398 | #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) | |
399 | #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) | |
400 | #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) | |
af074848 | 401 | |
ceb21835 | 402 | #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)) |
af074848 | 403 | |
75387b92 KM |
404 | #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) |
405 | #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) | |
406 | ||
a501e324 CM |
407 | #define __pgprot_modify(prot,mask,bits) \ |
408 | __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) | |
409 | ||
4f04d8f0 CM |
410 | /* |
411 | * Mark the prot value as uncacheable and unbufferable. | |
412 | */ | |
413 | #define pgprot_noncached(prot) \ | |
de2db743 | 414 | __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) |
4f04d8f0 | 415 | #define pgprot_writecombine(prot) \ |
de2db743 | 416 | __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) |
d1e6dc91 LD |
417 | #define pgprot_device(prot) \ |
418 | __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) | |
4f04d8f0 CM |
419 | #define __HAVE_PHYS_MEM_ACCESS_PROT |
420 | struct file; | |
421 | extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, | |
422 | unsigned long size, pgprot_t vma_prot); | |
423 | ||
424 | #define pmd_none(pmd) (!pmd_val(pmd)) | |
4f04d8f0 | 425 | |
ab4db1f2 | 426 | #define pmd_bad(pmd) (!(pmd_val(pmd) & PMD_TABLE_BIT)) |
4f04d8f0 | 427 | |
36311607 MZ |
428 | #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ |
429 | PMD_TYPE_TABLE) | |
430 | #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ | |
431 | PMD_TYPE_SECT) | |
432 | ||
cac4b8cd | 433 | #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 |
7d4e2dcf QC |
434 | static inline bool pud_sect(pud_t pud) { return false; } |
435 | static inline bool pud_table(pud_t pud) { return true; } | |
206a2a73 SC |
436 | #else |
437 | #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ | |
438 | PUD_TYPE_SECT) | |
523d6e9f | 439 | #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ |
440 | PUD_TYPE_TABLE) | |
206a2a73 | 441 | #endif |
36311607 | 442 | |
2330b7ca JY |
443 | extern pgd_t init_pg_dir[PTRS_PER_PGD]; |
444 | extern pgd_t init_pg_end[]; | |
445 | extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; | |
446 | extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; | |
447 | extern pgd_t tramp_pg_dir[PTRS_PER_PGD]; | |
448 | ||
449 | extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); | |
450 | ||
451 | static inline bool in_swapper_pgdir(void *addr) | |
452 | { | |
453 | return ((unsigned long)addr & PAGE_MASK) == | |
454 | ((unsigned long)swapper_pg_dir & PAGE_MASK); | |
455 | } | |
456 | ||
4f04d8f0 CM |
457 | static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) |
458 | { | |
e9ed821b JM |
459 | #ifdef __PAGETABLE_PMD_FOLDED |
460 | if (in_swapper_pgdir(pmdp)) { | |
2330b7ca JY |
461 | set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); |
462 | return; | |
463 | } | |
e9ed821b | 464 | #endif /* __PAGETABLE_PMD_FOLDED */ |
2330b7ca | 465 | |
20a004e7 | 466 | WRITE_ONCE(*pmdp, pmd); |
0795edaf | 467 | |
205546bf | 468 | if (pmd_valid(pmd)) { |
0795edaf | 469 | dsb(ishst); |
205546bf WD |
470 | isb(); |
471 | } | |
4f04d8f0 CM |
472 | } |
473 | ||
474 | static inline void pmd_clear(pmd_t *pmdp) | |
475 | { | |
476 | set_pmd(pmdp, __pmd(0)); | |
477 | } | |
478 | ||
dca56dca | 479 | static inline phys_addr_t pmd_page_paddr(pmd_t pmd) |
4f04d8f0 | 480 | { |
75387b92 | 481 | return __pmd_to_phys(pmd); |
4f04d8f0 CM |
482 | } |
483 | ||
74dd022f QC |
484 | static inline void pte_unmap(pte_t *pte) { } |
485 | ||
053520f7 MR |
486 | /* Find an entry in the third-level page table. */ |
487 | #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) | |
488 | ||
f069faba | 489 | #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) |
dca56dca | 490 | #define pte_offset_kernel(dir,addr) ((pte_t *)__va(pte_offset_phys((dir), (addr)))) |
053520f7 MR |
491 | |
492 | #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) | |
053520f7 | 493 | |
961faac1 MR |
494 | #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) |
495 | #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) | |
496 | #define pte_clear_fixmap() clear_fixmap(FIX_PTE) | |
497 | ||
75387b92 | 498 | #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(__pmd_to_phys(pmd))) |
4f04d8f0 | 499 | |
6533945a AB |
500 | /* use ONLY for statically allocated translation tables */ |
501 | #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) | |
502 | ||
4f04d8f0 CM |
503 | /* |
504 | * Conversion functions: convert a page and protection to a page entry, | |
505 | * and a page entry and page directory to the page they refer to. | |
506 | */ | |
507 | #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) | |
508 | ||
9f25e6ad | 509 | #if CONFIG_PGTABLE_LEVELS > 2 |
4f04d8f0 | 510 | |
7078db46 CM |
511 | #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd)) |
512 | ||
4f04d8f0 | 513 | #define pud_none(pud) (!pud_val(pud)) |
ab4db1f2 | 514 | #define pud_bad(pud) (!(pud_val(pud) & PUD_TABLE_BIT)) |
f02ab08a | 515 | #define pud_present(pud) pte_present(pud_pte(pud)) |
0795edaf | 516 | #define pud_valid(pud) pte_valid(pud_pte(pud)) |
4f04d8f0 CM |
517 | |
518 | static inline void set_pud(pud_t *pudp, pud_t pud) | |
519 | { | |
e9ed821b JM |
520 | #ifdef __PAGETABLE_PUD_FOLDED |
521 | if (in_swapper_pgdir(pudp)) { | |
2330b7ca JY |
522 | set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); |
523 | return; | |
524 | } | |
e9ed821b | 525 | #endif /* __PAGETABLE_PUD_FOLDED */ |
2330b7ca | 526 | |
20a004e7 | 527 | WRITE_ONCE(*pudp, pud); |
0795edaf | 528 | |
205546bf | 529 | if (pud_valid(pud)) { |
0795edaf | 530 | dsb(ishst); |
205546bf WD |
531 | isb(); |
532 | } | |
4f04d8f0 CM |
533 | } |
534 | ||
535 | static inline void pud_clear(pud_t *pudp) | |
536 | { | |
537 | set_pud(pudp, __pud(0)); | |
538 | } | |
539 | ||
dca56dca | 540 | static inline phys_addr_t pud_page_paddr(pud_t pud) |
4f04d8f0 | 541 | { |
75387b92 | 542 | return __pud_to_phys(pud); |
4f04d8f0 CM |
543 | } |
544 | ||
7078db46 CM |
545 | /* Find an entry in the second-level page table. */ |
546 | #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) | |
547 | ||
20a004e7 | 548 | #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) |
dca56dca | 549 | #define pmd_offset(dir, addr) ((pmd_t *)__va(pmd_offset_phys((dir), (addr)))) |
7078db46 | 550 | |
961faac1 MR |
551 | #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) |
552 | #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) | |
553 | #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) | |
7078db46 | 554 | |
75387b92 | 555 | #define pud_page(pud) pfn_to_page(__phys_to_pfn(__pud_to_phys(pud))) |
29e56940 | 556 | |
6533945a AB |
557 | /* use ONLY for statically allocated translation tables */ |
558 | #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) | |
559 | ||
dca56dca MR |
560 | #else |
561 | ||
562 | #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) | |
563 | ||
961faac1 MR |
564 | /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ |
565 | #define pmd_set_fixmap(addr) NULL | |
566 | #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) | |
567 | #define pmd_clear_fixmap() | |
568 | ||
6533945a AB |
569 | #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) |
570 | ||
9f25e6ad | 571 | #endif /* CONFIG_PGTABLE_LEVELS > 2 */ |
4f04d8f0 | 572 | |
9f25e6ad | 573 | #if CONFIG_PGTABLE_LEVELS > 3 |
c79b954b | 574 | |
7078db46 CM |
575 | #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud)) |
576 | ||
c79b954b JL |
577 | #define pgd_none(pgd) (!pgd_val(pgd)) |
578 | #define pgd_bad(pgd) (!(pgd_val(pgd) & 2)) | |
579 | #define pgd_present(pgd) (pgd_val(pgd)) | |
580 | ||
581 | static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) | |
582 | { | |
2330b7ca JY |
583 | if (in_swapper_pgdir(pgdp)) { |
584 | set_swapper_pgd(pgdp, pgd); | |
585 | return; | |
586 | } | |
587 | ||
20a004e7 | 588 | WRITE_ONCE(*pgdp, pgd); |
c79b954b JL |
589 | dsb(ishst); |
590 | } | |
591 | ||
592 | static inline void pgd_clear(pgd_t *pgdp) | |
593 | { | |
594 | set_pgd(pgdp, __pgd(0)); | |
595 | } | |
596 | ||
dca56dca | 597 | static inline phys_addr_t pgd_page_paddr(pgd_t pgd) |
c79b954b | 598 | { |
75387b92 | 599 | return __pgd_to_phys(pgd); |
c79b954b JL |
600 | } |
601 | ||
7078db46 CM |
602 | /* Find an entry in the frst-level page table. */ |
603 | #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) | |
604 | ||
20a004e7 | 605 | #define pud_offset_phys(dir, addr) (pgd_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t)) |
dca56dca | 606 | #define pud_offset(dir, addr) ((pud_t *)__va(pud_offset_phys((dir), (addr)))) |
7078db46 | 607 | |
961faac1 MR |
608 | #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr)) |
609 | #define pud_set_fixmap_offset(pgd, addr) pud_set_fixmap(pud_offset_phys(pgd, addr)) | |
610 | #define pud_clear_fixmap() clear_fixmap(FIX_PUD) | |
7078db46 | 611 | |
75387b92 | 612 | #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(__pgd_to_phys(pgd))) |
5d96e0cb | 613 | |
6533945a AB |
614 | /* use ONLY for statically allocated translation tables */ |
615 | #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr)))) | |
616 | ||
dca56dca MR |
617 | #else |
618 | ||
619 | #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;}) | |
620 | ||
961faac1 MR |
621 | /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ |
622 | #define pud_set_fixmap(addr) NULL | |
623 | #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) | |
624 | #define pud_clear_fixmap() | |
625 | ||
6533945a AB |
626 | #define pud_offset_kimg(dir,addr) ((pud_t *)dir) |
627 | ||
9f25e6ad | 628 | #endif /* CONFIG_PGTABLE_LEVELS > 3 */ |
c79b954b | 629 | |
7078db46 CM |
630 | #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) |
631 | ||
4f04d8f0 CM |
632 | /* to find an entry in a page-table-directory */ |
633 | #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) | |
634 | ||
dca56dca MR |
635 | #define pgd_offset_raw(pgd, addr) ((pgd) + pgd_index(addr)) |
636 | ||
637 | #define pgd_offset(mm, addr) (pgd_offset_raw((mm)->pgd, (addr))) | |
4f04d8f0 CM |
638 | |
639 | /* to find an entry in a kernel page-table-directory */ | |
640 | #define pgd_offset_k(addr) pgd_offset(&init_mm, addr) | |
641 | ||
961faac1 MR |
642 | #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) |
643 | #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) | |
644 | ||
4f04d8f0 CM |
645 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) |
646 | { | |
a6fadf7e | 647 | const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | |
1a541b4e | 648 | PTE_PROT_NONE | PTE_VALID | PTE_WRITE; |
2f4b829c CM |
649 | /* preserve the hardware dirty information */ |
650 | if (pte_hw_dirty(pte)) | |
62d96c71 | 651 | pte = pte_mkdirty(pte); |
4f04d8f0 CM |
652 | pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); |
653 | return pte; | |
654 | } | |
655 | ||
9c7e535f SC |
656 | static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) |
657 | { | |
658 | return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); | |
659 | } | |
660 | ||
66dbd6e6 CM |
661 | #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS |
662 | extern int ptep_set_access_flags(struct vm_area_struct *vma, | |
663 | unsigned long address, pte_t *ptep, | |
664 | pte_t entry, int dirty); | |
665 | ||
282aa705 CM |
666 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
667 | #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS | |
668 | static inline int pmdp_set_access_flags(struct vm_area_struct *vma, | |
669 | unsigned long address, pmd_t *pmdp, | |
670 | pmd_t entry, int dirty) | |
671 | { | |
672 | return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); | |
673 | } | |
73b20c84 RM |
674 | |
675 | static inline int pud_devmap(pud_t pud) | |
676 | { | |
677 | return 0; | |
678 | } | |
679 | ||
680 | static inline int pgd_devmap(pgd_t pgd) | |
681 | { | |
682 | return 0; | |
683 | } | |
282aa705 CM |
684 | #endif |
685 | ||
2f4b829c CM |
686 | /* |
687 | * Atomic pte/pmd modifications. | |
688 | */ | |
689 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG | |
06485053 | 690 | static inline int __ptep_test_and_clear_young(pte_t *ptep) |
2f4b829c | 691 | { |
3bbf7157 | 692 | pte_t old_pte, pte; |
2f4b829c | 693 | |
3bbf7157 CM |
694 | pte = READ_ONCE(*ptep); |
695 | do { | |
696 | old_pte = pte; | |
697 | pte = pte_mkold(pte); | |
698 | pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), | |
699 | pte_val(old_pte), pte_val(pte)); | |
700 | } while (pte_val(pte) != pte_val(old_pte)); | |
2f4b829c | 701 | |
3bbf7157 | 702 | return pte_young(pte); |
2f4b829c CM |
703 | } |
704 | ||
06485053 CM |
705 | static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, |
706 | unsigned long address, | |
707 | pte_t *ptep) | |
708 | { | |
709 | return __ptep_test_and_clear_young(ptep); | |
710 | } | |
711 | ||
3403e56b AVB |
712 | #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH |
713 | static inline int ptep_clear_flush_young(struct vm_area_struct *vma, | |
714 | unsigned long address, pte_t *ptep) | |
715 | { | |
716 | int young = ptep_test_and_clear_young(vma, address, ptep); | |
717 | ||
718 | if (young) { | |
719 | /* | |
720 | * We can elide the trailing DSB here since the worst that can | |
721 | * happen is that a CPU continues to use the young entry in its | |
722 | * TLB and we mistakenly reclaim the associated page. The | |
723 | * window for such an event is bounded by the next | |
724 | * context-switch, which provides a DSB to complete the TLB | |
725 | * invalidation. | |
726 | */ | |
727 | flush_tlb_page_nosync(vma, address); | |
728 | } | |
729 | ||
730 | return young; | |
731 | } | |
732 | ||
2f4b829c CM |
733 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
734 | #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG | |
735 | static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, | |
736 | unsigned long address, | |
737 | pmd_t *pmdp) | |
738 | { | |
739 | return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); | |
740 | } | |
741 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
742 | ||
743 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR | |
744 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, | |
745 | unsigned long address, pte_t *ptep) | |
746 | { | |
3bbf7157 | 747 | return __pte(xchg_relaxed(&pte_val(*ptep), 0)); |
2f4b829c CM |
748 | } |
749 | ||
750 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
911f56ee CM |
751 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR |
752 | static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, | |
753 | unsigned long address, pmd_t *pmdp) | |
2f4b829c CM |
754 | { |
755 | return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); | |
756 | } | |
757 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
758 | ||
759 | /* | |
8781bcbc SC |
760 | * ptep_set_wrprotect - mark read-only while trasferring potential hardware |
761 | * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. | |
2f4b829c CM |
762 | */ |
763 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT | |
764 | static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) | |
765 | { | |
3bbf7157 CM |
766 | pte_t old_pte, pte; |
767 | ||
768 | pte = READ_ONCE(*ptep); | |
769 | do { | |
770 | old_pte = pte; | |
8781bcbc SC |
771 | /* |
772 | * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY | |
773 | * clear), set the PTE_DIRTY bit. | |
774 | */ | |
775 | if (pte_hw_dirty(pte)) | |
776 | pte = pte_mkdirty(pte); | |
3bbf7157 CM |
777 | pte = pte_wrprotect(pte); |
778 | pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), | |
779 | pte_val(old_pte), pte_val(pte)); | |
780 | } while (pte_val(pte) != pte_val(old_pte)); | |
2f4b829c CM |
781 | } |
782 | ||
783 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
784 | #define __HAVE_ARCH_PMDP_SET_WRPROTECT | |
785 | static inline void pmdp_set_wrprotect(struct mm_struct *mm, | |
786 | unsigned long address, pmd_t *pmdp) | |
787 | { | |
788 | ptep_set_wrprotect(mm, address, (pte_t *)pmdp); | |
789 | } | |
1d78a62c CM |
790 | |
791 | #define pmdp_establish pmdp_establish | |
792 | static inline pmd_t pmdp_establish(struct vm_area_struct *vma, | |
793 | unsigned long address, pmd_t *pmdp, pmd_t pmd) | |
794 | { | |
795 | return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); | |
796 | } | |
2f4b829c | 797 | #endif |
2f4b829c | 798 | |
4f04d8f0 CM |
799 | /* |
800 | * Encode and decode a swap entry: | |
3676f9ef | 801 | * bits 0-1: present (must be zero) |
9b3e661e KS |
802 | * bits 2-7: swap type |
803 | * bits 8-57: swap offset | |
fdc69e7d | 804 | * bit 58: PTE_PROT_NONE (must be zero) |
4f04d8f0 | 805 | */ |
9b3e661e | 806 | #define __SWP_TYPE_SHIFT 2 |
4f04d8f0 | 807 | #define __SWP_TYPE_BITS 6 |
9b3e661e | 808 | #define __SWP_OFFSET_BITS 50 |
4f04d8f0 CM |
809 | #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) |
810 | #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) | |
3676f9ef | 811 | #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) |
4f04d8f0 CM |
812 | |
813 | #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) | |
3676f9ef | 814 | #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) |
4f04d8f0 CM |
815 | #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) |
816 | ||
817 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | |
818 | #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) | |
819 | ||
820 | /* | |
821 | * Ensure that there are not more swap files than can be encoded in the kernel | |
aad9061b | 822 | * PTEs. |
4f04d8f0 CM |
823 | */ |
824 | #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) | |
825 | ||
4f04d8f0 CM |
826 | extern int kern_addr_valid(unsigned long addr); |
827 | ||
828 | #include <asm-generic/pgtable.h> | |
829 | ||
615c48ad | 830 | static inline void pgtable_cache_init(void) { } |
4f04d8f0 | 831 | |
cba3574f WD |
832 | /* |
833 | * On AArch64, the cache coherency is handled via the set_pte_at() function. | |
834 | */ | |
835 | static inline void update_mmu_cache(struct vm_area_struct *vma, | |
836 | unsigned long addr, pte_t *ptep) | |
837 | { | |
838 | /* | |
120798d2 WD |
839 | * We don't do anything here, so there's a very small chance of |
840 | * us retaking a user fault which we just fixed up. The alternative | |
841 | * is doing a dsb(ishst), but that penalises the fastpath. | |
cba3574f | 842 | */ |
cba3574f WD |
843 | } |
844 | ||
845 | #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) | |
846 | ||
7db743c6 CM |
847 | #define kc_vaddr_to_offset(v) ((v) & ~VA_START) |
848 | #define kc_offset_to_vaddr(o) ((o) | VA_START) | |
849 | ||
529c4b05 KM |
850 | #ifdef CONFIG_ARM64_PA_BITS_52 |
851 | #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) | |
852 | #else | |
853 | #define phys_to_ttbr(addr) (addr) | |
854 | #endif | |
855 | ||
4f04d8f0 CM |
856 | #endif /* !__ASSEMBLY__ */ |
857 | ||
858 | #endif /* __ASM_PGTABLE_H */ |