[mirror_ubuntu-bionic-kernel.git] / arch / arm64 / include / asm / sysreg.h

/*
 * Macros for accessing system registers with older binutils.
 *
 * Copyright (C) 2014 ARM Ltd.
 * Author: Catalin Marinas <catalin.marinas@arm.com>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __ASM_SYSREG_H
#define __ASM_SYSREG_H

#include <linux/stringify.h>

/*
 * ARMv8 ARM reserves the following encoding for system registers:
 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
 *  C5.2, version:ARM DDI 0487A.f)
 *	[20-19] : Op0
 *	[18-16] : Op1
 *	[15-12] : CRn
 *	[11-8]  : CRm
 *	[7-5]   : Op2
 */
#define Op0_shift	19
#define Op0_mask	0x3
#define Op1_shift	16
#define Op1_mask	0x7
#define CRn_shift	12
#define CRn_mask	0xf
#define CRm_shift	8
#define CRm_mask	0xf
#define Op2_shift	5
#define Op2_mask	0x7

#define sys_reg(op0, op1, crn, crm, op2) \
	(((op0) << Op0_shift) | ((op1) << Op1_shift) | \
	 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
	 ((op2) << Op2_shift))

#define sys_reg_Op0(id)	(((id) >> Op0_shift) & Op0_mask)
#define sys_reg_Op1(id)	(((id) >> Op1_shift) & Op1_mask)
#define sys_reg_CRn(id)	(((id) >> CRn_shift) & CRn_mask)
#define sys_reg_CRm(id)	(((id) >> CRm_shift) & CRm_mask)
#define sys_reg_Op2(id)	(((id) >> Op2_shift) & Op2_mask)

#ifndef CONFIG_BROKEN_GAS_INST

#ifdef __ASSEMBLY__
#define __emit_inst(x)			.inst (x)
#else
#define __emit_inst(x)			".inst " __stringify((x)) "\n\t"
#endif

#else  /* CONFIG_BROKEN_GAS_INST */

#ifndef CONFIG_CPU_BIG_ENDIAN
#define __INSTR_BSWAP(x)		(x)
#else  /* CONFIG_CPU_BIG_ENDIAN */
#define __INSTR_BSWAP(x)		((((x) << 24) & 0xff000000)	| \
					 (((x) <<  8) & 0x00ff0000)	| \
					 (((x) >>  8) & 0x0000ff00)	| \
					 (((x) >> 24) & 0x000000ff))
#endif	/* CONFIG_CPU_BIG_ENDIAN */

#ifdef __ASSEMBLY__
#define __emit_inst(x)			.long __INSTR_BSWAP(x)
#else  /* __ASSEMBLY__ */
#define __emit_inst(x)			".long " __stringify(__INSTR_BSWAP(x)) "\n\t"
#endif	/* __ASSEMBLY__ */

#endif	/* CONFIG_BROKEN_GAS_INST */

#define REG_PSTATE_PAN_IMM		sys_reg(0, 0, 4, 0, 4)
#define REG_PSTATE_UAO_IMM		sys_reg(0, 0, 4, 0, 3)

#define SET_PSTATE_PAN(x) __emit_inst(0xd5000000 | REG_PSTATE_PAN_IMM |	\
				      (!!x)<<8 | 0x1f)
#define SET_PSTATE_UAO(x) __emit_inst(0xd5000000 | REG_PSTATE_UAO_IMM |	\
				      (!!x)<<8 | 0x1f)

#define SYS_OSDTRRX_EL1			sys_reg(2, 0, 0, 0, 2)
#define SYS_MDCCINT_EL1			sys_reg(2, 0, 0, 2, 0)
#define SYS_MDSCR_EL1			sys_reg(2, 0, 0, 2, 2)
#define SYS_OSDTRTX_EL1			sys_reg(2, 0, 0, 3, 2)
#define SYS_OSECCR_EL1			sys_reg(2, 0, 0, 6, 2)
#define SYS_DBGBVRn_EL1(n)		sys_reg(2, 0, 0, n, 4)
#define SYS_DBGBCRn_EL1(n)		sys_reg(2, 0, 0, n, 5)
#define SYS_DBGWVRn_EL1(n)		sys_reg(2, 0, 0, n, 6)
#define SYS_DBGWCRn_EL1(n)		sys_reg(2, 0, 0, n, 7)
#define SYS_MDRAR_EL1			sys_reg(2, 0, 1, 0, 0)
#define SYS_OSLAR_EL1			sys_reg(2, 0, 1, 0, 4)
#define SYS_OSLSR_EL1			sys_reg(2, 0, 1, 1, 4)
#define SYS_OSDLR_EL1			sys_reg(2, 0, 1, 3, 4)
#define SYS_DBGPRCR_EL1			sys_reg(2, 0, 1, 4, 4)
#define SYS_DBGCLAIMSET_EL1		sys_reg(2, 0, 7, 8, 6)
#define SYS_DBGCLAIMCLR_EL1		sys_reg(2, 0, 7, 9, 6)
#define SYS_DBGAUTHSTATUS_EL1		sys_reg(2, 0, 7, 14, 6)
#define SYS_MDCCSR_EL0			sys_reg(2, 3, 0, 1, 0)
#define SYS_DBGDTR_EL0			sys_reg(2, 3, 0, 4, 0)
#define SYS_DBGDTRRX_EL0		sys_reg(2, 3, 0, 5, 0)
#define SYS_DBGDTRTX_EL0		sys_reg(2, 3, 0, 5, 0)
#define SYS_DBGVCR32_EL2		sys_reg(2, 4, 0, 7, 0)

#define SYS_MIDR_EL1			sys_reg(3, 0, 0, 0, 0)
#define SYS_MPIDR_EL1			sys_reg(3, 0, 0, 0, 5)
#define SYS_REVIDR_EL1			sys_reg(3, 0, 0, 0, 6)

#define SYS_ID_PFR0_EL1			sys_reg(3, 0, 0, 1, 0)
#define SYS_ID_PFR1_EL1			sys_reg(3, 0, 0, 1, 1)
#define SYS_ID_DFR0_EL1			sys_reg(3, 0, 0, 1, 2)
#define SYS_ID_AFR0_EL1			sys_reg(3, 0, 0, 1, 3)
#define SYS_ID_MMFR0_EL1		sys_reg(3, 0, 0, 1, 4)
#define SYS_ID_MMFR1_EL1		sys_reg(3, 0, 0, 1, 5)
#define SYS_ID_MMFR2_EL1		sys_reg(3, 0, 0, 1, 6)
#define SYS_ID_MMFR3_EL1		sys_reg(3, 0, 0, 1, 7)

#define SYS_ID_ISAR0_EL1		sys_reg(3, 0, 0, 2, 0)
#define SYS_ID_ISAR1_EL1		sys_reg(3, 0, 0, 2, 1)
#define SYS_ID_ISAR2_EL1		sys_reg(3, 0, 0, 2, 2)
#define SYS_ID_ISAR3_EL1		sys_reg(3, 0, 0, 2, 3)
#define SYS_ID_ISAR4_EL1		sys_reg(3, 0, 0, 2, 4)
#define SYS_ID_ISAR5_EL1		sys_reg(3, 0, 0, 2, 5)
#define SYS_ID_MMFR4_EL1		sys_reg(3, 0, 0, 2, 6)

#define SYS_MVFR0_EL1			sys_reg(3, 0, 0, 3, 0)
#define SYS_MVFR1_EL1			sys_reg(3, 0, 0, 3, 1)
#define SYS_MVFR2_EL1			sys_reg(3, 0, 0, 3, 2)

#define SYS_ID_AA64PFR0_EL1		sys_reg(3, 0, 0, 4, 0)
#define SYS_ID_AA64PFR1_EL1		sys_reg(3, 0, 0, 4, 1)

#define SYS_ID_AA64DFR0_EL1		sys_reg(3, 0, 0, 5, 0)
#define SYS_ID_AA64DFR1_EL1		sys_reg(3, 0, 0, 5, 1)

#define SYS_ID_AA64ISAR0_EL1		sys_reg(3, 0, 0, 6, 0)
#define SYS_ID_AA64ISAR1_EL1		sys_reg(3, 0, 0, 6, 1)

#define SYS_ID_AA64MMFR0_EL1		sys_reg(3, 0, 0, 7, 0)
#define SYS_ID_AA64MMFR1_EL1		sys_reg(3, 0, 0, 7, 1)
#define SYS_ID_AA64MMFR2_EL1		sys_reg(3, 0, 0, 7, 2)

#define SYS_SCTLR_EL1			sys_reg(3, 0, 1, 0, 0)
#define SYS_ACTLR_EL1			sys_reg(3, 0, 1, 0, 1)
#define SYS_CPACR_EL1			sys_reg(3, 0, 1, 0, 2)

#define SYS_TTBR0_EL1			sys_reg(3, 0, 2, 0, 0)
#define SYS_TTBR1_EL1			sys_reg(3, 0, 2, 0, 1)
#define SYS_TCR_EL1			sys_reg(3, 0, 2, 0, 2)

#define SYS_ICC_PMR_EL1			sys_reg(3, 0, 4, 6, 0)

#define SYS_AFSR0_EL1			sys_reg(3, 0, 5, 1, 0)
#define SYS_AFSR1_EL1			sys_reg(3, 0, 5, 1, 1)
#define SYS_ESR_EL1			sys_reg(3, 0, 5, 2, 0)
#define SYS_FAR_EL1			sys_reg(3, 0, 6, 0, 0)
#define SYS_PAR_EL1			sys_reg(3, 0, 7, 4, 0)

#define SYS_PMINTENSET_EL1		sys_reg(3, 0, 9, 14, 1)
#define SYS_PMINTENCLR_EL1		sys_reg(3, 0, 9, 14, 2)

#define SYS_MAIR_EL1			sys_reg(3, 0, 10, 2, 0)
#define SYS_AMAIR_EL1			sys_reg(3, 0, 10, 3, 0)

#define SYS_VBAR_EL1			sys_reg(3, 0, 12, 0, 0)

#define SYS_ICC_DIR_EL1			sys_reg(3, 0, 12, 11, 1)
#define SYS_ICC_SGI1R_EL1		sys_reg(3, 0, 12, 11, 5)
#define SYS_ICC_IAR1_EL1		sys_reg(3, 0, 12, 12, 0)
#define SYS_ICC_EOIR1_EL1		sys_reg(3, 0, 12, 12, 1)
#define SYS_ICC_BPR1_EL1		sys_reg(3, 0, 12, 12, 3)
#define SYS_ICC_CTLR_EL1		sys_reg(3, 0, 12, 12, 4)
#define SYS_ICC_SRE_EL1			sys_reg(3, 0, 12, 12, 5)
#define SYS_ICC_GRPEN1_EL1		sys_reg(3, 0, 12, 12, 7)

#define SYS_CONTEXTIDR_EL1		sys_reg(3, 0, 13, 0, 1)
#define SYS_TPIDR_EL1			sys_reg(3, 0, 13, 0, 4)

#define SYS_CNTKCTL_EL1			sys_reg(3, 0, 14, 1, 0)

#define SYS_CLIDR_EL1			sys_reg(3, 1, 0, 0, 1)
#define SYS_AIDR_EL1			sys_reg(3, 1, 0, 0, 7)

#define SYS_CSSELR_EL1			sys_reg(3, 2, 0, 0, 0)

#define SYS_CTR_EL0			sys_reg(3, 3, 0, 0, 1)
#define SYS_DCZID_EL0			sys_reg(3, 3, 0, 0, 7)

#define SYS_PMCR_EL0			sys_reg(3, 3, 9, 12, 0)
#define SYS_PMCNTENSET_EL0		sys_reg(3, 3, 9, 12, 1)
#define SYS_PMCNTENCLR_EL0		sys_reg(3, 3, 9, 12, 2)
#define SYS_PMOVSCLR_EL0		sys_reg(3, 3, 9, 12, 3)
#define SYS_PMSWINC_EL0			sys_reg(3, 3, 9, 12, 4)
#define SYS_PMSELR_EL0			sys_reg(3, 3, 9, 12, 5)
#define SYS_PMCEID0_EL0			sys_reg(3, 3, 9, 12, 6)
#define SYS_PMCEID1_EL0			sys_reg(3, 3, 9, 12, 7)
#define SYS_PMCCNTR_EL0			sys_reg(3, 3, 9, 13, 0)
#define SYS_PMXEVTYPER_EL0		sys_reg(3, 3, 9, 13, 1)
#define SYS_PMXEVCNTR_EL0		sys_reg(3, 3, 9, 13, 2)
#define SYS_PMUSERENR_EL0		sys_reg(3, 3, 9, 14, 0)
#define SYS_PMOVSSET_EL0		sys_reg(3, 3, 9, 14, 3)

#define SYS_TPIDR_EL0			sys_reg(3, 3, 13, 0, 2)
#define SYS_TPIDRRO_EL0			sys_reg(3, 3, 13, 0, 3)

#define SYS_CNTFRQ_EL0			sys_reg(3, 3, 14, 0, 0)

#define SYS_CNTP_TVAL_EL0		sys_reg(3, 3, 14, 2, 0)
#define SYS_CNTP_CTL_EL0		sys_reg(3, 3, 14, 2, 1)
#define SYS_CNTP_CVAL_EL0		sys_reg(3, 3, 14, 2, 2)

#define __PMEV_op2(n)			((n) & 0x7)
#define __CNTR_CRm(n)			(0x8 | (((n) >> 3) & 0x3))
#define SYS_PMEVCNTRn_EL0(n)		sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
#define __TYPER_CRm(n)			(0xc | (((n) >> 3) & 0x3))
#define SYS_PMEVTYPERn_EL0(n)		sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))

#define SYS_PMCCFILTR_EL0		sys_reg (3, 3, 14, 15, 7)

#define SYS_DACR32_EL2			sys_reg(3, 4, 3, 0, 0)
#define SYS_IFSR32_EL2			sys_reg(3, 4, 5, 0, 1)
#define SYS_FPEXC32_EL2			sys_reg(3, 4, 5, 3, 0)

#define __SYS__AP0Rx_EL2(x)		sys_reg(3, 4, 12, 8, x)
#define SYS_ICH_AP0R0_EL2		__SYS__AP0Rx_EL2(0)
#define SYS_ICH_AP0R1_EL2		__SYS__AP0Rx_EL2(1)
#define SYS_ICH_AP0R2_EL2		__SYS__AP0Rx_EL2(2)
#define SYS_ICH_AP0R3_EL2		__SYS__AP0Rx_EL2(3)

#define __SYS__AP1Rx_EL2(x)		sys_reg(3, 4, 12, 9, x)
#define SYS_ICH_AP1R0_EL2		__SYS__AP1Rx_EL2(0)
#define SYS_ICH_AP1R1_EL2		__SYS__AP1Rx_EL2(1)
#define SYS_ICH_AP1R2_EL2		__SYS__AP1Rx_EL2(2)
#define SYS_ICH_AP1R3_EL2		__SYS__AP1Rx_EL2(3)

#define SYS_ICH_VSEIR_EL2		sys_reg(3, 4, 12, 9, 4)
#define SYS_ICC_SRE_EL2			sys_reg(3, 4, 12, 9, 5)
#define SYS_ICH_HCR_EL2			sys_reg(3, 4, 12, 11, 0)
#define SYS_ICH_VTR_EL2			sys_reg(3, 4, 12, 11, 1)
#define SYS_ICH_MISR_EL2		sys_reg(3, 4, 12, 11, 2)
#define SYS_ICH_EISR_EL2		sys_reg(3, 4, 12, 11, 3)
#define SYS_ICH_ELSR_EL2		sys_reg(3, 4, 12, 11, 5)
#define SYS_ICH_VMCR_EL2		sys_reg(3, 4, 12, 11, 7)

#define __SYS__LR0_EL2(x)		sys_reg(3, 4, 12, 12, x)
#define SYS_ICH_LR0_EL2			__SYS__LR0_EL2(0)
#define SYS_ICH_LR1_EL2			__SYS__LR0_EL2(1)
#define SYS_ICH_LR2_EL2			__SYS__LR0_EL2(2)
#define SYS_ICH_LR3_EL2			__SYS__LR0_EL2(3)
#define SYS_ICH_LR4_EL2			__SYS__LR0_EL2(4)
#define SYS_ICH_LR5_EL2			__SYS__LR0_EL2(5)
#define SYS_ICH_LR6_EL2			__SYS__LR0_EL2(6)
#define SYS_ICH_LR7_EL2			__SYS__LR0_EL2(7)

#define __SYS__LR8_EL2(x)		sys_reg(3, 4, 12, 13, x)
#define SYS_ICH_LR8_EL2			__SYS__LR8_EL2(0)
#define SYS_ICH_LR9_EL2			__SYS__LR8_EL2(1)
#define SYS_ICH_LR10_EL2		__SYS__LR8_EL2(2)
#define SYS_ICH_LR11_EL2		__SYS__LR8_EL2(3)
#define SYS_ICH_LR12_EL2		__SYS__LR8_EL2(4)
#define SYS_ICH_LR13_EL2		__SYS__LR8_EL2(5)
#define SYS_ICH_LR14_EL2		__SYS__LR8_EL2(6)
#define SYS_ICH_LR15_EL2		__SYS__LR8_EL2(7)

/* Common SCTLR_ELx flags. */
#define SCTLR_ELx_EE    (1 << 25)
#define SCTLR_ELx_I	(1 << 12)
#define SCTLR_ELx_SA	(1 << 3)
#define SCTLR_ELx_C	(1 << 2)
#define SCTLR_ELx_A	(1 << 1)
#define SCTLR_ELx_M	1

#define SCTLR_ELx_FLAGS	(SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \
			 SCTLR_ELx_SA | SCTLR_ELx_I)

/* SCTLR_EL1 specific flags. */
#define SCTLR_EL1_UCI		(1 << 26)
#define SCTLR_EL1_SPAN		(1 << 23)
#define SCTLR_EL1_UCT		(1 << 15)
#define SCTLR_EL1_SED		(1 << 8)
#define SCTLR_EL1_CP15BEN	(1 << 5)

/* id_aa64isar0 */
#define ID_AA64ISAR0_RDM_SHIFT		28
#define ID_AA64ISAR0_ATOMICS_SHIFT	20
#define ID_AA64ISAR0_CRC32_SHIFT	16
#define ID_AA64ISAR0_SHA2_SHIFT		12
#define ID_AA64ISAR0_SHA1_SHIFT		8
#define ID_AA64ISAR0_AES_SHIFT		4

/* id_aa64pfr0 */
#define ID_AA64PFR0_GIC_SHIFT		24
#define ID_AA64PFR0_ASIMD_SHIFT		20
#define ID_AA64PFR0_FP_SHIFT		16
#define ID_AA64PFR0_EL3_SHIFT		12
#define ID_AA64PFR0_EL2_SHIFT		8
#define ID_AA64PFR0_EL1_SHIFT		4
#define ID_AA64PFR0_EL0_SHIFT		0

#define ID_AA64PFR0_FP_NI		0xf
#define ID_AA64PFR0_FP_SUPPORTED	0x0
#define ID_AA64PFR0_ASIMD_NI		0xf
#define ID_AA64PFR0_ASIMD_SUPPORTED	0x0
#define ID_AA64PFR0_EL1_64BIT_ONLY	0x1
#define ID_AA64PFR0_EL0_64BIT_ONLY	0x1
#define ID_AA64PFR0_EL0_32BIT_64BIT	0x2

/* id_aa64mmfr0 */
#define ID_AA64MMFR0_TGRAN4_SHIFT	28
#define ID_AA64MMFR0_TGRAN64_SHIFT	24
#define ID_AA64MMFR0_TGRAN16_SHIFT	20
#define ID_AA64MMFR0_BIGENDEL0_SHIFT	16
#define ID_AA64MMFR0_SNSMEM_SHIFT	12
#define ID_AA64MMFR0_BIGENDEL_SHIFT	8
#define ID_AA64MMFR0_ASID_SHIFT		4
#define ID_AA64MMFR0_PARANGE_SHIFT	0

#define ID_AA64MMFR0_TGRAN4_NI		0xf
#define ID_AA64MMFR0_TGRAN4_SUPPORTED	0x0
#define ID_AA64MMFR0_TGRAN64_NI		0xf
#define ID_AA64MMFR0_TGRAN64_SUPPORTED	0x0
#define ID_AA64MMFR0_TGRAN16_NI		0x0
#define ID_AA64MMFR0_TGRAN16_SUPPORTED	0x1

/* id_aa64mmfr1 */
#define ID_AA64MMFR1_PAN_SHIFT		20
#define ID_AA64MMFR1_LOR_SHIFT		16
#define ID_AA64MMFR1_HPD_SHIFT		12
#define ID_AA64MMFR1_VHE_SHIFT		8
#define ID_AA64MMFR1_VMIDBITS_SHIFT	4
#define ID_AA64MMFR1_HADBS_SHIFT	0

#define ID_AA64MMFR1_VMIDBITS_8		0
#define ID_AA64MMFR1_VMIDBITS_16	2

/* id_aa64mmfr2 */
#define ID_AA64MMFR2_LVA_SHIFT		16
#define ID_AA64MMFR2_IESB_SHIFT		12
#define ID_AA64MMFR2_LSM_SHIFT		8
#define ID_AA64MMFR2_UAO_SHIFT		4
#define ID_AA64MMFR2_CNP_SHIFT		0

/* id_aa64dfr0 */
#define ID_AA64DFR0_PMSVER_SHIFT	32
#define ID_AA64DFR0_CTX_CMPS_SHIFT	28
#define ID_AA64DFR0_WRPS_SHIFT		20
#define ID_AA64DFR0_BRPS_SHIFT		12
#define ID_AA64DFR0_PMUVER_SHIFT	8
#define ID_AA64DFR0_TRACEVER_SHIFT	4
#define ID_AA64DFR0_DEBUGVER_SHIFT	0

#define ID_ISAR5_RDM_SHIFT		24
#define ID_ISAR5_CRC32_SHIFT		16
#define ID_ISAR5_SHA2_SHIFT		12
#define ID_ISAR5_SHA1_SHIFT		8
#define ID_ISAR5_AES_SHIFT		4
#define ID_ISAR5_SEVL_SHIFT		0

#define MVFR0_FPROUND_SHIFT		28
#define MVFR0_FPSHVEC_SHIFT		24
#define MVFR0_FPSQRT_SHIFT		20
#define MVFR0_FPDIVIDE_SHIFT		16
#define MVFR0_FPTRAP_SHIFT		12
#define MVFR0_FPDP_SHIFT		8
#define MVFR0_FPSP_SHIFT		4
#define MVFR0_SIMD_SHIFT		0

#define MVFR1_SIMDFMAC_SHIFT		28
#define MVFR1_FPHP_SHIFT		24
#define MVFR1_SIMDHP_SHIFT		20
#define MVFR1_SIMDSP_SHIFT		16
#define MVFR1_SIMDINT_SHIFT		12
#define MVFR1_SIMDLS_SHIFT		8
#define MVFR1_FPDNAN_SHIFT		4
#define MVFR1_FPFTZ_SHIFT		0


#define ID_AA64MMFR0_TGRAN4_SHIFT	28
#define ID_AA64MMFR0_TGRAN64_SHIFT	24
#define ID_AA64MMFR0_TGRAN16_SHIFT	20

#define ID_AA64MMFR0_TGRAN4_NI		0xf
#define ID_AA64MMFR0_TGRAN4_SUPPORTED	0x0
#define ID_AA64MMFR0_TGRAN64_NI		0xf
#define ID_AA64MMFR0_TGRAN64_SUPPORTED	0x0
#define ID_AA64MMFR0_TGRAN16_NI		0x0
#define ID_AA64MMFR0_TGRAN16_SUPPORTED	0x1

#if defined(CONFIG_ARM64_4K_PAGES)
#define ID_AA64MMFR0_TGRAN_SHIFT	ID_AA64MMFR0_TGRAN4_SHIFT
#define ID_AA64MMFR0_TGRAN_SUPPORTED	ID_AA64MMFR0_TGRAN4_SUPPORTED
#elif defined(CONFIG_ARM64_16K_PAGES)
#define ID_AA64MMFR0_TGRAN_SHIFT	ID_AA64MMFR0_TGRAN16_SHIFT
#define ID_AA64MMFR0_TGRAN_SUPPORTED	ID_AA64MMFR0_TGRAN16_SUPPORTED
#elif defined(CONFIG_ARM64_64K_PAGES)
#define ID_AA64MMFR0_TGRAN_SHIFT	ID_AA64MMFR0_TGRAN64_SHIFT
#define ID_AA64MMFR0_TGRAN_SUPPORTED	ID_AA64MMFR0_TGRAN64_SUPPORTED
#endif


/* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
#define SYS_MPIDR_SAFE_VAL		(1UL << 31)

#ifdef __ASSEMBLY__

	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
	.equ	.L__reg_num_x\num, \num
	.endr
	.equ	.L__reg_num_xzr, 31

	.macro	mrs_s, rt, sreg
	 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt))
	.endm

	.macro	msr_s, sreg, rt
	__emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt))
	.endm

#else

#include <linux/types.h>

asm(
"	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
"	.equ	.L__reg_num_x\\num, \\num\n"
"	.endr\n"
"	.equ	.L__reg_num_xzr, 31\n"
"\n"
"	.macro	mrs_s, rt, sreg\n"
	__emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt))
"	.endm\n"
"\n"
"	.macro	msr_s, sreg, rt\n"
	__emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt))
"	.endm\n"
);

/*
 * Unlike read_cpuid, calls to read_sysreg are never expected to be
 * optimized away or replaced with synthetic values.
 */
#define read_sysreg(r) ({					\
	u64 __val;						\
	asm volatile("mrs %0, " __stringify(r) : "=r" (__val));	\
	__val;							\
})

/*
 * The "Z" constraint normally means a zero immediate, but when combined with
 * the "%x0" template means XZR.
 */
#define write_sysreg(v, r) do {					\
	u64 __val = (u64)v;					\
	asm volatile("msr " __stringify(r) ", %x0"		\
		     : : "rZ" (__val));				\
} while (0)

/*
 * For registers without architectural names, or simply unsupported by
 * GAS.
 */
#define read_sysreg_s(r) ({						\
	u64 __val;							\
	asm volatile("mrs_s %0, " __stringify(r) : "=r" (__val));	\
	__val;								\
})

#define write_sysreg_s(v, r) do {					\
	u64 __val = (u64)v;						\
	asm volatile("msr_s " __stringify(r) ", %x0" : : "rZ" (__val));	\
} while (0)

static inline void config_sctlr_el1(u32 clear, u32 set)
{
	u32 val;

	val = read_sysreg(sctlr_el1);
	val &= ~clear;
	val |= set;
	write_sysreg(val, sctlr_el1);
}

#endif

#endif	/* __ASM_SYSREG_H */
Commit	Line	Data
72c58395 CM	1	/*
	2	* Macros for accessing system registers with older binutils.
	3	*
	4	* Copyright (C) 2014 ARM Ltd.
	5	* Author: Catalin Marinas <catalin.marinas@arm.com>
	6	*
	7	* This program is free software: you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#ifndef __ASM_SYSREG_H
	21	#define __ASM_SYSREG_H
	22
3600c2fd MR	23	#include <linux/stringify.h>
3600c2fd MR	24
9ded63aa SP	25	/*
	26	* ARMv8 ARM reserves the following encoding for system registers:
	27	* (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
	28	* C5.2, version:ARM DDI 0487A.f)
	29	* [20-19] : Op0
	30	* [18-16] : Op1
	31	* [15-12] : CRn
	32	* [11-8] : CRm
	33	* [7-5] : Op2
	34	*/
c9ee0f98 SP	35	#define Op0_shift 19
	36	#define Op0_mask 0x3
	37	#define Op1_shift 16
	38	#define Op1_mask 0x7
	39	#define CRn_shift 12
	40	#define CRn_mask 0xf
	41	#define CRm_shift 8
	42	#define CRm_mask 0xf
	43	#define Op2_shift 5
	44	#define Op2_mask 0x7
	45
72c58395	46	#define sys_reg(op0, op1, crn, crm, op2) \
c9ee0f98 SP	47	(((op0) << Op0_shift) \| ((op1) << Op1_shift) \| \
	48	((crn) << CRn_shift) \| ((crm) << CRm_shift) \| \
	49	((op2) << Op2_shift))
	50
	51	#define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask)
	52	#define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask)
	53	#define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask)
	54	#define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask)
	55	#define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask)
72c58395	56
cd9e1927 MZ	57	#ifndef CONFIG_BROKEN_GAS_INST
cd9e1927 MZ	58
bca8f17f MZ	59	#ifdef __ASSEMBLY__
	60	#define __emit_inst(x) .inst (x)
	61	#else
	62	#define __emit_inst(x) ".inst " __stringify((x)) "\n\t"
	63	#endif
	64
cd9e1927 MZ	65	#else /* CONFIG_BROKEN_GAS_INST */
	66
	67	#ifndef CONFIG_CPU_BIG_ENDIAN
	68	#define __INSTR_BSWAP(x) (x)
	69	#else /* CONFIG_CPU_BIG_ENDIAN */
	70	#define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) \| \
	71	(((x) << 8) & 0x00ff0000) \| \
	72	(((x) >> 8) & 0x0000ff00) \| \
	73	(((x) >> 24) & 0x000000ff))
	74	#endif /* CONFIG_CPU_BIG_ENDIAN */
	75
	76	#ifdef __ASSEMBLY__
	77	#define __emit_inst(x) .long __INSTR_BSWAP(x)
	78	#else /* __ASSEMBLY__ */
	79	#define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t"
	80	#endif /* __ASSEMBLY__ */
	81
	82	#endif /* CONFIG_BROKEN_GAS_INST */
	83
47863d41 MR	84	#define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4)
	85	#define REG_PSTATE_UAO_IMM sys_reg(0, 0, 4, 0, 3)
	86
	87	#define SET_PSTATE_PAN(x) __emit_inst(0xd5000000 \| REG_PSTATE_PAN_IMM \| \
	88	(!!x)<<8 \| 0x1f)
	89	#define SET_PSTATE_UAO(x) __emit_inst(0xd5000000 \| REG_PSTATE_UAO_IMM \| \
	90	(!!x)<<8 \| 0x1f)
	91
d9801207 MR	92	#define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2)
	93	#define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0)
	94	#define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2)
	95	#define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2)
	96	#define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2)
	97	#define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
	98	#define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
	99	#define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6)
	100	#define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
	101	#define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0)
	102	#define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4)
	103	#define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4)
	104	#define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
	105	#define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4)
	106	#define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
	107	#define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
	108	#define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
	109	#define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
	110	#define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
	111	#define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
	112	#define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
	113	#define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
	114
3c739b57 SP	115	#define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
	116	#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
	117	#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
	118
	119	#define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0)
	120	#define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1)
	121	#define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
14ae7518	122	#define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
3c739b57 SP	123	#define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4)
	124	#define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5)
	125	#define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6)
	126	#define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7)
	127
	128	#define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0)
	129	#define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1)
	130	#define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2)
	131	#define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3)
	132	#define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4)
	133	#define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5)
	134	#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6)
	135
	136	#define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)
	137	#define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1)
	138	#define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2)
	139
	140	#define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0)
	141	#define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1)
	142
	143	#define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0)
	144	#define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1)
	145
	146	#define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0)
	147	#define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1)
	148
	149	#define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0)
	150	#define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
406e3087	151	#define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
3c739b57	152
14ae7518 MR	153	#define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0)
	154	#define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
	155	#define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2)
	156
	157	#define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0)
	158	#define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1)
	159	#define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
	160
0e9884fe MR	161	#define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
0e9884fe MR	162
14ae7518 MR	163	#define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
	164	#define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
	165	#define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
	166	#define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0)
	167	#define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
	168
c7a3c61f MR	169	#define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
	170	#define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
	171
14ae7518 MR	172	#define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
	173	#define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
	174
	175	#define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
	176
0e9884fe MR	177	#define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
	178	#define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
	179	#define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
	180	#define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
	181	#define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
	182	#define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
	183	#define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
	184	#define SYS_ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
	185
14ae7518 MR	186	#define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1)
	187	#define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4)
	188
	189	#define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
	190
	191	#define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1)
	192	#define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
	193
	194	#define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0)
	195
3c739b57 SP	196	#define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
	197	#define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
	198
c7a3c61f MR	199	#define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
	200	#define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
	201	#define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
	202	#define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
	203	#define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
	204	#define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
	205	#define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
	206	#define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
	207	#define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
	208	#define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
	209	#define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
	210	#define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
	211	#define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
	212
14ae7518 MR	213	#define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
	214	#define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3)
	215
47863d41	216	#define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
338d4f49	217
147a70ce MR	218	#define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
	219	#define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
	220	#define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
	221
c7a3c61f MR	222	#define __PMEV_op2(n) ((n) & 0x7)
	223	#define __CNTR_CRm(n) (0x8 \| (((n) >> 3) & 0x3))
	224	#define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
	225	#define __TYPER_CRm(n) (0xc \| (((n) >> 3) & 0x3))
	226	#define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
	227
	228	#define SYS_PMCCFILTR_EL0 sys_reg (3, 3, 14, 15, 7)
	229
14ae7518 MR	230	#define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0)
	231	#define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
	232	#define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
	233
0e9884fe MR	234	#define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
	235	#define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0)
	236	#define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1)
	237	#define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2)
	238	#define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3)
	239
	240	#define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
	241	#define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0)
	242	#define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1)
	243	#define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2)
	244	#define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3)
	245
	246	#define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
	247	#define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
	248	#define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
	249	#define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
	250	#define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
	251	#define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
	252	#define SYS_ICH_ELSR_EL2 sys_reg(3, 4, 12, 11, 5)
	253	#define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
	254
	255	#define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
	256	#define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0)
	257	#define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1)
	258	#define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2)
	259	#define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3)
	260	#define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4)
	261	#define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5)
	262	#define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6)
	263	#define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7)
	264
	265	#define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
	266	#define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0)
	267	#define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1)
	268	#define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2)
	269	#define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3)
	270	#define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4)
	271	#define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5)
	272	#define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6)
	273	#define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7)
	274
e7227d0e GL	275	/* Common SCTLR_ELx flags. */
	276	#define SCTLR_ELx_EE (1 << 25)
	277	#define SCTLR_ELx_I (1 << 12)
	278	#define SCTLR_ELx_SA (1 << 3)
	279	#define SCTLR_ELx_C (1 << 2)
	280	#define SCTLR_ELx_A (1 << 1)
	281	#define SCTLR_ELx_M 1
	282
	283	#define SCTLR_ELx_FLAGS (SCTLR_ELx_M \| SCTLR_ELx_A \| SCTLR_ELx_C \| \
	284	SCTLR_ELx_SA \| SCTLR_ELx_I)
	285
	286	/* SCTLR_EL1 specific flags. */
7dd01aef	287	#define SCTLR_EL1_UCI (1 << 26)
e7227d0e	288	#define SCTLR_EL1_SPAN (1 << 23)
116c81f4	289	#define SCTLR_EL1_UCT (1 << 15)
e7227d0e GL	290	#define SCTLR_EL1_SED (1 << 8)
e7227d0e GL	291	#define SCTLR_EL1_CP15BEN (1 << 5)
3c739b57	292
3c739b57 SP	293	/* id_aa64isar0 */
	294	#define ID_AA64ISAR0_RDM_SHIFT 28
	295	#define ID_AA64ISAR0_ATOMICS_SHIFT 20
	296	#define ID_AA64ISAR0_CRC32_SHIFT 16
	297	#define ID_AA64ISAR0_SHA2_SHIFT 12
	298	#define ID_AA64ISAR0_SHA1_SHIFT 8
	299	#define ID_AA64ISAR0_AES_SHIFT 4
	300
	301	/* id_aa64pfr0 */
	302	#define ID_AA64PFR0_GIC_SHIFT 24
	303	#define ID_AA64PFR0_ASIMD_SHIFT 20
	304	#define ID_AA64PFR0_FP_SHIFT 16
	305	#define ID_AA64PFR0_EL3_SHIFT 12
	306	#define ID_AA64PFR0_EL2_SHIFT 8
	307	#define ID_AA64PFR0_EL1_SHIFT 4
	308	#define ID_AA64PFR0_EL0_SHIFT 0
	309
	310	#define ID_AA64PFR0_FP_NI 0xf
	311	#define ID_AA64PFR0_FP_SUPPORTED 0x0
	312	#define ID_AA64PFR0_ASIMD_NI 0xf
	313	#define ID_AA64PFR0_ASIMD_SUPPORTED 0x0
	314	#define ID_AA64PFR0_EL1_64BIT_ONLY 0x1
	315	#define ID_AA64PFR0_EL0_64BIT_ONLY 0x1
c80aba80	316	#define ID_AA64PFR0_EL0_32BIT_64BIT 0x2
3c739b57 SP	317
	318	/* id_aa64mmfr0 */
	319	#define ID_AA64MMFR0_TGRAN4_SHIFT 28
	320	#define ID_AA64MMFR0_TGRAN64_SHIFT 24
	321	#define ID_AA64MMFR0_TGRAN16_SHIFT 20
cdcf817b	322	#define ID_AA64MMFR0_BIGENDEL0_SHIFT 16
3c739b57	323	#define ID_AA64MMFR0_SNSMEM_SHIFT 12
cdcf817b	324	#define ID_AA64MMFR0_BIGENDEL_SHIFT 8
3c739b57 SP	325	#define ID_AA64MMFR0_ASID_SHIFT 4
	326	#define ID_AA64MMFR0_PARANGE_SHIFT 0
	327
	328	#define ID_AA64MMFR0_TGRAN4_NI 0xf
	329	#define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
	330	#define ID_AA64MMFR0_TGRAN64_NI 0xf
	331	#define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
	332	#define ID_AA64MMFR0_TGRAN16_NI 0x0
	333	#define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
	334
	335	/* id_aa64mmfr1 */
	336	#define ID_AA64MMFR1_PAN_SHIFT 20
	337	#define ID_AA64MMFR1_LOR_SHIFT 16
	338	#define ID_AA64MMFR1_HPD_SHIFT 12
	339	#define ID_AA64MMFR1_VHE_SHIFT 8
	340	#define ID_AA64MMFR1_VMIDBITS_SHIFT 4
	341	#define ID_AA64MMFR1_HADBS_SHIFT 0
	342
cb678d60 SP	343	#define ID_AA64MMFR1_VMIDBITS_8 0
	344	#define ID_AA64MMFR1_VMIDBITS_16 2
	345
406e3087	346	/* id_aa64mmfr2 */
7d7b4ae4 KW	347	#define ID_AA64MMFR2_LVA_SHIFT 16
	348	#define ID_AA64MMFR2_IESB_SHIFT 12
	349	#define ID_AA64MMFR2_LSM_SHIFT 8
406e3087	350	#define ID_AA64MMFR2_UAO_SHIFT 4
7d7b4ae4	351	#define ID_AA64MMFR2_CNP_SHIFT 0
406e3087	352
3c739b57	353	/* id_aa64dfr0 */
f31deaad	354	#define ID_AA64DFR0_PMSVER_SHIFT 32
3c739b57 SP	355	#define ID_AA64DFR0_CTX_CMPS_SHIFT 28
	356	#define ID_AA64DFR0_WRPS_SHIFT 20
	357	#define ID_AA64DFR0_BRPS_SHIFT 12
	358	#define ID_AA64DFR0_PMUVER_SHIFT 8
	359	#define ID_AA64DFR0_TRACEVER_SHIFT 4
	360	#define ID_AA64DFR0_DEBUGVER_SHIFT 0
	361
	362	#define ID_ISAR5_RDM_SHIFT 24
	363	#define ID_ISAR5_CRC32_SHIFT 16
	364	#define ID_ISAR5_SHA2_SHIFT 12
	365	#define ID_ISAR5_SHA1_SHIFT 8
	366	#define ID_ISAR5_AES_SHIFT 4
	367	#define ID_ISAR5_SEVL_SHIFT 0
	368
	369	#define MVFR0_FPROUND_SHIFT 28
	370	#define MVFR0_FPSHVEC_SHIFT 24
	371	#define MVFR0_FPSQRT_SHIFT 20
	372	#define MVFR0_FPDIVIDE_SHIFT 16
	373	#define MVFR0_FPTRAP_SHIFT 12
	374	#define MVFR0_FPDP_SHIFT 8
	375	#define MVFR0_FPSP_SHIFT 4
	376	#define MVFR0_SIMD_SHIFT 0
	377
	378	#define MVFR1_SIMDFMAC_SHIFT 28
	379	#define MVFR1_FPHP_SHIFT 24
	380	#define MVFR1_SIMDHP_SHIFT 20
	381	#define MVFR1_SIMDSP_SHIFT 16
	382	#define MVFR1_SIMDINT_SHIFT 12
	383	#define MVFR1_SIMDLS_SHIFT 8
	384	#define MVFR1_FPDNAN_SHIFT 4
	385	#define MVFR1_FPFTZ_SHIFT 0
	386
4bf8b96e SP	387
	388	#define ID_AA64MMFR0_TGRAN4_SHIFT 28
	389	#define ID_AA64MMFR0_TGRAN64_SHIFT 24
	390	#define ID_AA64MMFR0_TGRAN16_SHIFT 20
	391
	392	#define ID_AA64MMFR0_TGRAN4_NI 0xf
	393	#define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
	394	#define ID_AA64MMFR0_TGRAN64_NI 0xf
	395	#define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
	396	#define ID_AA64MMFR0_TGRAN16_NI 0x0
	397	#define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
	398
	399	#if defined(CONFIG_ARM64_4K_PAGES)
	400	#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT
	401	#define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED
44eaacf1 SP	402	#elif defined(CONFIG_ARM64_16K_PAGES)
	403	#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT
	404	#define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED
4bf8b96e SP	405	#elif defined(CONFIG_ARM64_64K_PAGES)
	406	#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT
	407	#define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED
	408	#endif
	409
77c97b4e SP	410
	411	/* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
	412	#define SYS_MPIDR_SAFE_VAL (1UL << 31)
	413
72c58395 CM	414	#ifdef __ASSEMBLY__
	415
	416	.irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
7abc7d83	417	.equ .L__reg_num_x\num, \num
72c58395	418	.endr
7abc7d83	419	.equ .L__reg_num_xzr, 31
72c58395 CM	420
72c58395 CM	421	.macro mrs_s, rt, sreg
cd9e1927	422	__emit_inst(0xd5200000\|(\sreg)\|(.L__reg_num_\rt))
72c58395 CM	423	.endm
	424
	425	.macro msr_s, sreg, rt
cd9e1927	426	__emit_inst(0xd5000000\|(\sreg)\|(.L__reg_num_\rt))
72c58395 CM	427	.endm
	428
	429	#else
	430
3600c2fd MR	431	#include <linux/types.h>
3600c2fd MR	432
72c58395 CM	433	asm(
72c58395 CM	434	" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
7abc7d83	435	" .equ .L__reg_num_x\\num, \\num\n"
72c58395	436	" .endr\n"
7abc7d83	437	" .equ .L__reg_num_xzr, 31\n"
72c58395 CM	438	"\n"
72c58395 CM	439	" .macro mrs_s, rt, sreg\n"
cd9e1927	440	__emit_inst(0xd5200000\|(\\sreg)\|(.L__reg_num_\\rt))
72c58395 CM	441	" .endm\n"
	442	"\n"
	443	" .macro msr_s, sreg, rt\n"
cd9e1927	444	__emit_inst(0xd5000000\|(\\sreg)\|(.L__reg_num_\\rt))
72c58395 CM	445	" .endm\n"
	446	);
	447
3600c2fd MR	448	/*
	449	* Unlike read_cpuid, calls to read_sysreg are never expected to be
	450	* optimized away or replaced with synthetic values.
	451	*/
	452	#define read_sysreg(r) ({ \
	453	u64 __val; \
	454	asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \
	455	__val; \
	456	})
	457
7aff4a2d MR	458	/*
	459	* The "Z" constraint normally means a zero immediate, but when combined with
	460	* the "%x0" template means XZR.
	461	*/
3600c2fd MR	462	#define write_sysreg(v, r) do { \
3600c2fd MR	463	u64 __val = (u64)v; \
7aff4a2d MR	464	asm volatile("msr " __stringify(r) ", %x0" \
7aff4a2d MR	465	: : "rZ" (__val)); \
3600c2fd MR	466	} while (0)
3600c2fd MR	467
8a71f0c6 WD	468	/*
	469	* For registers without architectural names, or simply unsupported by
	470	* GAS.
	471	*/
	472	#define read_sysreg_s(r) ({ \
	473	u64 __val; \
	474	asm volatile("mrs_s %0, " __stringify(r) : "=r" (__val)); \
	475	__val; \
	476	})
	477
	478	#define write_sysreg_s(v, r) do { \
	479	u64 __val = (u64)v; \
91cb163e	480	asm volatile("msr_s " __stringify(r) ", %x0" : : "rZ" (__val)); \
8a71f0c6 WD	481	} while (0)
8a71f0c6 WD	482
adf75899 MR	483	static inline void config_sctlr_el1(u32 clear, u32 set)
	484	{
	485	u32 val;
	486
	487	val = read_sysreg(sctlr_el1);
	488	val &= ~clear;
	489	val \|= set;
	490	write_sysreg(val, sctlr_el1);
	491	}
	492
72c58395 CM	493	#endif
	494
	495	#endif /* __ASM_SYSREG_H */