[mirror_ubuntu-jammy-kernel.git] / arch / arm64 / include / uapi / asm / kvm.h

/*
 * Copyright (C) 2012,2013 - ARM Ltd
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 * Derived from arch/arm/include/uapi/asm/kvm.h:
 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __ARM_KVM_H__
#define __ARM_KVM_H__

#define KVM_SPSR_EL1	0
#define KVM_NR_SPSR	1

#ifndef __ASSEMBLY__
#include <asm/types.h>
#include <asm/ptrace.h>

#define __KVM_HAVE_GUEST_DEBUG
#define __KVM_HAVE_IRQ_LINE

#define KVM_REG_SIZE(id)						\
	(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))

struct kvm_regs {
	struct user_pt_regs regs;	/* sp = sp_el0 */

	__u64	sp_el1;
	__u64	elr_el1;

	__u64	spsr[KVM_NR_SPSR];

	struct user_fpsimd_state fp_regs;
};

/* Supported Processor Types */
#define KVM_ARM_TARGET_AEM_V8		0
#define KVM_ARM_TARGET_FOUNDATION_V8	1
#define KVM_ARM_TARGET_CORTEX_A57	2

#define KVM_ARM_NUM_TARGETS		3

/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
#define KVM_ARM_DEVICE_TYPE_SHIFT	0
#define KVM_ARM_DEVICE_TYPE_MASK	(0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
#define KVM_ARM_DEVICE_ID_SHIFT		16
#define KVM_ARM_DEVICE_ID_MASK		(0xffff << KVM_ARM_DEVICE_ID_SHIFT)

/* Supported device IDs */
#define KVM_ARM_DEVICE_VGIC_V2		0

/* Supported VGIC address types  */
#define KVM_VGIC_V2_ADDR_TYPE_DIST	0
#define KVM_VGIC_V2_ADDR_TYPE_CPU	1

#define KVM_VGIC_V2_DIST_SIZE		0x1000
#define KVM_VGIC_V2_CPU_SIZE		0x2000

struct kvm_vcpu_init {
	__u32 target;
	__u32 features[7];
};

struct kvm_sregs {
};

struct kvm_fpu {
};

struct kvm_guest_debug_arch {
};

struct kvm_debug_exit_arch {
};

struct kvm_sync_regs {
};

struct kvm_arch_memory_slot {
};

/* If you need to interpret the index values, here is the key: */
#define KVM_REG_ARM_COPROC_MASK		0x000000000FFF0000
#define KVM_REG_ARM_COPROC_SHIFT	16

/* Normal registers are mapped as coprocessor 16. */
#define KVM_REG_ARM_CORE		(0x0010 << KVM_REG_ARM_COPROC_SHIFT)
#define KVM_REG_ARM_CORE_REG(name)	(offsetof(struct kvm_regs, name) / sizeof(__u32))

/* Some registers need more space to represent values. */
#define KVM_REG_ARM_DEMUX		(0x0011 << KVM_REG_ARM_COPROC_SHIFT)
#define KVM_REG_ARM_DEMUX_ID_MASK	0x000000000000FF00
#define KVM_REG_ARM_DEMUX_ID_SHIFT	8
#define KVM_REG_ARM_DEMUX_ID_CCSIDR	(0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
#define KVM_REG_ARM_DEMUX_VAL_MASK	0x00000000000000FF
#define KVM_REG_ARM_DEMUX_VAL_SHIFT	0

/* AArch64 system registers */
#define KVM_REG_ARM64_SYSREG		(0x0013 << KVM_REG_ARM_COPROC_SHIFT)
#define KVM_REG_ARM64_SYSREG_OP0_MASK	0x000000000000c000
#define KVM_REG_ARM64_SYSREG_OP0_SHIFT	14
#define KVM_REG_ARM64_SYSREG_OP1_MASK	0x0000000000003800
#define KVM_REG_ARM64_SYSREG_OP1_SHIFT	11
#define KVM_REG_ARM64_SYSREG_CRN_MASK	0x0000000000000780
#define KVM_REG_ARM64_SYSREG_CRN_SHIFT	7
#define KVM_REG_ARM64_SYSREG_CRM_MASK	0x0000000000000078
#define KVM_REG_ARM64_SYSREG_CRM_SHIFT	3
#define KVM_REG_ARM64_SYSREG_OP2_MASK	0x0000000000000007
#define KVM_REG_ARM64_SYSREG_OP2_SHIFT	0

/* KVM_IRQ_LINE irq field index values */
#define KVM_ARM_IRQ_TYPE_SHIFT		24
#define KVM_ARM_IRQ_TYPE_MASK		0xff
#define KVM_ARM_IRQ_VCPU_SHIFT		16
#define KVM_ARM_IRQ_VCPU_MASK		0xff
#define KVM_ARM_IRQ_NUM_SHIFT		0
#define KVM_ARM_IRQ_NUM_MASK		0xffff

/* irq_type field */
#define KVM_ARM_IRQ_TYPE_CPU		0
#define KVM_ARM_IRQ_TYPE_SPI		1
#define KVM_ARM_IRQ_TYPE_PPI		2

/* out-of-kernel GIC cpu interrupt injection irq_number field */
#define KVM_ARM_IRQ_CPU_IRQ		0
#define KVM_ARM_IRQ_CPU_FIQ		1

/* Highest supported SPI, from VGIC_NR_IRQS */
#define KVM_ARM_IRQ_GIC_MAX		127

#endif

#endif /* __ARM_KVM_H__ */
Commit	Line	Data
54f81d0e MZ	1	/*
	2	* Copyright (C) 2012,2013 - ARM Ltd
	3	* Author: Marc Zyngier <marc.zyngier@arm.com>
	4	*
	5	* Derived from arch/arm/include/uapi/asm/kvm.h:
	6	* Copyright (C) 2012 - Virtual Open Systems and Columbia University
	7	* Author: Christoffer Dall <c.dall@virtualopensystems.com>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	20	*/
	21
	22	#ifndef __ARM_KVM_H__
	23	#define __ARM_KVM_H__
	24
	25	#define KVM_SPSR_EL1 0
	26	#define KVM_NR_SPSR 1
	27
	28	#ifndef __ASSEMBLY__
	29	#include <asm/types.h>
	30	#include <asm/ptrace.h>
	31
	32	#define __KVM_HAVE_GUEST_DEBUG
	33	#define __KVM_HAVE_IRQ_LINE
	34
	35	#define KVM_REG_SIZE(id) \
	36	(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
	37
	38	struct kvm_regs {
	39	struct user_pt_regs regs; /* sp = sp_el0 */
	40
	41	__u64 sp_el1;
	42	__u64 elr_el1;
	43
	44	__u64 spsr[KVM_NR_SPSR];
	45
	46	struct user_fpsimd_state fp_regs;
	47	};
	48
	49	/* Supported Processor Types */
	50	#define KVM_ARM_TARGET_AEM_V8 0
	51	#define KVM_ARM_TARGET_FOUNDATION_V8 1
	52	#define KVM_ARM_TARGET_CORTEX_A57 2
	53
	54	#define KVM_ARM_NUM_TARGETS 3
	55
	56	/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
	57	#define KVM_ARM_DEVICE_TYPE_SHIFT 0
	58	#define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
	59	#define KVM_ARM_DEVICE_ID_SHIFT 16
	60	#define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
	61
	62	/* Supported device IDs */
	63	#define KVM_ARM_DEVICE_VGIC_V2 0
	64
65	/* Supported VGIC address types */
66	#define KVM_VGIC_V2_ADDR_TYPE_DIST 0
67	#define KVM_VGIC_V2_ADDR_TYPE_CPU 1
68
69	#define KVM_VGIC_V2_DIST_SIZE 0x1000
70	#define KVM_VGIC_V2_CPU_SIZE 0x2000
71
72	struct kvm_vcpu_init {
73	__u32 target;
74	__u32 features[7];
75	};
76
77	struct kvm_sregs {
78	};
79
80	struct kvm_fpu {
81	};
82
83	struct kvm_guest_debug_arch {
84	};
85
86	struct kvm_debug_exit_arch {
87	};
88
89	struct kvm_sync_regs {
90	};
91
92	struct kvm_arch_memory_slot {
93	};
94
7c8c5e6a MZ	95	/* If you need to interpret the index values, here is the key: */
	96	#define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000
	97	#define KVM_REG_ARM_COPROC_SHIFT 16
	98
	99	/* Normal registers are mapped as coprocessor 16. */
	100	#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
	101	#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32))
	102
	103	/* Some registers need more space to represent values. */
	104	#define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
	105	#define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00
	106	#define KVM_REG_ARM_DEMUX_ID_SHIFT 8
	107	#define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
	108	#define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF
	109	#define KVM_REG_ARM_DEMUX_VAL_SHIFT 0
	110
	111	/* AArch64 system registers */
	112	#define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT)
	113	#define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000
	114	#define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14
	115	#define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800
	116	#define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11
	117	#define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780
	118	#define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7
	119	#define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078
	120	#define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3
	121	#define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007
	122	#define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0
	123
54f81d0e MZ	124	/* KVM_IRQ_LINE irq field index values */
	125	#define KVM_ARM_IRQ_TYPE_SHIFT 24
	126	#define KVM_ARM_IRQ_TYPE_MASK 0xff
	127	#define KVM_ARM_IRQ_VCPU_SHIFT 16
	128	#define KVM_ARM_IRQ_VCPU_MASK 0xff
	129	#define KVM_ARM_IRQ_NUM_SHIFT 0
	130	#define KVM_ARM_IRQ_NUM_MASK 0xffff
	131
	132	/* irq_type field */
	133	#define KVM_ARM_IRQ_TYPE_CPU 0
	134	#define KVM_ARM_IRQ_TYPE_SPI 1
	135	#define KVM_ARM_IRQ_TYPE_PPI 2
	136
	137	/* out-of-kernel GIC cpu interrupt injection irq_number field */
	138	#define KVM_ARM_IRQ_CPU_IRQ 0
	139	#define KVM_ARM_IRQ_CPU_FIQ 1
	140
	141	/* Highest supported SPI, from VGIC_NR_IRQS */
	142	#define KVM_ARM_IRQ_GIC_MAX 127
	143
	144	#endif
	145
	146	#endif /* __ARM_KVM_H__ */