[mirror_ubuntu-zesty-kernel.git] / arch / arm64 / kernel / armv8_deprecated.c

/*
 *  Copyright (C) 2014 ARM Limited
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/cpu.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/perf_event.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/sysctl.h>

#include <asm/cpufeature.h>
#include <asm/insn.h>
#include <asm/sysreg.h>
#include <asm/system_misc.h>
#include <asm/traps.h>
#include <linux/uaccess.h>
#include <asm/cpufeature.h>

#define CREATE_TRACE_POINTS
#include "trace-events-emulation.h"

/*
 * The runtime support for deprecated instruction support can be in one of
 * following three states -
 *
 * 0 = undef
 * 1 = emulate (software emulation)
 * 2 = hw (supported in hardware)
 */
enum insn_emulation_mode {
	INSN_UNDEF,
	INSN_EMULATE,
	INSN_HW,
};

enum legacy_insn_status {
	INSN_DEPRECATED,
	INSN_OBSOLETE,
};

struct insn_emulation_ops {
	const char		*name;
	enum legacy_insn_status	status;
	struct undef_hook	*hooks;
	int			(*set_hw_mode)(bool enable);
};

struct insn_emulation {
	struct list_head node;
	struct insn_emulation_ops *ops;
	int current_mode;
	int min;
	int max;
};

static LIST_HEAD(insn_emulation);
static int nr_insn_emulated __initdata;
static DEFINE_RAW_SPINLOCK(insn_emulation_lock);

static void register_emulation_hooks(struct insn_emulation_ops *ops)
{
	struct undef_hook *hook;

	BUG_ON(!ops->hooks);

	for (hook = ops->hooks; hook->instr_mask; hook++)
		register_undef_hook(hook);

	pr_notice("Registered %s emulation handler\n", ops->name);
}

static void remove_emulation_hooks(struct insn_emulation_ops *ops)
{
	struct undef_hook *hook;

	BUG_ON(!ops->hooks);

	for (hook = ops->hooks; hook->instr_mask; hook++)
		unregister_undef_hook(hook);

	pr_notice("Removed %s emulation handler\n", ops->name);
}

static void enable_insn_hw_mode(void *data)
{
	struct insn_emulation *insn = (struct insn_emulation *)data;
	if (insn->ops->set_hw_mode)
		insn->ops->set_hw_mode(true);
}

static void disable_insn_hw_mode(void *data)
{
	struct insn_emulation *insn = (struct insn_emulation *)data;
	if (insn->ops->set_hw_mode)
		insn->ops->set_hw_mode(false);
}

/* Run set_hw_mode(mode) on all active CPUs */
static int run_all_cpu_set_hw_mode(struct insn_emulation *insn, bool enable)
{
	if (!insn->ops->set_hw_mode)
		return -EINVAL;
	if (enable)
		on_each_cpu(enable_insn_hw_mode, (void *)insn, true);
	else
		on_each_cpu(disable_insn_hw_mode, (void *)insn, true);
	return 0;
}

/*
 * Run set_hw_mode for all insns on a starting CPU.
 * Returns:
 *  0 		- If all the hooks ran successfully.
 * -EINVAL	- At least one hook is not supported by the CPU.
 */
static int run_all_insn_set_hw_mode(unsigned int cpu)
{
	int rc = 0;
	unsigned long flags;
	struct insn_emulation *insn;

	raw_spin_lock_irqsave(&insn_emulation_lock, flags);
	list_for_each_entry(insn, &insn_emulation, node) {
		bool enable = (insn->current_mode == INSN_HW);
		if (insn->ops->set_hw_mode && insn->ops->set_hw_mode(enable)) {
			pr_warn("CPU[%u] cannot support the emulation of %s",
				cpu, insn->ops->name);
			rc = -EINVAL;
		}
	}
	raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
	return rc;
}

static int update_insn_emulation_mode(struct insn_emulation *insn,
				       enum insn_emulation_mode prev)
{
	int ret = 0;

	switch (prev) {
	case INSN_UNDEF: /* Nothing to be done */
		break;
	case INSN_EMULATE:
		remove_emulation_hooks(insn->ops);
		break;
	case INSN_HW:
		if (!run_all_cpu_set_hw_mode(insn, false))
			pr_notice("Disabled %s support\n", insn->ops->name);
		break;
	}

	switch (insn->current_mode) {
	case INSN_UNDEF:
		break;
	case INSN_EMULATE:
		register_emulation_hooks(insn->ops);
		break;
	case INSN_HW:
		ret = run_all_cpu_set_hw_mode(insn, true);
		if (!ret)
			pr_notice("Enabled %s support\n", insn->ops->name);
		break;
	}

	return ret;
}

static void __init register_insn_emulation(struct insn_emulation_ops *ops)
{
	unsigned long flags;
	struct insn_emulation *insn;

	insn = kzalloc(sizeof(*insn), GFP_KERNEL);
	insn->ops = ops;
	insn->min = INSN_UNDEF;

	switch (ops->status) {
	case INSN_DEPRECATED:
		insn->current_mode = INSN_EMULATE;
		/* Disable the HW mode if it was turned on at early boot time */
		run_all_cpu_set_hw_mode(insn, false);
		insn->max = INSN_HW;
		break;
	case INSN_OBSOLETE:
		insn->current_mode = INSN_UNDEF;
		insn->max = INSN_EMULATE;
		break;
	}

	raw_spin_lock_irqsave(&insn_emulation_lock, flags);
	list_add(&insn->node, &insn_emulation);
	nr_insn_emulated++;
	raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);

	/* Register any handlers if required */
	update_insn_emulation_mode(insn, INSN_UNDEF);
}

static int emulation_proc_handler(struct ctl_table *table, int write,
				  void __user *buffer, size_t *lenp,
				  loff_t *ppos)
{
	int ret = 0;
	struct insn_emulation *insn = (struct insn_emulation *) table->data;
	enum insn_emulation_mode prev_mode = insn->current_mode;

	table->data = &insn->current_mode;
	ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos);

	if (ret || !write || prev_mode == insn->current_mode)
		goto ret;

	ret = update_insn_emulation_mode(insn, prev_mode);
	if (ret) {
		/* Mode change failed, revert to previous mode. */
		insn->current_mode = prev_mode;
		update_insn_emulation_mode(insn, INSN_UNDEF);
	}
ret:
	table->data = insn;
	return ret;
}

static struct ctl_table ctl_abi[] = {
	{
		.procname = "abi",
		.mode = 0555,
	},
	{ }
};

static void __init register_insn_emulation_sysctl(struct ctl_table *table)
{
	unsigned long flags;
	int i = 0;
	struct insn_emulation *insn;
	struct ctl_table *insns_sysctl, *sysctl;

	insns_sysctl = kzalloc(sizeof(*sysctl) * (nr_insn_emulated + 1),
			      GFP_KERNEL);

	raw_spin_lock_irqsave(&insn_emulation_lock, flags);
	list_for_each_entry(insn, &insn_emulation, node) {
		sysctl = &insns_sysctl[i];

		sysctl->mode = 0644;
		sysctl->maxlen = sizeof(int);

		sysctl->procname = insn->ops->name;
		sysctl->data = insn;
		sysctl->extra1 = &insn->min;
		sysctl->extra2 = &insn->max;
		sysctl->proc_handler = emulation_proc_handler;
		i++;
	}
	raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);

	table->child = insns_sysctl;
	register_sysctl_table(table);
}

/*
 *  Implement emulation of the SWP/SWPB instructions using load-exclusive and
 *  store-exclusive.
 *
 *  Syntax of SWP{B} instruction: SWP{B}<c> <Rt>, <Rt2>, [<Rn>]
 *  Where: Rt  = destination
 *	   Rt2 = source
 *	   Rn  = address
 */

/*
 * Error-checking SWP macros implemented using ldxr{b}/stxr{b}
 */

/* Arbitrary constant to ensure forward-progress of the LL/SC loop */
#define __SWP_LL_SC_LOOPS	4

#define __user_swpX_asm(data, addr, res, temp, temp2, B)	\
do {								\
	uaccess_enable();					\
	__asm__ __volatile__(					\
	"	mov		%w3, %w7\n"			\
	"0:	ldxr"B"		%w2, [%4]\n"			\
	"1:	stxr"B"		%w0, %w1, [%4]\n"		\
	"	cbz		%w0, 2f\n"			\
	"	sub		%w3, %w3, #1\n"			\
	"	cbnz		%w3, 0b\n"			\
	"	mov		%w0, %w5\n"			\
	"	b		3f\n"				\
	"2:\n"							\
	"	mov		%w1, %w2\n"			\
	"3:\n"							\
	"	.pushsection	 .fixup,\"ax\"\n"		\
	"	.align		2\n"				\
	"4:	mov		%w0, %w6\n"			\
	"	b		3b\n"				\
	"	.popsection"					\
	_ASM_EXTABLE(0b, 4b)					\
	_ASM_EXTABLE(1b, 4b)					\
	: "=&r" (res), "+r" (data), "=&r" (temp), "=&r" (temp2)	\
	: "r" (addr), "i" (-EAGAIN), "i" (-EFAULT),		\
	  "i" (__SWP_LL_SC_LOOPS)				\
	: "memory");						\
	uaccess_disable();					\
} while (0)

#define __user_swp_asm(data, addr, res, temp, temp2) \
	__user_swpX_asm(data, addr, res, temp, temp2, "")
#define __user_swpb_asm(data, addr, res, temp, temp2) \
	__user_swpX_asm(data, addr, res, temp, temp2, "b")

/*
 * Bit 22 of the instruction encoding distinguishes between
 * the SWP and SWPB variants (bit set means SWPB).
 */
#define TYPE_SWPB (1 << 22)

static int emulate_swpX(unsigned int address, unsigned int *data,
			unsigned int type)
{
	unsigned int res = 0;

	if ((type != TYPE_SWPB) && (address & 0x3)) {
		/* SWP to unaligned address not permitted */
		pr_debug("SWP instruction on unaligned pointer!\n");
		return -EFAULT;
	}

	while (1) {
		unsigned long temp, temp2;

		if (type == TYPE_SWPB)
			__user_swpb_asm(*data, address, res, temp, temp2);
		else
			__user_swp_asm(*data, address, res, temp, temp2);

		if (likely(res != -EAGAIN) || signal_pending(current))
			break;

		cond_resched();
	}

	return res;
}

#define ARM_OPCODE_CONDTEST_FAIL   0
#define ARM_OPCODE_CONDTEST_PASS   1
#define ARM_OPCODE_CONDTEST_UNCOND 2

#define	ARM_OPCODE_CONDITION_UNCOND	0xf

static unsigned int __kprobes aarch32_check_condition(u32 opcode, u32 psr)
{
	u32 cc_bits  = opcode >> 28;

	if (cc_bits != ARM_OPCODE_CONDITION_UNCOND) {
		if ((*aarch32_opcode_cond_checks[cc_bits])(psr))
			return ARM_OPCODE_CONDTEST_PASS;
		else
			return ARM_OPCODE_CONDTEST_FAIL;
	}
	return ARM_OPCODE_CONDTEST_UNCOND;
}

/*
 * swp_handler logs the id of calling process, dissects the instruction, sanity
 * checks the memory location, calls emulate_swpX for the actual operation and
 * deals with fixup/error handling before returning
 */
static int swp_handler(struct pt_regs *regs, u32 instr)
{
	u32 destreg, data, type, address = 0;
	int rn, rt2, res = 0;

	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);

	type = instr & TYPE_SWPB;

	switch (aarch32_check_condition(instr, regs->pstate)) {
	case ARM_OPCODE_CONDTEST_PASS:
		break;
	case ARM_OPCODE_CONDTEST_FAIL:
		/* Condition failed - return to next instruction */
		goto ret;
	case ARM_OPCODE_CONDTEST_UNCOND:
		/* If unconditional encoding - not a SWP, undef */
		return -EFAULT;
	default:
		return -EINVAL;
	}

	rn = aarch32_insn_extract_reg_num(instr, A32_RN_OFFSET);
	rt2 = aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET);

	address = (u32)regs->user_regs.regs[rn];
	data	= (u32)regs->user_regs.regs[rt2];
	destreg = aarch32_insn_extract_reg_num(instr, A32_RT_OFFSET);

	pr_debug("addr in r%d->0x%08x, dest is r%d, source in r%d->0x%08x)\n",
		rn, address, destreg,
		aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET), data);

	/* Check access in reasonable access range for both SWP and SWPB */
	if (!access_ok(VERIFY_WRITE, (address & ~3), 4)) {
		pr_debug("SWP{B} emulation: access to 0x%08x not allowed!\n",
			address);
		goto fault;
	}

	res = emulate_swpX(address, &data, type);
	if (res == -EFAULT)
		goto fault;
	else if (res == 0)
		regs->user_regs.regs[destreg] = data;

ret:
	if (type == TYPE_SWPB)
		trace_instruction_emulation("swpb", regs->pc);
	else
		trace_instruction_emulation("swp", regs->pc);

	pr_warn_ratelimited("\"%s\" (%ld) uses obsolete SWP{B} instruction at 0x%llx\n",
			current->comm, (unsigned long)current->pid, regs->pc);

	regs->pc += 4;
	return 0;

fault:
	pr_debug("SWP{B} emulation: access caused memory abort!\n");
	arm64_notify_segfault(regs, address);

	return 0;
}

/*
 * Only emulate SWP/SWPB executed in ARM state/User mode.
 * The kernel must be SWP free and SWP{B} does not exist in Thumb.
 */
static struct undef_hook swp_hooks[] = {
	{
		.instr_mask	= 0x0fb00ff0,
		.instr_val	= 0x01000090,
		.pstate_mask	= COMPAT_PSR_MODE_MASK,
		.pstate_val	= COMPAT_PSR_MODE_USR,
		.fn		= swp_handler
	},
	{ }
};

static struct insn_emulation_ops swp_ops = {
	.name = "swp",
	.status = INSN_OBSOLETE,
	.hooks = swp_hooks,
	.set_hw_mode = NULL,
};

static int cp15barrier_handler(struct pt_regs *regs, u32 instr)
{
	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);

	switch (aarch32_check_condition(instr, regs->pstate)) {
	case ARM_OPCODE_CONDTEST_PASS:
		break;
	case ARM_OPCODE_CONDTEST_FAIL:
		/* Condition failed - return to next instruction */
		goto ret;
	case ARM_OPCODE_CONDTEST_UNCOND:
		/* If unconditional encoding - not a barrier instruction */
		return -EFAULT;
	default:
		return -EINVAL;
	}

	switch (aarch32_insn_mcr_extract_crm(instr)) {
	case 10:
		/*
		 * dmb - mcr p15, 0, Rt, c7, c10, 5
		 * dsb - mcr p15, 0, Rt, c7, c10, 4
		 */
		if (aarch32_insn_mcr_extract_opc2(instr) == 5) {
			dmb(sy);
			trace_instruction_emulation(
				"mcr p15, 0, Rt, c7, c10, 5 ; dmb", regs->pc);
		} else {
			dsb(sy);
			trace_instruction_emulation(
				"mcr p15, 0, Rt, c7, c10, 4 ; dsb", regs->pc);
		}
		break;
	case 5:
		/*
		 * isb - mcr p15, 0, Rt, c7, c5, 4
		 *
		 * Taking an exception or returning from one acts as an
		 * instruction barrier. So no explicit barrier needed here.
		 */
		trace_instruction_emulation(
			"mcr p15, 0, Rt, c7, c5, 4 ; isb", regs->pc);
		break;
	}

ret:
	pr_warn_ratelimited("\"%s\" (%ld) uses deprecated CP15 Barrier instruction at 0x%llx\n",
			current->comm, (unsigned long)current->pid, regs->pc);

	regs->pc += 4;
	return 0;
}

static int cp15_barrier_set_hw_mode(bool enable)
{
	if (enable)
		config_sctlr_el1(0, SCTLR_EL1_CP15BEN);
	else
		config_sctlr_el1(SCTLR_EL1_CP15BEN, 0);
	return 0;
}

static struct undef_hook cp15_barrier_hooks[] = {
	{
		.instr_mask	= 0x0fff0fdf,
		.instr_val	= 0x0e070f9a,
		.pstate_mask	= COMPAT_PSR_MODE_MASK,
		.pstate_val	= COMPAT_PSR_MODE_USR,
		.fn		= cp15barrier_handler,
	},
	{
		.instr_mask	= 0x0fff0fff,
		.instr_val	= 0x0e070f95,
		.pstate_mask	= COMPAT_PSR_MODE_MASK,
		.pstate_val	= COMPAT_PSR_MODE_USR,
		.fn		= cp15barrier_handler,
	},
	{ }
};

static struct insn_emulation_ops cp15_barrier_ops = {
	.name = "cp15_barrier",
	.status = INSN_DEPRECATED,
	.hooks = cp15_barrier_hooks,
	.set_hw_mode = cp15_barrier_set_hw_mode,
};

static int setend_set_hw_mode(bool enable)
{
	if (!cpu_supports_mixed_endian_el0())
		return -EINVAL;

	if (enable)
		config_sctlr_el1(SCTLR_EL1_SED, 0);
	else
		config_sctlr_el1(0, SCTLR_EL1_SED);
	return 0;
}

static int compat_setend_handler(struct pt_regs *regs, u32 big_endian)
{
	char *insn;

	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);

	if (big_endian) {
		insn = "setend be";
		regs->pstate |= COMPAT_PSR_E_BIT;
	} else {
		insn = "setend le";
		regs->pstate &= ~COMPAT_PSR_E_BIT;
	}

	trace_instruction_emulation(insn, regs->pc);
	pr_warn_ratelimited("\"%s\" (%ld) uses deprecated setend instruction at 0x%llx\n",
			current->comm, (unsigned long)current->pid, regs->pc);

	return 0;
}

static int a32_setend_handler(struct pt_regs *regs, u32 instr)
{
	int rc = compat_setend_handler(regs, (instr >> 9) & 1);
	regs->pc += 4;
	return rc;
}

static int t16_setend_handler(struct pt_regs *regs, u32 instr)
{
	int rc = compat_setend_handler(regs, (instr >> 3) & 1);
	regs->pc += 2;
	return rc;
}

static struct undef_hook setend_hooks[] = {
	{
		.instr_mask	= 0xfffffdff,
		.instr_val	= 0xf1010000,
		.pstate_mask	= COMPAT_PSR_MODE_MASK,
		.pstate_val	= COMPAT_PSR_MODE_USR,
		.fn		= a32_setend_handler,
	},
	{
		/* Thumb mode */
		.instr_mask	= 0x0000fff7,
		.instr_val	= 0x0000b650,
		.pstate_mask	= (COMPAT_PSR_T_BIT | COMPAT_PSR_MODE_MASK),
		.pstate_val	= (COMPAT_PSR_T_BIT | COMPAT_PSR_MODE_USR),
		.fn		= t16_setend_handler,
	},
	{}
};

static struct insn_emulation_ops setend_ops = {
	.name = "setend",
	.status = INSN_DEPRECATED,
	.hooks = setend_hooks,
	.set_hw_mode = setend_set_hw_mode,
};

/*
 * Invoked as late_initcall, since not needed before init spawned.
 */
static int __init armv8_deprecated_init(void)
{
	if (IS_ENABLED(CONFIG_SWP_EMULATION))
		register_insn_emulation(&swp_ops);

	if (IS_ENABLED(CONFIG_CP15_BARRIER_EMULATION))
		register_insn_emulation(&cp15_barrier_ops);

	if (IS_ENABLED(CONFIG_SETEND_EMULATION)) {
		if(system_supports_mixed_endian_el0())
			register_insn_emulation(&setend_ops);
		else
			pr_info("setend instruction emulation is not supported on the system");
	}

	cpuhp_setup_state_nocalls(CPUHP_AP_ARM64_ISNDEP_STARTING,
				  "arm64/isndep:starting",
				  run_all_insn_set_hw_mode, NULL);
	register_insn_emulation_sysctl(ctl_abi);

	return 0;
}

late_initcall(armv8_deprecated_init);
Commit	Line	Data
587064b6 PA	1	/*
	2	* Copyright (C) 2014 ARM Limited
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
c852f320	9	#include <linux/cpu.h>
587064b6 PA	10	#include <linux/init.h>
587064b6 PA	11	#include <linux/list.h>
bd35a4ad PA	12	#include <linux/perf_event.h>
bd35a4ad PA	13	#include <linux/sched.h>
587064b6 PA	14	#include <linux/slab.h>
	15	#include <linux/sysctl.h>
	16
338d4f49	17	#include <asm/cpufeature.h>
bd35a4ad	18	#include <asm/insn.h>
870828e5	19	#include <asm/sysreg.h>
bd35a4ad	20	#include <asm/system_misc.h>
587064b6	21	#include <asm/traps.h>
7c0f6ba6	22	#include <linux/uaccess.h>
736d474f	23	#include <asm/cpufeature.h>
587064b6	24
d784e298 PA	25	#define CREATE_TRACE_POINTS
	26	#include "trace-events-emulation.h"
	27
587064b6 PA	28	/*
	29	* The runtime support for deprecated instruction support can be in one of
	30	* following three states -
	31	*
	32	* 0 = undef
	33	* 1 = emulate (software emulation)
	34	* 2 = hw (supported in hardware)
	35	*/
	36	enum insn_emulation_mode {
	37	INSN_UNDEF,
	38	INSN_EMULATE,
	39	INSN_HW,
	40	};
	41
	42	enum legacy_insn_status {
	43	INSN_DEPRECATED,
	44	INSN_OBSOLETE,
	45	};
	46
	47	struct insn_emulation_ops {
	48	const char *name;
	49	enum legacy_insn_status status;
	50	struct undef_hook *hooks;
	51	int (*set_hw_mode)(bool enable);
	52	};
	53
	54	struct insn_emulation {
	55	struct list_head node;
	56	struct insn_emulation_ops *ops;
	57	int current_mode;
	58	int min;
	59	int max;
	60	};
	61
	62	static LIST_HEAD(insn_emulation);
a7c61a34	63	static int nr_insn_emulated __initdata;
587064b6 PA	64	static DEFINE_RAW_SPINLOCK(insn_emulation_lock);
	65
	66	static void register_emulation_hooks(struct insn_emulation_ops *ops)
	67	{
	68	struct undef_hook *hook;
	69
	70	BUG_ON(!ops->hooks);
	71
	72	for (hook = ops->hooks; hook->instr_mask; hook++)
	73	register_undef_hook(hook);
	74
	75	pr_notice("Registered %s emulation handler\n", ops->name);
	76	}
	77
	78	static void remove_emulation_hooks(struct insn_emulation_ops *ops)
	79	{
	80	struct undef_hook *hook;
	81
	82	BUG_ON(!ops->hooks);
	83
	84	for (hook = ops->hooks; hook->instr_mask; hook++)
	85	unregister_undef_hook(hook);
	86
	87	pr_notice("Removed %s emulation handler\n", ops->name);
	88	}
	89
736d474f SP	90	static void enable_insn_hw_mode(void *data)
	91	{
	92	struct insn_emulation insn = (struct insn_emulation )data;
	93	if (insn->ops->set_hw_mode)
	94	insn->ops->set_hw_mode(true);
	95	}
	96
	97	static void disable_insn_hw_mode(void *data)
	98	{
	99	struct insn_emulation insn = (struct insn_emulation )data;
	100	if (insn->ops->set_hw_mode)
	101	insn->ops->set_hw_mode(false);
	102	}
	103
	104	/* Run set_hw_mode(mode) on all active CPUs */
	105	static int run_all_cpu_set_hw_mode(struct insn_emulation *insn, bool enable)
	106	{
	107	if (!insn->ops->set_hw_mode)
	108	return -EINVAL;
	109	if (enable)
	110	on_each_cpu(enable_insn_hw_mode, (void *)insn, true);
	111	else
	112	on_each_cpu(disable_insn_hw_mode, (void *)insn, true);
	113	return 0;
	114	}
	115
	116	/*
	117	* Run set_hw_mode for all insns on a starting CPU.
	118	* Returns:
	119	* 0 - If all the hooks ran successfully.
	120	* -EINVAL - At least one hook is not supported by the CPU.
	121	*/
27c01a8c	122	static int run_all_insn_set_hw_mode(unsigned int cpu)
736d474f SP	123	{
	124	int rc = 0;
	125	unsigned long flags;
	126	struct insn_emulation *insn;
	127
	128	raw_spin_lock_irqsave(&insn_emulation_lock, flags);
	129	list_for_each_entry(insn, &insn_emulation, node) {
	130	bool enable = (insn->current_mode == INSN_HW);
	131	if (insn->ops->set_hw_mode && insn->ops->set_hw_mode(enable)) {
27c01a8c	132	pr_warn("CPU[%u] cannot support the emulation of %s",
736d474f SP	133	cpu, insn->ops->name);
	134	rc = -EINVAL;
	135	}
	136	}
	137	raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
	138	return rc;
	139	}
	140
587064b6 PA	141	static int update_insn_emulation_mode(struct insn_emulation *insn,
	142	enum insn_emulation_mode prev)
	143	{
	144	int ret = 0;
	145
	146	switch (prev) {
	147	case INSN_UNDEF: /* Nothing to be done */
	148	break;
	149	case INSN_EMULATE:
	150	remove_emulation_hooks(insn->ops);
	151	break;
	152	case INSN_HW:
736d474f	153	if (!run_all_cpu_set_hw_mode(insn, false))
587064b6	154	pr_notice("Disabled %s support\n", insn->ops->name);
587064b6 PA	155	break;
	156	}
	157
	158	switch (insn->current_mode) {
	159	case INSN_UNDEF:
	160	break;
	161	case INSN_EMULATE:
	162	register_emulation_hooks(insn->ops);
	163	break;
	164	case INSN_HW:
736d474f SP	165	ret = run_all_cpu_set_hw_mode(insn, true);
736d474f SP	166	if (!ret)
587064b6	167	pr_notice("Enabled %s support\n", insn->ops->name);
587064b6 PA	168	break;
	169	}
	170
	171	return ret;
	172	}
	173
a7c61a34	174	static void __init register_insn_emulation(struct insn_emulation_ops *ops)
587064b6 PA	175	{
	176	unsigned long flags;
	177	struct insn_emulation *insn;
	178
	179	insn = kzalloc(sizeof(*insn), GFP_KERNEL);
	180	insn->ops = ops;
	181	insn->min = INSN_UNDEF;
	182
	183	switch (ops->status) {
	184	case INSN_DEPRECATED:
	185	insn->current_mode = INSN_EMULATE;
736d474f SP	186	/* Disable the HW mode if it was turned on at early boot time */
736d474f SP	187	run_all_cpu_set_hw_mode(insn, false);
587064b6 PA	188	insn->max = INSN_HW;
	189	break;
	190	case INSN_OBSOLETE:
	191	insn->current_mode = INSN_UNDEF;
	192	insn->max = INSN_EMULATE;
	193	break;
	194	}
	195
	196	raw_spin_lock_irqsave(&insn_emulation_lock, flags);
	197	list_add(&insn->node, &insn_emulation);
	198	nr_insn_emulated++;
	199	raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
	200
	201	/* Register any handlers if required */
	202	update_insn_emulation_mode(insn, INSN_UNDEF);
	203	}
	204
	205	static int emulation_proc_handler(struct ctl_table *table, int write,
	206	void __user buffer, size_t lenp,
	207	loff_t *ppos)
	208	{
	209	int ret = 0;
	210	struct insn_emulation insn = (struct insn_emulation ) table->data;
	211	enum insn_emulation_mode prev_mode = insn->current_mode;
	212
	213	table->data = &insn->current_mode;
	214	ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos);
	215
	216	if (ret \|\| !write \|\| prev_mode == insn->current_mode)
	217	goto ret;
	218
	219	ret = update_insn_emulation_mode(insn, prev_mode);
90963395	220	if (ret) {
587064b6 PA	221	/* Mode change failed, revert to previous mode. */
	222	insn->current_mode = prev_mode;
	223	update_insn_emulation_mode(insn, INSN_UNDEF);
	224	}
	225	ret:
	226	table->data = insn;
	227	return ret;
	228	}
	229
	230	static struct ctl_table ctl_abi[] = {
	231	{
	232	.procname = "abi",
	233	.mode = 0555,
	234	},
	235	{ }
	236	};
	237
a7c61a34	238	static void __init register_insn_emulation_sysctl(struct ctl_table *table)
587064b6 PA	239	{
	240	unsigned long flags;
	241	int i = 0;
	242	struct insn_emulation *insn;
	243	struct ctl_table insns_sysctl, sysctl;
	244
	245	insns_sysctl = kzalloc(sizeof(sysctl) (nr_insn_emulated + 1),
	246	GFP_KERNEL);
	247
	248	raw_spin_lock_irqsave(&insn_emulation_lock, flags);
	249	list_for_each_entry(insn, &insn_emulation, node) {
	250	sysctl = &insns_sysctl[i];
	251
	252	sysctl->mode = 0644;
	253	sysctl->maxlen = sizeof(int);
	254
	255	sysctl->procname = insn->ops->name;
	256	sysctl->data = insn;
	257	sysctl->extra1 = &insn->min;
	258	sysctl->extra2 = &insn->max;
	259	sysctl->proc_handler = emulation_proc_handler;
	260	i++;
	261	}
	262	raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
	263
	264	table->child = insns_sysctl;
	265	register_sysctl_table(table);
	266	}
	267
bd35a4ad PA	268	/*
	269	* Implement emulation of the SWP/SWPB instructions using load-exclusive and
	270	* store-exclusive.
	271	*
	272	* Syntax of SWP{B} instruction: SWP{B}<c> <Rt>, <Rt2>, [<Rn>]
	273	* Where: Rt = destination
	274	* Rt2 = source
	275	* Rn = address
	276	*/
	277
	278	/*
	279	* Error-checking SWP macros implemented using ldxr{b}/stxr{b}
	280	*/
1c5b51df WD	281
	282	/* Arbitrary constant to ensure forward-progress of the LL/SC loop */
	283	#define __SWP_LL_SC_LOOPS 4
	284
	285	#define __user_swpX_asm(data, addr, res, temp, temp2, B) \
bd38967d CM	286	do { \
bd38967d CM	287	uaccess_enable(); \
bd35a4ad	288	__asm__ __volatile__( \
1c5b51df	289	" mov %w3, %w7\n" \
1c5b51df WD	290	"0: ldxr"B" %w2, [%4]\n" \
1c5b51df WD	291	"1: stxr"B" %w0, %w1, [%4]\n" \
bd35a4ad	292	" cbz %w0, 2f\n" \
1c5b51df WD	293	" sub %w3, %w3, #1\n" \
	294	" cbnz %w3, 0b\n" \
	295	" mov %w0, %w5\n" \
589cb22b	296	" b 3f\n" \
bd35a4ad	297	"2:\n" \
589cb22b WD	298	" mov %w1, %w2\n" \
589cb22b WD	299	"3:\n" \
bd35a4ad PA	300	" .pushsection .fixup,\"ax\"\n" \
bd35a4ad PA	301	" .align 2\n" \
1c5b51df	302	"4: mov %w0, %w6\n" \
589cb22b	303	" b 3b\n" \
bd35a4ad	304	" .popsection" \
6c94f27a AB	305	_ASM_EXTABLE(0b, 4b) \
6c94f27a AB	306	_ASM_EXTABLE(1b, 4b) \
1c5b51df WD	307	: "=&r" (res), "+r" (data), "=&r" (temp), "=&r" (temp2) \
	308	: "r" (addr), "i" (-EAGAIN), "i" (-EFAULT), \
	309	"i" (__SWP_LL_SC_LOOPS) \
bd38967d CM	310	: "memory"); \
	311	uaccess_disable(); \
	312	} while (0)
bd35a4ad	313
1c5b51df WD	314	#define __user_swp_asm(data, addr, res, temp, temp2) \
	315	__user_swpX_asm(data, addr, res, temp, temp2, "")
	316	#define __user_swpb_asm(data, addr, res, temp, temp2) \
	317	__user_swpX_asm(data, addr, res, temp, temp2, "b")
bd35a4ad PA	318
	319	/*
	320	* Bit 22 of the instruction encoding distinguishes between
	321	* the SWP and SWPB variants (bit set means SWPB).
	322	*/
	323	#define TYPE_SWPB (1 << 22)
	324
bd35a4ad PA	325	static int emulate_swpX(unsigned int address, unsigned int *data,
	326	unsigned int type)
	327	{
	328	unsigned int res = 0;
	329
	330	if ((type != TYPE_SWPB) && (address & 0x3)) {
	331	/* SWP to unaligned address not permitted */
	332	pr_debug("SWP instruction on unaligned pointer!\n");
	333	return -EFAULT;
	334	}
	335
	336	while (1) {
1c5b51df	337	unsigned long temp, temp2;
bd35a4ad PA	338
bd35a4ad PA	339	if (type == TYPE_SWPB)
1c5b51df	340	__user_swpb_asm(*data, address, res, temp, temp2);
bd35a4ad	341	else
1c5b51df	342	__user_swp_asm(*data, address, res, temp, temp2);
bd35a4ad PA	343
	344	if (likely(res != -EAGAIN) \|\| signal_pending(current))
	345	break;
	346
	347	cond_resched();
	348	}
	349
	350	return res;
	351	}
	352
bca8f17f MZ	353	#define ARM_OPCODE_CONDTEST_FAIL 0
	354	#define ARM_OPCODE_CONDTEST_PASS 1
	355	#define ARM_OPCODE_CONDTEST_UNCOND 2
	356
2af3ec08 DL	357	#define ARM_OPCODE_CONDITION_UNCOND 0xf
	358
	359	static unsigned int __kprobes aarch32_check_condition(u32 opcode, u32 psr)
	360	{
	361	u32 cc_bits = opcode >> 28;
	362
	363	if (cc_bits != ARM_OPCODE_CONDITION_UNCOND) {
	364	if ((*aarch32_opcode_cond_checks[cc_bits])(psr))
	365	return ARM_OPCODE_CONDTEST_PASS;
	366	else
	367	return ARM_OPCODE_CONDTEST_FAIL;
	368	}
	369	return ARM_OPCODE_CONDTEST_UNCOND;
	370	}
	371
bd35a4ad PA	372	/*
	373	* swp_handler logs the id of calling process, dissects the instruction, sanity
	374	* checks the memory location, calls emulate_swpX for the actual operation and
	375	* deals with fixup/error handling before returning
	376	*/
	377	static int swp_handler(struct pt_regs *regs, u32 instr)
	378	{
	379	u32 destreg, data, type, address = 0;
	380	int rn, rt2, res = 0;
	381
	382	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
	383
	384	type = instr & TYPE_SWPB;
	385
2af3ec08	386	switch (aarch32_check_condition(instr, regs->pstate)) {
bd35a4ad PA	387	case ARM_OPCODE_CONDTEST_PASS:
	388	break;
	389	case ARM_OPCODE_CONDTEST_FAIL:
	390	/* Condition failed - return to next instruction */
	391	goto ret;
	392	case ARM_OPCODE_CONDTEST_UNCOND:
	393	/* If unconditional encoding - not a SWP, undef */
	394	return -EFAULT;
	395	default:
	396	return -EINVAL;
	397	}
	398
	399	rn = aarch32_insn_extract_reg_num(instr, A32_RN_OFFSET);
	400	rt2 = aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET);
	401
	402	address = (u32)regs->user_regs.regs[rn];
	403	data = (u32)regs->user_regs.regs[rt2];
	404	destreg = aarch32_insn_extract_reg_num(instr, A32_RT_OFFSET);
	405
	406	pr_debug("addr in r%d->0x%08x, dest is r%d, source in r%d->0x%08x)\n",
	407	rn, address, destreg,
	408	aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET), data);
	409
	410	/* Check access in reasonable access range for both SWP and SWPB */
	411	if (!access_ok(VERIFY_WRITE, (address & ~3), 4)) {
	412	pr_debug("SWP{B} emulation: access to 0x%08x not allowed!\n",
	413	address);
	414	goto fault;
	415	}
	416
	417	res = emulate_swpX(address, &data, type);
	418	if (res == -EFAULT)
	419	goto fault;
	420	else if (res == 0)
	421	regs->user_regs.regs[destreg] = data;
	422
	423	ret:
d784e298 PA	424	if (type == TYPE_SWPB)
	425	trace_instruction_emulation("swpb", regs->pc);
	426	else
	427	trace_instruction_emulation("swp", regs->pc);
	428
bd35a4ad PA	429	pr_warn_ratelimited("\"%s\" (%ld) uses obsolete SWP{B} instruction at 0x%llx\n",
	430	current->comm, (unsigned long)current->pid, regs->pc);
	431
	432	regs->pc += 4;
	433	return 0;
	434
	435	fault:
390bf177 AP	436	pr_debug("SWP{B} emulation: access caused memory abort!\n");
390bf177 AP	437	arm64_notify_segfault(regs, address);
bd35a4ad PA	438
	439	return 0;
	440	}
	441
	442	/*
	443	* Only emulate SWP/SWPB executed in ARM state/User mode.
	444	* The kernel must be SWP free and SWP{B} does not exist in Thumb.
	445	*/
	446	static struct undef_hook swp_hooks[] = {
	447	{
	448	.instr_mask = 0x0fb00ff0,
	449	.instr_val = 0x01000090,
	450	.pstate_mask = COMPAT_PSR_MODE_MASK,
	451	.pstate_val = COMPAT_PSR_MODE_USR,
	452	.fn = swp_handler
	453	},
	454	{ }
	455	};
	456
	457	static struct insn_emulation_ops swp_ops = {
	458	.name = "swp",
	459	.status = INSN_OBSOLETE,
	460	.hooks = swp_hooks,
	461	.set_hw_mode = NULL,
	462	};
	463
c852f320 PA	464	static int cp15barrier_handler(struct pt_regs *regs, u32 instr)
	465	{
	466	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
	467
2af3ec08	468	switch (aarch32_check_condition(instr, regs->pstate)) {
c852f320 PA	469	case ARM_OPCODE_CONDTEST_PASS:
	470	break;
	471	case ARM_OPCODE_CONDTEST_FAIL:
	472	/* Condition failed - return to next instruction */
	473	goto ret;
	474	case ARM_OPCODE_CONDTEST_UNCOND:
	475	/* If unconditional encoding - not a barrier instruction */
	476	return -EFAULT;
	477	default:
	478	return -EINVAL;
	479	}
	480
	481	switch (aarch32_insn_mcr_extract_crm(instr)) {
	482	case 10:
	483	/*
	484	* dmb - mcr p15, 0, Rt, c7, c10, 5
	485	* dsb - mcr p15, 0, Rt, c7, c10, 4
	486	*/
d784e298	487	if (aarch32_insn_mcr_extract_opc2(instr) == 5) {
c852f320	488	dmb(sy);
d784e298 PA	489	trace_instruction_emulation(
	490	"mcr p15, 0, Rt, c7, c10, 5 ; dmb", regs->pc);
	491	} else {
c852f320	492	dsb(sy);
d784e298 PA	493	trace_instruction_emulation(
	494	"mcr p15, 0, Rt, c7, c10, 4 ; dsb", regs->pc);
	495	}
c852f320 PA	496	break;
	497	case 5:
	498	/*
	499	* isb - mcr p15, 0, Rt, c7, c5, 4
	500	*
	501	* Taking an exception or returning from one acts as an
	502	* instruction barrier. So no explicit barrier needed here.
	503	*/
d784e298 PA	504	trace_instruction_emulation(
d784e298 PA	505	"mcr p15, 0, Rt, c7, c5, 4 ; isb", regs->pc);
c852f320 PA	506	break;
	507	}
	508
	509	ret:
	510	pr_warn_ratelimited("\"%s\" (%ld) uses deprecated CP15 Barrier instruction at 0x%llx\n",
	511	current->comm, (unsigned long)current->pid, regs->pc);
	512
	513	regs->pc += 4;
	514	return 0;
	515	}
	516
c852f320 PA	517	static int cp15_barrier_set_hw_mode(bool enable)
c852f320 PA	518	{
736d474f SP	519	if (enable)
	520	config_sctlr_el1(0, SCTLR_EL1_CP15BEN);
	521	else
	522	config_sctlr_el1(SCTLR_EL1_CP15BEN, 0);
	523	return 0;
c852f320 PA	524	}
	525
	526	static struct undef_hook cp15_barrier_hooks[] = {
	527	{
	528	.instr_mask = 0x0fff0fdf,
	529	.instr_val = 0x0e070f9a,
	530	.pstate_mask = COMPAT_PSR_MODE_MASK,
	531	.pstate_val = COMPAT_PSR_MODE_USR,
	532	.fn = cp15barrier_handler,
	533	},
	534	{
	535	.instr_mask = 0x0fff0fff,
	536	.instr_val = 0x0e070f95,
	537	.pstate_mask = COMPAT_PSR_MODE_MASK,
	538	.pstate_val = COMPAT_PSR_MODE_USR,
	539	.fn = cp15barrier_handler,
	540	},
	541	{ }
	542	};
	543
	544	static struct insn_emulation_ops cp15_barrier_ops = {
	545	.name = "cp15_barrier",
	546	.status = INSN_DEPRECATED,
	547	.hooks = cp15_barrier_hooks,
	548	.set_hw_mode = cp15_barrier_set_hw_mode,
	549	};
	550
2d888f48 SP	551	static int setend_set_hw_mode(bool enable)
	552	{
	553	if (!cpu_supports_mixed_endian_el0())
	554	return -EINVAL;
	555
	556	if (enable)
	557	config_sctlr_el1(SCTLR_EL1_SED, 0);
	558	else
	559	config_sctlr_el1(0, SCTLR_EL1_SED);
	560	return 0;
	561	}
	562
	563	static int compat_setend_handler(struct pt_regs *regs, u32 big_endian)
	564	{
	565	char *insn;
	566
	567	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
	568
	569	if (big_endian) {
	570	insn = "setend be";
	571	regs->pstate \|= COMPAT_PSR_E_BIT;
	572	} else {
	573	insn = "setend le";
	574	regs->pstate &= ~COMPAT_PSR_E_BIT;
	575	}
	576
	577	trace_instruction_emulation(insn, regs->pc);
	578	pr_warn_ratelimited("\"%s\" (%ld) uses deprecated setend instruction at 0x%llx\n",
	579	current->comm, (unsigned long)current->pid, regs->pc);
	580
	581	return 0;
	582	}
	583
	584	static int a32_setend_handler(struct pt_regs *regs, u32 instr)
	585	{
	586	int rc = compat_setend_handler(regs, (instr >> 9) & 1);
	587	regs->pc += 4;
	588	return rc;
	589	}
	590
	591	static int t16_setend_handler(struct pt_regs *regs, u32 instr)
	592	{
	593	int rc = compat_setend_handler(regs, (instr >> 3) & 1);
	594	regs->pc += 2;
	595	return rc;
	596	}
	597
	598	static struct undef_hook setend_hooks[] = {
	599	{
	600	.instr_mask = 0xfffffdff,
	601	.instr_val = 0xf1010000,
	602	.pstate_mask = COMPAT_PSR_MODE_MASK,
	603	.pstate_val = COMPAT_PSR_MODE_USR,
	604	.fn = a32_setend_handler,
	605	},
	606	{
	607	/* Thumb mode */
	608	.instr_mask = 0x0000fff7,
	609	.instr_val = 0x0000b650,
	610	.pstate_mask = (COMPAT_PSR_T_BIT \| COMPAT_PSR_MODE_MASK),
	611	.pstate_val = (COMPAT_PSR_T_BIT \| COMPAT_PSR_MODE_USR),
	612	.fn = t16_setend_handler,
	613	},
	614	{}
615	};
616
617	static struct insn_emulation_ops setend_ops = {
618	.name = "setend",
619	.status = INSN_DEPRECATED,
620	.hooks = setend_hooks,
621	.set_hw_mode = setend_set_hw_mode,
622	};
623
587064b6 PA	624	/*
	625	* Invoked as late_initcall, since not needed before init spawned.
	626	*/
	627	static int __init armv8_deprecated_init(void)
	628	{
bd35a4ad PA	629	if (IS_ENABLED(CONFIG_SWP_EMULATION))
	630	register_insn_emulation(&swp_ops);
	631
c852f320 PA	632	if (IS_ENABLED(CONFIG_CP15_BARRIER_EMULATION))
	633	register_insn_emulation(&cp15_barrier_ops);
	634
2d888f48 SP	635	if (IS_ENABLED(CONFIG_SETEND_EMULATION)) {
	636	if(system_supports_mixed_endian_el0())
	637	register_insn_emulation(&setend_ops);
	638	else
	639	pr_info("setend instruction emulation is not supported on the system");
	640	}
	641
27c01a8c	642	cpuhp_setup_state_nocalls(CPUHP_AP_ARM64_ISNDEP_STARTING,
73c1b41e	643	"arm64/isndep:starting",
27c01a8c	644	run_all_insn_set_hw_mode, NULL);
587064b6 PA	645	register_insn_emulation_sysctl(ctl_abi);
	646
	647	return 0;
	648	}
	649
	650	late_initcall(armv8_deprecated_init);