projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| ec52ee18 WD |
1 | /* |
| 2 | * Contains CPU specific branch predictor invalidation sequences | |
| 3 | * | |
| 4 | * Copyright (C) 2018 ARM Ltd. | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify | |
| 7 | * it under the terms of the GNU General Public License version 2 as | |
| 8 | * published by the Free Software Foundation. | |
| 9 | * | |
| 10 | * This program is distributed in the hope that it will be useful, | |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 13 | * GNU General Public License for more details. | |
| 14 | * | |
| 15 | * You should have received a copy of the GNU General Public License | |
| 16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
| 17 | */ | |
| 18 | ||
| 19 | #include <linux/linkage.h> | |
| a23a1a7e | 20 | #include <linux/arm-smccc.h> |
| ec52ee18 WD |
21 | |
| 22 | .macro ventry target | |
| 23 | .rept 31 | |
| 24 | nop | |
| 25 | .endr | |
| 26 | b \target | |
| 27 | .endm | |
| 28 | ||
| 29 | .macro vectors target | |
| 30 | ventry \target + 0x000 | |
| 31 | ventry \target + 0x080 | |
| 32 | ventry \target + 0x100 | |
| 33 | ventry \target + 0x180 | |
| 34 | ||
| 35 | ventry \target + 0x200 | |
| 36 | ventry \target + 0x280 | |
| 37 | ventry \target + 0x300 | |
| 38 | ventry \target + 0x380 | |
| 39 | ||
| 40 | ventry \target + 0x400 | |
| 41 | ventry \target + 0x480 | |
| 42 | ventry \target + 0x500 | |
| 43 | ventry \target + 0x580 | |
| 44 | ||
| 45 | ventry \target + 0x600 | |
| 46 | ventry \target + 0x680 | |
| 47 | ventry \target + 0x700 | |
| 48 | ventry \target + 0x780 | |
| 49 | .endm | |
| 50 | ||
| 51 | .align 11 | |
| 52 | ENTRY(__bp_harden_hyp_vecs_start) | |
| 53 | .rept 4 | |
| 54 | vectors __kvm_hyp_vector | |
| 55 | .endr | |
| 56 | ENTRY(__bp_harden_hyp_vecs_end) | |
| f2f427ad WD |
57 | ENTRY(__psci_hyp_bp_inval_start) |
| 58 | sub sp, sp, #(8 * 18) | |
| 59 | stp x16, x17, [sp, #(16 * 0)] | |
| 60 | stp x14, x15, [sp, #(16 * 1)] | |
| 61 | stp x12, x13, [sp, #(16 * 2)] | |
| 62 | stp x10, x11, [sp, #(16 * 3)] | |
| 63 | stp x8, x9, [sp, #(16 * 4)] | |
| 64 | stp x6, x7, [sp, #(16 * 5)] | |
| 65 | stp x4, x5, [sp, #(16 * 6)] | |
| 66 | stp x2, x3, [sp, #(16 * 7)] | |
| 67 | stp x0, x1, [sp, #(16 * 8)] | |
| 68 | mov x0, #0x84000000 | |
| 69 | smc #0 | |
| 70 | ldp x16, x17, [sp, #(16 * 0)] | |
| 71 | ldp x14, x15, [sp, #(16 * 1)] | |
| 72 | ldp x12, x13, [sp, #(16 * 2)] | |
| 73 | ldp x10, x11, [sp, #(16 * 3)] | |
| 74 | ldp x8, x9, [sp, #(16 * 4)] | |
| 75 | ldp x6, x7, [sp, #(16 * 5)] | |
| 76 | ldp x4, x5, [sp, #(16 * 6)] | |
| 77 | ldp x2, x3, [sp, #(16 * 7)] | |
| 78 | ldp x0, x1, [sp, #(16 * 8)] | |
| 79 | add sp, sp, #(8 * 18) | |
| 80 | ENTRY(__psci_hyp_bp_inval_end) | |
| a516894a SD |
81 | |
| 82 | ENTRY(__qcom_hyp_sanitize_link_stack_start) | |
| 83 | stp x29, x30, [sp, #-16]! | |
| 84 | .rept 16 | |
| 85 | bl . + 4 | |
| 86 | .endr | |
| 87 | ldp x29, x30, [sp], #16 | |
| 88 | ENTRY(__qcom_hyp_sanitize_link_stack_end) | |
| a23a1a7e MZ |
89 | |
| 90 | .macro smccc_workaround_1 inst | |
| 91 | sub sp, sp, #(8 * 4) | |
| 92 | stp x2, x3, [sp, #(8 * 0)] | |
| 93 | stp x0, x1, [sp, #(8 * 2)] | |
| 94 | mov w0, #ARM_SMCCC_ARCH_WORKAROUND_1 | |
| 95 | \inst #0 | |
| 96 | ldp x2, x3, [sp, #(8 * 0)] | |
| 97 | ldp x0, x1, [sp, #(8 * 2)] | |
| 98 | add sp, sp, #(8 * 4) | |
| 99 | .endm | |
| 100 | ||
| 101 | ENTRY(__smccc_workaround_1_smc_start) | |
| 102 | smccc_workaround_1 smc | |
| 103 | ENTRY(__smccc_workaround_1_smc_end) | |
| 104 | ||
| 105 | ENTRY(__smccc_workaround_1_hvc_start) | |
| 106 | smccc_workaround_1 hvc | |
| 107 | ENTRY(__smccc_workaround_1_hvc_end) |