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e116a375 AP |
1 | /* |
2 | * Contains CPU specific errata definitions | |
3 | * | |
4 | * Copyright (C) 2014 ARM Ltd. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
94a5d879 AB |
19 | #include <linux/arm-smccc.h> |
20 | #include <linux/psci.h> | |
e116a375 AP |
21 | #include <linux/types.h> |
22 | #include <asm/cpu.h> | |
23 | #include <asm/cputype.h> | |
24 | #include <asm/cpufeature.h> | |
25 | ||
301bcfac | 26 | static bool __maybe_unused |
92406f0c | 27 | is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) |
301bcfac | 28 | { |
e8002e02 AB |
29 | const struct arm64_midr_revidr *fix; |
30 | u32 midr = read_cpuid_id(), revidr; | |
31 | ||
92406f0c | 32 | WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); |
1df31050 | 33 | if (!is_midr_in_range(midr, &entry->midr_range)) |
e8002e02 AB |
34 | return false; |
35 | ||
36 | midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK; | |
37 | revidr = read_cpuid(REVIDR_EL1); | |
38 | for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++) | |
39 | if (midr == fix->midr_rv && (revidr & fix->revidr_mask)) | |
40 | return false; | |
41 | ||
42 | return true; | |
301bcfac AP |
43 | } |
44 | ||
be5b2998 SP |
45 | static bool __maybe_unused |
46 | is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry, | |
47 | int scope) | |
301bcfac | 48 | { |
92406f0c | 49 | WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); |
be5b2998 | 50 | return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list); |
301bcfac AP |
51 | } |
52 | ||
bb487118 SB |
53 | static bool __maybe_unused |
54 | is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope) | |
55 | { | |
56 | u32 model; | |
57 | ||
58 | WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); | |
59 | ||
60 | model = read_cpuid_id(); | |
61 | model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) | | |
62 | MIDR_ARCHITECTURE_MASK; | |
63 | ||
1df31050 | 64 | return model == entry->midr_range.model; |
bb487118 SB |
65 | } |
66 | ||
116c81f4 | 67 | static bool |
314d53d2 SP |
68 | has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry, |
69 | int scope) | |
116c81f4 | 70 | { |
4c4a39dd SP |
71 | u64 mask = CTR_CACHE_MINLINE_MASK; |
72 | ||
314d53d2 SP |
73 | /* Skip matching the min line sizes for cache type check */ |
74 | if (entry->capability == ARM64_MISMATCHED_CACHE_TYPE) | |
75 | mask ^= arm64_ftr_reg_ctrel0.strict_mask; | |
76 | ||
116c81f4 | 77 | WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); |
4c4a39dd SP |
78 | return (read_cpuid_cachetype() & mask) != |
79 | (arm64_ftr_reg_ctrel0.sys_val & mask); | |
116c81f4 SP |
80 | } |
81 | ||
c0cda3b8 DM |
82 | static void |
83 | cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *__unused) | |
116c81f4 | 84 | { |
25be597a | 85 | sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); |
116c81f4 SP |
86 | } |
87 | ||
4205a89b MZ |
88 | atomic_t arm64_el2_vector_last_slot = ATOMIC_INIT(-1); |
89 | ||
0f15adbb WD |
90 | #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR |
91 | #include <asm/mmu_context.h> | |
92 | #include <asm/cacheflush.h> | |
93 | ||
94 | DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); | |
95 | ||
e8b22d0f | 96 | #ifdef CONFIG_KVM_INDIRECT_VECTORS |
b092201e MZ |
97 | extern char __smccc_workaround_1_smc_start[]; |
98 | extern char __smccc_workaround_1_smc_end[]; | |
aa6acde6 | 99 | |
0f15adbb WD |
100 | static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start, |
101 | const char *hyp_vecs_end) | |
102 | { | |
103 | void *dst = lm_alias(__bp_harden_hyp_vecs_start + slot * SZ_2K); | |
104 | int i; | |
105 | ||
106 | for (i = 0; i < SZ_2K; i += 0x80) | |
107 | memcpy(dst + i, hyp_vecs_start, hyp_vecs_end - hyp_vecs_start); | |
108 | ||
3b8c9f1c | 109 | __flush_icache_range((uintptr_t)dst, (uintptr_t)dst + SZ_2K); |
0f15adbb WD |
110 | } |
111 | ||
112 | static void __install_bp_hardening_cb(bp_hardening_cb_t fn, | |
113 | const char *hyp_vecs_start, | |
114 | const char *hyp_vecs_end) | |
115 | { | |
0f15adbb WD |
116 | static DEFINE_SPINLOCK(bp_lock); |
117 | int cpu, slot = -1; | |
118 | ||
119 | spin_lock(&bp_lock); | |
120 | for_each_possible_cpu(cpu) { | |
121 | if (per_cpu(bp_hardening_data.fn, cpu) == fn) { | |
122 | slot = per_cpu(bp_hardening_data.hyp_vectors_slot, cpu); | |
123 | break; | |
124 | } | |
125 | } | |
126 | ||
127 | if (slot == -1) { | |
4205a89b MZ |
128 | slot = atomic_inc_return(&arm64_el2_vector_last_slot); |
129 | BUG_ON(slot >= BP_HARDEN_EL2_SLOTS); | |
0f15adbb WD |
130 | __copy_hyp_vect_bpi(slot, hyp_vecs_start, hyp_vecs_end); |
131 | } | |
132 | ||
133 | __this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot); | |
134 | __this_cpu_write(bp_hardening_data.fn, fn); | |
135 | spin_unlock(&bp_lock); | |
136 | } | |
137 | #else | |
b092201e MZ |
138 | #define __smccc_workaround_1_smc_start NULL |
139 | #define __smccc_workaround_1_smc_end NULL | |
aa6acde6 | 140 | |
0f15adbb WD |
141 | static void __install_bp_hardening_cb(bp_hardening_cb_t fn, |
142 | const char *hyp_vecs_start, | |
143 | const char *hyp_vecs_end) | |
144 | { | |
145 | __this_cpu_write(bp_hardening_data.fn, fn); | |
146 | } | |
e8b22d0f | 147 | #endif /* CONFIG_KVM_INDIRECT_VECTORS */ |
0f15adbb WD |
148 | |
149 | static void install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry, | |
150 | bp_hardening_cb_t fn, | |
151 | const char *hyp_vecs_start, | |
152 | const char *hyp_vecs_end) | |
153 | { | |
154 | u64 pfr0; | |
155 | ||
156 | if (!entry->matches(entry, SCOPE_LOCAL_CPU)) | |
157 | return; | |
158 | ||
159 | pfr0 = read_cpuid(ID_AA64PFR0_EL1); | |
160 | if (cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_CSV2_SHIFT)) | |
161 | return; | |
162 | ||
163 | __install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end); | |
164 | } | |
aa6acde6 | 165 | |
b092201e MZ |
166 | #include <uapi/linux/psci.h> |
167 | #include <linux/arm-smccc.h> | |
aa6acde6 WD |
168 | #include <linux/psci.h> |
169 | ||
b092201e MZ |
170 | static void call_smc_arch_workaround_1(void) |
171 | { | |
172 | arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL); | |
173 | } | |
174 | ||
175 | static void call_hvc_arch_workaround_1(void) | |
176 | { | |
177 | arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL); | |
178 | } | |
179 | ||
4bc352ff SD |
180 | static void qcom_link_stack_sanitization(void) |
181 | { | |
182 | u64 tmp; | |
183 | ||
184 | asm volatile("mov %0, x30 \n" | |
185 | ".rept 16 \n" | |
186 | "bl . + 4 \n" | |
187 | ".endr \n" | |
188 | "mov x30, %0 \n" | |
189 | : "=&r" (tmp)); | |
190 | } | |
191 | ||
c0cda3b8 DM |
192 | static void |
193 | enable_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry) | |
b092201e MZ |
194 | { |
195 | bp_hardening_cb_t cb; | |
196 | void *smccc_start, *smccc_end; | |
197 | struct arm_smccc_res res; | |
4bc352ff | 198 | u32 midr = read_cpuid_id(); |
b092201e MZ |
199 | |
200 | if (!entry->matches(entry, SCOPE_LOCAL_CPU)) | |
c0cda3b8 | 201 | return; |
b092201e MZ |
202 | |
203 | if (psci_ops.smccc_version == SMCCC_VERSION_1_0) | |
c0cda3b8 | 204 | return; |
b092201e MZ |
205 | |
206 | switch (psci_ops.conduit) { | |
207 | case PSCI_CONDUIT_HVC: | |
208 | arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, | |
209 | ARM_SMCCC_ARCH_WORKAROUND_1, &res); | |
e21da1c9 | 210 | if ((int)res.a0 < 0) |
c0cda3b8 | 211 | return; |
b092201e | 212 | cb = call_hvc_arch_workaround_1; |
22765f30 MZ |
213 | /* This is a guest, no need to patch KVM vectors */ |
214 | smccc_start = NULL; | |
215 | smccc_end = NULL; | |
b092201e MZ |
216 | break; |
217 | ||
218 | case PSCI_CONDUIT_SMC: | |
219 | arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, | |
220 | ARM_SMCCC_ARCH_WORKAROUND_1, &res); | |
e21da1c9 | 221 | if ((int)res.a0 < 0) |
c0cda3b8 | 222 | return; |
b092201e MZ |
223 | cb = call_smc_arch_workaround_1; |
224 | smccc_start = __smccc_workaround_1_smc_start; | |
225 | smccc_end = __smccc_workaround_1_smc_end; | |
226 | break; | |
227 | ||
228 | default: | |
c0cda3b8 | 229 | return; |
b092201e MZ |
230 | } |
231 | ||
4bc352ff SD |
232 | if (((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR) || |
233 | ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1)) | |
234 | cb = qcom_link_stack_sanitization; | |
235 | ||
b092201e MZ |
236 | install_bp_hardening_cb(entry, cb, smccc_start, smccc_end); |
237 | ||
c0cda3b8 | 238 | return; |
aa6acde6 | 239 | } |
0f15adbb WD |
240 | #endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */ |
241 | ||
8e290624 | 242 | #ifdef CONFIG_ARM64_SSBD |
5cf9ce6e MZ |
243 | DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required); |
244 | ||
a43ae4df MZ |
245 | int ssbd_state __read_mostly = ARM64_SSBD_KERNEL; |
246 | ||
247 | static const struct ssbd_options { | |
248 | const char *str; | |
249 | int state; | |
250 | } ssbd_options[] = { | |
251 | { "force-on", ARM64_SSBD_FORCE_ENABLE, }, | |
252 | { "force-off", ARM64_SSBD_FORCE_DISABLE, }, | |
253 | { "kernel", ARM64_SSBD_KERNEL, }, | |
254 | }; | |
255 | ||
256 | static int __init ssbd_cfg(char *buf) | |
257 | { | |
258 | int i; | |
259 | ||
260 | if (!buf || !buf[0]) | |
261 | return -EINVAL; | |
262 | ||
263 | for (i = 0; i < ARRAY_SIZE(ssbd_options); i++) { | |
264 | int len = strlen(ssbd_options[i].str); | |
265 | ||
266 | if (strncmp(buf, ssbd_options[i].str, len)) | |
267 | continue; | |
268 | ||
269 | ssbd_state = ssbd_options[i].state; | |
270 | return 0; | |
271 | } | |
272 | ||
273 | return -EINVAL; | |
274 | } | |
275 | early_param("ssbd", ssbd_cfg); | |
276 | ||
8e290624 MZ |
277 | void __init arm64_update_smccc_conduit(struct alt_instr *alt, |
278 | __le32 *origptr, __le32 *updptr, | |
279 | int nr_inst) | |
280 | { | |
281 | u32 insn; | |
282 | ||
283 | BUG_ON(nr_inst != 1); | |
284 | ||
285 | switch (psci_ops.conduit) { | |
286 | case PSCI_CONDUIT_HVC: | |
287 | insn = aarch64_insn_get_hvc_value(); | |
288 | break; | |
289 | case PSCI_CONDUIT_SMC: | |
290 | insn = aarch64_insn_get_smc_value(); | |
291 | break; | |
292 | default: | |
293 | return; | |
294 | } | |
295 | ||
296 | *updptr = cpu_to_le32(insn); | |
297 | } | |
a725e3dd | 298 | |
986372c4 MZ |
299 | void __init arm64_enable_wa2_handling(struct alt_instr *alt, |
300 | __le32 *origptr, __le32 *updptr, | |
301 | int nr_inst) | |
302 | { | |
303 | BUG_ON(nr_inst != 1); | |
304 | /* | |
305 | * Only allow mitigation on EL1 entry/exit and guest | |
306 | * ARCH_WORKAROUND_2 handling if the SSBD state allows it to | |
307 | * be flipped. | |
308 | */ | |
309 | if (arm64_get_ssbd_state() == ARM64_SSBD_KERNEL) | |
310 | *updptr = cpu_to_le32(aarch64_insn_gen_nop()); | |
311 | } | |
312 | ||
647d0519 | 313 | void arm64_set_ssbd_mitigation(bool state) |
a725e3dd MZ |
314 | { |
315 | switch (psci_ops.conduit) { | |
316 | case PSCI_CONDUIT_HVC: | |
317 | arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_2, state, NULL); | |
318 | break; | |
319 | ||
320 | case PSCI_CONDUIT_SMC: | |
321 | arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2, state, NULL); | |
322 | break; | |
323 | ||
324 | default: | |
325 | WARN_ON_ONCE(1); | |
326 | break; | |
327 | } | |
328 | } | |
329 | ||
330 | static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, | |
331 | int scope) | |
332 | { | |
333 | struct arm_smccc_res res; | |
a43ae4df MZ |
334 | bool required = true; |
335 | s32 val; | |
a725e3dd MZ |
336 | |
337 | WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); | |
338 | ||
a43ae4df MZ |
339 | if (psci_ops.smccc_version == SMCCC_VERSION_1_0) { |
340 | ssbd_state = ARM64_SSBD_UNKNOWN; | |
a725e3dd | 341 | return false; |
a43ae4df | 342 | } |
a725e3dd | 343 | |
a725e3dd MZ |
344 | switch (psci_ops.conduit) { |
345 | case PSCI_CONDUIT_HVC: | |
346 | arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, | |
347 | ARM_SMCCC_ARCH_WORKAROUND_2, &res); | |
a725e3dd MZ |
348 | break; |
349 | ||
350 | case PSCI_CONDUIT_SMC: | |
351 | arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, | |
352 | ARM_SMCCC_ARCH_WORKAROUND_2, &res); | |
a725e3dd MZ |
353 | break; |
354 | ||
355 | default: | |
a43ae4df MZ |
356 | ssbd_state = ARM64_SSBD_UNKNOWN; |
357 | return false; | |
a725e3dd MZ |
358 | } |
359 | ||
a43ae4df MZ |
360 | val = (s32)res.a0; |
361 | ||
362 | switch (val) { | |
363 | case SMCCC_RET_NOT_SUPPORTED: | |
364 | ssbd_state = ARM64_SSBD_UNKNOWN; | |
365 | return false; | |
366 | ||
367 | case SMCCC_RET_NOT_REQUIRED: | |
368 | pr_info_once("%s mitigation not required\n", entry->desc); | |
369 | ssbd_state = ARM64_SSBD_MITIGATED; | |
370 | return false; | |
371 | ||
372 | case SMCCC_RET_SUCCESS: | |
373 | required = true; | |
374 | break; | |
375 | ||
376 | case 1: /* Mitigation not required on this CPU */ | |
377 | required = false; | |
378 | break; | |
379 | ||
380 | default: | |
381 | WARN_ON(1); | |
382 | return false; | |
383 | } | |
384 | ||
385 | switch (ssbd_state) { | |
386 | case ARM64_SSBD_FORCE_DISABLE: | |
387 | pr_info_once("%s disabled from command-line\n", entry->desc); | |
388 | arm64_set_ssbd_mitigation(false); | |
389 | required = false; | |
390 | break; | |
391 | ||
392 | case ARM64_SSBD_KERNEL: | |
393 | if (required) { | |
394 | __this_cpu_write(arm64_ssbd_callback_required, 1); | |
395 | arm64_set_ssbd_mitigation(true); | |
396 | } | |
397 | break; | |
398 | ||
399 | case ARM64_SSBD_FORCE_ENABLE: | |
400 | pr_info_once("%s forced from command-line\n", entry->desc); | |
a725e3dd | 401 | arm64_set_ssbd_mitigation(true); |
a43ae4df MZ |
402 | required = true; |
403 | break; | |
404 | ||
405 | default: | |
406 | WARN_ON(1); | |
407 | break; | |
a725e3dd MZ |
408 | } |
409 | ||
a43ae4df | 410 | return required; |
a725e3dd | 411 | } |
8e290624 MZ |
412 | #endif /* CONFIG_ARM64_SSBD */ |
413 | ||
5e7951ce SP |
414 | #define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \ |
415 | .matches = is_affected_midr_range, \ | |
1df31050 | 416 | .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max) |
5e7951ce SP |
417 | |
418 | #define CAP_MIDR_ALL_VERSIONS(model) \ | |
419 | .matches = is_affected_midr_range, \ | |
1df31050 | 420 | .midr_range = MIDR_ALL_VERSIONS(model) |
06f1494f | 421 | |
e8002e02 AB |
422 | #define MIDR_FIXED(rev, revidr_mask) \ |
423 | .fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}} | |
424 | ||
5e7951ce SP |
425 | #define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \ |
426 | .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ | |
427 | CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) | |
428 | ||
be5b2998 SP |
429 | #define CAP_MIDR_RANGE_LIST(list) \ |
430 | .matches = is_affected_midr_range_list, \ | |
431 | .midr_range_list = list | |
432 | ||
5e7951ce SP |
433 | /* Errata affecting a range of revisions of given model variant */ |
434 | #define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \ | |
435 | ERRATA_MIDR_RANGE(m, var, r_min, var, r_max) | |
436 | ||
437 | /* Errata affecting a single variant/revision of a model */ | |
438 | #define ERRATA_MIDR_REV(model, var, rev) \ | |
439 | ERRATA_MIDR_RANGE(model, var, rev, var, rev) | |
440 | ||
441 | /* Errata affecting all variants/revisions of a given a model */ | |
442 | #define ERRATA_MIDR_ALL_VERSIONS(model) \ | |
443 | .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ | |
444 | CAP_MIDR_ALL_VERSIONS(model) | |
445 | ||
be5b2998 SP |
446 | /* Errata affecting a list of midr ranges, with same work around */ |
447 | #define ERRATA_MIDR_RANGE_LIST(midr_list) \ | |
448 | .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ | |
449 | CAP_MIDR_RANGE_LIST(midr_list) | |
450 | ||
ba7d9233 SP |
451 | /* |
452 | * Generic helper for handling capabilties with multiple (match,enable) pairs | |
453 | * of call backs, sharing the same capability bit. | |
454 | * Iterate over each entry to see if at least one matches. | |
455 | */ | |
12eb3691 WD |
456 | static bool __maybe_unused |
457 | multi_entry_cap_matches(const struct arm64_cpu_capabilities *entry, int scope) | |
ba7d9233 SP |
458 | { |
459 | const struct arm64_cpu_capabilities *caps; | |
460 | ||
461 | for (caps = entry->match_list; caps->matches; caps++) | |
462 | if (caps->matches(caps, scope)) | |
463 | return true; | |
464 | ||
465 | return false; | |
466 | } | |
467 | ||
468 | /* | |
469 | * Take appropriate action for all matching entries in the shared capability | |
470 | * entry. | |
471 | */ | |
12eb3691 | 472 | static void __maybe_unused |
ba7d9233 SP |
473 | multi_entry_cap_cpu_enable(const struct arm64_cpu_capabilities *entry) |
474 | { | |
475 | const struct arm64_cpu_capabilities *caps; | |
301bcfac | 476 | |
ba7d9233 SP |
477 | for (caps = entry->match_list; caps->matches; caps++) |
478 | if (caps->matches(caps, SCOPE_LOCAL_CPU) && | |
479 | caps->cpu_enable) | |
480 | caps->cpu_enable(caps); | |
481 | } | |
482 | ||
be5b2998 SP |
483 | #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR |
484 | ||
485 | /* | |
486 | * List of CPUs where we need to issue a psci call to | |
487 | * harden the branch predictor. | |
488 | */ | |
489 | static const struct midr_range arm64_bp_harden_smccc_cpus[] = { | |
490 | MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), | |
491 | MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), | |
492 | MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), | |
493 | MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), | |
494 | MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), | |
495 | MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), | |
be5b2998 SP |
496 | MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1), |
497 | MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR), | |
0583a4ef | 498 | MIDR_ALL_VERSIONS(MIDR_NVIDIA_DENVER), |
be5b2998 SP |
499 | {}, |
500 | }; | |
501 | ||
502 | #endif | |
06f1494f | 503 | |
8892b718 MZ |
504 | #ifdef CONFIG_HARDEN_EL2_VECTORS |
505 | ||
506 | static const struct midr_range arm64_harden_el2_vectors[] = { | |
507 | MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), | |
508 | MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), | |
509 | {}, | |
510 | }; | |
511 | ||
dc6ed61d MZ |
512 | #endif |
513 | ||
359b7064 | 514 | const struct arm64_cpu_capabilities arm64_errata[] = { |
c0a01b84 AP |
515 | #if defined(CONFIG_ARM64_ERRATUM_826319) || \ |
516 | defined(CONFIG_ARM64_ERRATUM_827319) || \ | |
517 | defined(CONFIG_ARM64_ERRATUM_824069) | |
301bcfac AP |
518 | { |
519 | /* Cortex-A53 r0p[012] */ | |
520 | .desc = "ARM errata 826319, 827319, 824069", | |
521 | .capability = ARM64_WORKAROUND_CLEAN_CACHE, | |
5e7951ce | 522 | ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2), |
c0cda3b8 | 523 | .cpu_enable = cpu_enable_cache_maint_trap, |
301bcfac | 524 | }, |
c0a01b84 AP |
525 | #endif |
526 | #ifdef CONFIG_ARM64_ERRATUM_819472 | |
527 | { | |
528 | /* Cortex-A53 r0p[01] */ | |
529 | .desc = "ARM errata 819472", | |
530 | .capability = ARM64_WORKAROUND_CLEAN_CACHE, | |
5e7951ce | 531 | ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1), |
c0cda3b8 | 532 | .cpu_enable = cpu_enable_cache_maint_trap, |
c0a01b84 AP |
533 | }, |
534 | #endif | |
535 | #ifdef CONFIG_ARM64_ERRATUM_832075 | |
301bcfac | 536 | { |
5afaa1fc AP |
537 | /* Cortex-A57 r0p0 - r1p2 */ |
538 | .desc = "ARM erratum 832075", | |
539 | .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE, | |
5e7951ce SP |
540 | ERRATA_MIDR_RANGE(MIDR_CORTEX_A57, |
541 | 0, 0, | |
542 | 1, 2), | |
5afaa1fc | 543 | }, |
905e8c5d | 544 | #endif |
498cd5c3 MZ |
545 | #ifdef CONFIG_ARM64_ERRATUM_834220 |
546 | { | |
547 | /* Cortex-A57 r0p0 - r1p2 */ | |
548 | .desc = "ARM erratum 834220", | |
549 | .capability = ARM64_WORKAROUND_834220, | |
5e7951ce SP |
550 | ERRATA_MIDR_RANGE(MIDR_CORTEX_A57, |
551 | 0, 0, | |
552 | 1, 2), | |
498cd5c3 MZ |
553 | }, |
554 | #endif | |
ca79acca AB |
555 | #ifdef CONFIG_ARM64_ERRATUM_843419 |
556 | { | |
557 | /* Cortex-A53 r0p[01234] */ | |
558 | .desc = "ARM erratum 843419", | |
559 | .capability = ARM64_WORKAROUND_843419, | |
5e7951ce | 560 | ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4), |
ca79acca | 561 | MIDR_FIXED(0x4, BIT(8)), |
498cd5c3 MZ |
562 | }, |
563 | #endif | |
905e8c5d WD |
564 | #ifdef CONFIG_ARM64_ERRATUM_845719 |
565 | { | |
566 | /* Cortex-A53 r0p[01234] */ | |
567 | .desc = "ARM erratum 845719", | |
568 | .capability = ARM64_WORKAROUND_845719, | |
5e7951ce | 569 | ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4), |
905e8c5d | 570 | }, |
6d4e11c5 RR |
571 | #endif |
572 | #ifdef CONFIG_CAVIUM_ERRATUM_23154 | |
573 | { | |
574 | /* Cavium ThunderX, pass 1.x */ | |
575 | .desc = "Cavium erratum 23154", | |
576 | .capability = ARM64_WORKAROUND_CAVIUM_23154, | |
5e7951ce | 577 | ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX, 0, 0, 1), |
6d4e11c5 | 578 | }, |
104a0c02 AP |
579 | #endif |
580 | #ifdef CONFIG_CAVIUM_ERRATUM_27456 | |
581 | { | |
582 | /* Cavium ThunderX, T88 pass 1.x - 2.1 */ | |
583 | .desc = "Cavium erratum 27456", | |
584 | .capability = ARM64_WORKAROUND_CAVIUM_27456, | |
5e7951ce SP |
585 | ERRATA_MIDR_RANGE(MIDR_THUNDERX, |
586 | 0, 0, | |
587 | 1, 1), | |
104a0c02 | 588 | }, |
47c459be GK |
589 | { |
590 | /* Cavium ThunderX, T81 pass 1.0 */ | |
591 | .desc = "Cavium erratum 27456", | |
592 | .capability = ARM64_WORKAROUND_CAVIUM_27456, | |
5e7951ce | 593 | ERRATA_MIDR_REV(MIDR_THUNDERX_81XX, 0, 0), |
47c459be | 594 | }, |
690a3415 DD |
595 | #endif |
596 | #ifdef CONFIG_CAVIUM_ERRATUM_30115 | |
597 | { | |
598 | /* Cavium ThunderX, T88 pass 1.x - 2.2 */ | |
599 | .desc = "Cavium erratum 30115", | |
600 | .capability = ARM64_WORKAROUND_CAVIUM_30115, | |
5e7951ce SP |
601 | ERRATA_MIDR_RANGE(MIDR_THUNDERX, |
602 | 0, 0, | |
603 | 1, 2), | |
690a3415 DD |
604 | }, |
605 | { | |
606 | /* Cavium ThunderX, T81 pass 1.0 - 1.2 */ | |
607 | .desc = "Cavium erratum 30115", | |
608 | .capability = ARM64_WORKAROUND_CAVIUM_30115, | |
5e7951ce | 609 | ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2), |
690a3415 DD |
610 | }, |
611 | { | |
612 | /* Cavium ThunderX, T83 pass 1.0 */ | |
613 | .desc = "Cavium erratum 30115", | |
614 | .capability = ARM64_WORKAROUND_CAVIUM_30115, | |
5e7951ce | 615 | ERRATA_MIDR_REV(MIDR_THUNDERX_83XX, 0, 0), |
690a3415 | 616 | }, |
c0a01b84 | 617 | #endif |
116c81f4 SP |
618 | { |
619 | .desc = "Mismatched cache line size", | |
620 | .capability = ARM64_MISMATCHED_CACHE_LINE_SIZE, | |
314d53d2 SP |
621 | .matches = has_mismatched_cache_type, |
622 | .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, | |
623 | .cpu_enable = cpu_enable_trap_ctr_access, | |
624 | }, | |
625 | { | |
626 | .desc = "Mismatched cache type", | |
627 | .capability = ARM64_MISMATCHED_CACHE_TYPE, | |
628 | .matches = has_mismatched_cache_type, | |
5b4747c5 | 629 | .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, |
c0cda3b8 | 630 | .cpu_enable = cpu_enable_trap_ctr_access, |
116c81f4 | 631 | }, |
38fd94b0 CC |
632 | #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 |
633 | { | |
634 | .desc = "Qualcomm Technologies Falkor erratum 1003", | |
635 | .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003, | |
5e7951ce | 636 | ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0), |
38fd94b0 | 637 | }, |
bb487118 SB |
638 | { |
639 | .desc = "Qualcomm Technologies Kryo erratum 1003", | |
640 | .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003, | |
5b4747c5 | 641 | .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, |
1df31050 | 642 | .midr_range.model = MIDR_QCOM_KRYO, |
bb487118 SB |
643 | .matches = is_kryo_midr, |
644 | }, | |
38fd94b0 | 645 | #endif |
d9ff80f8 CC |
646 | #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009 |
647 | { | |
648 | .desc = "Qualcomm Technologies Falkor erratum 1009", | |
649 | .capability = ARM64_WORKAROUND_REPEAT_TLBI, | |
5e7951ce | 650 | ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0), |
d9ff80f8 | 651 | }, |
eeb1efbc MZ |
652 | #endif |
653 | #ifdef CONFIG_ARM64_ERRATUM_858921 | |
654 | { | |
655 | /* Cortex-A73 all versions */ | |
656 | .desc = "ARM erratum 858921", | |
657 | .capability = ARM64_WORKAROUND_858921, | |
5e7951ce | 658 | ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), |
eeb1efbc | 659 | }, |
aa6acde6 WD |
660 | #endif |
661 | #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR | |
662 | { | |
663 | .capability = ARM64_HARDEN_BRANCH_PREDICTOR, | |
4bc352ff SD |
664 | .cpu_enable = enable_smccc_arch_workaround_1, |
665 | ERRATA_MIDR_RANGE_LIST(arm64_bp_harden_smccc_cpus), | |
f3d795d9 | 666 | }, |
4b472ffd MZ |
667 | #endif |
668 | #ifdef CONFIG_HARDEN_EL2_VECTORS | |
669 | { | |
8892b718 | 670 | .desc = "EL2 vector hardening", |
4b472ffd | 671 | .capability = ARM64_HARDEN_EL2_VECTORS, |
8892b718 | 672 | ERRATA_MIDR_RANGE_LIST(arm64_harden_el2_vectors), |
4b472ffd | 673 | }, |
a725e3dd MZ |
674 | #endif |
675 | #ifdef CONFIG_ARM64_SSBD | |
676 | { | |
677 | .desc = "Speculative Store Bypass Disable", | |
678 | .capability = ARM64_SSBD, | |
679 | .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, | |
680 | .matches = has_ssbd_mitigation, | |
681 | }, | |
d9ff80f8 | 682 | #endif |
5afaa1fc | 683 | { |
301bcfac | 684 | } |
e116a375 | 685 | }; |