[mirror_ubuntu-jammy-kernel.git] / arch / arm64 / kernel / cpu_errata.c

/*
 * Contains CPU specific errata definitions
 *
 * Copyright (C) 2014 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/types.h>
#include <asm/cpu.h>
#include <asm/cputype.h>
#include <asm/cpufeature.h>

static bool __maybe_unused
is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
{
	const struct arm64_midr_revidr *fix;
	u32 midr = read_cpuid_id(), revidr;

	WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
	if (!MIDR_IS_CPU_MODEL_RANGE(midr, entry->midr_model,
				     entry->midr_range_min,
				     entry->midr_range_max))
		return false;

	midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
	revidr = read_cpuid(REVIDR_EL1);
	for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
		if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
			return false;

	return true;
}

static bool __maybe_unused
is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
{
	u32 model;

	WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());

	model = read_cpuid_id();
	model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |
		 MIDR_ARCHITECTURE_MASK;

	return model == entry->midr_model;
}

static bool
has_mismatched_cache_line_size(const struct arm64_cpu_capabilities *entry,
				int scope)
{
	WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
	return (read_cpuid_cachetype() & arm64_ftr_reg_ctrel0.strict_mask) !=
		(arm64_ftr_reg_ctrel0.sys_val & arm64_ftr_reg_ctrel0.strict_mask);
}

static void
cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *__unused)
{
	/* Clear SCTLR_EL1.UCT */
	config_sctlr_el1(SCTLR_EL1_UCT, 0);
}

#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
#include <asm/mmu_context.h>
#include <asm/cacheflush.h>

DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);

#ifdef CONFIG_KVM
extern char __qcom_hyp_sanitize_link_stack_start[];
extern char __qcom_hyp_sanitize_link_stack_end[];
extern char __smccc_workaround_1_smc_start[];
extern char __smccc_workaround_1_smc_end[];
extern char __smccc_workaround_1_hvc_start[];
extern char __smccc_workaround_1_hvc_end[];

static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start,
				const char *hyp_vecs_end)
{
	void *dst = lm_alias(__bp_harden_hyp_vecs_start + slot * SZ_2K);
	int i;

	for (i = 0; i < SZ_2K; i += 0x80)
		memcpy(dst + i, hyp_vecs_start, hyp_vecs_end - hyp_vecs_start);

	flush_icache_range((uintptr_t)dst, (uintptr_t)dst + SZ_2K);
}

static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
				      const char *hyp_vecs_start,
				      const char *hyp_vecs_end)
{
	static int last_slot = -1;
	static DEFINE_SPINLOCK(bp_lock);
	int cpu, slot = -1;

	spin_lock(&bp_lock);
	for_each_possible_cpu(cpu) {
		if (per_cpu(bp_hardening_data.fn, cpu) == fn) {
			slot = per_cpu(bp_hardening_data.hyp_vectors_slot, cpu);
			break;
		}
	}

	if (slot == -1) {
		last_slot++;
		BUG_ON(((__bp_harden_hyp_vecs_end - __bp_harden_hyp_vecs_start)
			/ SZ_2K) <= last_slot);
		slot = last_slot;
		__copy_hyp_vect_bpi(slot, hyp_vecs_start, hyp_vecs_end);
	}

	__this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot);
	__this_cpu_write(bp_hardening_data.fn, fn);
	spin_unlock(&bp_lock);
}
#else
#define __qcom_hyp_sanitize_link_stack_start	NULL
#define __qcom_hyp_sanitize_link_stack_end	NULL
#define __smccc_workaround_1_smc_start		NULL
#define __smccc_workaround_1_smc_end		NULL
#define __smccc_workaround_1_hvc_start		NULL
#define __smccc_workaround_1_hvc_end		NULL

static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
				      const char *hyp_vecs_start,
				      const char *hyp_vecs_end)
{
	__this_cpu_write(bp_hardening_data.fn, fn);
}
#endif	/* CONFIG_KVM */

static void  install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry,
				     bp_hardening_cb_t fn,
				     const char *hyp_vecs_start,
				     const char *hyp_vecs_end)
{
	u64 pfr0;

	if (!entry->matches(entry, SCOPE_LOCAL_CPU))
		return;

	pfr0 = read_cpuid(ID_AA64PFR0_EL1);
	if (cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_CSV2_SHIFT))
		return;

	__install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end);
}

#include <uapi/linux/psci.h>
#include <linux/arm-smccc.h>
#include <linux/psci.h>

static void call_smc_arch_workaround_1(void)
{
	arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
}

static void call_hvc_arch_workaround_1(void)
{
	arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
}

static void
enable_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry)
{
	bp_hardening_cb_t cb;
	void *smccc_start, *smccc_end;
	struct arm_smccc_res res;

	if (!entry->matches(entry, SCOPE_LOCAL_CPU))
		return;

	if (psci_ops.smccc_version == SMCCC_VERSION_1_0)
		return;

	switch (psci_ops.conduit) {
	case PSCI_CONDUIT_HVC:
		arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
				  ARM_SMCCC_ARCH_WORKAROUND_1, &res);
		if (res.a0)
			return;
		cb = call_hvc_arch_workaround_1;
		smccc_start = __smccc_workaround_1_hvc_start;
		smccc_end = __smccc_workaround_1_hvc_end;
		break;

	case PSCI_CONDUIT_SMC:
		arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
				  ARM_SMCCC_ARCH_WORKAROUND_1, &res);
		if (res.a0)
			return;
		cb = call_smc_arch_workaround_1;
		smccc_start = __smccc_workaround_1_smc_start;
		smccc_end = __smccc_workaround_1_smc_end;
		break;

	default:
		return;
	}

	install_bp_hardening_cb(entry, cb, smccc_start, smccc_end);

	return;
}

static void qcom_link_stack_sanitization(void)
{
	u64 tmp;

	asm volatile("mov	%0, x30		\n"
		     ".rept	16		\n"
		     "bl	. + 4		\n"
		     ".endr			\n"
		     "mov	x30, %0		\n"
		     : "=&r" (tmp));
}

static void
qcom_enable_link_stack_sanitization(const struct arm64_cpu_capabilities *entry)
{
	install_bp_hardening_cb(entry, qcom_link_stack_sanitization,
				__qcom_hyp_sanitize_link_stack_start,
				__qcom_hyp_sanitize_link_stack_end);
}
#endif	/* CONFIG_HARDEN_BRANCH_PREDICTOR */

#define MIDR_RANGE(model, min, max) \
	.type = ARM64_CPUCAP_SCOPE_LOCAL_CPU, \
	.matches = is_affected_midr_range, \
	.midr_model = model, \
	.midr_range_min = min, \
	.midr_range_max = max

#define MIDR_ALL_VERSIONS(model) \
	.type = ARM64_CPUCAP_SCOPE_LOCAL_CPU, \
	.matches = is_affected_midr_range, \
	.midr_model = model, \
	.midr_range_min = 0, \
	.midr_range_max = (MIDR_VARIANT_MASK | MIDR_REVISION_MASK)

#define MIDR_FIXED(rev, revidr_mask) \
	.fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}

const struct arm64_cpu_capabilities arm64_errata[] = {
#if	defined(CONFIG_ARM64_ERRATUM_826319) || \
	defined(CONFIG_ARM64_ERRATUM_827319) || \
	defined(CONFIG_ARM64_ERRATUM_824069)
	{
	/* Cortex-A53 r0p[012] */
		.desc = "ARM errata 826319, 827319, 824069",
		.capability = ARM64_WORKAROUND_CLEAN_CACHE,
		MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02),
		.cpu_enable = cpu_enable_cache_maint_trap,
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_819472
	{
	/* Cortex-A53 r0p[01] */
		.desc = "ARM errata 819472",
		.capability = ARM64_WORKAROUND_CLEAN_CACHE,
		MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x01),
		.cpu_enable = cpu_enable_cache_maint_trap,
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_832075
	{
	/* Cortex-A57 r0p0 - r1p2 */
		.desc = "ARM erratum 832075",
		.capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
		MIDR_RANGE(MIDR_CORTEX_A57,
			   MIDR_CPU_VAR_REV(0, 0),
			   MIDR_CPU_VAR_REV(1, 2)),
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_834220
	{
	/* Cortex-A57 r0p0 - r1p2 */
		.desc = "ARM erratum 834220",
		.capability = ARM64_WORKAROUND_834220,
		MIDR_RANGE(MIDR_CORTEX_A57,
			   MIDR_CPU_VAR_REV(0, 0),
			   MIDR_CPU_VAR_REV(1, 2)),
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_843419
	{
	/* Cortex-A53 r0p[01234] */
		.desc = "ARM erratum 843419",
		.capability = ARM64_WORKAROUND_843419,
		MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04),
		MIDR_FIXED(0x4, BIT(8)),
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_845719
	{
	/* Cortex-A53 r0p[01234] */
		.desc = "ARM erratum 845719",
		.capability = ARM64_WORKAROUND_845719,
		MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04),
	},
#endif
#ifdef CONFIG_CAVIUM_ERRATUM_23154
	{
	/* Cavium ThunderX, pass 1.x */
		.desc = "Cavium erratum 23154",
		.capability = ARM64_WORKAROUND_CAVIUM_23154,
		MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01),
	},
#endif
#ifdef CONFIG_CAVIUM_ERRATUM_27456
	{
	/* Cavium ThunderX, T88 pass 1.x - 2.1 */
		.desc = "Cavium erratum 27456",
		.capability = ARM64_WORKAROUND_CAVIUM_27456,
		MIDR_RANGE(MIDR_THUNDERX,
			   MIDR_CPU_VAR_REV(0, 0),
			   MIDR_CPU_VAR_REV(1, 1)),
	},
	{
	/* Cavium ThunderX, T81 pass 1.0 */
		.desc = "Cavium erratum 27456",
		.capability = ARM64_WORKAROUND_CAVIUM_27456,
		MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x00),
	},
#endif
#ifdef CONFIG_CAVIUM_ERRATUM_30115
	{
	/* Cavium ThunderX, T88 pass 1.x - 2.2 */
		.desc = "Cavium erratum 30115",
		.capability = ARM64_WORKAROUND_CAVIUM_30115,
		MIDR_RANGE(MIDR_THUNDERX, 0x00,
			   (1 << MIDR_VARIANT_SHIFT) | 2),
	},
	{
	/* Cavium ThunderX, T81 pass 1.0 - 1.2 */
		.desc = "Cavium erratum 30115",
		.capability = ARM64_WORKAROUND_CAVIUM_30115,
		MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x02),
	},
	{
	/* Cavium ThunderX, T83 pass 1.0 */
		.desc = "Cavium erratum 30115",
		.capability = ARM64_WORKAROUND_CAVIUM_30115,
		MIDR_RANGE(MIDR_THUNDERX_83XX, 0x00, 0x00),
	},
#endif
	{
		.desc = "Mismatched cache line size",
		.capability = ARM64_MISMATCHED_CACHE_LINE_SIZE,
		.matches = has_mismatched_cache_line_size,
		.type = ARM64_CPUCAP_SCOPE_LOCAL_CPU,
		.cpu_enable = cpu_enable_trap_ctr_access,
	},
#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
	{
		.desc = "Qualcomm Technologies Falkor erratum 1003",
		.capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
		MIDR_RANGE(MIDR_QCOM_FALKOR_V1,
			   MIDR_CPU_VAR_REV(0, 0),
			   MIDR_CPU_VAR_REV(0, 0)),
	},
	{
		.desc = "Qualcomm Technologies Kryo erratum 1003",
		.capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
		.type = ARM64_CPUCAP_SCOPE_LOCAL_CPU,
		.midr_model = MIDR_QCOM_KRYO,
		.matches = is_kryo_midr,
	},
#endif
#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
	{
		.desc = "Qualcomm Technologies Falkor erratum 1009",
		.capability = ARM64_WORKAROUND_REPEAT_TLBI,
		MIDR_RANGE(MIDR_QCOM_FALKOR_V1,
			   MIDR_CPU_VAR_REV(0, 0),
			   MIDR_CPU_VAR_REV(0, 0)),
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_858921
	{
	/* Cortex-A73 all versions */
		.desc = "ARM erratum 858921",
		.capability = ARM64_WORKAROUND_858921,
		MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
	},
#endif
#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
	{
		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
		MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
		.cpu_enable = enable_smccc_arch_workaround_1,
	},
	{
		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
		MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
		.cpu_enable = enable_smccc_arch_workaround_1,
	},
	{
		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
		MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
		.cpu_enable = enable_smccc_arch_workaround_1,
	},
	{
		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
		MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
		.cpu_enable = enable_smccc_arch_workaround_1,
	},
	{
		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
		MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
		.cpu_enable = qcom_enable_link_stack_sanitization,
	},
	{
		.capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,
		MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
	},
	{
		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
		MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
		.cpu_enable = qcom_enable_link_stack_sanitization,
	},
	{
		.capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,
		MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
	},
	{
		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
		MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
		.cpu_enable = enable_smccc_arch_workaround_1,
	},
	{
		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
		MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
		.cpu_enable = enable_smccc_arch_workaround_1,
	},
#endif
	{
	}
};
Commit	Line	Data
e116a375 AP	1	/*
	2	* Contains CPU specific errata definitions
	3	*
	4	* Copyright (C) 2014 ARM Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	17	*/
	18
e116a375 AP	19	#include <linux/types.h>
	20	#include <asm/cpu.h>
	21	#include <asm/cputype.h>
	22	#include <asm/cpufeature.h>
	23
301bcfac	24	static bool __maybe_unused
92406f0c	25	is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
301bcfac	26	{
e8002e02 AB	27	const struct arm64_midr_revidr *fix;
	28	u32 midr = read_cpuid_id(), revidr;
	29
92406f0c	30	WARN_ON(scope != SCOPE_LOCAL_CPU \|\| preemptible());
e8002e02 AB	31	if (!MIDR_IS_CPU_MODEL_RANGE(midr, entry->midr_model,
	32	entry->midr_range_min,
	33	entry->midr_range_max))
	34	return false;
	35
	36	midr &= MIDR_REVISION_MASK \| MIDR_VARIANT_MASK;
	37	revidr = read_cpuid(REVIDR_EL1);
	38	for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
	39	if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
	40	return false;
	41
	42	return true;
301bcfac AP	43	}
301bcfac AP	44
bb487118 SB	45	static bool __maybe_unused
	46	is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
	47	{
	48	u32 model;
	49
	50	WARN_ON(scope != SCOPE_LOCAL_CPU \|\| preemptible());
	51
	52	model = read_cpuid_id();
	53	model &= MIDR_IMPLEMENTOR_MASK \| (0xf00 << MIDR_PARTNUM_SHIFT) \|
	54	MIDR_ARCHITECTURE_MASK;
	55
	56	return model == entry->midr_model;
	57	}
	58
116c81f4 SP	59	static bool
	60	has_mismatched_cache_line_size(const struct arm64_cpu_capabilities *entry,
	61	int scope)
	62	{
	63	WARN_ON(scope != SCOPE_LOCAL_CPU \|\| preemptible());
	64	return (read_cpuid_cachetype() & arm64_ftr_reg_ctrel0.strict_mask) !=
	65	(arm64_ftr_reg_ctrel0.sys_val & arm64_ftr_reg_ctrel0.strict_mask);
	66	}
	67
c0cda3b8 DM	68	static void
c0cda3b8 DM	69	cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *__unused)
116c81f4 SP	70	{
	71	/* Clear SCTLR_EL1.UCT */
	72	config_sctlr_el1(SCTLR_EL1_UCT, 0);
	73	}
	74
0f15adbb WD	75	#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
	76	#include <asm/mmu_context.h>
	77	#include <asm/cacheflush.h>
	78
	79	DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);
	80
	81	#ifdef CONFIG_KVM
ec82b567 SD	82	extern char __qcom_hyp_sanitize_link_stack_start[];
ec82b567 SD	83	extern char __qcom_hyp_sanitize_link_stack_end[];
b092201e MZ	84	extern char __smccc_workaround_1_smc_start[];
	85	extern char __smccc_workaround_1_smc_end[];
	86	extern char __smccc_workaround_1_hvc_start[];
	87	extern char __smccc_workaround_1_hvc_end[];
aa6acde6	88
0f15adbb WD	89	static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start,
	90	const char *hyp_vecs_end)
	91	{
	92	void dst = lm_alias(__bp_harden_hyp_vecs_start + slot SZ_2K);
	93	int i;
	94
	95	for (i = 0; i < SZ_2K; i += 0x80)
	96	memcpy(dst + i, hyp_vecs_start, hyp_vecs_end - hyp_vecs_start);
	97
	98	flush_icache_range((uintptr_t)dst, (uintptr_t)dst + SZ_2K);
	99	}
	100
	101	static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
	102	const char *hyp_vecs_start,
	103	const char *hyp_vecs_end)
	104	{
	105	static int last_slot = -1;
	106	static DEFINE_SPINLOCK(bp_lock);
	107	int cpu, slot = -1;
	108
	109	spin_lock(&bp_lock);
	110	for_each_possible_cpu(cpu) {
	111	if (per_cpu(bp_hardening_data.fn, cpu) == fn) {
	112	slot = per_cpu(bp_hardening_data.hyp_vectors_slot, cpu);
	113	break;
	114	}
	115	}
	116
	117	if (slot == -1) {
	118	last_slot++;
	119	BUG_ON(((__bp_harden_hyp_vecs_end - __bp_harden_hyp_vecs_start)
	120	/ SZ_2K) <= last_slot);
	121	slot = last_slot;
	122	__copy_hyp_vect_bpi(slot, hyp_vecs_start, hyp_vecs_end);
	123	}
	124
	125	__this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot);
	126	__this_cpu_write(bp_hardening_data.fn, fn);
	127	spin_unlock(&bp_lock);
	128	}
	129	#else
ec82b567 SD	130	#define __qcom_hyp_sanitize_link_stack_start NULL
ec82b567 SD	131	#define __qcom_hyp_sanitize_link_stack_end NULL
b092201e MZ	132	#define __smccc_workaround_1_smc_start NULL
	133	#define __smccc_workaround_1_smc_end NULL
	134	#define __smccc_workaround_1_hvc_start NULL
	135	#define __smccc_workaround_1_hvc_end NULL
aa6acde6	136
0f15adbb WD	137	static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
	138	const char *hyp_vecs_start,
	139	const char *hyp_vecs_end)
	140	{
	141	__this_cpu_write(bp_hardening_data.fn, fn);
	142	}
	143	#endif /* CONFIG_KVM */
	144
	145	static void install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry,
	146	bp_hardening_cb_t fn,
	147	const char *hyp_vecs_start,
	148	const char *hyp_vecs_end)
	149	{
	150	u64 pfr0;
	151
	152	if (!entry->matches(entry, SCOPE_LOCAL_CPU))
	153	return;
	154
	155	pfr0 = read_cpuid(ID_AA64PFR0_EL1);
	156	if (cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_CSV2_SHIFT))
	157	return;
	158
	159	__install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end);
	160	}
aa6acde6	161
b092201e MZ	162	#include <uapi/linux/psci.h>
b092201e MZ	163	#include <linux/arm-smccc.h>
aa6acde6 WD	164	#include <linux/psci.h>
aa6acde6 WD	165
b092201e MZ	166	static void call_smc_arch_workaround_1(void)
	167	{
	168	arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
	169	}
	170
	171	static void call_hvc_arch_workaround_1(void)
	172	{
	173	arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
	174	}
	175
c0cda3b8 DM	176	static void
c0cda3b8 DM	177	enable_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry)
b092201e MZ	178	{
	179	bp_hardening_cb_t cb;
	180	void smccc_start, smccc_end;
	181	struct arm_smccc_res res;
	182
	183	if (!entry->matches(entry, SCOPE_LOCAL_CPU))
c0cda3b8	184	return;
b092201e MZ	185
b092201e MZ	186	if (psci_ops.smccc_version == SMCCC_VERSION_1_0)
c0cda3b8	187	return;
b092201e MZ	188
	189	switch (psci_ops.conduit) {
	190	case PSCI_CONDUIT_HVC:
	191	arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
	192	ARM_SMCCC_ARCH_WORKAROUND_1, &res);
	193	if (res.a0)
c0cda3b8	194	return;
b092201e MZ	195	cb = call_hvc_arch_workaround_1;
	196	smccc_start = __smccc_workaround_1_hvc_start;
	197	smccc_end = __smccc_workaround_1_hvc_end;
	198	break;
	199
	200	case PSCI_CONDUIT_SMC:
	201	arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
	202	ARM_SMCCC_ARCH_WORKAROUND_1, &res);
	203	if (res.a0)
c0cda3b8	204	return;
b092201e MZ	205	cb = call_smc_arch_workaround_1;
	206	smccc_start = __smccc_workaround_1_smc_start;
	207	smccc_end = __smccc_workaround_1_smc_end;
	208	break;
	209
	210	default:
c0cda3b8	211	return;
b092201e MZ	212	}
	213
	214	install_bp_hardening_cb(entry, cb, smccc_start, smccc_end);
	215
c0cda3b8	216	return;
aa6acde6	217	}
ec82b567 SD	218
	219	static void qcom_link_stack_sanitization(void)
	220	{
	221	u64 tmp;
	222
	223	asm volatile("mov %0, x30 \n"
	224	".rept 16 \n"
	225	"bl . + 4 \n"
	226	".endr \n"
	227	"mov x30, %0 \n"
	228	: "=&r" (tmp));
	229	}
	230
c0cda3b8 DM	231	static void
c0cda3b8 DM	232	qcom_enable_link_stack_sanitization(const struct arm64_cpu_capabilities *entry)
ec82b567	233	{
ec82b567 SD	234	install_bp_hardening_cb(entry, qcom_link_stack_sanitization,
	235	__qcom_hyp_sanitize_link_stack_start,
	236	__qcom_hyp_sanitize_link_stack_end);
ec82b567	237	}
0f15adbb WD	238	#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */
0f15adbb WD	239
301bcfac	240	#define MIDR_RANGE(model, min, max) \
143ba05d	241	.type = ARM64_CPUCAP_SCOPE_LOCAL_CPU, \
359b7064	242	.matches = is_affected_midr_range, \
301bcfac AP	243	.midr_model = model, \
	244	.midr_range_min = min, \
	245	.midr_range_max = max
	246
06f1494f	247	#define MIDR_ALL_VERSIONS(model) \
143ba05d	248	.type = ARM64_CPUCAP_SCOPE_LOCAL_CPU, \
06f1494f MZ	249	.matches = is_affected_midr_range, \
	250	.midr_model = model, \
	251	.midr_range_min = 0, \
	252	.midr_range_max = (MIDR_VARIANT_MASK \| MIDR_REVISION_MASK)
	253
e8002e02 AB	254	#define MIDR_FIXED(rev, revidr_mask) \
	255	.fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}
	256
359b7064	257	const struct arm64_cpu_capabilities arm64_errata[] = {
c0a01b84 AP	258	#if defined(CONFIG_ARM64_ERRATUM_826319) \|\| \
	259	defined(CONFIG_ARM64_ERRATUM_827319) \|\| \
	260	defined(CONFIG_ARM64_ERRATUM_824069)
301bcfac AP	261	{
	262	/* Cortex-A53 r0p[012] */
	263	.desc = "ARM errata 826319, 827319, 824069",
	264	.capability = ARM64_WORKAROUND_CLEAN_CACHE,
	265	MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02),
c0cda3b8	266	.cpu_enable = cpu_enable_cache_maint_trap,
301bcfac	267	},
c0a01b84 AP	268	#endif
	269	#ifdef CONFIG_ARM64_ERRATUM_819472
	270	{
	271	/* Cortex-A53 r0p[01] */
	272	.desc = "ARM errata 819472",
	273	.capability = ARM64_WORKAROUND_CLEAN_CACHE,
	274	MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x01),
c0cda3b8	275	.cpu_enable = cpu_enable_cache_maint_trap,
c0a01b84 AP	276	},
	277	#endif
	278	#ifdef CONFIG_ARM64_ERRATUM_832075
301bcfac	279	{
5afaa1fc AP	280	/* Cortex-A57 r0p0 - r1p2 */
	281	.desc = "ARM erratum 832075",
	282	.capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
fa5ce3d1 RR	283	MIDR_RANGE(MIDR_CORTEX_A57,
	284	MIDR_CPU_VAR_REV(0, 0),
	285	MIDR_CPU_VAR_REV(1, 2)),
5afaa1fc	286	},
905e8c5d	287	#endif
498cd5c3 MZ	288	#ifdef CONFIG_ARM64_ERRATUM_834220
	289	{
	290	/* Cortex-A57 r0p0 - r1p2 */
	291	.desc = "ARM erratum 834220",
	292	.capability = ARM64_WORKAROUND_834220,
fa5ce3d1 RR	293	MIDR_RANGE(MIDR_CORTEX_A57,
	294	MIDR_CPU_VAR_REV(0, 0),
	295	MIDR_CPU_VAR_REV(1, 2)),
498cd5c3 MZ	296	},
498cd5c3 MZ	297	#endif
ca79acca AB	298	#ifdef CONFIG_ARM64_ERRATUM_843419
	299	{
	300	/* Cortex-A53 r0p[01234] */
	301	.desc = "ARM erratum 843419",
	302	.capability = ARM64_WORKAROUND_843419,
	303	MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04),
	304	MIDR_FIXED(0x4, BIT(8)),
	305	},
	306	#endif
905e8c5d WD	307	#ifdef CONFIG_ARM64_ERRATUM_845719
	308	{
	309	/* Cortex-A53 r0p[01234] */
	310	.desc = "ARM erratum 845719",
	311	.capability = ARM64_WORKAROUND_845719,
	312	MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04),
	313	},
6d4e11c5 RR	314	#endif
	315	#ifdef CONFIG_CAVIUM_ERRATUM_23154
	316	{
	317	/* Cavium ThunderX, pass 1.x */
	318	.desc = "Cavium erratum 23154",
	319	.capability = ARM64_WORKAROUND_CAVIUM_23154,
	320	MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01),
	321	},
104a0c02 AP	322	#endif
	323	#ifdef CONFIG_CAVIUM_ERRATUM_27456
	324	{
	325	/* Cavium ThunderX, T88 pass 1.x - 2.1 */
	326	.desc = "Cavium erratum 27456",
	327	.capability = ARM64_WORKAROUND_CAVIUM_27456,
fa5ce3d1 RR	328	MIDR_RANGE(MIDR_THUNDERX,
	329	MIDR_CPU_VAR_REV(0, 0),
	330	MIDR_CPU_VAR_REV(1, 1)),
104a0c02	331	},
47c459be GK	332	{
	333	/* Cavium ThunderX, T81 pass 1.0 */
	334	.desc = "Cavium erratum 27456",
	335	.capability = ARM64_WORKAROUND_CAVIUM_27456,
	336	MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x00),
	337	},
690a3415 DD	338	#endif
	339	#ifdef CONFIG_CAVIUM_ERRATUM_30115
	340	{
	341	/* Cavium ThunderX, T88 pass 1.x - 2.2 */
	342	.desc = "Cavium erratum 30115",
	343	.capability = ARM64_WORKAROUND_CAVIUM_30115,
	344	MIDR_RANGE(MIDR_THUNDERX, 0x00,
	345	(1 << MIDR_VARIANT_SHIFT) \| 2),
	346	},
	347	{
	348	/* Cavium ThunderX, T81 pass 1.0 - 1.2 */
	349	.desc = "Cavium erratum 30115",
	350	.capability = ARM64_WORKAROUND_CAVIUM_30115,
	351	MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x02),
	352	},
	353	{
	354	/* Cavium ThunderX, T83 pass 1.0 */
	355	.desc = "Cavium erratum 30115",
	356	.capability = ARM64_WORKAROUND_CAVIUM_30115,
	357	MIDR_RANGE(MIDR_THUNDERX_83XX, 0x00, 0x00),
	358	},
c0a01b84	359	#endif
116c81f4 SP	360	{
	361	.desc = "Mismatched cache line size",
	362	.capability = ARM64_MISMATCHED_CACHE_LINE_SIZE,
	363	.matches = has_mismatched_cache_line_size,
143ba05d	364	.type = ARM64_CPUCAP_SCOPE_LOCAL_CPU,
c0cda3b8	365	.cpu_enable = cpu_enable_trap_ctr_access,
116c81f4	366	},
38fd94b0 CC	367	#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
	368	{
	369	.desc = "Qualcomm Technologies Falkor erratum 1003",
	370	.capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
	371	MIDR_RANGE(MIDR_QCOM_FALKOR_V1,
	372	MIDR_CPU_VAR_REV(0, 0),
	373	MIDR_CPU_VAR_REV(0, 0)),
	374	},
bb487118 SB	375	{
	376	.desc = "Qualcomm Technologies Kryo erratum 1003",
	377	.capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
143ba05d	378	.type = ARM64_CPUCAP_SCOPE_LOCAL_CPU,
bb487118 SB	379	.midr_model = MIDR_QCOM_KRYO,
	380	.matches = is_kryo_midr,
	381	},
38fd94b0	382	#endif
d9ff80f8 CC	383	#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
	384	{
	385	.desc = "Qualcomm Technologies Falkor erratum 1009",
	386	.capability = ARM64_WORKAROUND_REPEAT_TLBI,
	387	MIDR_RANGE(MIDR_QCOM_FALKOR_V1,
	388	MIDR_CPU_VAR_REV(0, 0),
	389	MIDR_CPU_VAR_REV(0, 0)),
	390	},
eeb1efbc MZ	391	#endif
	392	#ifdef CONFIG_ARM64_ERRATUM_858921
	393	{
	394	/* Cortex-A73 all versions */
	395	.desc = "ARM erratum 858921",
	396	.capability = ARM64_WORKAROUND_858921,
	397	MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
	398	},
aa6acde6 WD	399	#endif
	400	#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
	401	{
	402	.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
	403	MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
c0cda3b8	404	.cpu_enable = enable_smccc_arch_workaround_1,
aa6acde6 WD	405	},
	406	{
	407	.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
	408	MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
c0cda3b8	409	.cpu_enable = enable_smccc_arch_workaround_1,
aa6acde6 WD	410	},
	411	{
	412	.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
	413	MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
c0cda3b8	414	.cpu_enable = enable_smccc_arch_workaround_1,
aa6acde6 WD	415	},
	416	{
	417	.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
	418	MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
c0cda3b8	419	.cpu_enable = enable_smccc_arch_workaround_1,
aa6acde6	420	},
ec82b567 SD	421	{
	422	.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
	423	MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
c0cda3b8	424	.cpu_enable = qcom_enable_link_stack_sanitization,
ec82b567 SD	425	},
	426	{
	427	.capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,
	428	MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
	429	},
16e574d7 SD	430	{
	431	.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
	432	MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
c0cda3b8	433	.cpu_enable = qcom_enable_link_stack_sanitization,
16e574d7 SD	434	},
	435	{
	436	.capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,
	437	MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
	438	},
f3d795d9 J	439	{
	440	.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
	441	MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
c0cda3b8	442	.cpu_enable = enable_smccc_arch_workaround_1,
f3d795d9 J	443	},
	444	{
	445	.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
	446	MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
c0cda3b8	447	.cpu_enable = enable_smccc_arch_workaround_1,
f3d795d9	448	},
d9ff80f8	449	#endif
5afaa1fc	450	{
301bcfac	451	}
e116a375	452	};