[mirror_ubuntu-jammy-kernel.git] / arch / arm64 / kernel / cpu_errata.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Contains CPU specific errata definitions
 *
 * Copyright (C) 2014 ARM Ltd.
 */

#include <linux/arm-smccc.h>
#include <linux/types.h>
#include <linux/cpu.h>
#include <asm/cpu.h>
#include <asm/cputype.h>
#include <asm/cpufeature.h>
#include <asm/kvm_asm.h>
#include <asm/smp_plat.h>

static bool __maybe_unused
is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
{
	const struct arm64_midr_revidr *fix;
	u32 midr = read_cpuid_id(), revidr;

	WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
	if (!is_midr_in_range(midr, &entry->midr_range))
		return false;

	midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
	revidr = read_cpuid(REVIDR_EL1);
	for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
		if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
			return false;

	return true;
}

static bool __maybe_unused
is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,
			    int scope)
{
	WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
	return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);
}

static bool __maybe_unused
is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
{
	u32 model;

	WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());

	model = read_cpuid_id();
	model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |
		 MIDR_ARCHITECTURE_MASK;

	return model == entry->midr_range.model;
}

static bool
has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry,
			  int scope)
{
	u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
	u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask;
	u64 ctr_raw, ctr_real;

	WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());

	/*
	 * We want to make sure that all the CPUs in the system expose
	 * a consistent CTR_EL0 to make sure that applications behaves
	 * correctly with migration.
	 *
	 * If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 :
	 *
	 * 1) It is safe if the system doesn't support IDC, as CPU anyway
	 *    reports IDC = 0, consistent with the rest.
	 *
	 * 2) If the system has IDC, it is still safe as we trap CTR_EL0
	 *    access on this CPU via the ARM64_HAS_CACHE_IDC capability.
	 *
	 * So, we need to make sure either the raw CTR_EL0 or the effective
	 * CTR_EL0 matches the system's copy to allow a secondary CPU to boot.
	 */
	ctr_raw = read_cpuid_cachetype() & mask;
	ctr_real = read_cpuid_effective_cachetype() & mask;

	return (ctr_real != sys) && (ctr_raw != sys);
}

static void
cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap)
{
	u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
	bool enable_uct_trap = false;

	/* Trap CTR_EL0 access on this CPU, only if it has a mismatch */
	if ((read_cpuid_cachetype() & mask) !=
	    (arm64_ftr_reg_ctrel0.sys_val & mask))
		enable_uct_trap = true;

	/* ... or if the system is affected by an erratum */
	if (cap->capability == ARM64_WORKAROUND_1542419)
		enable_uct_trap = true;

	if (enable_uct_trap)
		sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
}

#ifdef CONFIG_ARM64_ERRATUM_1463225
static bool
has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry,
			       int scope)
{
	return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode();
}
#endif

static void __maybe_unused
cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)
{
	sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0);
}

#define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)	\
	.matches = is_affected_midr_range,			\
	.midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)

#define CAP_MIDR_ALL_VERSIONS(model)					\
	.matches = is_affected_midr_range,				\
	.midr_range = MIDR_ALL_VERSIONS(model)

#define MIDR_FIXED(rev, revidr_mask) \
	.fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}

#define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max)		\
	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,				\
	CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)

#define CAP_MIDR_RANGE_LIST(list)				\
	.matches = is_affected_midr_range_list,			\
	.midr_range_list = list

/* Errata affecting a range of revisions of  given model variant */
#define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max)	 \
	ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)

/* Errata affecting a single variant/revision of a model */
#define ERRATA_MIDR_REV(model, var, rev)	\
	ERRATA_MIDR_RANGE(model, var, rev, var, rev)

/* Errata affecting all variants/revisions of a given a model */
#define ERRATA_MIDR_ALL_VERSIONS(model)				\
	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,			\
	CAP_MIDR_ALL_VERSIONS(model)

/* Errata affecting a list of midr ranges, with same work around */
#define ERRATA_MIDR_RANGE_LIST(midr_list)			\
	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,			\
	CAP_MIDR_RANGE_LIST(midr_list)

static const __maybe_unused struct midr_range tx2_family_cpus[] = {
	MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
	MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
	{},
};

static bool __maybe_unused
needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry,
			 int scope)
{
	int i;

	if (!is_affected_midr_range_list(entry, scope) ||
	    !is_hyp_mode_available())
		return false;

	for_each_possible_cpu(i) {
		if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0)
			return true;
	}

	return false;
}

static bool __maybe_unused
has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry,
				int scope)
{
	u32 midr = read_cpuid_id();
	bool has_dic = read_cpuid_cachetype() & BIT(CTR_DIC_SHIFT);
	const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1);

	WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
	return is_midr_in_range(midr, &range) && has_dic;
}

#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
	{
		ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0)
	},
	{
		.midr_range.model = MIDR_QCOM_KRYO,
		.matches = is_kryo_midr,
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_1286807
	{
		ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
	},
#endif
	{},
};
#endif

#ifdef CONFIG_CAVIUM_ERRATUM_27456
const struct midr_range cavium_erratum_27456_cpus[] = {
	/* Cavium ThunderX, T88 pass 1.x - 2.1 */
	MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1),
	/* Cavium ThunderX, T81 pass 1.0 */
	MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),
	{},
};
#endif

#ifdef CONFIG_CAVIUM_ERRATUM_30115
static const struct midr_range cavium_erratum_30115_cpus[] = {
	/* Cavium ThunderX, T88 pass 1.x - 2.2 */
	MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2),
	/* Cavium ThunderX, T81 pass 1.0 - 1.2 */
	MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),
	/* Cavium ThunderX, T83 pass 1.0 */
	MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),
	{},
};
#endif

#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = {
	{
		ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
	},
	{
		.midr_range.model = MIDR_QCOM_KRYO,
		.matches = is_kryo_midr,
	},
	{},
};
#endif

#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
static const struct midr_range workaround_clean_cache[] = {
#if	defined(CONFIG_ARM64_ERRATUM_826319) || \
	defined(CONFIG_ARM64_ERRATUM_827319) || \
	defined(CONFIG_ARM64_ERRATUM_824069)
	/* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */
	MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
#endif
#ifdef	CONFIG_ARM64_ERRATUM_819472
	/* Cortex-A53 r0p[01] : ARM errata 819472 */
	MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
#endif
	{},
};
#endif

#ifdef CONFIG_ARM64_ERRATUM_1418040
/*
 * - 1188873 affects r0p0 to r2p0
 * - 1418040 affects r0p0 to r3p1
 */
static const struct midr_range erratum_1418040_list[] = {
	/* Cortex-A76 r0p0 to r3p1 */
	MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
	/* Neoverse-N1 r0p0 to r3p1 */
	MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1),
	/* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
	MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
	{},
};
#endif

#ifdef CONFIG_ARM64_ERRATUM_845719
static const struct midr_range erratum_845719_list[] = {
	/* Cortex-A53 r0p[01234] */
	MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
	/* Brahma-B53 r0p[0] */
	MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
	/* Kryo2XX Silver rAp4 */
	MIDR_REV(MIDR_QCOM_KRYO_2XX_SILVER, 0xa, 0x4),
	{},
};
#endif

#ifdef CONFIG_ARM64_ERRATUM_843419
static const struct arm64_cpu_capabilities erratum_843419_list[] = {
	{
		/* Cortex-A53 r0p[01234] */
		.matches = is_affected_midr_range,
		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
		MIDR_FIXED(0x4, BIT(8)),
	},
	{
		/* Brahma-B53 r0p[0] */
		.matches = is_affected_midr_range,
		ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
	},
	{},
};
#endif

#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
static const struct midr_range erratum_speculative_at_list[] = {
#ifdef CONFIG_ARM64_ERRATUM_1165522
	/* Cortex A76 r0p0 to r2p0 */
	MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
#endif
#ifdef CONFIG_ARM64_ERRATUM_1319367
	MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
	MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
#endif
#ifdef CONFIG_ARM64_ERRATUM_1530923
	/* Cortex A55 r0p0 to r2p0 */
	MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0),
	/* Kryo4xx Silver (rdpe => r1p0) */
	MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
#endif
	{},
};
#endif

#ifdef CONFIG_ARM64_ERRATUM_1463225
static const struct midr_range erratum_1463225[] = {
	/* Cortex-A76 r0p0 - r3p1 */
	MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
	/* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
	MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
	{},
};
#endif

const struct arm64_cpu_capabilities arm64_errata[] = {
#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
	{
		.desc = "ARM errata 826319, 827319, 824069, or 819472",
		.capability = ARM64_WORKAROUND_CLEAN_CACHE,
		ERRATA_MIDR_RANGE_LIST(workaround_clean_cache),
		.cpu_enable = cpu_enable_cache_maint_trap,
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_832075
	{
	/* Cortex-A57 r0p0 - r1p2 */
		.desc = "ARM erratum 832075",
		.capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
		ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
				  0, 0,
				  1, 2),
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_834220
	{
	/* Cortex-A57 r0p0 - r1p2 */
		.desc = "ARM erratum 834220",
		.capability = ARM64_WORKAROUND_834220,
		ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
				  0, 0,
				  1, 2),
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_843419
	{
		.desc = "ARM erratum 843419",
		.capability = ARM64_WORKAROUND_843419,
		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
		.matches = cpucap_multi_entry_cap_matches,
		.match_list = erratum_843419_list,
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_845719
	{
		.desc = "ARM erratum 845719",
		.capability = ARM64_WORKAROUND_845719,
		ERRATA_MIDR_RANGE_LIST(erratum_845719_list),
	},
#endif
#ifdef CONFIG_CAVIUM_ERRATUM_23154
	{
	/* Cavium ThunderX, pass 1.x */
		.desc = "Cavium erratum 23154",
		.capability = ARM64_WORKAROUND_CAVIUM_23154,
		ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX, 0, 0, 1),
	},
#endif
#ifdef CONFIG_CAVIUM_ERRATUM_27456
	{
		.desc = "Cavium erratum 27456",
		.capability = ARM64_WORKAROUND_CAVIUM_27456,
		ERRATA_MIDR_RANGE_LIST(cavium_erratum_27456_cpus),
	},
#endif
#ifdef CONFIG_CAVIUM_ERRATUM_30115
	{
		.desc = "Cavium erratum 30115",
		.capability = ARM64_WORKAROUND_CAVIUM_30115,
		ERRATA_MIDR_RANGE_LIST(cavium_erratum_30115_cpus),
	},
#endif
	{
		.desc = "Mismatched cache type (CTR_EL0)",
		.capability = ARM64_MISMATCHED_CACHE_TYPE,
		.matches = has_mismatched_cache_type,
		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
		.cpu_enable = cpu_enable_trap_ctr_access,
	},
#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
	{
		.desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",
		.capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
		.matches = cpucap_multi_entry_cap_matches,
		.match_list = qcom_erratum_1003_list,
	},
#endif
#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
	{
		.desc = "Qualcomm erratum 1009, or ARM erratum 1286807",
		.capability = ARM64_WORKAROUND_REPEAT_TLBI,
		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
		.matches = cpucap_multi_entry_cap_matches,
		.match_list = arm64_repeat_tlbi_list,
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_858921
	{
	/* Cortex-A73 all versions */
		.desc = "ARM erratum 858921",
		.capability = ARM64_WORKAROUND_858921,
		ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
	},
#endif
	{
		.desc = "Spectre-v2",
		.capability = ARM64_SPECTRE_V2,
		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
		.matches = has_spectre_v2,
		.cpu_enable = spectre_v2_enable_mitigation,
	},
#ifdef CONFIG_RANDOMIZE_BASE
	{
	/* Must come after the Spectre-v2 entry */
		.desc = "Spectre-v3a",
		.capability = ARM64_SPECTRE_V3A,
		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
		.matches = has_spectre_v3a,
		.cpu_enable = spectre_v3a_enable_mitigation,
	},
#endif
	{
		.desc = "Spectre-v4",
		.capability = ARM64_SPECTRE_V4,
		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
		.matches = has_spectre_v4,
		.cpu_enable = spectre_v4_enable_mitigation,
	},
#ifdef CONFIG_ARM64_ERRATUM_1418040
	{
		.desc = "ARM erratum 1418040",
		.capability = ARM64_WORKAROUND_1418040,
		ERRATA_MIDR_RANGE_LIST(erratum_1418040_list),
		/*
		 * We need to allow affected CPUs to come in late, but
		 * also need the non-affected CPUs to be able to come
		 * in at any point in time. Wonderful.
		 */
		.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
	},
#endif
#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
	{
		.desc = "ARM errata 1165522, 1319367, or 1530923",
		.capability = ARM64_WORKAROUND_SPECULATIVE_AT,
		ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list),
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_1463225
	{
		.desc = "ARM erratum 1463225",
		.capability = ARM64_WORKAROUND_1463225,
		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
		.matches = has_cortex_a76_erratum_1463225,
		.midr_range_list = erratum_1463225,
	},
#endif
#ifdef CONFIG_CAVIUM_TX2_ERRATUM_219
	{
		.desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)",
		.capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM,
		ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
		.matches = needs_tx2_tvm_workaround,
	},
	{
		.desc = "Cavium ThunderX2 erratum 219 (PRFM removal)",
		.capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM,
		ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_1542419
	{
		/* we depend on the firmware portion for correctness */
		.desc = "ARM erratum 1542419 (kernel portion)",
		.capability = ARM64_WORKAROUND_1542419,
		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
		.matches = has_neoverse_n1_erratum_1542419,
		.cpu_enable = cpu_enable_trap_ctr_access,
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_1508412
	{
		/* we depend on the firmware portion for correctness */
		.desc = "ARM erratum 1508412 (kernel portion)",
		.capability = ARM64_WORKAROUND_1508412,
		ERRATA_MIDR_RANGE(MIDR_CORTEX_A77,
				  0, 0,
				  1, 0),
	},
#endif
#ifdef CONFIG_NVIDIA_CARMEL_CNP_ERRATUM
	{
		/* NVIDIA Carmel */
		.desc = "NVIDIA Carmel CNP erratum",
		.capability = ARM64_WORKAROUND_NVIDIA_CARMEL_CNP,
		ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
	},
#endif
	{
	}
};
Commit	Line	Data
caab277b	1	// SPDX-License-Identifier: GPL-2.0-only
e116a375 AP	2	/*
	3	* Contains CPU specific errata definitions
	4	*
	5	* Copyright (C) 2014 ARM Ltd.
e116a375 AP	6	*/
e116a375 AP	7
94a5d879	8	#include <linux/arm-smccc.h>
e116a375	9	#include <linux/types.h>
a111b7c0	10	#include <linux/cpu.h>
e116a375 AP	11	#include <asm/cpu.h>
	12	#include <asm/cputype.h>
	13	#include <asm/cpufeature.h>
4db61fef	14	#include <asm/kvm_asm.h>
93916beb	15	#include <asm/smp_plat.h>
e116a375	16
301bcfac	17	static bool __maybe_unused
92406f0c	18	is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
301bcfac	19	{
e8002e02 AB	20	const struct arm64_midr_revidr *fix;
	21	u32 midr = read_cpuid_id(), revidr;
	22
92406f0c	23	WARN_ON(scope != SCOPE_LOCAL_CPU \|\| preemptible());
1df31050	24	if (!is_midr_in_range(midr, &entry->midr_range))
e8002e02 AB	25	return false;
	26
	27	midr &= MIDR_REVISION_MASK \| MIDR_VARIANT_MASK;
	28	revidr = read_cpuid(REVIDR_EL1);
	29	for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
	30	if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
	31	return false;
	32
	33	return true;
301bcfac AP	34	}
301bcfac AP	35
be5b2998 SP	36	static bool __maybe_unused
	37	is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,
	38	int scope)
301bcfac	39	{
92406f0c	40	WARN_ON(scope != SCOPE_LOCAL_CPU \|\| preemptible());
be5b2998	41	return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);
301bcfac AP	42	}
301bcfac AP	43
bb487118 SB	44	static bool __maybe_unused
	45	is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
	46	{
	47	u32 model;
	48
	49	WARN_ON(scope != SCOPE_LOCAL_CPU \|\| preemptible());
	50
	51	model = read_cpuid_id();
	52	model &= MIDR_IMPLEMENTOR_MASK \| (0xf00 << MIDR_PARTNUM_SHIFT) \|
	53	MIDR_ARCHITECTURE_MASK;
	54
1df31050	55	return model == entry->midr_range.model;
bb487118 SB	56	}
bb487118 SB	57
116c81f4	58	static bool
314d53d2 SP	59	has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry,
314d53d2 SP	60	int scope)
116c81f4	61	{
1602df02 SP	62	u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
	63	u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask;
	64	u64 ctr_raw, ctr_real;
314d53d2	65
116c81f4	66	WARN_ON(scope != SCOPE_LOCAL_CPU \|\| preemptible());
1602df02 SP	67
	68	/*
	69	* We want to make sure that all the CPUs in the system expose
	70	* a consistent CTR_EL0 to make sure that applications behaves
	71	* correctly with migration.
	72	*
	73	* If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 :
	74	*
	75	* 1) It is safe if the system doesn't support IDC, as CPU anyway
	76	* reports IDC = 0, consistent with the rest.
	77	*
	78	* 2) If the system has IDC, it is still safe as we trap CTR_EL0
	79	* access on this CPU via the ARM64_HAS_CACHE_IDC capability.
	80	*
	81	* So, we need to make sure either the raw CTR_EL0 or the effective
	82	* CTR_EL0 matches the system's copy to allow a secondary CPU to boot.
	83	*/
	84	ctr_raw = read_cpuid_cachetype() & mask;
	85	ctr_real = read_cpuid_effective_cachetype() & mask;
	86
	87	return (ctr_real != sys) && (ctr_raw != sys);
116c81f4 SP	88	}
116c81f4 SP	89
c0cda3b8	90	static void
05460849	91	cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap)
116c81f4	92	{
4afe8e79	93	u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
05460849	94	bool enable_uct_trap = false;
4afe8e79 SP	95
	96	/* Trap CTR_EL0 access on this CPU, only if it has a mismatch */
	97	if ((read_cpuid_cachetype() & mask) !=
	98	(arm64_ftr_reg_ctrel0.sys_val & mask))
05460849 JM	99	enable_uct_trap = true;
	100
	101	/* ... or if the system is affected by an erratum */
	102	if (cap->capability == ARM64_WORKAROUND_1542419)
	103	enable_uct_trap = true;
	104
	105	if (enable_uct_trap)
4afe8e79	106	sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
116c81f4 SP	107	}
116c81f4 SP	108
969f5ea6	109	#ifdef CONFIG_ARM64_ERRATUM_1463225
969f5ea6 WD	110	static bool
	111	has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry,
	112	int scope)
	113	{
a9e821b8	114	return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode();
969f5ea6 WD	115	}
	116	#endif
	117
b8925ee2 WD	118	static void __maybe_unused
	119	cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)
	120	{
	121	sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0);
	122	}
	123
5e7951ce SP	124	#define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
5e7951ce SP	125	.matches = is_affected_midr_range, \
1df31050	126	.midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)
5e7951ce SP	127
	128	#define CAP_MIDR_ALL_VERSIONS(model) \
	129	.matches = is_affected_midr_range, \
1df31050	130	.midr_range = MIDR_ALL_VERSIONS(model)
06f1494f	131
e8002e02 AB	132	#define MIDR_FIXED(rev, revidr_mask) \
	133	.fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}
	134
5e7951ce SP	135	#define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
	136	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
	137	CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)
	138
be5b2998 SP	139	#define CAP_MIDR_RANGE_LIST(list) \
	140	.matches = is_affected_midr_range_list, \
	141	.midr_range_list = list
	142
5e7951ce SP	143	/* Errata affecting a range of revisions of given model variant */
	144	#define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \
	145	ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)
	146
	147	/* Errata affecting a single variant/revision of a model */
	148	#define ERRATA_MIDR_REV(model, var, rev) \
	149	ERRATA_MIDR_RANGE(model, var, rev, var, rev)
	150
	151	/* Errata affecting all variants/revisions of a given a model */
	152	#define ERRATA_MIDR_ALL_VERSIONS(model) \
	153	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
	154	CAP_MIDR_ALL_VERSIONS(model)
	155
be5b2998 SP	156	/* Errata affecting a list of midr ranges, with same work around */
	157	#define ERRATA_MIDR_RANGE_LIST(midr_list) \
	158	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
	159	CAP_MIDR_RANGE_LIST(midr_list)
	160
93916beb MZ	161	static const __maybe_unused struct midr_range tx2_family_cpus[] = {
	162	MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
	163	MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
	164	{},
	165	};
	166
	167	static bool __maybe_unused
	168	needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry,
	169	int scope)
	170	{
	171	int i;
	172
	173	if (!is_affected_midr_range_list(entry, scope) \|\|
	174	!is_hyp_mode_available())
	175	return false;
	176
	177	for_each_possible_cpu(i) {
	178	if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0)
	179	return true;
	180	}
	181
	182	return false;
	183	}
	184
05460849 JM	185	static bool __maybe_unused
	186	has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry,
	187	int scope)
	188	{
	189	u32 midr = read_cpuid_id();
	190	bool has_dic = read_cpuid_cachetype() & BIT(CTR_DIC_SHIFT);
	191	const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1);
	192
	193	WARN_ON(scope != SCOPE_LOCAL_CPU \|\| preemptible());
	194	return is_midr_in_range(midr, &range) && has_dic;
	195	}
8892b718	196
ce8c80c5	197	#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
36c602dc	198	static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
ce8c80c5	199	#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
36c602dc BA	200	{
	201	ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0)
	202	},
	203	{
	204	.midr_range.model = MIDR_QCOM_KRYO,
	205	.matches = is_kryo_midr,
	206	},
ce8c80c5 CM	207	#endif
ce8c80c5 CM	208	#ifdef CONFIG_ARM64_ERRATUM_1286807
36c602dc BA	209	{
	210	ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
	211	},
ce8c80c5 CM	212	#endif
	213	{},
	214	};
ce8c80c5 CM	215	#endif
ce8c80c5 CM	216
f58cdf7e	217	#ifdef CONFIG_CAVIUM_ERRATUM_27456
b89d82ef	218	const struct midr_range cavium_erratum_27456_cpus[] = {
f58cdf7e SP	219	/* Cavium ThunderX, T88 pass 1.x - 2.1 */
	220	MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1),
	221	/* Cavium ThunderX, T81 pass 1.0 */
	222	MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),
	223	{},
	224	};
	225	#endif
	226
	227	#ifdef CONFIG_CAVIUM_ERRATUM_30115
	228	static const struct midr_range cavium_erratum_30115_cpus[] = {
	229	/* Cavium ThunderX, T88 pass 1.x - 2.2 */
	230	MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2),
	231	/* Cavium ThunderX, T81 pass 1.0 - 1.2 */
	232	MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),
	233	/* Cavium ThunderX, T83 pass 1.0 */
	234	MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),
	235	{},
	236	};
	237	#endif
	238
a3dcea2c SP	239	#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
	240	static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = {
	241	{
	242	ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
	243	},
	244	{
	245	.midr_range.model = MIDR_QCOM_KRYO,
	246	.matches = is_kryo_midr,
	247	},
	248	{},
	249	};
	250	#endif
	251
c9460dcb SP	252	#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
c9460dcb SP	253	static const struct midr_range workaround_clean_cache[] = {
c0a01b84 AP	254	#if defined(CONFIG_ARM64_ERRATUM_826319) \|\| \
	255	defined(CONFIG_ARM64_ERRATUM_827319) \|\| \
	256	defined(CONFIG_ARM64_ERRATUM_824069)
c9460dcb SP	257	/* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */
	258	MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
	259	#endif
	260	#ifdef CONFIG_ARM64_ERRATUM_819472
	261	/* Cortex-A53 r0p[01] : ARM errata 819472 */
	262	MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
c0a01b84	263	#endif
c9460dcb SP	264	{},
	265	};
	266	#endif
	267
a5325089 MZ	268	#ifdef CONFIG_ARM64_ERRATUM_1418040
	269	/*
	270	* - 1188873 affects r0p0 to r2p0
	271	* - 1418040 affects r0p0 to r3p1
	272	*/
	273	static const struct midr_range erratum_1418040_list[] = {
	274	/* Cortex-A76 r0p0 to r3p1 */
	275	MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
	276	/* Neoverse-N1 r0p0 to r3p1 */
	277	MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1),
a9e821b8 SPR	278	/* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
a9e821b8 SPR	279	MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
6989303a MZ	280	{},
	281	};
	282	#endif
	283
bfc97f9f DB	284	#ifdef CONFIG_ARM64_ERRATUM_845719
	285	static const struct midr_range erratum_845719_list[] = {
	286	/* Cortex-A53 r0p[01234] */
	287	MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
	288	/* Brahma-B53 r0p[0] */
	289	MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
23c21641 KD	290	/* Kryo2XX Silver rAp4 */
23c21641 KD	291	MIDR_REV(MIDR_QCOM_KRYO_2XX_SILVER, 0xa, 0x4),
bfc97f9f DB	292	{},
	293	};
	294	#endif
	295
1cf45b8f FF	296	#ifdef CONFIG_ARM64_ERRATUM_843419
	297	static const struct arm64_cpu_capabilities erratum_843419_list[] = {
	298	{
	299	/* Cortex-A53 r0p[01234] */
	300	.matches = is_affected_midr_range,
	301	ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
	302	MIDR_FIXED(0x4, BIT(8)),
	303	},
	304	{
	305	/* Brahma-B53 r0p[0] */
	306	.matches = is_affected_midr_range,
	307	ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
	308	},
	309	{},
	310	};
	311	#endif
	312
02ab1f50 AS	313	#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
02ab1f50 AS	314	static const struct midr_range erratum_speculative_at_list[] = {
e85d68fa SP	315	#ifdef CONFIG_ARM64_ERRATUM_1165522
	316	/* Cortex A76 r0p0 to r2p0 */
	317	MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
275fa0ea	318	#endif
02ab1f50 AS	319	#ifdef CONFIG_ARM64_ERRATUM_1319367
	320	MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
	321	MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
	322	#endif
275fa0ea SP	323	#ifdef CONFIG_ARM64_ERRATUM_1530923
	324	/* Cortex A55 r0p0 to r2p0 */
	325	MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0),
9b23d95c SPR	326	/* Kryo4xx Silver (rdpe => r1p0) */
9b23d95c SPR	327	MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
e85d68fa SP	328	#endif
	329	{},
	330	};
	331	#endif
	332
a9e821b8 SPR	333	#ifdef CONFIG_ARM64_ERRATUM_1463225
	334	static const struct midr_range erratum_1463225[] = {
	335	/* Cortex-A76 r0p0 - r3p1 */
	336	MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
	337	/* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
	338	MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
09c717c9	339	{},
a9e821b8 SPR	340	};
	341	#endif
	342
c9460dcb SP	343	const struct arm64_cpu_capabilities arm64_errata[] = {
c9460dcb SP	344	#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
c0a01b84	345	{
357dd8a2	346	.desc = "ARM errata 826319, 827319, 824069, or 819472",
c0a01b84	347	.capability = ARM64_WORKAROUND_CLEAN_CACHE,
c9460dcb	348	ERRATA_MIDR_RANGE_LIST(workaround_clean_cache),
c0cda3b8	349	.cpu_enable = cpu_enable_cache_maint_trap,
c0a01b84 AP	350	},
	351	#endif
	352	#ifdef CONFIG_ARM64_ERRATUM_832075
301bcfac	353	{
5afaa1fc AP	354	/* Cortex-A57 r0p0 - r1p2 */
	355	.desc = "ARM erratum 832075",
	356	.capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
5e7951ce SP	357	ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
	358	0, 0,
	359	1, 2),
5afaa1fc	360	},
905e8c5d	361	#endif
498cd5c3 MZ	362	#ifdef CONFIG_ARM64_ERRATUM_834220
	363	{
	364	/* Cortex-A57 r0p0 - r1p2 */
	365	.desc = "ARM erratum 834220",
	366	.capability = ARM64_WORKAROUND_834220,
5e7951ce SP	367	ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
	368	0, 0,
	369	1, 2),
498cd5c3 MZ	370	},
498cd5c3 MZ	371	#endif
ca79acca AB	372	#ifdef CONFIG_ARM64_ERRATUM_843419
ca79acca AB	373	{
ca79acca AB	374	.desc = "ARM erratum 843419",
ca79acca AB	375	.capability = ARM64_WORKAROUND_843419,
1cf45b8f FF	376	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
	377	.matches = cpucap_multi_entry_cap_matches,
	378	.match_list = erratum_843419_list,
498cd5c3 MZ	379	},
498cd5c3 MZ	380	#endif
905e8c5d WD	381	#ifdef CONFIG_ARM64_ERRATUM_845719
905e8c5d WD	382	{
905e8c5d WD	383	.desc = "ARM erratum 845719",
905e8c5d WD	384	.capability = ARM64_WORKAROUND_845719,
bfc97f9f	385	ERRATA_MIDR_RANGE_LIST(erratum_845719_list),
905e8c5d	386	},
6d4e11c5 RR	387	#endif
	388	#ifdef CONFIG_CAVIUM_ERRATUM_23154
	389	{
	390	/* Cavium ThunderX, pass 1.x */
	391	.desc = "Cavium erratum 23154",
	392	.capability = ARM64_WORKAROUND_CAVIUM_23154,
5e7951ce	393	ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX, 0, 0, 1),
6d4e11c5	394	},
104a0c02 AP	395	#endif
	396	#ifdef CONFIG_CAVIUM_ERRATUM_27456
	397	{
47c459be GK	398	.desc = "Cavium erratum 27456",
47c459be GK	399	.capability = ARM64_WORKAROUND_CAVIUM_27456,
f58cdf7e	400	ERRATA_MIDR_RANGE_LIST(cavium_erratum_27456_cpus),
47c459be	401	},
690a3415 DD	402	#endif
	403	#ifdef CONFIG_CAVIUM_ERRATUM_30115
	404	{
690a3415 DD	405	.desc = "Cavium erratum 30115",
690a3415 DD	406	.capability = ARM64_WORKAROUND_CAVIUM_30115,
f58cdf7e	407	ERRATA_MIDR_RANGE_LIST(cavium_erratum_30115_cpus),
690a3415	408	},
c0a01b84	409	#endif
116c81f4	410	{
880f7cc4	411	.desc = "Mismatched cache type (CTR_EL0)",
314d53d2 SP	412	.capability = ARM64_MISMATCHED_CACHE_TYPE,
314d53d2 SP	413	.matches = has_mismatched_cache_type,
5b4747c5	414	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
c0cda3b8	415	.cpu_enable = cpu_enable_trap_ctr_access,
116c81f4	416	},
38fd94b0 CC	417	#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
38fd94b0 CC	418	{
a3dcea2c	419	.desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",
bb487118	420	.capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
d4af3c4b	421	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
1e013d06	422	.matches = cpucap_multi_entry_cap_matches,
a3dcea2c	423	.match_list = qcom_erratum_1003_list,
bb487118	424	},
38fd94b0	425	#endif
ce8c80c5	426	#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
d9ff80f8	427	{
357dd8a2	428	.desc = "Qualcomm erratum 1009, or ARM erratum 1286807",
d9ff80f8	429	.capability = ARM64_WORKAROUND_REPEAT_TLBI,
36c602dc BA	430	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
	431	.matches = cpucap_multi_entry_cap_matches,
	432	.match_list = arm64_repeat_tlbi_list,
d9ff80f8	433	},
eeb1efbc MZ	434	#endif
	435	#ifdef CONFIG_ARM64_ERRATUM_858921
	436	{
	437	/* Cortex-A73 all versions */
	438	.desc = "ARM erratum 858921",
	439	.capability = ARM64_WORKAROUND_858921,
5e7951ce	440	ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
eeb1efbc	441	},
aa6acde6	442	#endif
aa6acde6	443	{
d4647f0a	444	.desc = "Spectre-v2",
688f1e4b	445	.capability = ARM64_SPECTRE_V2,
73f38166	446	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
d4647f0a WD	447	.matches = has_spectre_v2,
d4647f0a WD	448	.cpu_enable = spectre_v2_enable_mitigation,
f3d795d9	449	},
a59a2edb	450	#ifdef CONFIG_RANDOMIZE_BASE
4b472ffd	451	{
b881cdce	452	/* Must come after the Spectre-v2 entry */
c4792b6d WD	453	.desc = "Spectre-v3a",
c4792b6d WD	454	.capability = ARM64_SPECTRE_V3A,
cd1f56b9 WD	455	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
cd1f56b9 WD	456	.matches = has_spectre_v3a,
c4792b6d	457	.cpu_enable = spectre_v3a_enable_mitigation,
4b472ffd	458	},
a725e3dd	459	#endif
a725e3dd	460	{
c2876207	461	.desc = "Spectre-v4",
9b0955ba	462	.capability = ARM64_SPECTRE_V4,
a725e3dd	463	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
c2876207 WD	464	.matches = has_spectre_v4,
c2876207 WD	465	.cpu_enable = spectre_v4_enable_mitigation,
a725e3dd	466	},
a5325089	467	#ifdef CONFIG_ARM64_ERRATUM_1418040
95b861a4	468	{
a5325089 MZ	469	.desc = "ARM erratum 1418040",
	470	.capability = ARM64_WORKAROUND_1418040,
	471	ERRATA_MIDR_RANGE_LIST(erratum_1418040_list),
ed888cb0 MZ	472	/*
	473	* We need to allow affected CPUs to come in late, but
	474	* also need the non-affected CPUs to be able to come
	475	* in at any point in time. Wonderful.
	476	*/
	477	.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
95b861a4	478	},
8b2cca9a	479	#endif
02ab1f50	480	#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
8b2cca9a	481	{
c350717e	482	.desc = "ARM errata 1165522, 1319367, or 1530923",
02ab1f50 AS	483	.capability = ARM64_WORKAROUND_SPECULATIVE_AT,
02ab1f50 AS	484	ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list),
8b2cca9a	485	},
969f5ea6 WD	486	#endif
	487	#ifdef CONFIG_ARM64_ERRATUM_1463225
	488	{
	489	.desc = "ARM erratum 1463225",
	490	.capability = ARM64_WORKAROUND_1463225,
	491	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
	492	.matches = has_cortex_a76_erratum_1463225,
a9e821b8	493	.midr_range_list = erratum_1463225,
969f5ea6	494	},
93916beb MZ	495	#endif
	496	#ifdef CONFIG_CAVIUM_TX2_ERRATUM_219
	497	{
	498	.desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)",
	499	.capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM,
	500	ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
	501	.matches = needs_tx2_tvm_workaround,
	502	},
9405447e MZ	503	{
	504	.desc = "Cavium ThunderX2 erratum 219 (PRFM removal)",
	505	.capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM,
	506	ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
	507	},
6a036afb	508	#endif
05460849 JM	509	#ifdef CONFIG_ARM64_ERRATUM_1542419
	510	{
	511	/* we depend on the firmware portion for correctness */
	512	.desc = "ARM erratum 1542419 (kernel portion)",
	513	.capability = ARM64_WORKAROUND_1542419,
	514	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
	515	.matches = has_neoverse_n1_erratum_1542419,
	516	.cpu_enable = cpu_enable_trap_ctr_access,
	517	},
96d389ca RH	518	#endif
	519	#ifdef CONFIG_ARM64_ERRATUM_1508412
	520	{
	521	/* we depend on the firmware portion for correctness */
	522	.desc = "ARM erratum 1508412 (kernel portion)",
	523	.capability = ARM64_WORKAROUND_1508412,
	524	ERRATA_MIDR_RANGE(MIDR_CORTEX_A77,
	525	0, 0,
	526	1, 0),
	527	},
20109a85 RW	528	#endif
	529	#ifdef CONFIG_NVIDIA_CARMEL_CNP_ERRATUM
	530	{
	531	/* NVIDIA Carmel */
	532	.desc = "NVIDIA Carmel CNP erratum",
	533	.capability = ARM64_WORKAROUND_NVIDIA_CARMEL_CNP,
	534	ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
	535	},
d9ff80f8	536	#endif
5afaa1fc	537	{
301bcfac	538	}
e116a375	539	};