[mirror_ubuntu-jammy-kernel.git] / arch / arm64 / kernel / cpu_errata.c

/*
 * Contains CPU specific errata definitions
 *
 * Copyright (C) 2014 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/types.h>
#include <asm/cpu.h>
#include <asm/cputype.h>
#include <asm/cpufeature.h>

static bool __maybe_unused
is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
{
	const struct arm64_midr_revidr *fix;
	u32 midr = read_cpuid_id(), revidr;

	WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
	if (!is_midr_in_range(midr, &entry->midr_range))
		return false;

	midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
	revidr = read_cpuid(REVIDR_EL1);
	for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
		if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
			return false;

	return true;
}

static bool __maybe_unused
is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,
			    int scope)
{
	WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
	return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);
}

static bool __maybe_unused
is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
{
	u32 model;

	WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());

	model = read_cpuid_id();
	model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |
		 MIDR_ARCHITECTURE_MASK;

	return model == entry->midr_range.model;
}

static bool
has_mismatched_cache_line_size(const struct arm64_cpu_capabilities *entry,
				int scope)
{
	WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
	return (read_cpuid_cachetype() & arm64_ftr_reg_ctrel0.strict_mask) !=
		(arm64_ftr_reg_ctrel0.sys_val & arm64_ftr_reg_ctrel0.strict_mask);
}

static void
cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *__unused)
{
	/* Clear SCTLR_EL1.UCT */
	config_sctlr_el1(SCTLR_EL1_UCT, 0);
}

atomic_t arm64_el2_vector_last_slot = ATOMIC_INIT(-1);

#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
#include <asm/mmu_context.h>
#include <asm/cacheflush.h>

DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);

#ifdef CONFIG_KVM
extern char __smccc_workaround_1_smc_start[];
extern char __smccc_workaround_1_smc_end[];
extern char __smccc_workaround_1_hvc_start[];
extern char __smccc_workaround_1_hvc_end[];

static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start,
				const char *hyp_vecs_end)
{
	void *dst = lm_alias(__bp_harden_hyp_vecs_start + slot * SZ_2K);
	int i;

	for (i = 0; i < SZ_2K; i += 0x80)
		memcpy(dst + i, hyp_vecs_start, hyp_vecs_end - hyp_vecs_start);

	flush_icache_range((uintptr_t)dst, (uintptr_t)dst + SZ_2K);
}

static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
				      const char *hyp_vecs_start,
				      const char *hyp_vecs_end)
{
	static DEFINE_SPINLOCK(bp_lock);
	int cpu, slot = -1;

	spin_lock(&bp_lock);
	for_each_possible_cpu(cpu) {
		if (per_cpu(bp_hardening_data.fn, cpu) == fn) {
			slot = per_cpu(bp_hardening_data.hyp_vectors_slot, cpu);
			break;
		}
	}

	if (slot == -1) {
		slot = atomic_inc_return(&arm64_el2_vector_last_slot);
		BUG_ON(slot >= BP_HARDEN_EL2_SLOTS);
		__copy_hyp_vect_bpi(slot, hyp_vecs_start, hyp_vecs_end);
	}

	__this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot);
	__this_cpu_write(bp_hardening_data.fn, fn);
	spin_unlock(&bp_lock);
}
#else
#define __smccc_workaround_1_smc_start		NULL
#define __smccc_workaround_1_smc_end		NULL
#define __smccc_workaround_1_hvc_start		NULL
#define __smccc_workaround_1_hvc_end		NULL

static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
				      const char *hyp_vecs_start,
				      const char *hyp_vecs_end)
{
	__this_cpu_write(bp_hardening_data.fn, fn);
}
#endif	/* CONFIG_KVM */

static void  install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry,
				     bp_hardening_cb_t fn,
				     const char *hyp_vecs_start,
				     const char *hyp_vecs_end)
{
	u64 pfr0;

	if (!entry->matches(entry, SCOPE_LOCAL_CPU))
		return;

	pfr0 = read_cpuid(ID_AA64PFR0_EL1);
	if (cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_CSV2_SHIFT))
		return;

	__install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end);
}

#include <uapi/linux/psci.h>
#include <linux/arm-smccc.h>
#include <linux/psci.h>

static void call_smc_arch_workaround_1(void)
{
	arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
}

static void call_hvc_arch_workaround_1(void)
{
	arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
}

static void qcom_link_stack_sanitization(void)
{
	u64 tmp;

	asm volatile("mov	%0, x30		\n"
		     ".rept	16		\n"
		     "bl	. + 4		\n"
		     ".endr			\n"
		     "mov	x30, %0		\n"
		     : "=&r" (tmp));
}

static void
enable_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry)
{
	bp_hardening_cb_t cb;
	void *smccc_start, *smccc_end;
	struct arm_smccc_res res;
	u32 midr = read_cpuid_id();

	if (!entry->matches(entry, SCOPE_LOCAL_CPU))
		return;

	if (psci_ops.smccc_version == SMCCC_VERSION_1_0)
		return;

	switch (psci_ops.conduit) {
	case PSCI_CONDUIT_HVC:
		arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
				  ARM_SMCCC_ARCH_WORKAROUND_1, &res);
		if ((int)res.a0 < 0)
			return;
		cb = call_hvc_arch_workaround_1;
		smccc_start = __smccc_workaround_1_hvc_start;
		smccc_end = __smccc_workaround_1_hvc_end;
		break;

	case PSCI_CONDUIT_SMC:
		arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
				  ARM_SMCCC_ARCH_WORKAROUND_1, &res);
		if ((int)res.a0 < 0)
			return;
		cb = call_smc_arch_workaround_1;
		smccc_start = __smccc_workaround_1_smc_start;
		smccc_end = __smccc_workaround_1_smc_end;
		break;

	default:
		return;
	}

	if (((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR) ||
	    ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1))
		cb = qcom_link_stack_sanitization;

	install_bp_hardening_cb(entry, cb, smccc_start, smccc_end);

	return;
}
#endif	/* CONFIG_HARDEN_BRANCH_PREDICTOR */

#define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)	\
	.matches = is_affected_midr_range,			\
	.midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)

#define CAP_MIDR_ALL_VERSIONS(model)					\
	.matches = is_affected_midr_range,				\
	.midr_range = MIDR_ALL_VERSIONS(model)

#define MIDR_FIXED(rev, revidr_mask) \
	.fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}

#define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max)		\
	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,				\
	CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)

#define CAP_MIDR_RANGE_LIST(list)				\
	.matches = is_affected_midr_range_list,			\
	.midr_range_list = list

/* Errata affecting a range of revisions of  given model variant */
#define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max)	 \
	ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)

/* Errata affecting a single variant/revision of a model */
#define ERRATA_MIDR_REV(model, var, rev)	\
	ERRATA_MIDR_RANGE(model, var, rev, var, rev)

/* Errata affecting all variants/revisions of a given a model */
#define ERRATA_MIDR_ALL_VERSIONS(model)				\
	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,			\
	CAP_MIDR_ALL_VERSIONS(model)

/* Errata affecting a list of midr ranges, with same work around */
#define ERRATA_MIDR_RANGE_LIST(midr_list)			\
	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,			\
	CAP_MIDR_RANGE_LIST(midr_list)

/*
 * Generic helper for handling capabilties with multiple (match,enable) pairs
 * of call backs, sharing the same capability bit.
 * Iterate over each entry to see if at least one matches.
 */
static bool __maybe_unused
multi_entry_cap_matches(const struct arm64_cpu_capabilities *entry, int scope)
{
	const struct arm64_cpu_capabilities *caps;

	for (caps = entry->match_list; caps->matches; caps++)
		if (caps->matches(caps, scope))
			return true;

	return false;
}

/*
 * Take appropriate action for all matching entries in the shared capability
 * entry.
 */
static void __maybe_unused
multi_entry_cap_cpu_enable(const struct arm64_cpu_capabilities *entry)
{
	const struct arm64_cpu_capabilities *caps;

	for (caps = entry->match_list; caps->matches; caps++)
		if (caps->matches(caps, SCOPE_LOCAL_CPU) &&
		    caps->cpu_enable)
			caps->cpu_enable(caps);
}

#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR

/*
 * List of CPUs where we need to issue a psci call to
 * harden the branch predictor.
 */
static const struct midr_range arm64_bp_harden_smccc_cpus[] = {
	MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
	MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
	MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
	MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
	MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
	MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
	MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
	MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
	{},
};

#endif

#ifndef ERRATA_MIDR_ALL_VERSIONS
#define	ERRATA_MIDR_ALL_VERSIONS(x)	MIDR_ALL_VERSIONS(x)
#endif

const struct arm64_cpu_capabilities arm64_errata[] = {
#if	defined(CONFIG_ARM64_ERRATUM_826319) || \
	defined(CONFIG_ARM64_ERRATUM_827319) || \
	defined(CONFIG_ARM64_ERRATUM_824069)
	{
	/* Cortex-A53 r0p[012] */
		.desc = "ARM errata 826319, 827319, 824069",
		.capability = ARM64_WORKAROUND_CLEAN_CACHE,
		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
		.cpu_enable = cpu_enable_cache_maint_trap,
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_819472
	{
	/* Cortex-A53 r0p[01] */
		.desc = "ARM errata 819472",
		.capability = ARM64_WORKAROUND_CLEAN_CACHE,
		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
		.cpu_enable = cpu_enable_cache_maint_trap,
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_832075
	{
	/* Cortex-A57 r0p0 - r1p2 */
		.desc = "ARM erratum 832075",
		.capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
		ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
				  0, 0,
				  1, 2),
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_834220
	{
	/* Cortex-A57 r0p0 - r1p2 */
		.desc = "ARM erratum 834220",
		.capability = ARM64_WORKAROUND_834220,
		ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
				  0, 0,
				  1, 2),
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_843419
	{
	/* Cortex-A53 r0p[01234] */
		.desc = "ARM erratum 843419",
		.capability = ARM64_WORKAROUND_843419,
		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
		MIDR_FIXED(0x4, BIT(8)),
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_845719
	{
	/* Cortex-A53 r0p[01234] */
		.desc = "ARM erratum 845719",
		.capability = ARM64_WORKAROUND_845719,
		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
	},
#endif
#ifdef CONFIG_CAVIUM_ERRATUM_23154
	{
	/* Cavium ThunderX, pass 1.x */
		.desc = "Cavium erratum 23154",
		.capability = ARM64_WORKAROUND_CAVIUM_23154,
		ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX, 0, 0, 1),
	},
#endif
#ifdef CONFIG_CAVIUM_ERRATUM_27456
	{
	/* Cavium ThunderX, T88 pass 1.x - 2.1 */
		.desc = "Cavium erratum 27456",
		.capability = ARM64_WORKAROUND_CAVIUM_27456,
		ERRATA_MIDR_RANGE(MIDR_THUNDERX,
				  0, 0,
				  1, 1),
	},
	{
	/* Cavium ThunderX, T81 pass 1.0 */
		.desc = "Cavium erratum 27456",
		.capability = ARM64_WORKAROUND_CAVIUM_27456,
		ERRATA_MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),
	},
#endif
#ifdef CONFIG_CAVIUM_ERRATUM_30115
	{
	/* Cavium ThunderX, T88 pass 1.x - 2.2 */
		.desc = "Cavium erratum 30115",
		.capability = ARM64_WORKAROUND_CAVIUM_30115,
		ERRATA_MIDR_RANGE(MIDR_THUNDERX,
				      0, 0,
				      1, 2),
	},
	{
	/* Cavium ThunderX, T81 pass 1.0 - 1.2 */
		.desc = "Cavium erratum 30115",
		.capability = ARM64_WORKAROUND_CAVIUM_30115,
		ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),
	},
	{
	/* Cavium ThunderX, T83 pass 1.0 */
		.desc = "Cavium erratum 30115",
		.capability = ARM64_WORKAROUND_CAVIUM_30115,
		ERRATA_MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),
	},
#endif
	{
		.desc = "Mismatched cache line size",
		.capability = ARM64_MISMATCHED_CACHE_LINE_SIZE,
		.matches = has_mismatched_cache_line_size,
		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
		.cpu_enable = cpu_enable_trap_ctr_access,
	},
#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
	{
		.desc = "Qualcomm Technologies Falkor erratum 1003",
		.capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
		ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
	},
	{
		.desc = "Qualcomm Technologies Kryo erratum 1003",
		.capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
		.midr_range.model = MIDR_QCOM_KRYO,
		.matches = is_kryo_midr,
	},
#endif
#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
	{
		.desc = "Qualcomm Technologies Falkor erratum 1009",
		.capability = ARM64_WORKAROUND_REPEAT_TLBI,
		ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_858921
	{
	/* Cortex-A73 all versions */
		.desc = "ARM erratum 858921",
		.capability = ARM64_WORKAROUND_858921,
		ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
	},
#endif
#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
	{
		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
		.cpu_enable = enable_smccc_arch_workaround_1,
		ERRATA_MIDR_RANGE_LIST(arm64_bp_harden_smccc_cpus),
	},
#endif
#ifdef CONFIG_HARDEN_EL2_VECTORS
	{
		.desc = "Cortex-A57 EL2 vector hardening",
		.capability = ARM64_HARDEN_EL2_VECTORS,
		ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
	},
	{
		.desc = "Cortex-A72 EL2 vector hardening",
		.capability = ARM64_HARDEN_EL2_VECTORS,
		ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
	},
#endif
	{
	}
};
Commit	Line	Data
e116a375 AP	1	/*
	2	* Contains CPU specific errata definitions
	3	*
	4	* Copyright (C) 2014 ARM Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	17	*/
	18
e116a375 AP	19	#include <linux/types.h>
	20	#include <asm/cpu.h>
	21	#include <asm/cputype.h>
	22	#include <asm/cpufeature.h>
	23
301bcfac	24	static bool __maybe_unused
92406f0c	25	is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
301bcfac	26	{
e8002e02 AB	27	const struct arm64_midr_revidr *fix;
	28	u32 midr = read_cpuid_id(), revidr;
	29
92406f0c	30	WARN_ON(scope != SCOPE_LOCAL_CPU \|\| preemptible());
1df31050	31	if (!is_midr_in_range(midr, &entry->midr_range))
e8002e02 AB	32	return false;
	33
	34	midr &= MIDR_REVISION_MASK \| MIDR_VARIANT_MASK;
	35	revidr = read_cpuid(REVIDR_EL1);
	36	for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
	37	if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
	38	return false;
	39
	40	return true;
301bcfac AP	41	}
301bcfac AP	42
be5b2998 SP	43	static bool __maybe_unused
	44	is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,
	45	int scope)
301bcfac	46	{
92406f0c	47	WARN_ON(scope != SCOPE_LOCAL_CPU \|\| preemptible());
be5b2998	48	return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);
301bcfac AP	49	}
301bcfac AP	50
bb487118 SB	51	static bool __maybe_unused
	52	is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
	53	{
	54	u32 model;
	55
	56	WARN_ON(scope != SCOPE_LOCAL_CPU \|\| preemptible());
	57
	58	model = read_cpuid_id();
	59	model &= MIDR_IMPLEMENTOR_MASK \| (0xf00 << MIDR_PARTNUM_SHIFT) \|
	60	MIDR_ARCHITECTURE_MASK;
	61
1df31050	62	return model == entry->midr_range.model;
bb487118 SB	63	}
bb487118 SB	64
116c81f4 SP	65	static bool
	66	has_mismatched_cache_line_size(const struct arm64_cpu_capabilities *entry,
	67	int scope)
	68	{
	69	WARN_ON(scope != SCOPE_LOCAL_CPU \|\| preemptible());
	70	return (read_cpuid_cachetype() & arm64_ftr_reg_ctrel0.strict_mask) !=
	71	(arm64_ftr_reg_ctrel0.sys_val & arm64_ftr_reg_ctrel0.strict_mask);
	72	}
	73
c0cda3b8 DM	74	static void
c0cda3b8 DM	75	cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *__unused)
116c81f4 SP	76	{
	77	/* Clear SCTLR_EL1.UCT */
	78	config_sctlr_el1(SCTLR_EL1_UCT, 0);
	79	}
	80
4205a89b MZ	81	atomic_t arm64_el2_vector_last_slot = ATOMIC_INIT(-1);
4205a89b MZ	82
0f15adbb WD	83	#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
	84	#include <asm/mmu_context.h>
	85	#include <asm/cacheflush.h>
	86
	87	DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);
	88
	89	#ifdef CONFIG_KVM
b092201e MZ	90	extern char __smccc_workaround_1_smc_start[];
	91	extern char __smccc_workaround_1_smc_end[];
	92	extern char __smccc_workaround_1_hvc_start[];
	93	extern char __smccc_workaround_1_hvc_end[];
aa6acde6	94
0f15adbb WD	95	static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start,
	96	const char *hyp_vecs_end)
	97	{
	98	void dst = lm_alias(__bp_harden_hyp_vecs_start + slot SZ_2K);
	99	int i;
	100
	101	for (i = 0; i < SZ_2K; i += 0x80)
	102	memcpy(dst + i, hyp_vecs_start, hyp_vecs_end - hyp_vecs_start);
	103
	104	flush_icache_range((uintptr_t)dst, (uintptr_t)dst + SZ_2K);
	105	}
	106
	107	static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
	108	const char *hyp_vecs_start,
	109	const char *hyp_vecs_end)
	110	{
0f15adbb WD	111	static DEFINE_SPINLOCK(bp_lock);
	112	int cpu, slot = -1;
	113
	114	spin_lock(&bp_lock);
	115	for_each_possible_cpu(cpu) {
	116	if (per_cpu(bp_hardening_data.fn, cpu) == fn) {
	117	slot = per_cpu(bp_hardening_data.hyp_vectors_slot, cpu);
	118	break;
	119	}
	120	}
	121
	122	if (slot == -1) {
4205a89b MZ	123	slot = atomic_inc_return(&arm64_el2_vector_last_slot);
4205a89b MZ	124	BUG_ON(slot >= BP_HARDEN_EL2_SLOTS);
0f15adbb WD	125	__copy_hyp_vect_bpi(slot, hyp_vecs_start, hyp_vecs_end);
	126	}
	127
	128	__this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot);
	129	__this_cpu_write(bp_hardening_data.fn, fn);
	130	spin_unlock(&bp_lock);
	131	}
	132	#else
b092201e MZ	133	#define __smccc_workaround_1_smc_start NULL
	134	#define __smccc_workaround_1_smc_end NULL
	135	#define __smccc_workaround_1_hvc_start NULL
	136	#define __smccc_workaround_1_hvc_end NULL
aa6acde6	137
0f15adbb WD	138	static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
	139	const char *hyp_vecs_start,
	140	const char *hyp_vecs_end)
	141	{
	142	__this_cpu_write(bp_hardening_data.fn, fn);
	143	}
	144	#endif /* CONFIG_KVM */
	145
	146	static void install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry,
	147	bp_hardening_cb_t fn,
	148	const char *hyp_vecs_start,
	149	const char *hyp_vecs_end)
	150	{
	151	u64 pfr0;
	152
	153	if (!entry->matches(entry, SCOPE_LOCAL_CPU))
	154	return;
	155
	156	pfr0 = read_cpuid(ID_AA64PFR0_EL1);
	157	if (cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_CSV2_SHIFT))
	158	return;
	159
	160	__install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end);
	161	}
aa6acde6	162
b092201e MZ	163	#include <uapi/linux/psci.h>
b092201e MZ	164	#include <linux/arm-smccc.h>
aa6acde6 WD	165	#include <linux/psci.h>
aa6acde6 WD	166
b092201e MZ	167	static void call_smc_arch_workaround_1(void)
	168	{
	169	arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
	170	}
	171
	172	static void call_hvc_arch_workaround_1(void)
	173	{
	174	arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
	175	}
	176
4bc352ff SD	177	static void qcom_link_stack_sanitization(void)
	178	{
	179	u64 tmp;
	180
	181	asm volatile("mov %0, x30 \n"
	182	".rept 16 \n"
	183	"bl . + 4 \n"
	184	".endr \n"
	185	"mov x30, %0 \n"
	186	: "=&r" (tmp));
	187	}
	188
c0cda3b8 DM	189	static void
c0cda3b8 DM	190	enable_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry)
b092201e MZ	191	{
	192	bp_hardening_cb_t cb;
	193	void smccc_start, smccc_end;
	194	struct arm_smccc_res res;
4bc352ff	195	u32 midr = read_cpuid_id();
b092201e MZ	196
b092201e MZ	197	if (!entry->matches(entry, SCOPE_LOCAL_CPU))
c0cda3b8	198	return;
b092201e MZ	199
b092201e MZ	200	if (psci_ops.smccc_version == SMCCC_VERSION_1_0)
c0cda3b8	201	return;
b092201e MZ	202
	203	switch (psci_ops.conduit) {
	204	case PSCI_CONDUIT_HVC:
	205	arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
	206	ARM_SMCCC_ARCH_WORKAROUND_1, &res);
e21da1c9	207	if ((int)res.a0 < 0)
c0cda3b8	208	return;
b092201e MZ	209	cb = call_hvc_arch_workaround_1;
	210	smccc_start = __smccc_workaround_1_hvc_start;
	211	smccc_end = __smccc_workaround_1_hvc_end;
	212	break;
	213
	214	case PSCI_CONDUIT_SMC:
	215	arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
	216	ARM_SMCCC_ARCH_WORKAROUND_1, &res);
e21da1c9	217	if ((int)res.a0 < 0)
c0cda3b8	218	return;
b092201e MZ	219	cb = call_smc_arch_workaround_1;
	220	smccc_start = __smccc_workaround_1_smc_start;
	221	smccc_end = __smccc_workaround_1_smc_end;
	222	break;
	223
	224	default:
c0cda3b8	225	return;
b092201e MZ	226	}
b092201e MZ	227
4bc352ff SD	228	if (((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR) \|\|
	229	((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1))
	230	cb = qcom_link_stack_sanitization;
	231
b092201e MZ	232	install_bp_hardening_cb(entry, cb, smccc_start, smccc_end);
b092201e MZ	233
c0cda3b8	234	return;
aa6acde6	235	}
0f15adbb WD	236	#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */
0f15adbb WD	237
5e7951ce SP	238	#define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
5e7951ce SP	239	.matches = is_affected_midr_range, \
1df31050	240	.midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)
5e7951ce SP	241
	242	#define CAP_MIDR_ALL_VERSIONS(model) \
	243	.matches = is_affected_midr_range, \
1df31050	244	.midr_range = MIDR_ALL_VERSIONS(model)
06f1494f	245
e8002e02 AB	246	#define MIDR_FIXED(rev, revidr_mask) \
	247	.fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}
	248
5e7951ce SP	249	#define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
	250	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
	251	CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)
	252
be5b2998 SP	253	#define CAP_MIDR_RANGE_LIST(list) \
	254	.matches = is_affected_midr_range_list, \
	255	.midr_range_list = list
	256
5e7951ce SP	257	/* Errata affecting a range of revisions of given model variant */
	258	#define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \
	259	ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)
	260
	261	/* Errata affecting a single variant/revision of a model */
	262	#define ERRATA_MIDR_REV(model, var, rev) \
	263	ERRATA_MIDR_RANGE(model, var, rev, var, rev)
	264
	265	/* Errata affecting all variants/revisions of a given a model */
	266	#define ERRATA_MIDR_ALL_VERSIONS(model) \
	267	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
	268	CAP_MIDR_ALL_VERSIONS(model)
	269
be5b2998 SP	270	/* Errata affecting a list of midr ranges, with same work around */
	271	#define ERRATA_MIDR_RANGE_LIST(midr_list) \
	272	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
	273	CAP_MIDR_RANGE_LIST(midr_list)
	274
ba7d9233 SP	275	/*
	276	* Generic helper for handling capabilties with multiple (match,enable) pairs
	277	* of call backs, sharing the same capability bit.
	278	* Iterate over each entry to see if at least one matches.
	279	*/
12eb3691 WD	280	static bool __maybe_unused
12eb3691 WD	281	multi_entry_cap_matches(const struct arm64_cpu_capabilities *entry, int scope)
ba7d9233 SP	282	{
	283	const struct arm64_cpu_capabilities *caps;
	284
	285	for (caps = entry->match_list; caps->matches; caps++)
	286	if (caps->matches(caps, scope))
	287	return true;
	288
	289	return false;
	290	}
	291
	292	/*
	293	* Take appropriate action for all matching entries in the shared capability
	294	* entry.
	295	*/
12eb3691	296	static void __maybe_unused
ba7d9233 SP	297	multi_entry_cap_cpu_enable(const struct arm64_cpu_capabilities *entry)
	298	{
	299	const struct arm64_cpu_capabilities *caps;
301bcfac	300
ba7d9233 SP	301	for (caps = entry->match_list; caps->matches; caps++)
	302	if (caps->matches(caps, SCOPE_LOCAL_CPU) &&
	303	caps->cpu_enable)
	304	caps->cpu_enable(caps);
	305	}
	306
be5b2998 SP	307	#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
	308
	309	/*
	310	* List of CPUs where we need to issue a psci call to
	311	* harden the branch predictor.
	312	*/
	313	static const struct midr_range arm64_bp_harden_smccc_cpus[] = {
	314	MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
	315	MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
	316	MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
	317	MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
	318	MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
	319	MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
be5b2998 SP	320	MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
	321	MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
	322	{},
	323	};
	324
	325	#endif
06f1494f	326
dc6ed61d MZ	327	#ifndef ERRATA_MIDR_ALL_VERSIONS
	328	#define ERRATA_MIDR_ALL_VERSIONS(x) MIDR_ALL_VERSIONS(x)
	329	#endif
	330
359b7064	331	const struct arm64_cpu_capabilities arm64_errata[] = {
c0a01b84 AP	332	#if defined(CONFIG_ARM64_ERRATUM_826319) \|\| \
	333	defined(CONFIG_ARM64_ERRATUM_827319) \|\| \
	334	defined(CONFIG_ARM64_ERRATUM_824069)
301bcfac AP	335	{
	336	/* Cortex-A53 r0p[012] */
	337	.desc = "ARM errata 826319, 827319, 824069",
	338	.capability = ARM64_WORKAROUND_CLEAN_CACHE,
5e7951ce	339	ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
c0cda3b8	340	.cpu_enable = cpu_enable_cache_maint_trap,
301bcfac	341	},
c0a01b84 AP	342	#endif
	343	#ifdef CONFIG_ARM64_ERRATUM_819472
	344	{
	345	/* Cortex-A53 r0p[01] */
	346	.desc = "ARM errata 819472",
	347	.capability = ARM64_WORKAROUND_CLEAN_CACHE,
5e7951ce	348	ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
c0cda3b8	349	.cpu_enable = cpu_enable_cache_maint_trap,
c0a01b84 AP	350	},
	351	#endif
	352	#ifdef CONFIG_ARM64_ERRATUM_832075
301bcfac	353	{
5afaa1fc AP	354	/* Cortex-A57 r0p0 - r1p2 */
	355	.desc = "ARM erratum 832075",
	356	.capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
5e7951ce SP	357	ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
	358	0, 0,
	359	1, 2),
5afaa1fc	360	},
905e8c5d	361	#endif
498cd5c3 MZ	362	#ifdef CONFIG_ARM64_ERRATUM_834220
	363	{
	364	/* Cortex-A57 r0p0 - r1p2 */
	365	.desc = "ARM erratum 834220",
	366	.capability = ARM64_WORKAROUND_834220,
5e7951ce SP	367	ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
	368	0, 0,
	369	1, 2),
498cd5c3 MZ	370	},
498cd5c3 MZ	371	#endif
ca79acca AB	372	#ifdef CONFIG_ARM64_ERRATUM_843419
	373	{
	374	/* Cortex-A53 r0p[01234] */
	375	.desc = "ARM erratum 843419",
	376	.capability = ARM64_WORKAROUND_843419,
5e7951ce	377	ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
ca79acca	378	MIDR_FIXED(0x4, BIT(8)),
498cd5c3 MZ	379	},
498cd5c3 MZ	380	#endif
905e8c5d WD	381	#ifdef CONFIG_ARM64_ERRATUM_845719
	382	{
	383	/* Cortex-A53 r0p[01234] */
	384	.desc = "ARM erratum 845719",
	385	.capability = ARM64_WORKAROUND_845719,
5e7951ce	386	ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
905e8c5d	387	},
6d4e11c5 RR	388	#endif
	389	#ifdef CONFIG_CAVIUM_ERRATUM_23154
	390	{
	391	/* Cavium ThunderX, pass 1.x */
	392	.desc = "Cavium erratum 23154",
	393	.capability = ARM64_WORKAROUND_CAVIUM_23154,
5e7951ce	394	ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX, 0, 0, 1),
6d4e11c5	395	},
104a0c02 AP	396	#endif
	397	#ifdef CONFIG_CAVIUM_ERRATUM_27456
	398	{
	399	/* Cavium ThunderX, T88 pass 1.x - 2.1 */
	400	.desc = "Cavium erratum 27456",
	401	.capability = ARM64_WORKAROUND_CAVIUM_27456,
5e7951ce SP	402	ERRATA_MIDR_RANGE(MIDR_THUNDERX,
	403	0, 0,
	404	1, 1),
104a0c02	405	},
47c459be GK	406	{
	407	/* Cavium ThunderX, T81 pass 1.0 */
	408	.desc = "Cavium erratum 27456",
	409	.capability = ARM64_WORKAROUND_CAVIUM_27456,
5e7951ce	410	ERRATA_MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),
47c459be	411	},
690a3415 DD	412	#endif
	413	#ifdef CONFIG_CAVIUM_ERRATUM_30115
	414	{
	415	/* Cavium ThunderX, T88 pass 1.x - 2.2 */
	416	.desc = "Cavium erratum 30115",
	417	.capability = ARM64_WORKAROUND_CAVIUM_30115,
5e7951ce SP	418	ERRATA_MIDR_RANGE(MIDR_THUNDERX,
	419	0, 0,
	420	1, 2),
690a3415 DD	421	},
	422	{
	423	/* Cavium ThunderX, T81 pass 1.0 - 1.2 */
	424	.desc = "Cavium erratum 30115",
	425	.capability = ARM64_WORKAROUND_CAVIUM_30115,
5e7951ce	426	ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),
690a3415 DD	427	},
	428	{
	429	/* Cavium ThunderX, T83 pass 1.0 */
	430	.desc = "Cavium erratum 30115",
	431	.capability = ARM64_WORKAROUND_CAVIUM_30115,
5e7951ce	432	ERRATA_MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),
690a3415	433	},
c0a01b84	434	#endif
116c81f4 SP	435	{
	436	.desc = "Mismatched cache line size",
	437	.capability = ARM64_MISMATCHED_CACHE_LINE_SIZE,
	438	.matches = has_mismatched_cache_line_size,
5b4747c5	439	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
c0cda3b8	440	.cpu_enable = cpu_enable_trap_ctr_access,
116c81f4	441	},
38fd94b0 CC	442	#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
	443	{
	444	.desc = "Qualcomm Technologies Falkor erratum 1003",
	445	.capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
5e7951ce	446	ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
38fd94b0	447	},
bb487118 SB	448	{
	449	.desc = "Qualcomm Technologies Kryo erratum 1003",
	450	.capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
5b4747c5	451	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
1df31050	452	.midr_range.model = MIDR_QCOM_KRYO,
bb487118 SB	453	.matches = is_kryo_midr,
bb487118 SB	454	},
38fd94b0	455	#endif
d9ff80f8 CC	456	#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
	457	{
	458	.desc = "Qualcomm Technologies Falkor erratum 1009",
	459	.capability = ARM64_WORKAROUND_REPEAT_TLBI,
5e7951ce	460	ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
d9ff80f8	461	},
eeb1efbc MZ	462	#endif
	463	#ifdef CONFIG_ARM64_ERRATUM_858921
	464	{
	465	/* Cortex-A73 all versions */
	466	.desc = "ARM erratum 858921",
	467	.capability = ARM64_WORKAROUND_858921,
5e7951ce	468	ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
eeb1efbc	469	},
aa6acde6 WD	470	#endif
	471	#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
	472	{
	473	.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
ba7d9233	474	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
4bc352ff SD	475	.cpu_enable = enable_smccc_arch_workaround_1,
4bc352ff SD	476	ERRATA_MIDR_RANGE_LIST(arm64_bp_harden_smccc_cpus),
f3d795d9	477	},
4b472ffd MZ	478	#endif
	479	#ifdef CONFIG_HARDEN_EL2_VECTORS
	480	{
	481	.desc = "Cortex-A57 EL2 vector hardening",
	482	.capability = ARM64_HARDEN_EL2_VECTORS,
dc6ed61d	483	ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
4b472ffd MZ	484	},
	485	{
	486	.desc = "Cortex-A72 EL2 vector hardening",
	487	.capability = ARM64_HARDEN_EL2_VECTORS,
dc6ed61d	488	ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
4b472ffd	489	},
d9ff80f8	490	#endif
5afaa1fc	491	{
301bcfac	492	}
e116a375	493	};