[mirror_ubuntu-artful-kernel.git] / arch / arm64 / kernel / cpu_errata.c

/*
 * Contains CPU specific errata definitions
 *
 * Copyright (C) 2014 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/types.h>
#include <asm/cpu.h>
#include <asm/cputype.h>
#include <asm/cpufeature.h>

#define MIDR_CORTEX_A53 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
#define MIDR_CORTEX_A57 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)

#define CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \
			MIDR_ARCHITECTURE_MASK)

static bool __maybe_unused
is_affected_midr_range(const struct arm64_cpu_capabilities *entry)
{
	u32 midr = read_cpuid_id();

	if ((midr & CPU_MODEL_MASK) != entry->midr_model)
		return false;

	midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;

	return (midr >= entry->midr_range_min && midr <= entry->midr_range_max);
}

#define MIDR_RANGE(model, min, max) \
	.matches = is_affected_midr_range, \
	.midr_model = model, \
	.midr_range_min = min, \
	.midr_range_max = max

const struct arm64_cpu_capabilities arm64_errata[] = {
#if	defined(CONFIG_ARM64_ERRATUM_826319) || \
	defined(CONFIG_ARM64_ERRATUM_827319) || \
	defined(CONFIG_ARM64_ERRATUM_824069)
	{
	/* Cortex-A53 r0p[012] */
		.desc = "ARM errata 826319, 827319, 824069",
		.capability = ARM64_WORKAROUND_CLEAN_CACHE,
		MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02),
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_819472
	{
	/* Cortex-A53 r0p[01] */
		.desc = "ARM errata 819472",
		.capability = ARM64_WORKAROUND_CLEAN_CACHE,
		MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x01),
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_832075
	{
	/* Cortex-A57 r0p0 - r1p2 */
		.desc = "ARM erratum 832075",
		.capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
		MIDR_RANGE(MIDR_CORTEX_A57, 0x00,
			   (1 << MIDR_VARIANT_SHIFT) | 2),
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_845719
	{
	/* Cortex-A53 r0p[01234] */
		.desc = "ARM erratum 845719",
		.capability = ARM64_WORKAROUND_845719,
		MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04),
	},
#endif
	{
	}
};

void check_local_cpu_errata(void)
{
	check_cpu_capabilities(arm64_errata, "enabling workaround for");
}
Commit	Line	Data
e116a375 AP	1	/*
	2	* Contains CPU specific errata definitions
	3	*
	4	* Copyright (C) 2014 ARM Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	17	*/
	18
e116a375 AP	19	#include <linux/types.h>
	20	#include <asm/cpu.h>
	21	#include <asm/cputype.h>
	22	#include <asm/cpufeature.h>
	23
301bcfac	24	#define MIDR_CORTEX_A53 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
5afaa1fc	25	#define MIDR_CORTEX_A57 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
301bcfac	26
301bcfac AP	27	#define CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK \| MIDR_PARTNUM_MASK \| \
	28	MIDR_ARCHITECTURE_MASK)
	29
	30	static bool __maybe_unused
359b7064	31	is_affected_midr_range(const struct arm64_cpu_capabilities *entry)
301bcfac AP	32	{
	33	u32 midr = read_cpuid_id();
	34
	35	if ((midr & CPU_MODEL_MASK) != entry->midr_model)
	36	return false;
	37
	38	midr &= MIDR_REVISION_MASK \| MIDR_VARIANT_MASK;
	39
	40	return (midr >= entry->midr_range_min && midr <= entry->midr_range_max);
	41	}
	42
	43	#define MIDR_RANGE(model, min, max) \
359b7064	44	.matches = is_affected_midr_range, \
301bcfac AP	45	.midr_model = model, \
	46	.midr_range_min = min, \
	47	.midr_range_max = max
	48
359b7064	49	const struct arm64_cpu_capabilities arm64_errata[] = {
c0a01b84 AP	50	#if defined(CONFIG_ARM64_ERRATUM_826319) \|\| \
	51	defined(CONFIG_ARM64_ERRATUM_827319) \|\| \
	52	defined(CONFIG_ARM64_ERRATUM_824069)
301bcfac AP	53	{
	54	/* Cortex-A53 r0p[012] */
	55	.desc = "ARM errata 826319, 827319, 824069",
	56	.capability = ARM64_WORKAROUND_CLEAN_CACHE,
	57	MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02),
	58	},
c0a01b84 AP	59	#endif
	60	#ifdef CONFIG_ARM64_ERRATUM_819472
	61	{
	62	/* Cortex-A53 r0p[01] */
	63	.desc = "ARM errata 819472",
	64	.capability = ARM64_WORKAROUND_CLEAN_CACHE,
	65	MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x01),
	66	},
	67	#endif
	68	#ifdef CONFIG_ARM64_ERRATUM_832075
301bcfac	69	{
5afaa1fc AP	70	/* Cortex-A57 r0p0 - r1p2 */
	71	.desc = "ARM erratum 832075",
	72	.capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
6d1966df BY	73	MIDR_RANGE(MIDR_CORTEX_A57, 0x00,
6d1966df BY	74	(1 << MIDR_VARIANT_SHIFT) \| 2),
5afaa1fc	75	},
905e8c5d WD	76	#endif
	77	#ifdef CONFIG_ARM64_ERRATUM_845719
	78	{
	79	/* Cortex-A53 r0p[01234] */
	80	.desc = "ARM erratum 845719",
	81	.capability = ARM64_WORKAROUND_845719,
	82	MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04),
	83	},
c0a01b84	84	#endif
5afaa1fc	85	{
301bcfac	86	}
e116a375 AP	87	};
	88
	89	void check_local_cpu_errata(void)
	90	{
359b7064	91	check_cpu_capabilities(arm64_errata, "enabling workaround for");
e116a375	92	}