[mirror_ubuntu-jammy-kernel.git] / arch / arm64 / kernel / cpu_errata.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Contains CPU specific errata definitions
 *
 * Copyright (C) 2014 ARM Ltd.
 */

#include <linux/arm-smccc.h>
#include <linux/types.h>
#include <linux/cpu.h>
#include <asm/cpu.h>
#include <asm/cputype.h>
#include <asm/cpufeature.h>
#include <asm/kvm_asm.h>
#include <asm/smp_plat.h>

static bool __maybe_unused
is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
{
	const struct arm64_midr_revidr *fix;
	u32 midr = read_cpuid_id(), revidr;

	WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
	if (!is_midr_in_range(midr, &entry->midr_range))
		return false;

	midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
	revidr = read_cpuid(REVIDR_EL1);
	for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
		if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
			return false;

	return true;
}

static bool __maybe_unused
is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,
			    int scope)
{
	WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
	return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);
}

static bool __maybe_unused
is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
{
	u32 model;

	WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());

	model = read_cpuid_id();
	model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |
		 MIDR_ARCHITECTURE_MASK;

	return model == entry->midr_range.model;
}

static bool
has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry,
			  int scope)
{
	u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
	u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask;
	u64 ctr_raw, ctr_real;

	WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());

	/*
	 * We want to make sure that all the CPUs in the system expose
	 * a consistent CTR_EL0 to make sure that applications behaves
	 * correctly with migration.
	 *
	 * If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 :
	 *
	 * 1) It is safe if the system doesn't support IDC, as CPU anyway
	 *    reports IDC = 0, consistent with the rest.
	 *
	 * 2) If the system has IDC, it is still safe as we trap CTR_EL0
	 *    access on this CPU via the ARM64_HAS_CACHE_IDC capability.
	 *
	 * So, we need to make sure either the raw CTR_EL0 or the effective
	 * CTR_EL0 matches the system's copy to allow a secondary CPU to boot.
	 */
	ctr_raw = read_cpuid_cachetype() & mask;
	ctr_real = read_cpuid_effective_cachetype() & mask;

	return (ctr_real != sys) && (ctr_raw != sys);
}

static void
cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap)
{
	u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
	bool enable_uct_trap = false;

	/* Trap CTR_EL0 access on this CPU, only if it has a mismatch */
	if ((read_cpuid_cachetype() & mask) !=
	    (arm64_ftr_reg_ctrel0.sys_val & mask))
		enable_uct_trap = true;

	/* ... or if the system is affected by an erratum */
	if (cap->capability == ARM64_WORKAROUND_1542419)
		enable_uct_trap = true;

	if (enable_uct_trap)
		sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
}

int ssbd_state __read_mostly = ARM64_SSBD_UNKNOWN;

void __init arm64_enable_wa2_handling(struct alt_instr *alt,
				      __le32 *origptr, __le32 *updptr,
				      int nr_inst)
{
	BUG_ON(nr_inst != 1);
	/*
	 * Only allow mitigation on EL1 entry/exit and guest
	 * ARCH_WORKAROUND_2 handling if the SSBD state allows it to
	 * be flipped.
	 */
	if (arm64_get_ssbd_state() == ARM64_SSBD_KERNEL)
		*updptr = cpu_to_le32(aarch64_insn_gen_nop());
}

#ifdef CONFIG_ARM64_ERRATUM_1463225
DEFINE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa);

static bool
has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry,
			       int scope)
{
	return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode();
}
#endif

static void __maybe_unused
cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)
{
	sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0);
}

#define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)	\
	.matches = is_affected_midr_range,			\
	.midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)

#define CAP_MIDR_ALL_VERSIONS(model)					\
	.matches = is_affected_midr_range,				\
	.midr_range = MIDR_ALL_VERSIONS(model)

#define MIDR_FIXED(rev, revidr_mask) \
	.fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}

#define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max)		\
	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,				\
	CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)

#define CAP_MIDR_RANGE_LIST(list)				\
	.matches = is_affected_midr_range_list,			\
	.midr_range_list = list

/* Errata affecting a range of revisions of  given model variant */
#define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max)	 \
	ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)

/* Errata affecting a single variant/revision of a model */
#define ERRATA_MIDR_REV(model, var, rev)	\
	ERRATA_MIDR_RANGE(model, var, rev, var, rev)

/* Errata affecting all variants/revisions of a given a model */
#define ERRATA_MIDR_ALL_VERSIONS(model)				\
	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,			\
	CAP_MIDR_ALL_VERSIONS(model)

/* Errata affecting a list of midr ranges, with same work around */
#define ERRATA_MIDR_RANGE_LIST(midr_list)			\
	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,			\
	CAP_MIDR_RANGE_LIST(midr_list)

static const __maybe_unused struct midr_range tx2_family_cpus[] = {
	MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
	MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
	{},
};

static bool __maybe_unused
needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry,
			 int scope)
{
	int i;

	if (!is_affected_midr_range_list(entry, scope) ||
	    !is_hyp_mode_available())
		return false;

	for_each_possible_cpu(i) {
		if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0)
			return true;
	}

	return false;
}

static bool __maybe_unused
has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry,
				int scope)
{
	u32 midr = read_cpuid_id();
	bool has_dic = read_cpuid_cachetype() & BIT(CTR_DIC_SHIFT);
	const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1);

	WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
	return is_midr_in_range(midr, &range) && has_dic;
}

#ifdef CONFIG_RANDOMIZE_BASE

static const struct midr_range ca57_a72[] = {
	MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
	MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
	{},
};

#endif

#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
	{
		ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0)
	},
	{
		.midr_range.model = MIDR_QCOM_KRYO,
		.matches = is_kryo_midr,
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_1286807
	{
		ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
	},
#endif
	{},
};
#endif

#ifdef CONFIG_CAVIUM_ERRATUM_27456
const struct midr_range cavium_erratum_27456_cpus[] = {
	/* Cavium ThunderX, T88 pass 1.x - 2.1 */
	MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1),
	/* Cavium ThunderX, T81 pass 1.0 */
	MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),
	{},
};
#endif

#ifdef CONFIG_CAVIUM_ERRATUM_30115
static const struct midr_range cavium_erratum_30115_cpus[] = {
	/* Cavium ThunderX, T88 pass 1.x - 2.2 */
	MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2),
	/* Cavium ThunderX, T81 pass 1.0 - 1.2 */
	MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),
	/* Cavium ThunderX, T83 pass 1.0 */
	MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),
	{},
};
#endif

#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = {
	{
		ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
	},
	{
		.midr_range.model = MIDR_QCOM_KRYO,
		.matches = is_kryo_midr,
	},
	{},
};
#endif

#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
static const struct midr_range workaround_clean_cache[] = {
#if	defined(CONFIG_ARM64_ERRATUM_826319) || \
	defined(CONFIG_ARM64_ERRATUM_827319) || \
	defined(CONFIG_ARM64_ERRATUM_824069)
	/* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */
	MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
#endif
#ifdef	CONFIG_ARM64_ERRATUM_819472
	/* Cortex-A53 r0p[01] : ARM errata 819472 */
	MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
#endif
	{},
};
#endif

#ifdef CONFIG_ARM64_ERRATUM_1418040
/*
 * - 1188873 affects r0p0 to r2p0
 * - 1418040 affects r0p0 to r3p1
 */
static const struct midr_range erratum_1418040_list[] = {
	/* Cortex-A76 r0p0 to r3p1 */
	MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
	/* Neoverse-N1 r0p0 to r3p1 */
	MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1),
	/* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
	MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
	{},
};
#endif

#ifdef CONFIG_ARM64_ERRATUM_845719
static const struct midr_range erratum_845719_list[] = {
	/* Cortex-A53 r0p[01234] */
	MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
	/* Brahma-B53 r0p[0] */
	MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
	{},
};
#endif

#ifdef CONFIG_ARM64_ERRATUM_843419
static const struct arm64_cpu_capabilities erratum_843419_list[] = {
	{
		/* Cortex-A53 r0p[01234] */
		.matches = is_affected_midr_range,
		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
		MIDR_FIXED(0x4, BIT(8)),
	},
	{
		/* Brahma-B53 r0p[0] */
		.matches = is_affected_midr_range,
		ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
	},
	{},
};
#endif

#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
static const struct midr_range erratum_speculative_at_list[] = {
#ifdef CONFIG_ARM64_ERRATUM_1165522
	/* Cortex A76 r0p0 to r2p0 */
	MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
#endif
#ifdef CONFIG_ARM64_ERRATUM_1319367
	MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
	MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
#endif
#ifdef CONFIG_ARM64_ERRATUM_1530923
	/* Cortex A55 r0p0 to r2p0 */
	MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0),
	/* Kryo4xx Silver (rdpe => r1p0) */
	MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
#endif
	{},
};
#endif

#ifdef CONFIG_ARM64_ERRATUM_1463225
static const struct midr_range erratum_1463225[] = {
	/* Cortex-A76 r0p0 - r3p1 */
	MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
	/* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
	MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
	{},
};
#endif

const struct arm64_cpu_capabilities arm64_errata[] = {
#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
	{
		.desc = "ARM errata 826319, 827319, 824069, or 819472",
		.capability = ARM64_WORKAROUND_CLEAN_CACHE,
		ERRATA_MIDR_RANGE_LIST(workaround_clean_cache),
		.cpu_enable = cpu_enable_cache_maint_trap,
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_832075
	{
	/* Cortex-A57 r0p0 - r1p2 */
		.desc = "ARM erratum 832075",
		.capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
		ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
				  0, 0,
				  1, 2),
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_834220
	{
	/* Cortex-A57 r0p0 - r1p2 */
		.desc = "ARM erratum 834220",
		.capability = ARM64_WORKAROUND_834220,
		ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
				  0, 0,
				  1, 2),
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_843419
	{
		.desc = "ARM erratum 843419",
		.capability = ARM64_WORKAROUND_843419,
		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
		.matches = cpucap_multi_entry_cap_matches,
		.match_list = erratum_843419_list,
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_845719
	{
		.desc = "ARM erratum 845719",
		.capability = ARM64_WORKAROUND_845719,
		ERRATA_MIDR_RANGE_LIST(erratum_845719_list),
	},
#endif
#ifdef CONFIG_CAVIUM_ERRATUM_23154
	{
	/* Cavium ThunderX, pass 1.x */
		.desc = "Cavium erratum 23154",
		.capability = ARM64_WORKAROUND_CAVIUM_23154,
		ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX, 0, 0, 1),
	},
#endif
#ifdef CONFIG_CAVIUM_ERRATUM_27456
	{
		.desc = "Cavium erratum 27456",
		.capability = ARM64_WORKAROUND_CAVIUM_27456,
		ERRATA_MIDR_RANGE_LIST(cavium_erratum_27456_cpus),
	},
#endif
#ifdef CONFIG_CAVIUM_ERRATUM_30115
	{
		.desc = "Cavium erratum 30115",
		.capability = ARM64_WORKAROUND_CAVIUM_30115,
		ERRATA_MIDR_RANGE_LIST(cavium_erratum_30115_cpus),
	},
#endif
	{
		.desc = "Mismatched cache type (CTR_EL0)",
		.capability = ARM64_MISMATCHED_CACHE_TYPE,
		.matches = has_mismatched_cache_type,
		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
		.cpu_enable = cpu_enable_trap_ctr_access,
	},
#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
	{
		.desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",
		.capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
		.matches = cpucap_multi_entry_cap_matches,
		.match_list = qcom_erratum_1003_list,
	},
#endif
#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
	{
		.desc = "Qualcomm erratum 1009, or ARM erratum 1286807",
		.capability = ARM64_WORKAROUND_REPEAT_TLBI,
		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
		.matches = cpucap_multi_entry_cap_matches,
		.match_list = arm64_repeat_tlbi_list,
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_858921
	{
	/* Cortex-A73 all versions */
		.desc = "ARM erratum 858921",
		.capability = ARM64_WORKAROUND_858921,
		ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
	},
#endif
	{
		.desc = "Spectre-v2",
		.capability = ARM64_SPECTRE_V2,
		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
		.matches = has_spectre_v2,
		.cpu_enable = spectre_v2_enable_mitigation,
	},
#ifdef CONFIG_RANDOMIZE_BASE
	{
		.desc = "EL2 vector hardening",
		.capability = ARM64_HARDEN_EL2_VECTORS,
		ERRATA_MIDR_RANGE_LIST(ca57_a72),
	},
#endif
	{
		.desc = "Spectre-v4",
		.capability = ARM64_SPECTRE_V4,
		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
		.matches = has_spectre_v4,
		.cpu_enable = spectre_v4_enable_mitigation,
	},
#ifdef CONFIG_ARM64_ERRATUM_1418040
	{
		.desc = "ARM erratum 1418040",
		.capability = ARM64_WORKAROUND_1418040,
		ERRATA_MIDR_RANGE_LIST(erratum_1418040_list),
		.type = (ARM64_CPUCAP_SCOPE_LOCAL_CPU |
			 ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU),
	},
#endif
#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
	{
		.desc = "ARM errata 1165522, 1319367, or 1530923",
		.capability = ARM64_WORKAROUND_SPECULATIVE_AT,
		ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list),
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_1463225
	{
		.desc = "ARM erratum 1463225",
		.capability = ARM64_WORKAROUND_1463225,
		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
		.matches = has_cortex_a76_erratum_1463225,
		.midr_range_list = erratum_1463225,
	},
#endif
#ifdef CONFIG_CAVIUM_TX2_ERRATUM_219
	{
		.desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)",
		.capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM,
		ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
		.matches = needs_tx2_tvm_workaround,
	},
	{
		.desc = "Cavium ThunderX2 erratum 219 (PRFM removal)",
		.capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM,
		ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_1542419
	{
		/* we depend on the firmware portion for correctness */
		.desc = "ARM erratum 1542419 (kernel portion)",
		.capability = ARM64_WORKAROUND_1542419,
		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
		.matches = has_neoverse_n1_erratum_1542419,
		.cpu_enable = cpu_enable_trap_ctr_access,
	},
#endif
	{
	}
};
Commit	Line	Data
caab277b	1	// SPDX-License-Identifier: GPL-2.0-only
e116a375 AP	2	/*
	3	* Contains CPU specific errata definitions
	4	*
	5	* Copyright (C) 2014 ARM Ltd.
e116a375 AP	6	*/
e116a375 AP	7
94a5d879	8	#include <linux/arm-smccc.h>
e116a375	9	#include <linux/types.h>
a111b7c0	10	#include <linux/cpu.h>
e116a375 AP	11	#include <asm/cpu.h>
	12	#include <asm/cputype.h>
	13	#include <asm/cpufeature.h>
4db61fef	14	#include <asm/kvm_asm.h>
93916beb	15	#include <asm/smp_plat.h>
e116a375	16
301bcfac	17	static bool __maybe_unused
92406f0c	18	is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
301bcfac	19	{
e8002e02 AB	20	const struct arm64_midr_revidr *fix;
	21	u32 midr = read_cpuid_id(), revidr;
	22
92406f0c	23	WARN_ON(scope != SCOPE_LOCAL_CPU \|\| preemptible());
1df31050	24	if (!is_midr_in_range(midr, &entry->midr_range))
e8002e02 AB	25	return false;
	26
	27	midr &= MIDR_REVISION_MASK \| MIDR_VARIANT_MASK;
	28	revidr = read_cpuid(REVIDR_EL1);
	29	for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
	30	if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
	31	return false;
	32
	33	return true;
301bcfac AP	34	}
301bcfac AP	35
be5b2998 SP	36	static bool __maybe_unused
	37	is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,
	38	int scope)
301bcfac	39	{
92406f0c	40	WARN_ON(scope != SCOPE_LOCAL_CPU \|\| preemptible());
be5b2998	41	return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);
301bcfac AP	42	}
301bcfac AP	43
bb487118 SB	44	static bool __maybe_unused
	45	is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
	46	{
	47	u32 model;
	48
	49	WARN_ON(scope != SCOPE_LOCAL_CPU \|\| preemptible());
	50
	51	model = read_cpuid_id();
	52	model &= MIDR_IMPLEMENTOR_MASK \| (0xf00 << MIDR_PARTNUM_SHIFT) \|
	53	MIDR_ARCHITECTURE_MASK;
	54
1df31050	55	return model == entry->midr_range.model;
bb487118 SB	56	}
bb487118 SB	57
116c81f4	58	static bool
314d53d2 SP	59	has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry,
314d53d2 SP	60	int scope)
116c81f4	61	{
1602df02 SP	62	u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
	63	u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask;
	64	u64 ctr_raw, ctr_real;
314d53d2	65
116c81f4	66	WARN_ON(scope != SCOPE_LOCAL_CPU \|\| preemptible());
1602df02 SP	67
	68	/*
	69	* We want to make sure that all the CPUs in the system expose
	70	* a consistent CTR_EL0 to make sure that applications behaves
	71	* correctly with migration.
	72	*
	73	* If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 :
	74	*
	75	* 1) It is safe if the system doesn't support IDC, as CPU anyway
	76	* reports IDC = 0, consistent with the rest.
	77	*
	78	* 2) If the system has IDC, it is still safe as we trap CTR_EL0
	79	* access on this CPU via the ARM64_HAS_CACHE_IDC capability.
	80	*
	81	* So, we need to make sure either the raw CTR_EL0 or the effective
	82	* CTR_EL0 matches the system's copy to allow a secondary CPU to boot.
	83	*/
	84	ctr_raw = read_cpuid_cachetype() & mask;
	85	ctr_real = read_cpuid_effective_cachetype() & mask;
	86
	87	return (ctr_real != sys) && (ctr_raw != sys);
116c81f4 SP	88	}
116c81f4 SP	89
c0cda3b8	90	static void
05460849	91	cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap)
116c81f4	92	{
4afe8e79	93	u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
05460849	94	bool enable_uct_trap = false;
4afe8e79 SP	95
	96	/* Trap CTR_EL0 access on this CPU, only if it has a mismatch */
	97	if ((read_cpuid_cachetype() & mask) !=
	98	(arm64_ftr_reg_ctrel0.sys_val & mask))
05460849 JM	99	enable_uct_trap = true;
	100
	101	/* ... or if the system is affected by an erratum */
	102	if (cap->capability == ARM64_WORKAROUND_1542419)
	103	enable_uct_trap = true;
	104
	105	if (enable_uct_trap)
4afe8e79	106	sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
116c81f4 SP	107	}
116c81f4 SP	108
c2876207	109	int ssbd_state __read_mostly = ARM64_SSBD_UNKNOWN;
a725e3dd	110
986372c4 MZ	111	void __init arm64_enable_wa2_handling(struct alt_instr *alt,
	112	__le32 origptr, __le32 updptr,
	113	int nr_inst)
	114	{
	115	BUG_ON(nr_inst != 1);
	116	/*
	117	* Only allow mitigation on EL1 entry/exit and guest
	118	* ARCH_WORKAROUND_2 handling if the SSBD state allows it to
	119	* be flipped.
	120	*/
	121	if (arm64_get_ssbd_state() == ARM64_SSBD_KERNEL)
	122	*updptr = cpu_to_le32(aarch64_insn_gen_nop());
	123	}
	124
969f5ea6 WD	125	#ifdef CONFIG_ARM64_ERRATUM_1463225
	126	DEFINE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa);
	127
	128	static bool
	129	has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry,
	130	int scope)
	131	{
a9e821b8	132	return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode();
969f5ea6 WD	133	}
	134	#endif
	135
b8925ee2 WD	136	static void __maybe_unused
	137	cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)
	138	{
	139	sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0);
	140	}
	141
5e7951ce SP	142	#define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
5e7951ce SP	143	.matches = is_affected_midr_range, \
1df31050	144	.midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)
5e7951ce SP	145
	146	#define CAP_MIDR_ALL_VERSIONS(model) \
	147	.matches = is_affected_midr_range, \
1df31050	148	.midr_range = MIDR_ALL_VERSIONS(model)
06f1494f	149
e8002e02 AB	150	#define MIDR_FIXED(rev, revidr_mask) \
	151	.fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}
	152
5e7951ce SP	153	#define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
	154	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
	155	CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)
	156
be5b2998 SP	157	#define CAP_MIDR_RANGE_LIST(list) \
	158	.matches = is_affected_midr_range_list, \
	159	.midr_range_list = list
	160
5e7951ce SP	161	/* Errata affecting a range of revisions of given model variant */
	162	#define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \
	163	ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)
	164
	165	/* Errata affecting a single variant/revision of a model */
	166	#define ERRATA_MIDR_REV(model, var, rev) \
	167	ERRATA_MIDR_RANGE(model, var, rev, var, rev)
	168
	169	/* Errata affecting all variants/revisions of a given a model */
	170	#define ERRATA_MIDR_ALL_VERSIONS(model) \
	171	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
	172	CAP_MIDR_ALL_VERSIONS(model)
	173
be5b2998 SP	174	/* Errata affecting a list of midr ranges, with same work around */
	175	#define ERRATA_MIDR_RANGE_LIST(midr_list) \
	176	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
	177	CAP_MIDR_RANGE_LIST(midr_list)
	178
93916beb MZ	179	static const __maybe_unused struct midr_range tx2_family_cpus[] = {
	180	MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
	181	MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
	182	{},
	183	};
	184
	185	static bool __maybe_unused
	186	needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry,
	187	int scope)
	188	{
	189	int i;
	190
	191	if (!is_affected_midr_range_list(entry, scope) \|\|
	192	!is_hyp_mode_available())
	193	return false;
	194
	195	for_each_possible_cpu(i) {
	196	if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0)
	197	return true;
	198	}
	199
	200	return false;
	201	}
	202
05460849 JM	203	static bool __maybe_unused
	204	has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry,
	205	int scope)
	206	{
	207	u32 midr = read_cpuid_id();
	208	bool has_dic = read_cpuid_cachetype() & BIT(CTR_DIC_SHIFT);
	209	const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1);
	210
	211	WARN_ON(scope != SCOPE_LOCAL_CPU \|\| preemptible());
	212	return is_midr_in_range(midr, &range) && has_dic;
	213	}
8892b718	214
a59a2edb	215	#ifdef CONFIG_RANDOMIZE_BASE
8892b718	216
f75e2294	217	static const struct midr_range ca57_a72[] = {
8892b718 MZ	218	MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
	219	MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
	220	{},
	221	};
	222
dc6ed61d MZ	223	#endif
dc6ed61d MZ	224
ce8c80c5	225	#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
36c602dc	226	static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
ce8c80c5	227	#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
36c602dc BA	228	{
	229	ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0)
	230	},
	231	{
	232	.midr_range.model = MIDR_QCOM_KRYO,
	233	.matches = is_kryo_midr,
	234	},
ce8c80c5 CM	235	#endif
ce8c80c5 CM	236	#ifdef CONFIG_ARM64_ERRATUM_1286807
36c602dc BA	237	{
	238	ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
	239	},
ce8c80c5 CM	240	#endif
	241	{},
	242	};
ce8c80c5 CM	243	#endif
ce8c80c5 CM	244
f58cdf7e	245	#ifdef CONFIG_CAVIUM_ERRATUM_27456
b89d82ef	246	const struct midr_range cavium_erratum_27456_cpus[] = {
f58cdf7e SP	247	/* Cavium ThunderX, T88 pass 1.x - 2.1 */
	248	MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1),
	249	/* Cavium ThunderX, T81 pass 1.0 */
	250	MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),
	251	{},
	252	};
	253	#endif
	254
	255	#ifdef CONFIG_CAVIUM_ERRATUM_30115
	256	static const struct midr_range cavium_erratum_30115_cpus[] = {
	257	/* Cavium ThunderX, T88 pass 1.x - 2.2 */
	258	MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2),
	259	/* Cavium ThunderX, T81 pass 1.0 - 1.2 */
	260	MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),
	261	/* Cavium ThunderX, T83 pass 1.0 */
	262	MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),
	263	{},
	264	};
	265	#endif
	266
a3dcea2c SP	267	#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
	268	static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = {
	269	{
	270	ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
	271	},
	272	{
	273	.midr_range.model = MIDR_QCOM_KRYO,
	274	.matches = is_kryo_midr,
	275	},
	276	{},
	277	};
	278	#endif
	279
c9460dcb SP	280	#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
c9460dcb SP	281	static const struct midr_range workaround_clean_cache[] = {
c0a01b84 AP	282	#if defined(CONFIG_ARM64_ERRATUM_826319) \|\| \
	283	defined(CONFIG_ARM64_ERRATUM_827319) \|\| \
	284	defined(CONFIG_ARM64_ERRATUM_824069)
c9460dcb SP	285	/* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */
	286	MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
	287	#endif
	288	#ifdef CONFIG_ARM64_ERRATUM_819472
	289	/* Cortex-A53 r0p[01] : ARM errata 819472 */
	290	MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
c0a01b84	291	#endif
c9460dcb SP	292	{},
	293	};
	294	#endif
	295
a5325089 MZ	296	#ifdef CONFIG_ARM64_ERRATUM_1418040
	297	/*
	298	* - 1188873 affects r0p0 to r2p0
	299	* - 1418040 affects r0p0 to r3p1
	300	*/
	301	static const struct midr_range erratum_1418040_list[] = {
	302	/* Cortex-A76 r0p0 to r3p1 */
	303	MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
	304	/* Neoverse-N1 r0p0 to r3p1 */
	305	MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1),
a9e821b8 SPR	306	/* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
a9e821b8 SPR	307	MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
6989303a MZ	308	{},
	309	};
	310	#endif
	311
bfc97f9f DB	312	#ifdef CONFIG_ARM64_ERRATUM_845719
	313	static const struct midr_range erratum_845719_list[] = {
	314	/* Cortex-A53 r0p[01234] */
	315	MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
	316	/* Brahma-B53 r0p[0] */
	317	MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
	318	{},
	319	};
	320	#endif
	321
1cf45b8f FF	322	#ifdef CONFIG_ARM64_ERRATUM_843419
	323	static const struct arm64_cpu_capabilities erratum_843419_list[] = {
	324	{
	325	/* Cortex-A53 r0p[01234] */
	326	.matches = is_affected_midr_range,
	327	ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
	328	MIDR_FIXED(0x4, BIT(8)),
	329	},
	330	{
	331	/* Brahma-B53 r0p[0] */
	332	.matches = is_affected_midr_range,
	333	ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
	334	},
	335	{},
	336	};
	337	#endif
	338
02ab1f50 AS	339	#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
02ab1f50 AS	340	static const struct midr_range erratum_speculative_at_list[] = {
e85d68fa SP	341	#ifdef CONFIG_ARM64_ERRATUM_1165522
	342	/* Cortex A76 r0p0 to r2p0 */
	343	MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
275fa0ea	344	#endif
02ab1f50 AS	345	#ifdef CONFIG_ARM64_ERRATUM_1319367
	346	MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
	347	MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
	348	#endif
275fa0ea SP	349	#ifdef CONFIG_ARM64_ERRATUM_1530923
	350	/* Cortex A55 r0p0 to r2p0 */
	351	MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0),
9b23d95c SPR	352	/* Kryo4xx Silver (rdpe => r1p0) */
9b23d95c SPR	353	MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
e85d68fa SP	354	#endif
	355	{},
	356	};
	357	#endif
	358
a9e821b8 SPR	359	#ifdef CONFIG_ARM64_ERRATUM_1463225
	360	static const struct midr_range erratum_1463225[] = {
	361	/* Cortex-A76 r0p0 - r3p1 */
	362	MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
	363	/* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
	364	MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
09c717c9	365	{},
a9e821b8 SPR	366	};
	367	#endif
	368
c9460dcb SP	369	const struct arm64_cpu_capabilities arm64_errata[] = {
c9460dcb SP	370	#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
c0a01b84	371	{
357dd8a2	372	.desc = "ARM errata 826319, 827319, 824069, or 819472",
c0a01b84	373	.capability = ARM64_WORKAROUND_CLEAN_CACHE,
c9460dcb	374	ERRATA_MIDR_RANGE_LIST(workaround_clean_cache),
c0cda3b8	375	.cpu_enable = cpu_enable_cache_maint_trap,
c0a01b84 AP	376	},
	377	#endif
	378	#ifdef CONFIG_ARM64_ERRATUM_832075
301bcfac	379	{
5afaa1fc AP	380	/* Cortex-A57 r0p0 - r1p2 */
	381	.desc = "ARM erratum 832075",
	382	.capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
5e7951ce SP	383	ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
	384	0, 0,
	385	1, 2),
5afaa1fc	386	},
905e8c5d	387	#endif
498cd5c3 MZ	388	#ifdef CONFIG_ARM64_ERRATUM_834220
	389	{
	390	/* Cortex-A57 r0p0 - r1p2 */
	391	.desc = "ARM erratum 834220",
	392	.capability = ARM64_WORKAROUND_834220,
5e7951ce SP	393	ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
	394	0, 0,
	395	1, 2),
498cd5c3 MZ	396	},
498cd5c3 MZ	397	#endif
ca79acca AB	398	#ifdef CONFIG_ARM64_ERRATUM_843419
ca79acca AB	399	{
ca79acca AB	400	.desc = "ARM erratum 843419",
ca79acca AB	401	.capability = ARM64_WORKAROUND_843419,
1cf45b8f FF	402	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
	403	.matches = cpucap_multi_entry_cap_matches,
	404	.match_list = erratum_843419_list,
498cd5c3 MZ	405	},
498cd5c3 MZ	406	#endif
905e8c5d WD	407	#ifdef CONFIG_ARM64_ERRATUM_845719
905e8c5d WD	408	{
905e8c5d WD	409	.desc = "ARM erratum 845719",
905e8c5d WD	410	.capability = ARM64_WORKAROUND_845719,
bfc97f9f	411	ERRATA_MIDR_RANGE_LIST(erratum_845719_list),
905e8c5d	412	},
6d4e11c5 RR	413	#endif
	414	#ifdef CONFIG_CAVIUM_ERRATUM_23154
	415	{
	416	/* Cavium ThunderX, pass 1.x */
	417	.desc = "Cavium erratum 23154",
	418	.capability = ARM64_WORKAROUND_CAVIUM_23154,
5e7951ce	419	ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX, 0, 0, 1),
6d4e11c5	420	},
104a0c02 AP	421	#endif
	422	#ifdef CONFIG_CAVIUM_ERRATUM_27456
	423	{
47c459be GK	424	.desc = "Cavium erratum 27456",
47c459be GK	425	.capability = ARM64_WORKAROUND_CAVIUM_27456,
f58cdf7e	426	ERRATA_MIDR_RANGE_LIST(cavium_erratum_27456_cpus),
47c459be	427	},
690a3415 DD	428	#endif
	429	#ifdef CONFIG_CAVIUM_ERRATUM_30115
	430	{
690a3415 DD	431	.desc = "Cavium erratum 30115",
690a3415 DD	432	.capability = ARM64_WORKAROUND_CAVIUM_30115,
f58cdf7e	433	ERRATA_MIDR_RANGE_LIST(cavium_erratum_30115_cpus),
690a3415	434	},
c0a01b84	435	#endif
116c81f4	436	{
880f7cc4	437	.desc = "Mismatched cache type (CTR_EL0)",
314d53d2 SP	438	.capability = ARM64_MISMATCHED_CACHE_TYPE,
314d53d2 SP	439	.matches = has_mismatched_cache_type,
5b4747c5	440	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
c0cda3b8	441	.cpu_enable = cpu_enable_trap_ctr_access,
116c81f4	442	},
38fd94b0 CC	443	#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
38fd94b0 CC	444	{
a3dcea2c	445	.desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",
bb487118	446	.capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
d4af3c4b	447	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
1e013d06	448	.matches = cpucap_multi_entry_cap_matches,
a3dcea2c	449	.match_list = qcom_erratum_1003_list,
bb487118	450	},
38fd94b0	451	#endif
ce8c80c5	452	#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
d9ff80f8	453	{
357dd8a2	454	.desc = "Qualcomm erratum 1009, or ARM erratum 1286807",
d9ff80f8	455	.capability = ARM64_WORKAROUND_REPEAT_TLBI,
36c602dc BA	456	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
	457	.matches = cpucap_multi_entry_cap_matches,
	458	.match_list = arm64_repeat_tlbi_list,
d9ff80f8	459	},
eeb1efbc MZ	460	#endif
	461	#ifdef CONFIG_ARM64_ERRATUM_858921
	462	{
	463	/* Cortex-A73 all versions */
	464	.desc = "ARM erratum 858921",
	465	.capability = ARM64_WORKAROUND_858921,
5e7951ce	466	ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
eeb1efbc	467	},
aa6acde6	468	#endif
aa6acde6	469	{
d4647f0a	470	.desc = "Spectre-v2",
688f1e4b	471	.capability = ARM64_SPECTRE_V2,
73f38166	472	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
d4647f0a WD	473	.matches = has_spectre_v2,
d4647f0a WD	474	.cpu_enable = spectre_v2_enable_mitigation,
f3d795d9	475	},
a59a2edb	476	#ifdef CONFIG_RANDOMIZE_BASE
4b472ffd	477	{
8892b718	478	.desc = "EL2 vector hardening",
4b472ffd	479	.capability = ARM64_HARDEN_EL2_VECTORS,
f75e2294	480	ERRATA_MIDR_RANGE_LIST(ca57_a72),
4b472ffd	481	},
a725e3dd	482	#endif
a725e3dd	483	{
c2876207	484	.desc = "Spectre-v4",
9b0955ba	485	.capability = ARM64_SPECTRE_V4,
a725e3dd	486	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
c2876207 WD	487	.matches = has_spectre_v4,
c2876207 WD	488	.cpu_enable = spectre_v4_enable_mitigation,
a725e3dd	489	},
a5325089	490	#ifdef CONFIG_ARM64_ERRATUM_1418040
95b861a4	491	{
a5325089 MZ	492	.desc = "ARM erratum 1418040",
	493	.capability = ARM64_WORKAROUND_1418040,
	494	ERRATA_MIDR_RANGE_LIST(erratum_1418040_list),
bf87bb08 MZ	495	.type = (ARM64_CPUCAP_SCOPE_LOCAL_CPU \|
bf87bb08 MZ	496	ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU),
95b861a4	497	},
8b2cca9a	498	#endif
02ab1f50	499	#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
8b2cca9a	500	{
c350717e	501	.desc = "ARM errata 1165522, 1319367, or 1530923",
02ab1f50 AS	502	.capability = ARM64_WORKAROUND_SPECULATIVE_AT,
02ab1f50 AS	503	ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list),
8b2cca9a	504	},
969f5ea6 WD	505	#endif
	506	#ifdef CONFIG_ARM64_ERRATUM_1463225
	507	{
	508	.desc = "ARM erratum 1463225",
	509	.capability = ARM64_WORKAROUND_1463225,
	510	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
	511	.matches = has_cortex_a76_erratum_1463225,
a9e821b8	512	.midr_range_list = erratum_1463225,
969f5ea6	513	},
93916beb MZ	514	#endif
	515	#ifdef CONFIG_CAVIUM_TX2_ERRATUM_219
	516	{
	517	.desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)",
	518	.capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM,
	519	ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
	520	.matches = needs_tx2_tvm_workaround,
	521	},
9405447e MZ	522	{
	523	.desc = "Cavium ThunderX2 erratum 219 (PRFM removal)",
	524	.capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM,
	525	ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
	526	},
6a036afb	527	#endif
05460849 JM	528	#ifdef CONFIG_ARM64_ERRATUM_1542419
	529	{
	530	/* we depend on the firmware portion for correctness */
	531	.desc = "ARM erratum 1542419 (kernel portion)",
	532	.capability = ARM64_WORKAROUND_1542419,
	533	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
	534	.matches = has_neoverse_n1_erratum_1542419,
	535	.cpu_enable = cpu_enable_trap_ctr_access,
	536	},
d9ff80f8	537	#endif
5afaa1fc	538	{
301bcfac	539	}
e116a375	540	};