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359b7064 MZ |
1 | /* |
2 | * Contains CPU feature definitions | |
3 | * | |
4 | * Copyright (C) 2015 ARM Ltd. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
9cdf8ec4 | 19 | #define pr_fmt(fmt) "CPU features: " fmt |
359b7064 | 20 | |
3c739b57 | 21 | #include <linux/bsearch.h> |
2a6dcb2b | 22 | #include <linux/cpumask.h> |
3c739b57 | 23 | #include <linux/sort.h> |
2a6dcb2b | 24 | #include <linux/stop_machine.h> |
359b7064 | 25 | #include <linux/types.h> |
2077be67 | 26 | #include <linux/mm.h> |
359b7064 MZ |
27 | #include <asm/cpu.h> |
28 | #include <asm/cpufeature.h> | |
dbb4e152 | 29 | #include <asm/cpu_ops.h> |
13f417f3 | 30 | #include <asm/mmu_context.h> |
338d4f49 | 31 | #include <asm/processor.h> |
cdcf817b | 32 | #include <asm/sysreg.h> |
77c97b4e | 33 | #include <asm/traps.h> |
d88701be | 34 | #include <asm/virt.h> |
359b7064 | 35 | |
9cdf8ec4 SP |
36 | unsigned long elf_hwcap __read_mostly; |
37 | EXPORT_SYMBOL_GPL(elf_hwcap); | |
38 | ||
39 | #ifdef CONFIG_COMPAT | |
40 | #define COMPAT_ELF_HWCAP_DEFAULT \ | |
41 | (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ | |
42 | COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ | |
43 | COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\ | |
44 | COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\ | |
45 | COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\ | |
46 | COMPAT_HWCAP_LPAE) | |
47 | unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; | |
48 | unsigned int compat_elf_hwcap2 __read_mostly; | |
49 | #endif | |
50 | ||
51 | DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); | |
4b65a5db | 52 | EXPORT_SYMBOL(cpu_hwcaps); |
9cdf8ec4 | 53 | |
efd9e03f CM |
54 | DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS); |
55 | EXPORT_SYMBOL(cpu_hwcap_keys); | |
56 | ||
fe4fbdbc | 57 | #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ |
3c739b57 | 58 | { \ |
4f0a606b | 59 | .sign = SIGNED, \ |
fe4fbdbc | 60 | .visible = VISIBLE, \ |
3c739b57 SP |
61 | .strict = STRICT, \ |
62 | .type = TYPE, \ | |
63 | .shift = SHIFT, \ | |
64 | .width = WIDTH, \ | |
65 | .safe_val = SAFE_VAL, \ | |
66 | } | |
67 | ||
0710cfdb | 68 | /* Define a feature with unsigned values */ |
fe4fbdbc SP |
69 | #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ |
70 | __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) | |
4f0a606b | 71 | |
0710cfdb | 72 | /* Define a feature with a signed value */ |
fe4fbdbc SP |
73 | #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ |
74 | __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) | |
0710cfdb | 75 | |
3c739b57 SP |
76 | #define ARM64_FTR_END \ |
77 | { \ | |
78 | .width = 0, \ | |
79 | } | |
80 | ||
70544196 JM |
81 | /* meta feature for alternatives */ |
82 | static bool __maybe_unused | |
92406f0c SP |
83 | cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused); |
84 | ||
70544196 | 85 | |
4aa8a472 SP |
86 | /* |
87 | * NOTE: Any changes to the visibility of features should be kept in | |
88 | * sync with the documentation of the CPU feature register ABI. | |
89 | */ | |
5e49d73c | 90 | static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { |
fe4fbdbc SP |
91 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0), |
92 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), | |
93 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0), | |
94 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0), | |
95 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0), | |
96 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0), | |
3c739b57 SP |
97 | ARM64_FTR_END, |
98 | }; | |
99 | ||
c8c3798d | 100 | static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { |
c651aae5 | 101 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0), |
cb567e79 | 102 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), |
c8c3798d SP |
103 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), |
104 | ARM64_FTR_END, | |
105 | }; | |
106 | ||
5e49d73c | 107 | static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { |
fe4fbdbc SP |
108 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0), |
109 | S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), | |
110 | S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), | |
3c739b57 | 111 | /* Linux doesn't care about the EL3 */ |
fe4fbdbc SP |
112 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0), |
113 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0), | |
114 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY), | |
115 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY), | |
3c739b57 SP |
116 | ARM64_FTR_END, |
117 | }; | |
118 | ||
5e49d73c | 119 | static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { |
fe4fbdbc SP |
120 | S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), |
121 | S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), | |
122 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI), | |
123 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0), | |
3c739b57 | 124 | /* Linux shouldn't care about secure memory */ |
fe4fbdbc SP |
125 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0), |
126 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0), | |
127 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0), | |
3c739b57 SP |
128 | /* |
129 | * Differing PARange is fine as long as all peripherals and memory are mapped | |
130 | * within the minimum PARange of all CPUs | |
131 | */ | |
fe4fbdbc | 132 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0), |
3c739b57 SP |
133 | ARM64_FTR_END, |
134 | }; | |
135 | ||
5e49d73c | 136 | static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { |
fe4fbdbc SP |
137 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0), |
138 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0), | |
139 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0), | |
140 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0), | |
141 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0), | |
142 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0), | |
3c739b57 SP |
143 | ARM64_FTR_END, |
144 | }; | |
145 | ||
5e49d73c | 146 | static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { |
fe4fbdbc SP |
147 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LVA_SHIFT, 4, 0), |
148 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_IESB_SHIFT, 4, 0), | |
149 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LSM_SHIFT, 4, 0), | |
150 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_UAO_SHIFT, 4, 0), | |
151 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_CNP_SHIFT, 4, 0), | |
406e3087 JM |
152 | ARM64_FTR_END, |
153 | }; | |
154 | ||
5e49d73c | 155 | static const struct arm64_ftr_bits ftr_ctr[] = { |
fe4fbdbc SP |
156 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */ |
157 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */ | |
158 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */ | |
159 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */ | |
3c739b57 SP |
160 | /* |
161 | * Linux can handle differing I-cache policies. Userspace JITs will | |
ee7bc638 | 162 | * make use of *minLine. |
155433cb | 163 | * If we have differing I-cache policies, report it as the weakest - VIPT. |
3c739b57 | 164 | */ |
155433cb | 165 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */ |
fe4fbdbc | 166 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */ |
3c739b57 SP |
167 | ARM64_FTR_END, |
168 | }; | |
169 | ||
675b0563 AB |
170 | struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { |
171 | .name = "SYS_CTR_EL0", | |
172 | .ftr_bits = ftr_ctr | |
173 | }; | |
174 | ||
5e49d73c | 175 | static const struct arm64_ftr_bits ftr_id_mmfr0[] = { |
fe4fbdbc SP |
176 | S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 28, 4, 0xf), /* InnerShr */ |
177 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 24, 4, 0), /* FCSE */ | |
178 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */ | |
179 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 16, 4, 0), /* TCM */ | |
180 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 12, 4, 0), /* ShareLvl */ | |
181 | S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 8, 4, 0xf), /* OuterShr */ | |
182 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */ | |
183 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */ | |
3c739b57 SP |
184 | ARM64_FTR_END, |
185 | }; | |
186 | ||
5e49d73c | 187 | static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { |
fe4fbdbc SP |
188 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0), |
189 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0), | |
190 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0), | |
191 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0), | |
192 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0), | |
b20d1ba3 WD |
193 | /* |
194 | * We can instantiate multiple PMU instances with different levels | |
195 | * of support. | |
fe4fbdbc SP |
196 | */ |
197 | S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0), | |
198 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0), | |
199 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6), | |
3c739b57 SP |
200 | ARM64_FTR_END, |
201 | }; | |
202 | ||
5e49d73c | 203 | static const struct arm64_ftr_bits ftr_mvfr2[] = { |
fe4fbdbc SP |
204 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0), /* FPMisc */ |
205 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 4, 0), /* SIMDMisc */ | |
3c739b57 SP |
206 | ARM64_FTR_END, |
207 | }; | |
208 | ||
5e49d73c | 209 | static const struct arm64_ftr_bits ftr_dczid[] = { |
fe4fbdbc SP |
210 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */ |
211 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */ | |
3c739b57 SP |
212 | ARM64_FTR_END, |
213 | }; | |
214 | ||
215 | ||
5e49d73c | 216 | static const struct arm64_ftr_bits ftr_id_isar5[] = { |
fe4fbdbc SP |
217 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0), |
218 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0), | |
219 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0), | |
220 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0), | |
221 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0), | |
222 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0), | |
3c739b57 SP |
223 | ARM64_FTR_END, |
224 | }; | |
225 | ||
5e49d73c | 226 | static const struct arm64_ftr_bits ftr_id_mmfr4[] = { |
fe4fbdbc | 227 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0), /* ac2 */ |
3c739b57 SP |
228 | ARM64_FTR_END, |
229 | }; | |
230 | ||
5e49d73c | 231 | static const struct arm64_ftr_bits ftr_id_pfr0[] = { |
fe4fbdbc SP |
232 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 12, 4, 0), /* State3 */ |
233 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 8, 4, 0), /* State2 */ | |
234 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0), /* State1 */ | |
235 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 4, 0), /* State0 */ | |
3c739b57 SP |
236 | ARM64_FTR_END, |
237 | }; | |
238 | ||
5e49d73c | 239 | static const struct arm64_ftr_bits ftr_id_dfr0[] = { |
fe4fbdbc SP |
240 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), |
241 | S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */ | |
242 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), | |
243 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), | |
244 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), | |
245 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), | |
246 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), | |
247 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), | |
e5343503 SP |
248 | ARM64_FTR_END, |
249 | }; | |
250 | ||
3c739b57 SP |
251 | /* |
252 | * Common ftr bits for a 32bit register with all hidden, strict | |
253 | * attributes, with 4bit feature fields and a default safe value of | |
254 | * 0. Covers the following 32bit registers: | |
255 | * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1] | |
256 | */ | |
5e49d73c | 257 | static const struct arm64_ftr_bits ftr_generic_32bits[] = { |
fe4fbdbc SP |
258 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), |
259 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), | |
260 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), | |
261 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), | |
262 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), | |
263 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), | |
264 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), | |
265 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), | |
3c739b57 SP |
266 | ARM64_FTR_END, |
267 | }; | |
268 | ||
eab43e88 SP |
269 | /* Table for a single 32bit feature value */ |
270 | static const struct arm64_ftr_bits ftr_single32[] = { | |
fe4fbdbc | 271 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), |
3c739b57 SP |
272 | ARM64_FTR_END, |
273 | }; | |
274 | ||
eab43e88 | 275 | static const struct arm64_ftr_bits ftr_raz[] = { |
3c739b57 SP |
276 | ARM64_FTR_END, |
277 | }; | |
278 | ||
6f2b7eef AB |
279 | #define ARM64_FTR_REG(id, table) { \ |
280 | .sys_id = id, \ | |
281 | .reg = &(struct arm64_ftr_reg){ \ | |
3c739b57 SP |
282 | .name = #id, \ |
283 | .ftr_bits = &((table)[0]), \ | |
6f2b7eef | 284 | }} |
3c739b57 | 285 | |
6f2b7eef AB |
286 | static const struct __ftr_reg_entry { |
287 | u32 sys_id; | |
288 | struct arm64_ftr_reg *reg; | |
289 | } arm64_ftr_regs[] = { | |
3c739b57 SP |
290 | |
291 | /* Op1 = 0, CRn = 0, CRm = 1 */ | |
292 | ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), | |
293 | ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits), | |
e5343503 | 294 | ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), |
3c739b57 SP |
295 | ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), |
296 | ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), | |
297 | ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), | |
298 | ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), | |
299 | ||
300 | /* Op1 = 0, CRn = 0, CRm = 2 */ | |
301 | ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits), | |
302 | ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), | |
303 | ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), | |
304 | ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), | |
305 | ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits), | |
306 | ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), | |
307 | ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), | |
308 | ||
309 | /* Op1 = 0, CRn = 0, CRm = 3 */ | |
310 | ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits), | |
311 | ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits), | |
312 | ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), | |
313 | ||
314 | /* Op1 = 0, CRn = 0, CRm = 4 */ | |
315 | ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), | |
eab43e88 | 316 | ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_raz), |
3c739b57 SP |
317 | |
318 | /* Op1 = 0, CRn = 0, CRm = 5 */ | |
319 | ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), | |
eab43e88 | 320 | ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), |
3c739b57 SP |
321 | |
322 | /* Op1 = 0, CRn = 0, CRm = 6 */ | |
323 | ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), | |
c8c3798d | 324 | ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1), |
3c739b57 SP |
325 | |
326 | /* Op1 = 0, CRn = 0, CRm = 7 */ | |
327 | ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), | |
328 | ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1), | |
406e3087 | 329 | ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), |
3c739b57 SP |
330 | |
331 | /* Op1 = 3, CRn = 0, CRm = 0 */ | |
675b0563 | 332 | { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, |
3c739b57 SP |
333 | ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), |
334 | ||
335 | /* Op1 = 3, CRn = 14, CRm = 0 */ | |
eab43e88 | 336 | ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), |
3c739b57 SP |
337 | }; |
338 | ||
339 | static int search_cmp_ftr_reg(const void *id, const void *regp) | |
340 | { | |
6f2b7eef | 341 | return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; |
3c739b57 SP |
342 | } |
343 | ||
344 | /* | |
345 | * get_arm64_ftr_reg - Lookup a feature register entry using its | |
346 | * sys_reg() encoding. With the array arm64_ftr_regs sorted in the | |
347 | * ascending order of sys_id , we use binary search to find a matching | |
348 | * entry. | |
349 | * | |
350 | * returns - Upon success, matching ftr_reg entry for id. | |
351 | * - NULL on failure. It is upto the caller to decide | |
352 | * the impact of a failure. | |
353 | */ | |
354 | static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) | |
355 | { | |
6f2b7eef AB |
356 | const struct __ftr_reg_entry *ret; |
357 | ||
358 | ret = bsearch((const void *)(unsigned long)sys_id, | |
3c739b57 SP |
359 | arm64_ftr_regs, |
360 | ARRAY_SIZE(arm64_ftr_regs), | |
361 | sizeof(arm64_ftr_regs[0]), | |
362 | search_cmp_ftr_reg); | |
6f2b7eef AB |
363 | if (ret) |
364 | return ret->reg; | |
365 | return NULL; | |
3c739b57 SP |
366 | } |
367 | ||
5e49d73c AB |
368 | static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, |
369 | s64 ftr_val) | |
3c739b57 SP |
370 | { |
371 | u64 mask = arm64_ftr_mask(ftrp); | |
372 | ||
373 | reg &= ~mask; | |
374 | reg |= (ftr_val << ftrp->shift) & mask; | |
375 | return reg; | |
376 | } | |
377 | ||
5e49d73c AB |
378 | static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, |
379 | s64 cur) | |
3c739b57 SP |
380 | { |
381 | s64 ret = 0; | |
382 | ||
383 | switch (ftrp->type) { | |
384 | case FTR_EXACT: | |
385 | ret = ftrp->safe_val; | |
386 | break; | |
387 | case FTR_LOWER_SAFE: | |
388 | ret = new < cur ? new : cur; | |
389 | break; | |
390 | case FTR_HIGHER_SAFE: | |
391 | ret = new > cur ? new : cur; | |
392 | break; | |
393 | default: | |
394 | BUG(); | |
395 | } | |
396 | ||
397 | return ret; | |
398 | } | |
399 | ||
3c739b57 SP |
400 | static void __init sort_ftr_regs(void) |
401 | { | |
6f2b7eef AB |
402 | int i; |
403 | ||
404 | /* Check that the array is sorted so that we can do the binary search */ | |
405 | for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++) | |
406 | BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id); | |
3c739b57 SP |
407 | } |
408 | ||
409 | /* | |
410 | * Initialise the CPU feature register from Boot CPU values. | |
411 | * Also initiliases the strict_mask for the register. | |
b389d799 MR |
412 | * Any bits that are not covered by an arm64_ftr_bits entry are considered |
413 | * RES0 for the system-wide value, and must strictly match. | |
3c739b57 SP |
414 | */ |
415 | static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new) | |
416 | { | |
417 | u64 val = 0; | |
418 | u64 strict_mask = ~0x0ULL; | |
fe4fbdbc | 419 | u64 user_mask = 0; |
b389d799 MR |
420 | u64 valid_mask = 0; |
421 | ||
5e49d73c | 422 | const struct arm64_ftr_bits *ftrp; |
3c739b57 SP |
423 | struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); |
424 | ||
425 | BUG_ON(!reg); | |
426 | ||
427 | for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { | |
b389d799 | 428 | u64 ftr_mask = arm64_ftr_mask(ftrp); |
3c739b57 SP |
429 | s64 ftr_new = arm64_ftr_value(ftrp, new); |
430 | ||
431 | val = arm64_ftr_set_value(ftrp, val, ftr_new); | |
b389d799 MR |
432 | |
433 | valid_mask |= ftr_mask; | |
3c739b57 | 434 | if (!ftrp->strict) |
b389d799 | 435 | strict_mask &= ~ftr_mask; |
fe4fbdbc SP |
436 | if (ftrp->visible) |
437 | user_mask |= ftr_mask; | |
438 | else | |
439 | reg->user_val = arm64_ftr_set_value(ftrp, | |
440 | reg->user_val, | |
441 | ftrp->safe_val); | |
3c739b57 | 442 | } |
b389d799 MR |
443 | |
444 | val &= valid_mask; | |
445 | ||
3c739b57 SP |
446 | reg->sys_val = val; |
447 | reg->strict_mask = strict_mask; | |
fe4fbdbc | 448 | reg->user_mask = user_mask; |
3c739b57 SP |
449 | } |
450 | ||
451 | void __init init_cpu_features(struct cpuinfo_arm64 *info) | |
452 | { | |
453 | /* Before we start using the tables, make sure it is sorted */ | |
454 | sort_ftr_regs(); | |
455 | ||
456 | init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); | |
457 | init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); | |
458 | init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); | |
459 | init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); | |
460 | init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); | |
461 | init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); | |
462 | init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); | |
463 | init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); | |
464 | init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); | |
406e3087 | 465 | init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); |
3c739b57 SP |
466 | init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); |
467 | init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); | |
a6dc3cd7 SP |
468 | |
469 | if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { | |
470 | init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); | |
471 | init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); | |
472 | init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); | |
473 | init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); | |
474 | init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); | |
475 | init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); | |
476 | init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); | |
477 | init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); | |
478 | init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); | |
479 | init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); | |
480 | init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); | |
481 | init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); | |
482 | init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); | |
483 | init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); | |
484 | init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); | |
485 | init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); | |
486 | } | |
487 | ||
3c739b57 SP |
488 | } |
489 | ||
3086d391 | 490 | static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) |
3c739b57 | 491 | { |
5e49d73c | 492 | const struct arm64_ftr_bits *ftrp; |
3c739b57 SP |
493 | |
494 | for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { | |
495 | s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); | |
496 | s64 ftr_new = arm64_ftr_value(ftrp, new); | |
497 | ||
498 | if (ftr_cur == ftr_new) | |
499 | continue; | |
500 | /* Find a safe value */ | |
501 | ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); | |
502 | reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); | |
503 | } | |
504 | ||
505 | } | |
506 | ||
3086d391 | 507 | static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) |
cdcf817b | 508 | { |
3086d391 SP |
509 | struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); |
510 | ||
511 | BUG_ON(!regp); | |
512 | update_cpu_ftr_reg(regp, val); | |
513 | if ((boot & regp->strict_mask) == (val & regp->strict_mask)) | |
514 | return 0; | |
515 | pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", | |
516 | regp->name, boot, cpu, val); | |
517 | return 1; | |
518 | } | |
519 | ||
520 | /* | |
521 | * Update system wide CPU feature registers with the values from a | |
522 | * non-boot CPU. Also performs SANITY checks to make sure that there | |
523 | * aren't any insane variations from that of the boot CPU. | |
524 | */ | |
525 | void update_cpu_features(int cpu, | |
526 | struct cpuinfo_arm64 *info, | |
527 | struct cpuinfo_arm64 *boot) | |
528 | { | |
529 | int taint = 0; | |
530 | ||
531 | /* | |
532 | * The kernel can handle differing I-cache policies, but otherwise | |
533 | * caches should look identical. Userspace JITs will make use of | |
534 | * *minLine. | |
535 | */ | |
536 | taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, | |
537 | info->reg_ctr, boot->reg_ctr); | |
538 | ||
539 | /* | |
540 | * Userspace may perform DC ZVA instructions. Mismatched block sizes | |
541 | * could result in too much or too little memory being zeroed if a | |
542 | * process is preempted and migrated between CPUs. | |
543 | */ | |
544 | taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, | |
545 | info->reg_dczid, boot->reg_dczid); | |
546 | ||
547 | /* If different, timekeeping will be broken (especially with KVM) */ | |
548 | taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, | |
549 | info->reg_cntfrq, boot->reg_cntfrq); | |
550 | ||
551 | /* | |
552 | * The kernel uses self-hosted debug features and expects CPUs to | |
553 | * support identical debug features. We presently need CTX_CMPs, WRPs, | |
554 | * and BRPs to be identical. | |
555 | * ID_AA64DFR1 is currently RES0. | |
556 | */ | |
557 | taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, | |
558 | info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); | |
559 | taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, | |
560 | info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); | |
561 | /* | |
562 | * Even in big.LITTLE, processors should be identical instruction-set | |
563 | * wise. | |
564 | */ | |
565 | taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, | |
566 | info->reg_id_aa64isar0, boot->reg_id_aa64isar0); | |
567 | taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, | |
568 | info->reg_id_aa64isar1, boot->reg_id_aa64isar1); | |
569 | ||
570 | /* | |
571 | * Differing PARange support is fine as long as all peripherals and | |
572 | * memory are mapped within the minimum PARange of all CPUs. | |
573 | * Linux should not care about secure memory. | |
574 | */ | |
575 | taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, | |
576 | info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); | |
577 | taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, | |
578 | info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); | |
406e3087 JM |
579 | taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, |
580 | info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); | |
3086d391 SP |
581 | |
582 | /* | |
583 | * EL3 is not our concern. | |
584 | * ID_AA64PFR1 is currently RES0. | |
585 | */ | |
586 | taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, | |
587 | info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); | |
588 | taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, | |
589 | info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); | |
590 | ||
591 | /* | |
a6dc3cd7 SP |
592 | * If we have AArch32, we care about 32-bit features for compat. |
593 | * If the system doesn't support AArch32, don't update them. | |
3086d391 | 594 | */ |
46823dd1 | 595 | if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) && |
a6dc3cd7 SP |
596 | id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { |
597 | ||
598 | taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, | |
3086d391 | 599 | info->reg_id_dfr0, boot->reg_id_dfr0); |
a6dc3cd7 | 600 | taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, |
3086d391 | 601 | info->reg_id_isar0, boot->reg_id_isar0); |
a6dc3cd7 | 602 | taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, |
3086d391 | 603 | info->reg_id_isar1, boot->reg_id_isar1); |
a6dc3cd7 | 604 | taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, |
3086d391 | 605 | info->reg_id_isar2, boot->reg_id_isar2); |
a6dc3cd7 | 606 | taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, |
3086d391 | 607 | info->reg_id_isar3, boot->reg_id_isar3); |
a6dc3cd7 | 608 | taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, |
3086d391 | 609 | info->reg_id_isar4, boot->reg_id_isar4); |
a6dc3cd7 | 610 | taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, |
3086d391 SP |
611 | info->reg_id_isar5, boot->reg_id_isar5); |
612 | ||
a6dc3cd7 SP |
613 | /* |
614 | * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and | |
615 | * ACTLR formats could differ across CPUs and therefore would have to | |
616 | * be trapped for virtualization anyway. | |
617 | */ | |
618 | taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, | |
3086d391 | 619 | info->reg_id_mmfr0, boot->reg_id_mmfr0); |
a6dc3cd7 | 620 | taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, |
3086d391 | 621 | info->reg_id_mmfr1, boot->reg_id_mmfr1); |
a6dc3cd7 | 622 | taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, |
3086d391 | 623 | info->reg_id_mmfr2, boot->reg_id_mmfr2); |
a6dc3cd7 | 624 | taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, |
3086d391 | 625 | info->reg_id_mmfr3, boot->reg_id_mmfr3); |
a6dc3cd7 | 626 | taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, |
3086d391 | 627 | info->reg_id_pfr0, boot->reg_id_pfr0); |
a6dc3cd7 | 628 | taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, |
3086d391 | 629 | info->reg_id_pfr1, boot->reg_id_pfr1); |
a6dc3cd7 | 630 | taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, |
3086d391 | 631 | info->reg_mvfr0, boot->reg_mvfr0); |
a6dc3cd7 | 632 | taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, |
3086d391 | 633 | info->reg_mvfr1, boot->reg_mvfr1); |
a6dc3cd7 | 634 | taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, |
3086d391 | 635 | info->reg_mvfr2, boot->reg_mvfr2); |
a6dc3cd7 | 636 | } |
3086d391 SP |
637 | |
638 | /* | |
639 | * Mismatched CPU features are a recipe for disaster. Don't even | |
640 | * pretend to support them. | |
641 | */ | |
3fde2999 WD |
642 | pr_warn_once("Unsupported CPU feature variation detected.\n"); |
643 | add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); | |
cdcf817b SP |
644 | } |
645 | ||
46823dd1 | 646 | u64 read_sanitised_ftr_reg(u32 id) |
b3f15378 SP |
647 | { |
648 | struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); | |
649 | ||
650 | /* We shouldn't get a request for an unsupported register */ | |
651 | BUG_ON(!regp); | |
652 | return regp->sys_val; | |
653 | } | |
359b7064 | 654 | |
965861d6 MR |
655 | #define read_sysreg_case(r) \ |
656 | case r: return read_sysreg_s(r) | |
657 | ||
92406f0c | 658 | /* |
46823dd1 | 659 | * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. |
92406f0c SP |
660 | * Read the system register on the current CPU |
661 | */ | |
46823dd1 | 662 | static u64 __read_sysreg_by_encoding(u32 sys_id) |
92406f0c SP |
663 | { |
664 | switch (sys_id) { | |
965861d6 MR |
665 | read_sysreg_case(SYS_ID_PFR0_EL1); |
666 | read_sysreg_case(SYS_ID_PFR1_EL1); | |
667 | read_sysreg_case(SYS_ID_DFR0_EL1); | |
668 | read_sysreg_case(SYS_ID_MMFR0_EL1); | |
669 | read_sysreg_case(SYS_ID_MMFR1_EL1); | |
670 | read_sysreg_case(SYS_ID_MMFR2_EL1); | |
671 | read_sysreg_case(SYS_ID_MMFR3_EL1); | |
672 | read_sysreg_case(SYS_ID_ISAR0_EL1); | |
673 | read_sysreg_case(SYS_ID_ISAR1_EL1); | |
674 | read_sysreg_case(SYS_ID_ISAR2_EL1); | |
675 | read_sysreg_case(SYS_ID_ISAR3_EL1); | |
676 | read_sysreg_case(SYS_ID_ISAR4_EL1); | |
677 | read_sysreg_case(SYS_ID_ISAR5_EL1); | |
678 | read_sysreg_case(SYS_MVFR0_EL1); | |
679 | read_sysreg_case(SYS_MVFR1_EL1); | |
680 | read_sysreg_case(SYS_MVFR2_EL1); | |
681 | ||
682 | read_sysreg_case(SYS_ID_AA64PFR0_EL1); | |
683 | read_sysreg_case(SYS_ID_AA64PFR1_EL1); | |
684 | read_sysreg_case(SYS_ID_AA64DFR0_EL1); | |
685 | read_sysreg_case(SYS_ID_AA64DFR1_EL1); | |
686 | read_sysreg_case(SYS_ID_AA64MMFR0_EL1); | |
687 | read_sysreg_case(SYS_ID_AA64MMFR1_EL1); | |
688 | read_sysreg_case(SYS_ID_AA64MMFR2_EL1); | |
689 | read_sysreg_case(SYS_ID_AA64ISAR0_EL1); | |
690 | read_sysreg_case(SYS_ID_AA64ISAR1_EL1); | |
691 | ||
692 | read_sysreg_case(SYS_CNTFRQ_EL0); | |
693 | read_sysreg_case(SYS_CTR_EL0); | |
694 | read_sysreg_case(SYS_DCZID_EL0); | |
695 | ||
92406f0c SP |
696 | default: |
697 | BUG(); | |
698 | return 0; | |
699 | } | |
700 | } | |
701 | ||
963fcd40 MZ |
702 | #include <linux/irqchip/arm-gic-v3.h> |
703 | ||
18ffa046 JM |
704 | static bool |
705 | feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) | |
706 | { | |
28c5dcb2 | 707 | int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign); |
18ffa046 JM |
708 | |
709 | return val >= entry->min_field_value; | |
710 | } | |
711 | ||
da8d02d1 | 712 | static bool |
92406f0c | 713 | has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) |
da8d02d1 SP |
714 | { |
715 | u64 val; | |
94a9e04a | 716 | |
92406f0c SP |
717 | WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); |
718 | if (scope == SCOPE_SYSTEM) | |
46823dd1 | 719 | val = read_sanitised_ftr_reg(entry->sys_reg); |
92406f0c | 720 | else |
46823dd1 | 721 | val = __read_sysreg_by_encoding(entry->sys_reg); |
92406f0c | 722 | |
da8d02d1 SP |
723 | return feature_matches(val, entry); |
724 | } | |
338d4f49 | 725 | |
92406f0c | 726 | static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) |
963fcd40 MZ |
727 | { |
728 | bool has_sre; | |
729 | ||
92406f0c | 730 | if (!has_cpuid_feature(entry, scope)) |
963fcd40 MZ |
731 | return false; |
732 | ||
733 | has_sre = gic_enable_sre(); | |
734 | if (!has_sre) | |
735 | pr_warn_once("%s present but disabled by higher exception level\n", | |
736 | entry->desc); | |
737 | ||
738 | return has_sre; | |
739 | } | |
740 | ||
92406f0c | 741 | static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) |
d5370f75 WD |
742 | { |
743 | u32 midr = read_cpuid_id(); | |
d5370f75 WD |
744 | |
745 | /* Cavium ThunderX pass 1.x and 2.x */ | |
fa5ce3d1 RR |
746 | return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, |
747 | MIDR_CPU_VAR_REV(0, 0), | |
748 | MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); | |
d5370f75 WD |
749 | } |
750 | ||
92406f0c | 751 | static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) |
d88701be MZ |
752 | { |
753 | return is_kernel_in_hyp_mode(); | |
754 | } | |
755 | ||
d1745910 MZ |
756 | static bool hyp_offset_low(const struct arm64_cpu_capabilities *entry, |
757 | int __unused) | |
758 | { | |
2077be67 | 759 | phys_addr_t idmap_addr = __pa_symbol(__hyp_idmap_text_start); |
d1745910 MZ |
760 | |
761 | /* | |
762 | * Activate the lower HYP offset only if: | |
763 | * - the idmap doesn't clash with it, | |
764 | * - the kernel is not running at EL2. | |
765 | */ | |
766 | return idmap_addr > GENMASK(VA_BITS - 2, 0) && !is_kernel_in_hyp_mode(); | |
767 | } | |
768 | ||
82e0191a SP |
769 | static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused) |
770 | { | |
46823dd1 | 771 | u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); |
82e0191a SP |
772 | |
773 | return cpuid_feature_extract_signed_field(pfr0, | |
774 | ID_AA64PFR0_FP_SHIFT) < 0; | |
775 | } | |
776 | ||
359b7064 | 777 | static const struct arm64_cpu_capabilities arm64_features[] = { |
94a9e04a MZ |
778 | { |
779 | .desc = "GIC system register CPU interface", | |
780 | .capability = ARM64_HAS_SYSREG_GIC_CPUIF, | |
92406f0c | 781 | .def_scope = SCOPE_SYSTEM, |
963fcd40 | 782 | .matches = has_useable_gicv3_cpuif, |
da8d02d1 SP |
783 | .sys_reg = SYS_ID_AA64PFR0_EL1, |
784 | .field_pos = ID_AA64PFR0_GIC_SHIFT, | |
ff96f7bc | 785 | .sign = FTR_UNSIGNED, |
18ffa046 | 786 | .min_field_value = 1, |
94a9e04a | 787 | }, |
338d4f49 JM |
788 | #ifdef CONFIG_ARM64_PAN |
789 | { | |
790 | .desc = "Privileged Access Never", | |
791 | .capability = ARM64_HAS_PAN, | |
92406f0c | 792 | .def_scope = SCOPE_SYSTEM, |
da8d02d1 SP |
793 | .matches = has_cpuid_feature, |
794 | .sys_reg = SYS_ID_AA64MMFR1_EL1, | |
795 | .field_pos = ID_AA64MMFR1_PAN_SHIFT, | |
ff96f7bc | 796 | .sign = FTR_UNSIGNED, |
338d4f49 JM |
797 | .min_field_value = 1, |
798 | .enable = cpu_enable_pan, | |
799 | }, | |
800 | #endif /* CONFIG_ARM64_PAN */ | |
2e94da13 WD |
801 | #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS) |
802 | { | |
803 | .desc = "LSE atomic instructions", | |
804 | .capability = ARM64_HAS_LSE_ATOMICS, | |
92406f0c | 805 | .def_scope = SCOPE_SYSTEM, |
da8d02d1 SP |
806 | .matches = has_cpuid_feature, |
807 | .sys_reg = SYS_ID_AA64ISAR0_EL1, | |
808 | .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, | |
ff96f7bc | 809 | .sign = FTR_UNSIGNED, |
2e94da13 WD |
810 | .min_field_value = 2, |
811 | }, | |
812 | #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */ | |
d5370f75 WD |
813 | { |
814 | .desc = "Software prefetching using PRFM", | |
815 | .capability = ARM64_HAS_NO_HW_PREFETCH, | |
92406f0c | 816 | .def_scope = SCOPE_SYSTEM, |
d5370f75 WD |
817 | .matches = has_no_hw_prefetch, |
818 | }, | |
57f4959b JM |
819 | #ifdef CONFIG_ARM64_UAO |
820 | { | |
821 | .desc = "User Access Override", | |
822 | .capability = ARM64_HAS_UAO, | |
92406f0c | 823 | .def_scope = SCOPE_SYSTEM, |
57f4959b JM |
824 | .matches = has_cpuid_feature, |
825 | .sys_reg = SYS_ID_AA64MMFR2_EL1, | |
826 | .field_pos = ID_AA64MMFR2_UAO_SHIFT, | |
827 | .min_field_value = 1, | |
c8b06e3f JM |
828 | /* |
829 | * We rely on stop_machine() calling uao_thread_switch() to set | |
830 | * UAO immediately after patching. | |
831 | */ | |
57f4959b JM |
832 | }, |
833 | #endif /* CONFIG_ARM64_UAO */ | |
70544196 JM |
834 | #ifdef CONFIG_ARM64_PAN |
835 | { | |
836 | .capability = ARM64_ALT_PAN_NOT_UAO, | |
92406f0c | 837 | .def_scope = SCOPE_SYSTEM, |
70544196 JM |
838 | .matches = cpufeature_pan_not_uao, |
839 | }, | |
840 | #endif /* CONFIG_ARM64_PAN */ | |
d88701be MZ |
841 | { |
842 | .desc = "Virtualization Host Extensions", | |
843 | .capability = ARM64_HAS_VIRT_HOST_EXTN, | |
92406f0c | 844 | .def_scope = SCOPE_SYSTEM, |
d88701be MZ |
845 | .matches = runs_at_el2, |
846 | }, | |
042446a3 SP |
847 | { |
848 | .desc = "32-bit EL0 Support", | |
849 | .capability = ARM64_HAS_32BIT_EL0, | |
92406f0c | 850 | .def_scope = SCOPE_SYSTEM, |
042446a3 SP |
851 | .matches = has_cpuid_feature, |
852 | .sys_reg = SYS_ID_AA64PFR0_EL1, | |
853 | .sign = FTR_UNSIGNED, | |
854 | .field_pos = ID_AA64PFR0_EL0_SHIFT, | |
855 | .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT, | |
856 | }, | |
d1745910 MZ |
857 | { |
858 | .desc = "Reduced HYP mapping offset", | |
859 | .capability = ARM64_HYP_OFFSET_LOW, | |
860 | .def_scope = SCOPE_SYSTEM, | |
861 | .matches = hyp_offset_low, | |
862 | }, | |
82e0191a SP |
863 | { |
864 | /* FP/SIMD is not implemented */ | |
865 | .capability = ARM64_HAS_NO_FPSIMD, | |
866 | .def_scope = SCOPE_SYSTEM, | |
867 | .min_field_value = 0, | |
868 | .matches = has_no_fpsimd, | |
869 | }, | |
359b7064 MZ |
870 | {}, |
871 | }; | |
872 | ||
ff96f7bc | 873 | #define HWCAP_CAP(reg, field, s, min_value, type, cap) \ |
37b01d53 SP |
874 | { \ |
875 | .desc = #cap, \ | |
92406f0c | 876 | .def_scope = SCOPE_SYSTEM, \ |
37b01d53 SP |
877 | .matches = has_cpuid_feature, \ |
878 | .sys_reg = reg, \ | |
879 | .field_pos = field, \ | |
ff96f7bc | 880 | .sign = s, \ |
37b01d53 SP |
881 | .min_field_value = min_value, \ |
882 | .hwcap_type = type, \ | |
883 | .hwcap = cap, \ | |
884 | } | |
885 | ||
f3efb675 | 886 | static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { |
ff96f7bc SP |
887 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL), |
888 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES), | |
889 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1), | |
890 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2), | |
891 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32), | |
892 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS), | |
f92f5ce0 | 893 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM), |
ff96f7bc | 894 | HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP), |
bf500618 | 895 | HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP), |
ff96f7bc | 896 | HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD), |
bf500618 | 897 | HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP), |
c8c3798d | 898 | HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT), |
cb567e79 | 899 | HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA), |
c651aae5 | 900 | HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC), |
75283501 SP |
901 | {}, |
902 | }; | |
903 | ||
904 | static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { | |
37b01d53 | 905 | #ifdef CONFIG_COMPAT |
ff96f7bc SP |
906 | HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), |
907 | HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), | |
908 | HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), | |
909 | HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), | |
910 | HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), | |
37b01d53 SP |
911 | #endif |
912 | {}, | |
913 | }; | |
914 | ||
f3efb675 | 915 | static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) |
37b01d53 SP |
916 | { |
917 | switch (cap->hwcap_type) { | |
918 | case CAP_HWCAP: | |
919 | elf_hwcap |= cap->hwcap; | |
920 | break; | |
921 | #ifdef CONFIG_COMPAT | |
922 | case CAP_COMPAT_HWCAP: | |
923 | compat_elf_hwcap |= (u32)cap->hwcap; | |
924 | break; | |
925 | case CAP_COMPAT_HWCAP2: | |
926 | compat_elf_hwcap2 |= (u32)cap->hwcap; | |
927 | break; | |
928 | #endif | |
929 | default: | |
930 | WARN_ON(1); | |
931 | break; | |
932 | } | |
933 | } | |
934 | ||
935 | /* Check if we have a particular HWCAP enabled */ | |
f3efb675 | 936 | static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) |
37b01d53 SP |
937 | { |
938 | bool rc; | |
939 | ||
940 | switch (cap->hwcap_type) { | |
941 | case CAP_HWCAP: | |
942 | rc = (elf_hwcap & cap->hwcap) != 0; | |
943 | break; | |
944 | #ifdef CONFIG_COMPAT | |
945 | case CAP_COMPAT_HWCAP: | |
946 | rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; | |
947 | break; | |
948 | case CAP_COMPAT_HWCAP2: | |
949 | rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; | |
950 | break; | |
951 | #endif | |
952 | default: | |
953 | WARN_ON(1); | |
954 | rc = false; | |
955 | } | |
956 | ||
957 | return rc; | |
958 | } | |
959 | ||
75283501 | 960 | static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) |
37b01d53 | 961 | { |
77c97b4e SP |
962 | /* We support emulation of accesses to CPU ID feature registers */ |
963 | elf_hwcap |= HWCAP_CPUID; | |
75283501 | 964 | for (; hwcaps->matches; hwcaps++) |
92406f0c | 965 | if (hwcaps->matches(hwcaps, hwcaps->def_scope)) |
75283501 | 966 | cap_set_elf_hwcap(hwcaps); |
37b01d53 SP |
967 | } |
968 | ||
ce8b602c | 969 | void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps, |
359b7064 MZ |
970 | const char *info) |
971 | { | |
75283501 | 972 | for (; caps->matches; caps++) { |
92406f0c | 973 | if (!caps->matches(caps, caps->def_scope)) |
359b7064 MZ |
974 | continue; |
975 | ||
75283501 SP |
976 | if (!cpus_have_cap(caps->capability) && caps->desc) |
977 | pr_info("%s %s\n", info, caps->desc); | |
978 | cpus_set_cap(caps->capability); | |
359b7064 | 979 | } |
ce8b602c SP |
980 | } |
981 | ||
982 | /* | |
dbb4e152 SP |
983 | * Run through the enabled capabilities and enable() it on all active |
984 | * CPUs | |
ce8b602c | 985 | */ |
8e231852 | 986 | void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps) |
ce8b602c | 987 | { |
63a1e1c9 MR |
988 | for (; caps->matches; caps++) { |
989 | unsigned int num = caps->capability; | |
990 | ||
991 | if (!cpus_have_cap(num)) | |
992 | continue; | |
993 | ||
994 | /* Ensure cpus_have_const_cap(num) works */ | |
995 | static_branch_enable(&cpu_hwcap_keys[num]); | |
996 | ||
997 | if (caps->enable) { | |
2a6dcb2b JM |
998 | /* |
999 | * Use stop_machine() as it schedules the work allowing | |
1000 | * us to modify PSTATE, instead of on_each_cpu() which | |
1001 | * uses an IPI, giving us a PSTATE that disappears when | |
1002 | * we return. | |
1003 | */ | |
1004 | stop_machine(caps->enable, NULL, cpu_online_mask); | |
63a1e1c9 MR |
1005 | } |
1006 | } | |
dbb4e152 SP |
1007 | } |
1008 | ||
dbb4e152 SP |
1009 | /* |
1010 | * Flag to indicate if we have computed the system wide | |
1011 | * capabilities based on the boot time active CPUs. This | |
1012 | * will be used to determine if a new booting CPU should | |
1013 | * go through the verification process to make sure that it | |
1014 | * supports the system capabilities, without using a hotplug | |
1015 | * notifier. | |
1016 | */ | |
1017 | static bool sys_caps_initialised; | |
1018 | ||
1019 | static inline void set_sys_caps_initialised(void) | |
1020 | { | |
1021 | sys_caps_initialised = true; | |
1022 | } | |
1023 | ||
1024 | /* | |
13f417f3 SP |
1025 | * Check for CPU features that are used in early boot |
1026 | * based on the Boot CPU value. | |
dbb4e152 | 1027 | */ |
13f417f3 | 1028 | static void check_early_cpu_features(void) |
dbb4e152 | 1029 | { |
ac1ad20f | 1030 | verify_cpu_run_el(); |
13f417f3 | 1031 | verify_cpu_asid_bits(); |
dbb4e152 | 1032 | } |
1c076303 | 1033 | |
75283501 SP |
1034 | static void |
1035 | verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) | |
1036 | { | |
1037 | ||
92406f0c SP |
1038 | for (; caps->matches; caps++) |
1039 | if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { | |
75283501 SP |
1040 | pr_crit("CPU%d: missing HWCAP: %s\n", |
1041 | smp_processor_id(), caps->desc); | |
1042 | cpu_die_early(); | |
1043 | } | |
75283501 SP |
1044 | } |
1045 | ||
1046 | static void | |
1047 | verify_local_cpu_features(const struct arm64_cpu_capabilities *caps) | |
1048 | { | |
1049 | for (; caps->matches; caps++) { | |
92406f0c | 1050 | if (!cpus_have_cap(caps->capability)) |
75283501 SP |
1051 | continue; |
1052 | /* | |
1053 | * If the new CPU misses an advertised feature, we cannot proceed | |
1054 | * further, park the cpu. | |
1055 | */ | |
92406f0c | 1056 | if (!caps->matches(caps, SCOPE_LOCAL_CPU)) { |
75283501 SP |
1057 | pr_crit("CPU%d: missing feature: %s\n", |
1058 | smp_processor_id(), caps->desc); | |
1059 | cpu_die_early(); | |
1060 | } | |
1061 | if (caps->enable) | |
1062 | caps->enable(NULL); | |
1063 | } | |
1064 | } | |
1065 | ||
dbb4e152 SP |
1066 | /* |
1067 | * Run through the enabled system capabilities and enable() it on this CPU. | |
1068 | * The capabilities were decided based on the available CPUs at the boot time. | |
1069 | * Any new CPU should match the system wide status of the capability. If the | |
1070 | * new CPU doesn't have a capability which the system now has enabled, we | |
1071 | * cannot do anything to fix it up and could cause unexpected failures. So | |
1072 | * we park the CPU. | |
1073 | */ | |
c47a1900 | 1074 | static void verify_local_cpu_capabilities(void) |
dbb4e152 | 1075 | { |
c47a1900 SP |
1076 | verify_local_cpu_errata_workarounds(); |
1077 | verify_local_cpu_features(arm64_features); | |
1078 | verify_local_elf_hwcaps(arm64_elf_hwcaps); | |
1079 | if (system_supports_32bit_el0()) | |
1080 | verify_local_elf_hwcaps(compat_elf_hwcaps); | |
1081 | } | |
dbb4e152 | 1082 | |
c47a1900 SP |
1083 | void check_local_cpu_capabilities(void) |
1084 | { | |
1085 | /* | |
1086 | * All secondary CPUs should conform to the early CPU features | |
1087 | * in use by the kernel based on boot CPU. | |
1088 | */ | |
13f417f3 SP |
1089 | check_early_cpu_features(); |
1090 | ||
dbb4e152 | 1091 | /* |
c47a1900 SP |
1092 | * If we haven't finalised the system capabilities, this CPU gets |
1093 | * a chance to update the errata work arounds. | |
1094 | * Otherwise, this CPU should verify that it has all the system | |
1095 | * advertised capabilities. | |
dbb4e152 SP |
1096 | */ |
1097 | if (!sys_caps_initialised) | |
c47a1900 SP |
1098 | update_cpu_errata_workarounds(); |
1099 | else | |
1100 | verify_local_cpu_capabilities(); | |
359b7064 MZ |
1101 | } |
1102 | ||
a7c61a34 | 1103 | static void __init setup_feature_capabilities(void) |
359b7064 | 1104 | { |
ce8b602c SP |
1105 | update_cpu_capabilities(arm64_features, "detected feature:"); |
1106 | enable_cpu_capabilities(arm64_features); | |
359b7064 MZ |
1107 | } |
1108 | ||
63a1e1c9 MR |
1109 | DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready); |
1110 | EXPORT_SYMBOL(arm64_const_caps_ready); | |
1111 | ||
1112 | static void __init mark_const_caps_ready(void) | |
1113 | { | |
1114 | static_branch_enable(&arm64_const_caps_ready); | |
1115 | } | |
1116 | ||
e3661b12 MZ |
1117 | /* |
1118 | * Check if the current CPU has a given feature capability. | |
1119 | * Should be called from non-preemptible context. | |
1120 | */ | |
8f413758 MZ |
1121 | static bool __this_cpu_has_cap(const struct arm64_cpu_capabilities *cap_array, |
1122 | unsigned int cap) | |
e3661b12 MZ |
1123 | { |
1124 | const struct arm64_cpu_capabilities *caps; | |
1125 | ||
1126 | if (WARN_ON(preemptible())) | |
1127 | return false; | |
1128 | ||
8f413758 | 1129 | for (caps = cap_array; caps->desc; caps++) |
e3661b12 MZ |
1130 | if (caps->capability == cap && caps->matches) |
1131 | return caps->matches(caps, SCOPE_LOCAL_CPU); | |
1132 | ||
1133 | return false; | |
1134 | } | |
1135 | ||
8f413758 MZ |
1136 | extern const struct arm64_cpu_capabilities arm64_errata[]; |
1137 | ||
1138 | bool this_cpu_has_cap(unsigned int cap) | |
1139 | { | |
1140 | return (__this_cpu_has_cap(arm64_features, cap) || | |
1141 | __this_cpu_has_cap(arm64_errata, cap)); | |
1142 | } | |
1143 | ||
9cdf8ec4 | 1144 | void __init setup_cpu_features(void) |
359b7064 | 1145 | { |
9cdf8ec4 SP |
1146 | u32 cwg; |
1147 | int cls; | |
1148 | ||
dbb4e152 SP |
1149 | /* Set the CPU feature capabilies */ |
1150 | setup_feature_capabilities(); | |
8e231852 | 1151 | enable_errata_workarounds(); |
63a1e1c9 | 1152 | mark_const_caps_ready(); |
75283501 | 1153 | setup_elf_hwcaps(arm64_elf_hwcaps); |
643d703d SP |
1154 | |
1155 | if (system_supports_32bit_el0()) | |
1156 | setup_elf_hwcaps(compat_elf_hwcaps); | |
dbb4e152 SP |
1157 | |
1158 | /* Advertise that we have computed the system capabilities */ | |
1159 | set_sys_caps_initialised(); | |
1160 | ||
9cdf8ec4 SP |
1161 | /* |
1162 | * Check for sane CTR_EL0.CWG value. | |
1163 | */ | |
1164 | cwg = cache_type_cwg(); | |
1165 | cls = cache_line_size(); | |
1166 | if (!cwg) | |
1167 | pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n", | |
1168 | cls); | |
1169 | if (L1_CACHE_BYTES < cls) | |
1170 | pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n", | |
1171 | L1_CACHE_BYTES, cls); | |
359b7064 | 1172 | } |
70544196 JM |
1173 | |
1174 | static bool __maybe_unused | |
92406f0c | 1175 | cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused) |
70544196 | 1176 | { |
a4023f68 | 1177 | return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO)); |
70544196 | 1178 | } |
77c97b4e SP |
1179 | |
1180 | /* | |
1181 | * We emulate only the following system register space. | |
1182 | * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7] | |
1183 | * See Table C5-6 System instruction encodings for System register accesses, | |
1184 | * ARMv8 ARM(ARM DDI 0487A.f) for more details. | |
1185 | */ | |
1186 | static inline bool __attribute_const__ is_emulated(u32 id) | |
1187 | { | |
1188 | return (sys_reg_Op0(id) == 0x3 && | |
1189 | sys_reg_CRn(id) == 0x0 && | |
1190 | sys_reg_Op1(id) == 0x0 && | |
1191 | (sys_reg_CRm(id) == 0 || | |
1192 | ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7)))); | |
1193 | } | |
1194 | ||
1195 | /* | |
1196 | * With CRm == 0, reg should be one of : | |
1197 | * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. | |
1198 | */ | |
1199 | static inline int emulate_id_reg(u32 id, u64 *valp) | |
1200 | { | |
1201 | switch (id) { | |
1202 | case SYS_MIDR_EL1: | |
1203 | *valp = read_cpuid_id(); | |
1204 | break; | |
1205 | case SYS_MPIDR_EL1: | |
1206 | *valp = SYS_MPIDR_SAFE_VAL; | |
1207 | break; | |
1208 | case SYS_REVIDR_EL1: | |
1209 | /* IMPLEMENTATION DEFINED values are emulated with 0 */ | |
1210 | *valp = 0; | |
1211 | break; | |
1212 | default: | |
1213 | return -EINVAL; | |
1214 | } | |
1215 | ||
1216 | return 0; | |
1217 | } | |
1218 | ||
1219 | static int emulate_sys_reg(u32 id, u64 *valp) | |
1220 | { | |
1221 | struct arm64_ftr_reg *regp; | |
1222 | ||
1223 | if (!is_emulated(id)) | |
1224 | return -EINVAL; | |
1225 | ||
1226 | if (sys_reg_CRm(id) == 0) | |
1227 | return emulate_id_reg(id, valp); | |
1228 | ||
1229 | regp = get_arm64_ftr_reg(id); | |
1230 | if (regp) | |
1231 | *valp = arm64_ftr_reg_user_value(regp); | |
1232 | else | |
1233 | /* | |
1234 | * The untracked registers are either IMPLEMENTATION DEFINED | |
1235 | * (e.g, ID_AFR0_EL1) or reserved RAZ. | |
1236 | */ | |
1237 | *valp = 0; | |
1238 | return 0; | |
1239 | } | |
1240 | ||
1241 | static int emulate_mrs(struct pt_regs *regs, u32 insn) | |
1242 | { | |
1243 | int rc; | |
1244 | u32 sys_reg, dst; | |
1245 | u64 val; | |
1246 | ||
1247 | /* | |
1248 | * sys_reg values are defined as used in mrs/msr instruction. | |
1249 | * shift the imm value to get the encoding. | |
1250 | */ | |
1251 | sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; | |
1252 | rc = emulate_sys_reg(sys_reg, &val); | |
1253 | if (!rc) { | |
1254 | dst = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); | |
521c6461 | 1255 | pt_regs_write_reg(regs, dst, val); |
77c97b4e SP |
1256 | regs->pc += 4; |
1257 | } | |
1258 | ||
1259 | return rc; | |
1260 | } | |
1261 | ||
1262 | static struct undef_hook mrs_hook = { | |
1263 | .instr_mask = 0xfff00000, | |
1264 | .instr_val = 0xd5300000, | |
1265 | .pstate_mask = COMPAT_PSR_MODE_MASK, | |
1266 | .pstate_val = PSR_MODE_EL0t, | |
1267 | .fn = emulate_mrs, | |
1268 | }; | |
1269 | ||
1270 | static int __init enable_mrs_emulation(void) | |
1271 | { | |
1272 | register_undef_hook(&mrs_hook); | |
1273 | return 0; | |
1274 | } | |
1275 | ||
1276 | late_initcall(enable_mrs_emulation); |