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arm64/cpufeature: Introduce ID_PFR2 CPU register
[mirror_ubuntu-jammy-kernel.git] / arch / arm64 / kernel / cpufeature.c
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caab277b 1// SPDX-License-Identifier: GPL-2.0-only
359b7064
MZ		 2/*
3 * Contains CPU feature definitions
4 *
5 * Copyright (C) 2015 ARM Ltd.
a2a69963
WD		 6 *
7 * A note for the weary kernel hacker: the code here is confusing and hard to
8 * follow! That's partly because it's solving a nasty problem, but also because
9 * there's a little bit of over-abstraction that tends to obscure what's going
10 * on behind a maze of helper functions and macros.
11 *
12 * The basic problem is that hardware folks have started gluing together CPUs
13 * with distinct architectural features; in some cases even creating SoCs where
14 * user-visible instructions are available only on a subset of the available
15 * cores. We try to address this by snapshotting the feature registers of the
16 * boot CPU and comparing these with the feature registers of each secondary
17 * CPU when bringing them up. If there is a mismatch, then we update the
18 * snapshot state to indicate the lowest-common denominator of the feature,
19 * known as the "safe" value. This snapshot state can be queried to view the
20 * "sanitised" value of a feature register.
21 *
22 * The sanitised register values are used to decide which capabilities we
23 * have in the system. These may be in the form of traditional "hwcaps"
24 * advertised to userspace or internal "cpucaps" which are used to configure
25 * things like alternative patching and static keys. While a feature mismatch
26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch
27 * may prevent a CPU from being onlined at all.
28 *
29 * Some implementation details worth remembering:
30 *
31 * - Mismatched features are *always* sanitised to a "safe" value, which
32 * usually indicates that the feature is not supported.
33 *
34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
35 * warning when onlining an offending CPU and the kernel will be tainted
36 * with TAINT_CPU_OUT_OF_SPEC.
37 *
38 * - Features marked as FTR_VISIBLE have their sanitised value visible to
39 * userspace. FTR_VISIBLE features in registers that are only visible
40 * to EL0 by trapping *must* have a corresponding HWCAP so that late
41 * onlining of CPUs cannot lead to features disappearing at runtime.
42 *
43 * - A "feature" is typically a 4-bit register field. A "capability" is the
44 * high-level description derived from the sanitised field value.
45 *
46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID
47 * scheme for fields in ID registers") to understand when feature fields
48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly).
49 *
50 * - KVM exposes its own view of the feature registers to guest operating
51 * systems regardless of FTR_VISIBLE. This is typically driven from the
52 * sanitised register values to allow virtual CPUs to be migrated between
53 * arbitrary physical CPUs, but some features not present on the host are
54 * also advertised and emulated. Look at sys_reg_descs[] for the gory
55 * details.
433022b5
WD		 56 *
57 * - If the arm64_ftr_bits[] for a register has a missing field, then this
58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg().
59 * This is stronger than FTR_HIDDEN and can be used to hide features from
60 * KVM guests.
359b7064
MZ		 61 */
62
9cdf8ec4 63#define pr_fmt(fmt) "CPU features: " fmt
359b7064 64
3c739b57 65#include <linux/bsearch.h>
2a6dcb2b 66#include <linux/cpumask.h>
5ffdfaed 67#include <linux/crash_dump.h>
3c739b57 68#include <linux/sort.h>
2a6dcb2b 69#include <linux/stop_machine.h>
359b7064 70#include <linux/types.h>
2077be67 71#include <linux/mm.h>
a111b7c0 72#include <linux/cpu.h>
359b7064
MZ		 73#include <asm/cpu.h>
74#include <asm/cpufeature.h>
dbb4e152 75#include <asm/cpu_ops.h>
2e0f2478 76#include <asm/fpsimd.h>
13f417f3 77#include <asm/mmu_context.h>
338d4f49 78#include <asm/processor.h>
cdcf817b 79#include <asm/sysreg.h>
77c97b4e 80#include <asm/traps.h>
d88701be 81#include <asm/virt.h>
359b7064 82
aec0bff7
AM		 83/* Kernel representation of AT_HWCAP and AT_HWCAP2 */
84static unsigned long elf_hwcap __read_mostly;
9cdf8ec4
SP		 85
86#ifdef CONFIG_COMPAT
87#define COMPAT_ELF_HWCAP_DEFAULT \
88 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
89 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
7559950a 90 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
9cdf8ec4
SP		 91 COMPAT_HWCAP_LPAE)
92unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
93unsigned int compat_elf_hwcap2 __read_mostly;
94#endif
95
96DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
4b65a5db 97EXPORT_SYMBOL(cpu_hwcaps);
82a3a21b 98static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
9cdf8ec4 99
0ceb0d56
DT		 100/* Need also bit for ARM64_CB_PATCH */
101DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
102
09e3c22a
MB		 103bool arm64_use_ng_mappings = false;
104EXPORT_SYMBOL(arm64_use_ng_mappings);
105
8f1eec57
DM		 106/*
107 * Flag to indicate if we have computed the system wide
108 * capabilities based on the boot time active CPUs. This
109 * will be used to determine if a new booting CPU should
110 * go through the verification process to make sure that it
111 * supports the system capabilities, without using a hotplug
b51c6ac2
SP		 112 * notifier. This is also used to decide if we could use
113 * the fast path for checking constant CPU caps.
8f1eec57 114 */
b51c6ac2
SP		 115DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
116EXPORT_SYMBOL(arm64_const_caps_ready);
117static inline void finalize_system_capabilities(void)
8f1eec57 118{
b51c6ac2 119 static_branch_enable(&arm64_const_caps_ready);
8f1eec57
DM		 120}
121
8effeaaf
MR		 122static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
123{
124 /* file-wide pr_fmt adds "CPU features: " prefix */
125 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
126 return 0;
127}
128
129static struct notifier_block cpu_hwcaps_notifier = {
130 .notifier_call = dump_cpu_hwcaps
131};
132
133static int __init register_cpu_hwcaps_dumper(void)
134{
135 atomic_notifier_chain_register(&panic_notifier_list,
136 &cpu_hwcaps_notifier);
137 return 0;
138}
139__initcall(register_cpu_hwcaps_dumper);
140
efd9e03f
CM		 141DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
142EXPORT_SYMBOL(cpu_hwcap_keys);
143
fe4fbdbc 144#define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
3c739b57 145 { \
4f0a606b 146 .sign = SIGNED, \
fe4fbdbc 147 .visible = VISIBLE, \
3c739b57
SP		 148 .strict = STRICT, \
149 .type = TYPE, \
150 .shift = SHIFT, \
151 .width = WIDTH, \
152 .safe_val = SAFE_VAL, \
153 }
154
0710cfdb 155/* Define a feature with unsigned values */
fe4fbdbc
SP		 156#define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
157 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
4f0a606b 158
0710cfdb 159/* Define a feature with a signed value */
fe4fbdbc
SP		 160#define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
161 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
0710cfdb 162
3c739b57
SP		 163#define ARM64_FTR_END \
164 { \
165 .width = 0, \
166 }
167
70544196
JM		 168/* meta feature for alternatives */
169static bool __maybe_unused
92406f0c
SP		 170cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
171
5ffdfaed 172static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
70544196 173
3ff047f6
ADK		 174static bool __system_matches_cap(unsigned int n);
175
4aa8a472
SP		 176/*
177 * NOTE: Any changes to the visibility of features should be kept in
178 * sync with the documentation of the CPU feature register ABI.
179 */
5e49d73c 180static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
1a50ec0b 181 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0),
7206dc93 182 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
3b3b6810 183 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
5bdecb79
SP		 184 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
185 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
186 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
187 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
188 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
fe4fbdbc
SP		 189 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
190 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
191 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
192 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
193 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
3c739b57
SP		 194 ARM64_FTR_END,
195};
196
c8c3798d 197static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
d4209d8b
SP		 198 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0),
199 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0),
200 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0),
201 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0),
bd4fb6d2 202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
7230f7e9 203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
6984eb47
MR		 204 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
205 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
206 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
207 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
5bdecb79
SP		 208 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
209 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
210 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
6984eb47
MR		 211 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
212 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0),
213 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
214 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0),
5bdecb79 215 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
c8c3798d
SP		 216 ARM64_FTR_END,
217};
218
5e49d73c 219static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
179a56f6 220 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
0f15adbb 221 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
7206dc93 222 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
2c9d45b4 223 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0),
3fab3999
DM		 224 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
225 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
64c02720 226 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
5bdecb79 227 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
fe4fbdbc
SP		 228 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
229 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
5bdecb79 230 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
98448cdf
WD		 231 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
232 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
233 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
3c739b57
SP		 234 ARM64_FTR_END,
235};
236
d71be2b6
WD		 237static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
238 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
239 ARM64_FTR_END,
240};
241
06a916fe 242static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
d4209d8b
SP		 243 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
244 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0),
245 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
246 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0),
247 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
248 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0),
ec52c713
JG		 249 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
250 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
251 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
252 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
d4209d8b
SP		 253 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
254 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0),
ec52c713
JG		 255 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
256 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
257 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
258 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
259 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
260 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
06a916fe
DM		 261 ARM64_FTR_END,
262};
263
5e49d73c 264static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
5717fe5a
WD		 265 /*
266 * We already refuse to boot CPUs that don't support our configured
267 * page size, so we can only detect mismatches for a page size other
268 * than the one we're currently using. Unfortunately, SoCs like this
269 * exist in the wild so, even though we don't like it, we'll have to go
270 * along with it and treat them as non-strict.
271 */
272 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
273 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
274 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
275
5bdecb79 276 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
3c739b57 277 /* Linux shouldn't care about secure memory */
5bdecb79
SP		 278 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
279 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
280 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
3c739b57
SP		 281 /*
282 * Differing PARange is fine as long as all peripherals and memory are mapped
283 * within the minimum PARange of all CPUs
284 */
fe4fbdbc 285 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
3c739b57
SP		 286 ARM64_FTR_END,
287};
288
5e49d73c 289static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
fe4fbdbc 290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
5bdecb79
SP		 291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
292 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
293 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
295 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
3c739b57
SP		 296 ARM64_FTR_END,
297};
298
5e49d73c 299static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
3e6c69a0 300 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0),
e48d53a9 301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
7206dc93 302 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
5bdecb79 303 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
9d3f8881 304 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
5bdecb79
SP		 305 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
306 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
307 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
406e3087
JM		 308 ARM64_FTR_END,
309};
310
5e49d73c 311static const struct arm64_ftr_bits ftr_ctr[] = {
6ae4b6e0
SD		 312 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
313 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
314 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
147b9635
WD		 315 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
316 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
6ae4b6e0 317 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
3c739b57
SP		 318 /*
319 * Linux can handle differing I-cache policies. Userspace JITs will
ee7bc638 320 * make use of *minLine.
155433cb 321 * If we have differing I-cache policies, report it as the weakest - VIPT.
3c739b57 322 */
155433cb 323 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */
4c4a39dd 324 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
3c739b57
SP		 325 ARM64_FTR_END,
326};
327
675b0563
AB		 328struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
329 .name = "SYS_CTR_EL0",
330 .ftr_bits = ftr_ctr
331};
332
5e49d73c 333static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
5bdecb79
SP		 334 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf), /* InnerShr */
335 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), /* FCSE */
fe4fbdbc 336 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
5bdecb79
SP		 337 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), /* TCM */
338 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* ShareLvl */
339 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf), /* OuterShr */
340 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* PMSA */
341 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* VMSA */
3c739b57
SP		 342 ARM64_FTR_END,
343};
344
5e49d73c 345static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
e965bcb0 346 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 36, 4, 0),
fe4fbdbc
SP		 347 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
348 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
349 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
350 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
b20d1ba3
WD		 351 /*
352 * We can instantiate multiple PMU instances with different levels
353 * of support.
fe4fbdbc
SP		 354 */
355 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
356 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
357 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
3c739b57
SP		 358 ARM64_FTR_END,
359};
360
5e49d73c 361static const struct arm64_ftr_bits ftr_mvfr2[] = {
5bdecb79
SP		 362 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* FPMisc */
363 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* SIMDMisc */
3c739b57
SP		 364 ARM64_FTR_END,
365};
366
5e49d73c 367static const struct arm64_ftr_bits ftr_dczid[] = {
fe4fbdbc
SP		 368 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
369 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
3c739b57
SP		 370 ARM64_FTR_END,
371};
372
2a5bc6c4
AK		 373static const struct arm64_ftr_bits ftr_id_isar0[] = {
374 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0),
375 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0),
376 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0),
377 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0),
378 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0),
379 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0),
380 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0),
381 ARM64_FTR_END,
382};
3c739b57 383
5e49d73c 384static const struct arm64_ftr_bits ftr_id_isar5[] = {
5bdecb79
SP		 385 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
386 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
387 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
388 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
389 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
390 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
3c739b57
SP		 391 ARM64_FTR_END,
392};
393
5e49d73c 394static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
5bdecb79 395 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* ac2 */
3c739b57
SP		 396 ARM64_FTR_END,
397};
398
0113340e
WD		 399static const struct arm64_ftr_bits ftr_id_isar4[] = {
400 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0),
401 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0),
402 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0),
403 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0),
404 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0),
405 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0),
406 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0),
407 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0),
408 ARM64_FTR_END,
409};
410
8e3747be
AK		 411static const struct arm64_ftr_bits ftr_id_isar6[] = {
412 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),
413 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
414 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),
415 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),
416 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),
417 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0),
418 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0),
419 ARM64_FTR_END,
420};
421
5e49d73c 422static const struct arm64_ftr_bits ftr_id_pfr0[] = {
5bdecb79
SP		 423 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* State3 */
424 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), /* State2 */
425 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* State1 */
426 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* State0 */
3c739b57
SP		 427 ARM64_FTR_END,
428};
429
0113340e
WD		 430static const struct arm64_ftr_bits ftr_id_pfr1[] = {
431 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0),
432 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0),
433 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0),
434 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0),
435 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0),
436 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0),
437 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0),
438 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0),
439 ARM64_FTR_END,
440};
441
16824085
AK		 442static const struct arm64_ftr_bits ftr_id_pfr2[] = {
443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0),
444 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0),
445 ARM64_FTR_END,
446};
447
5e49d73c 448static const struct arm64_ftr_bits ftr_id_dfr0[] = {
1ed1b90a 449 /* [31:28] TraceFilt */
fe4fbdbc
SP		 450 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */
451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
453 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
454 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
455 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
456 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
e5343503
SP		 457 ARM64_FTR_END,
458};
459
2e0f2478
DM		 460static const struct arm64_ftr_bits ftr_zcr[] = {
461 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
462 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */
463 ARM64_FTR_END,
464};
465
3c739b57
SP		 466/*
467 * Common ftr bits for a 32bit register with all hidden, strict
468 * attributes, with 4bit feature fields and a default safe value of
469 * 0. Covers the following 32bit registers:
2a5bc6c4 470 * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
3c739b57 471 */
5e49d73c 472static const struct arm64_ftr_bits ftr_generic_32bits[] = {
fe4fbdbc
SP		 473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
477 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
478 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
479 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
480 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
3c739b57
SP		 481 ARM64_FTR_END,
482};
483
eab43e88
SP		 484/* Table for a single 32bit feature value */
485static const struct arm64_ftr_bits ftr_single32[] = {
fe4fbdbc 486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
3c739b57
SP		 487 ARM64_FTR_END,
488};
489
eab43e88 490static const struct arm64_ftr_bits ftr_raz[] = {
3c739b57
SP		 491 ARM64_FTR_END,
492};
493
6f2b7eef
AB		 494#define ARM64_FTR_REG(id, table) { \
495 .sys_id = id, \
496 .reg = &(struct arm64_ftr_reg){ \
3c739b57
SP		 497 .name = #id, \
498 .ftr_bits = &((table)[0]), \
6f2b7eef 499 }}
3c739b57 500
6f2b7eef
AB		 501static const struct __ftr_reg_entry {
502 u32 sys_id;
503 struct arm64_ftr_reg *reg;
504} arm64_ftr_regs[] = {
3c739b57
SP		 505
506 /* Op1 = 0, CRn = 0, CRm = 1 */
507 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
0113340e 508 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1),
e5343503 509 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
3c739b57
SP		 510 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
511 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
512 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
513 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
514
515 /* Op1 = 0, CRn = 0, CRm = 2 */
2a5bc6c4 516 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0),
3c739b57
SP		 517 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
518 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
519 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
0113340e 520 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4),
3c739b57
SP		 521 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
522 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
8e3747be 523 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),
3c739b57
SP		 524
525 /* Op1 = 0, CRn = 0, CRm = 3 */
526 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
527 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
528 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
16824085 529 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
3c739b57
SP		 530
531 /* Op1 = 0, CRn = 0, CRm = 4 */
532 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
d71be2b6 533 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
06a916fe 534 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
3c739b57
SP		 535
536 /* Op1 = 0, CRn = 0, CRm = 5 */
537 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
eab43e88 538 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
3c739b57
SP		 539
540 /* Op1 = 0, CRn = 0, CRm = 6 */
541 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
c8c3798d 542 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
3c739b57
SP		 543
544 /* Op1 = 0, CRn = 0, CRm = 7 */
545 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
546 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
406e3087 547 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
3c739b57 548
2e0f2478
DM		 549 /* Op1 = 0, CRn = 1, CRm = 2 */
550 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
551
3c739b57 552 /* Op1 = 3, CRn = 0, CRm = 0 */
675b0563 553 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
3c739b57
SP		 554 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
555
556 /* Op1 = 3, CRn = 14, CRm = 0 */
eab43e88 557 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
3c739b57
SP		 558};
559
560static int search_cmp_ftr_reg(const void *id, const void *regp)
561{
6f2b7eef 562 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
3c739b57
SP		 563}
564
565/*
566 * get_arm64_ftr_reg - Lookup a feature register entry using its
567 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
568 * ascending order of sys_id , we use binary search to find a matching
569 * entry.
570 *
571 * returns - Upon success, matching ftr_reg entry for id.
572 * - NULL on failure. It is upto the caller to decide
573 * the impact of a failure.
574 */
575static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
576{
6f2b7eef
AB		 577 const struct __ftr_reg_entry *ret;
578
579 ret = bsearch((const void *)(unsigned long)sys_id,
3c739b57
SP		 580 arm64_ftr_regs,
581 ARRAY_SIZE(arm64_ftr_regs),
582 sizeof(arm64_ftr_regs[0]),
583 search_cmp_ftr_reg);
6f2b7eef
AB		 584 if (ret)
585 return ret->reg;
586 return NULL;
3c739b57
SP		 587}
588
5e49d73c
AB		 589static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
590 s64 ftr_val)
3c739b57
SP		 591{
592 u64 mask = arm64_ftr_mask(ftrp);
593
594 reg &= ~mask;
595 reg |= (ftr_val << ftrp->shift) & mask;
596 return reg;
597}
598
5e49d73c
AB		 599static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
600 s64 cur)
3c739b57
SP		 601{
602 s64 ret = 0;
603
604 switch (ftrp->type) {
605 case FTR_EXACT:
606 ret = ftrp->safe_val;
607 break;
608 case FTR_LOWER_SAFE:
609 ret = new < cur ? new : cur;
610 break;
147b9635
WD		 611 case FTR_HIGHER_OR_ZERO_SAFE:
612 if (!cur || !new)
613 break;
614 /* Fallthrough */
3c739b57
SP		 615 case FTR_HIGHER_SAFE:
616 ret = new > cur ? new : cur;
617 break;
618 default:
619 BUG();
620 }
621
622 return ret;
623}
624
3c739b57
SP		 625static void __init sort_ftr_regs(void)
626{
6f2b7eef
AB		 627 int i;
628
629 /* Check that the array is sorted so that we can do the binary search */
630 for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
631 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
3c739b57
SP		 632}
633
634/*
635 * Initialise the CPU feature register from Boot CPU values.
636 * Also initiliases the strict_mask for the register.
b389d799
MR		 637 * Any bits that are not covered by an arm64_ftr_bits entry are considered
638 * RES0 for the system-wide value, and must strictly match.
3c739b57
SP		 639 */
640static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
641{
642 u64 val = 0;
643 u64 strict_mask = ~0x0ULL;
fe4fbdbc 644 u64 user_mask = 0;
b389d799
MR		 645 u64 valid_mask = 0;
646
5e49d73c 647 const struct arm64_ftr_bits *ftrp;
3c739b57
SP		 648 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
649
650 BUG_ON(!reg);
651
24b2cce9 652 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
b389d799 653 u64 ftr_mask = arm64_ftr_mask(ftrp);
3c739b57
SP		 654 s64 ftr_new = arm64_ftr_value(ftrp, new);
655
656 val = arm64_ftr_set_value(ftrp, val, ftr_new);
b389d799
MR		 657
658 valid_mask |= ftr_mask;
3c739b57 659 if (!ftrp->strict)
b389d799 660 strict_mask &= ~ftr_mask;
fe4fbdbc
SP		 661 if (ftrp->visible)
662 user_mask |= ftr_mask;
663 else
664 reg->user_val = arm64_ftr_set_value(ftrp,
665 reg->user_val,
666 ftrp->safe_val);
3c739b57 667 }
b389d799
MR		 668
669 val &= valid_mask;
670
3c739b57
SP		 671 reg->sys_val = val;
672 reg->strict_mask = strict_mask;
fe4fbdbc 673 reg->user_mask = user_mask;
3c739b57
SP		 674}
675
1e89baed 676extern const struct arm64_cpu_capabilities arm64_errata[];
82a3a21b
SP		 677static const struct arm64_cpu_capabilities arm64_features[];
678
679static void __init
680init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
681{
682 for (; caps->matches; caps++) {
683 if (WARN(caps->capability >= ARM64_NCAPS,
684 "Invalid capability %d\n", caps->capability))
685 continue;
686 if (WARN(cpu_hwcaps_ptrs[caps->capability],
687 "Duplicate entry for capability %d\n",
688 caps->capability))
689 continue;
690 cpu_hwcaps_ptrs[caps->capability] = caps;
691 }
692}
693
694static void __init init_cpu_hwcaps_indirect_list(void)
695{
696 init_cpu_hwcaps_indirect_list_from_array(arm64_features);
697 init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
698}
699
fd9d63da 700static void __init setup_boot_cpu_capabilities(void);
1e89baed 701
3c739b57
SP		 702void __init init_cpu_features(struct cpuinfo_arm64 *info)
703{
704 /* Before we start using the tables, make sure it is sorted */
705 sort_ftr_regs();
706
707 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
708 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
709 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
710 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
711 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
712 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
713 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
714 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
715 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
406e3087 716 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
3c739b57
SP		 717 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
718 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
2e0f2478 719 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
a6dc3cd7
SP		 720
721 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
722 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
723 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
724 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
725 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
726 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
727 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
728 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
8e3747be 729 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6);
a6dc3cd7
SP		 730 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
731 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
732 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
733 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
734 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
735 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
16824085 736 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2);
a6dc3cd7
SP		 737 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
738 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
739 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
740 }
741
2e0f2478
DM		 742 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
743 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
744 sve_init_vq_map();
745 }
5e91107b 746
82a3a21b
SP		 747 /*
748 * Initialize the indirect array of CPU hwcaps capabilities pointers
749 * before we handle the boot CPU below.
750 */
751 init_cpu_hwcaps_indirect_list();
752
5e91107b 753 /*
fd9d63da
SP		 754 * Detect and enable early CPU capabilities based on the boot CPU,
755 * after we have initialised the CPU feature infrastructure.
5e91107b 756 */
fd9d63da 757 setup_boot_cpu_capabilities();
3c739b57
SP		 758}
759
3086d391 760static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
3c739b57 761{
5e49d73c 762 const struct arm64_ftr_bits *ftrp;
3c739b57
SP		 763
764 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
765 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
766 s64 ftr_new = arm64_ftr_value(ftrp, new);
767
768 if (ftr_cur == ftr_new)
769 continue;
770 /* Find a safe value */
771 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
772 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
773 }
774
775}
776
3086d391 777static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
cdcf817b 778{
3086d391
SP		 779 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
780
781 BUG_ON(!regp);
782 update_cpu_ftr_reg(regp, val);
783 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
784 return 0;
785 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
786 regp->name, boot, cpu, val);
787 return 1;
788}
789
eab2f926
WD		 790static void relax_cpu_ftr_reg(u32 sys_id, int field)
791{
792 const struct arm64_ftr_bits *ftrp;
793 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
794
795 if (WARN_ON(!regp))
796 return;
797
798 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) {
799 if (ftrp->shift == field) {
800 regp->strict_mask &= ~arm64_ftr_mask(ftrp);
801 break;
802 }
803 }
804
805 /* Bogus field? */
806 WARN_ON(!ftrp->width);
807}
808
1efcfe79
WD		 809static int update_32bit_cpu_features(int cpu, struct cpuinfo_arm64 *info,
810 struct cpuinfo_arm64 *boot)
811{
812 int taint = 0;
813 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
814
815 /*
816 * If we don't have AArch32 at all then skip the checks entirely
817 * as the register values may be UNKNOWN and we're not going to be
818 * using them for anything.
819 */
820 if (!id_aa64pfr0_32bit_el0(pfr0))
821 return taint;
822
eab2f926
WD		 823 /*
824 * If we don't have AArch32 at EL1, then relax the strictness of
825 * EL1-dependent register fields to avoid spurious sanity check fails.
826 */
827 if (!id_aa64pfr0_32bit_el1(pfr0)) {
828 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT);
829 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT);
830 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT);
831 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT);
832 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT);
833 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT);
834 }
835
1efcfe79
WD		 836 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
837 info->reg_id_dfr0, boot->reg_id_dfr0);
838 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
839 info->reg_id_isar0, boot->reg_id_isar0);
840 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
841 info->reg_id_isar1, boot->reg_id_isar1);
842 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
843 info->reg_id_isar2, boot->reg_id_isar2);
844 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
845 info->reg_id_isar3, boot->reg_id_isar3);
846 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
847 info->reg_id_isar4, boot->reg_id_isar4);
848 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
849 info->reg_id_isar5, boot->reg_id_isar5);
850 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu,
851 info->reg_id_isar6, boot->reg_id_isar6);
852
853 /*
854 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
855 * ACTLR formats could differ across CPUs and therefore would have to
856 * be trapped for virtualization anyway.
857 */
858 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
859 info->reg_id_mmfr0, boot->reg_id_mmfr0);
860 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
861 info->reg_id_mmfr1, boot->reg_id_mmfr1);
862 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
863 info->reg_id_mmfr2, boot->reg_id_mmfr2);
864 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
865 info->reg_id_mmfr3, boot->reg_id_mmfr3);
866 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
867 info->reg_id_pfr0, boot->reg_id_pfr0);
868 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
869 info->reg_id_pfr1, boot->reg_id_pfr1);
16824085
AK		 870 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu,
871 info->reg_id_pfr2, boot->reg_id_pfr2);
1efcfe79
WD		 872 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
873 info->reg_mvfr0, boot->reg_mvfr0);
874 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
875 info->reg_mvfr1, boot->reg_mvfr1);
876 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
877 info->reg_mvfr2, boot->reg_mvfr2);
878
879 return taint;
880}
881
3086d391
SP		 882/*
883 * Update system wide CPU feature registers with the values from a
884 * non-boot CPU. Also performs SANITY checks to make sure that there
885 * aren't any insane variations from that of the boot CPU.
886 */
887void update_cpu_features(int cpu,
888 struct cpuinfo_arm64 *info,
889 struct cpuinfo_arm64 *boot)
890{
891 int taint = 0;
892
893 /*
894 * The kernel can handle differing I-cache policies, but otherwise
895 * caches should look identical. Userspace JITs will make use of
896 * *minLine.
897 */
898 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
899 info->reg_ctr, boot->reg_ctr);
900
901 /*
902 * Userspace may perform DC ZVA instructions. Mismatched block sizes
903 * could result in too much or too little memory being zeroed if a
904 * process is preempted and migrated between CPUs.
905 */
906 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
907 info->reg_dczid, boot->reg_dczid);
908
909 /* If different, timekeeping will be broken (especially with KVM) */
910 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
911 info->reg_cntfrq, boot->reg_cntfrq);
912
913 /*
914 * The kernel uses self-hosted debug features and expects CPUs to
915 * support identical debug features. We presently need CTX_CMPs, WRPs,
916 * and BRPs to be identical.
917 * ID_AA64DFR1 is currently RES0.
918 */
919 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
920 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
921 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
922 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
923 /*
924 * Even in big.LITTLE, processors should be identical instruction-set
925 * wise.
926 */
927 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
928 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
929 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
930 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
931
932 /*
933 * Differing PARange support is fine as long as all peripherals and
934 * memory are mapped within the minimum PARange of all CPUs.
935 * Linux should not care about secure memory.
936 */
937 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
938 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
939 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
940 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
406e3087
JM		 941 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
942 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
3086d391 943
3086d391
SP		 944 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
945 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
946 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
947 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
948
2e0f2478
DM		 949 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
950 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
951
2e0f2478
DM		 952 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
953 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
954 info->reg_zcr, boot->reg_zcr);
955
956 /* Probe vector lengths, unless we already gave up on SVE */
957 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
b51c6ac2 958 !system_capabilities_finalized())
2e0f2478
DM		 959 sve_update_vq_map();
960 }
961
1efcfe79
WD		 962 /*
963 * This relies on a sanitised view of the AArch64 ID registers
964 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last.
965 */
966 taint |= update_32bit_cpu_features(cpu, info, boot);
967
3086d391
SP		 968 /*
969 * Mismatched CPU features are a recipe for disaster. Don't even
970 * pretend to support them.
971 */
8dd0ee65
WD		 972 if (taint) {
973 pr_warn_once("Unsupported CPU feature variation detected.\n");
974 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
975 }
cdcf817b
SP		 976}
977
46823dd1 978u64 read_sanitised_ftr_reg(u32 id)
b3f15378
SP		 979{
980 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
981
982 /* We shouldn't get a request for an unsupported register */
983 BUG_ON(!regp);
984 return regp->sys_val;
985}
359b7064 986
965861d6
MR		 987#define read_sysreg_case(r) \
988 case r: return read_sysreg_s(r)
989
92406f0c 990/*
46823dd1 991 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
92406f0c
SP		 992 * Read the system register on the current CPU
993 */
46823dd1 994static u64 __read_sysreg_by_encoding(u32 sys_id)
92406f0c
SP		 995{
996 switch (sys_id) {
965861d6
MR		 997 read_sysreg_case(SYS_ID_PFR0_EL1);
998 read_sysreg_case(SYS_ID_PFR1_EL1);
16824085 999 read_sysreg_case(SYS_ID_PFR2_EL1);
965861d6
MR		 1000 read_sysreg_case(SYS_ID_DFR0_EL1);
1001 read_sysreg_case(SYS_ID_MMFR0_EL1);
1002 read_sysreg_case(SYS_ID_MMFR1_EL1);
1003 read_sysreg_case(SYS_ID_MMFR2_EL1);
1004 read_sysreg_case(SYS_ID_MMFR3_EL1);
1005 read_sysreg_case(SYS_ID_ISAR0_EL1);
1006 read_sysreg_case(SYS_ID_ISAR1_EL1);
1007 read_sysreg_case(SYS_ID_ISAR2_EL1);
1008 read_sysreg_case(SYS_ID_ISAR3_EL1);
1009 read_sysreg_case(SYS_ID_ISAR4_EL1);
1010 read_sysreg_case(SYS_ID_ISAR5_EL1);
8e3747be 1011 read_sysreg_case(SYS_ID_ISAR6_EL1);
965861d6
MR		 1012 read_sysreg_case(SYS_MVFR0_EL1);
1013 read_sysreg_case(SYS_MVFR1_EL1);
1014 read_sysreg_case(SYS_MVFR2_EL1);
1015
1016 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
1017 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
78ed70bf 1018 read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
965861d6
MR		 1019 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
1020 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
1021 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
1022 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
1023 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
1024 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
1025 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
1026
1027 read_sysreg_case(SYS_CNTFRQ_EL0);
1028 read_sysreg_case(SYS_CTR_EL0);
1029 read_sysreg_case(SYS_DCZID_EL0);
1030
92406f0c
SP		 1031 default:
1032 BUG();
1033 return 0;
1034 }
1035}
1036
963fcd40
MZ		 1037#include <linux/irqchip/arm-gic-v3.h>
1038
18ffa046
JM		 1039static bool
1040feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
1041{
28c5dcb2 1042 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
18ffa046
JM		 1043
1044 return val >= entry->min_field_value;
1045}
1046
da8d02d1 1047static bool
92406f0c 1048has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
da8d02d1
SP		 1049{
1050 u64 val;
94a9e04a 1051
92406f0c
SP		 1052 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1053 if (scope == SCOPE_SYSTEM)
46823dd1 1054 val = read_sanitised_ftr_reg(entry->sys_reg);
92406f0c 1055 else
46823dd1 1056 val = __read_sysreg_by_encoding(entry->sys_reg);
92406f0c 1057
da8d02d1
SP		 1058 return feature_matches(val, entry);
1059}
338d4f49 1060
92406f0c 1061static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
963fcd40
MZ		 1062{
1063 bool has_sre;
1064
92406f0c 1065 if (!has_cpuid_feature(entry, scope))
963fcd40
MZ		 1066 return false;
1067
1068 has_sre = gic_enable_sre();
1069 if (!has_sre)
1070 pr_warn_once("%s present but disabled by higher exception level\n",
1071 entry->desc);
1072
1073 return has_sre;
1074}
1075
92406f0c 1076static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
d5370f75
WD		 1077{
1078 u32 midr = read_cpuid_id();
d5370f75
WD		 1079
1080 /* Cavium ThunderX pass 1.x and 2.x */
b99286b0 1081 return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
fa5ce3d1
RR		 1082 MIDR_CPU_VAR_REV(0, 0),
1083 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
d5370f75
WD		 1084}
1085
82e0191a
SP		 1086static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
1087{
46823dd1 1088 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
82e0191a
SP		 1089
1090 return cpuid_feature_extract_signed_field(pfr0,
1091 ID_AA64PFR0_FP_SHIFT) < 0;
1092}
1093
6ae4b6e0 1094static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
8ab66cbe 1095 int scope)
6ae4b6e0 1096{
8ab66cbe
SP		 1097 u64 ctr;
1098
1099 if (scope == SCOPE_SYSTEM)
1100 ctr = arm64_ftr_reg_ctrel0.sys_val;
1101 else
1602df02 1102 ctr = read_cpuid_effective_cachetype();
8ab66cbe
SP		 1103
1104 return ctr & BIT(CTR_IDC_SHIFT);
6ae4b6e0
SD		 1105}
1106
1602df02
SP		 1107static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
1108{
1109 /*
1110 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
1111 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
1112 * to the CTR_EL0 on this CPU and emulate it with the real/safe
1113 * value.
1114 */
1115 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
1116 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
1117}
1118
6ae4b6e0 1119static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
8ab66cbe 1120 int scope)
6ae4b6e0 1121{
8ab66cbe
SP		 1122 u64 ctr;
1123
1124 if (scope == SCOPE_SYSTEM)
1125 ctr = arm64_ftr_reg_ctrel0.sys_val;
1126 else
1127 ctr = read_cpuid_cachetype();
1128
1129 return ctr & BIT(CTR_DIC_SHIFT);
6ae4b6e0
SD		 1130}
1131
5ffdfaed
VM		 1132static bool __maybe_unused
1133has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
1134{
1135 /*
1136 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
1137 * may share TLB entries with a CPU stuck in the crashed
1138 * kernel.
1139 */
1140 if (is_kdump_kernel())
1141 return false;
1142
1143 return has_cpuid_feature(entry, scope);
1144}
1145
09e3c22a
MB		 1146/*
1147 * This check is triggered during the early boot before the cpufeature
1148 * is initialised. Checking the status on the local CPU allows the boot
1149 * CPU to detect the need for non-global mappings and thus avoiding a
1150 * pagetable re-write after all the CPUs are booted. This check will be
1151 * anyway run on individual CPUs, allowing us to get the consistent
1152 * state once the SMP CPUs are up and thus make the switch to non-global
1153 * mappings if required.
1154 */
1155bool kaslr_requires_kpti(void)
1156{
09e3c22a
MB		 1157 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE))
1158 return false;
1159
1160 /*
1161 * E0PD does a similar job to KPTI so can be used instead
1162 * where available.
1163 */
1164 if (IS_ENABLED(CONFIG_ARM64_E0PD)) {
a569f5f3
WD		 1165 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1);
1166 if (cpuid_feature_extract_unsigned_field(mmfr2,
1167 ID_AA64MMFR2_E0PD_SHIFT))
09e3c22a
MB		 1168 return false;
1169 }
1170
1171 /*
1172 * Systems affected by Cavium erratum 24756 are incompatible
1173 * with KPTI.
1174 */
ebac96ed 1175 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) {
09e3c22a
MB		 1176 extern const struct midr_range cavium_erratum_27456_cpus[];
1177
ebac96ed
WD		 1178 if (is_midr_in_range_list(read_cpuid_id(),
1179 cavium_erratum_27456_cpus))
1180 return false;
09e3c22a 1181 }
09e3c22a
MB		 1182
1183 return kaslr_offset() > 0;
1184}
1185
1b3ccf4b 1186static bool __meltdown_safe = true;
ea1e3de8
WD		 1187static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
1188
1189static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
d3aec8a2 1190 int scope)
ea1e3de8 1191{
be5b2998
SP		 1192 /* List of CPUs that are not vulnerable and don't need KPTI */
1193 static const struct midr_range kpti_safe_list[] = {
1194 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
1195 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
31d868c4 1196 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
2a355ec2
WD		 1197 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
1198 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
1199 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1200 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
1201 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
1202 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
0ecc471a 1203 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
918e1946 1204 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
71c751f2 1205 { /* sentinel */ }
be5b2998 1206 };
a111b7c0 1207 char const *str = "kpti command line option";
1b3ccf4b
JL		 1208 bool meltdown_safe;
1209
1210 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
1211
1212 /* Defer to CPU feature registers */
1213 if (has_cpuid_feature(entry, scope))
1214 meltdown_safe = true;
1215
1216 if (!meltdown_safe)
1217 __meltdown_safe = false;
179a56f6 1218
6dc52b15
MZ		 1219 /*
1220 * For reasons that aren't entirely clear, enabling KPTI on Cavium
1221 * ThunderX leads to apparent I-cache corruption of kernel text, which
1222 * ends as well as you might imagine. Don't even try.
1223 */
1224 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1225 str = "ARM64_WORKAROUND_CAVIUM_27456";
1226 __kpti_forced = -1;
1227 }
1228
1b3ccf4b 1229 /* Useful for KASLR robustness */
c2d92353 1230 if (kaslr_requires_kpti()) {
1b3ccf4b
JL		 1231 if (!__kpti_forced) {
1232 str = "KASLR";
1233 __kpti_forced = 1;
1234 }
1235 }
1236
a111b7c0
JP		 1237 if (cpu_mitigations_off() && !__kpti_forced) {
1238 str = "mitigations=off";
1239 __kpti_forced = -1;
1240 }
1241
1b3ccf4b
JL		 1242 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1243 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1244 return false;
1245 }
1246
6dc52b15 1247 /* Forced? */
ea1e3de8 1248 if (__kpti_forced) {
6dc52b15
MZ		 1249 pr_info_once("kernel page table isolation forced %s by %s\n",
1250 __kpti_forced > 0 ? "ON" : "OFF", str);
ea1e3de8
WD		 1251 return __kpti_forced > 0;
1252 }
1253
1b3ccf4b 1254 return !meltdown_safe;
ea1e3de8
WD		 1255}
1256
1b3ccf4b 1257#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
c0cda3b8
DM		 1258static void
1259kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
f992b4df
WD		 1260{
1261 typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1262 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1263 kpti_remap_fn *remap_fn;
1264
f992b4df
WD		 1265 int cpu = smp_processor_id();
1266
b89d82ef
WD		 1267 /*
1268 * We don't need to rewrite the page-tables if either we've done
1269 * it already or we have KASLR enabled and therefore have not
1270 * created any global mappings at all.
1271 */
09e3c22a 1272 if (arm64_use_ng_mappings)
c0cda3b8 1273 return;
f992b4df
WD		 1274
1275 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
1276
1277 cpu_install_idmap();
1278 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1279 cpu_uninstall_idmap();
1280
1281 if (!cpu)
09e3c22a 1282 arm64_use_ng_mappings = true;
f992b4df 1283
c0cda3b8 1284 return;
f992b4df 1285}
1b3ccf4b
JL		 1286#else
1287static void
1288kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1289{
1290}
1291#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
f992b4df 1292
ea1e3de8
WD		 1293static int __init parse_kpti(char *str)
1294{
1295 bool enabled;
1296 int ret = strtobool(str, &enabled);
1297
1298 if (ret)
1299 return ret;
1300
1301 __kpti_forced = enabled ? 1 : -1;
1302 return 0;
1303}
b5b7dd64 1304early_param("kpti", parse_kpti);
ea1e3de8 1305
05abb595
SP		 1306#ifdef CONFIG_ARM64_HW_AFDBM
1307static inline void __cpu_enable_hw_dbm(void)
1308{
1309 u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1310
1311 write_sysreg(tcr, tcr_el1);
1312 isb();
1313}
1314
ece1397c
SP		 1315static bool cpu_has_broken_dbm(void)
1316{
1317 /* List of CPUs which have broken DBM support. */
1318 static const struct midr_range cpus[] = {
1319#ifdef CONFIG_ARM64_ERRATUM_1024718
1320 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0
1321#endif
1322 {},
1323 };
1324
1325 return is_midr_in_range_list(read_cpuid_id(), cpus);
1326}
1327
05abb595
SP		 1328static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1329{
ece1397c
SP		 1330 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1331 !cpu_has_broken_dbm();
05abb595
SP		 1332}
1333
1334static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1335{
1336 if (cpu_can_use_dbm(cap))
1337 __cpu_enable_hw_dbm();
1338}
1339
1340static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1341 int __unused)
1342{
1343 static bool detected = false;
1344 /*
1345 * DBM is a non-conflicting feature. i.e, the kernel can safely
1346 * run a mix of CPUs with and without the feature. So, we
1347 * unconditionally enable the capability to allow any late CPU
1348 * to use the feature. We only enable the control bits on the
1349 * CPU, if it actually supports.
1350 *
1351 * We have to make sure we print the "feature" detection only
1352 * when at least one CPU actually uses it. So check if this CPU
1353 * can actually use it and print the message exactly once.
1354 *
1355 * This is safe as all CPUs (including secondary CPUs - due to the
1356 * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1357 * goes through the "matches" check exactly once. Also if a CPU
1358 * matches the criteria, it is guaranteed that the CPU will turn
1359 * the DBM on, as the capability is unconditionally enabled.
1360 */
1361 if (!detected && cpu_can_use_dbm(cap)) {
1362 detected = true;
1363 pr_info("detected: Hardware dirty bit management\n");
1364 }
1365
1366 return true;
1367}
1368
1369#endif
1370
2c9d45b4
IV		 1371#ifdef CONFIG_ARM64_AMU_EXTN
1372
1373/*
1374 * The "amu_cpus" cpumask only signals that the CPU implementation for the
1375 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide
1376 * information regarding all the events that it supports. When a CPU bit is
1377 * set in the cpumask, the user of this feature can only rely on the presence
1378 * of the 4 fixed counters for that CPU. But this does not guarantee that the
1379 * counters are enabled or access to these counters is enabled by code
1380 * executed at higher exception levels (firmware).
1381 */
1382static struct cpumask amu_cpus __read_mostly;
1383
1384bool cpu_has_amu_feat(int cpu)
1385{
1386 return cpumask_test_cpu(cpu, &amu_cpus);
1387}
1388
cd0ed03a
IV		 1389/* Initialize the use of AMU counters for frequency invariance */
1390extern void init_cpu_freq_invariance_counters(void);
1391
2c9d45b4
IV		 1392static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)
1393{
1394 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) {
1395 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n",
1396 smp_processor_id());
1397 cpumask_set_cpu(smp_processor_id(), &amu_cpus);
cd0ed03a 1398 init_cpu_freq_invariance_counters();
2c9d45b4
IV		 1399 }
1400}
1401
1402static bool has_amu(const struct arm64_cpu_capabilities *cap,
1403 int __unused)
1404{
1405 /*
1406 * The AMU extension is a non-conflicting feature: the kernel can
1407 * safely run a mix of CPUs with and without support for the
1408 * activity monitors extension. Therefore, unconditionally enable
1409 * the capability to allow any late CPU to use the feature.
1410 *
1411 * With this feature unconditionally enabled, the cpu_enable
1412 * function will be called for all CPUs that match the criteria,
1413 * including secondary and hotplugged, marking this feature as
1414 * present on that respective CPU. The enable function will also
1415 * print a detection message.
1416 */
1417
1418 return true;
1419}
1420#endif
1421
12eb3691
WD		 1422#ifdef CONFIG_ARM64_VHE
1423static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1424{
1425 return is_kernel_in_hyp_mode();
1426}
1427
c0cda3b8 1428static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
6d99b689
JM		 1429{
1430 /*
1431 * Copy register values that aren't redirected by hardware.
1432 *
1433 * Before code patching, we only set tpidr_el1, all CPUs need to copy
1434 * this value to tpidr_el2 before we patch the code. Once we've done
1435 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1436 * do anything here.
1437 */
e9ab7a2e 1438 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
6d99b689 1439 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
6d99b689 1440}
12eb3691 1441#endif
6d99b689 1442
e48d53a9
MZ		 1443static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1444{
1445 u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1446
1447 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1448 WARN_ON(val & (7 << 27 | 7 << 21));
1449}
1450
8f04e8e6
WD		 1451#ifdef CONFIG_ARM64_SSBD
1452static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
1453{
1454 if (user_mode(regs))
1455 return 1;
1456
74e24828 1457 if (instr & BIT(PSTATE_Imm_shift))
8f04e8e6
WD		 1458 regs->pstate |= PSR_SSBS_BIT;
1459 else
1460 regs->pstate &= ~PSR_SSBS_BIT;
1461
1462 arm64_skip_faulting_instruction(regs, 4);
1463 return 0;
1464}
1465
1466static struct undef_hook ssbs_emulation_hook = {
74e24828
SP		 1467 .instr_mask = ~(1U << PSTATE_Imm_shift),
1468 .instr_val = 0xd500401f | PSTATE_SSBS,
8f04e8e6
WD		 1469 .fn = ssbs_emulation_handler,
1470};
1471
1472static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
1473{
1474 static bool undef_hook_registered = false;
27e6e7d6 1475 static DEFINE_RAW_SPINLOCK(hook_lock);
8f04e8e6 1476
27e6e7d6 1477 raw_spin_lock(&hook_lock);
8f04e8e6
WD		 1478 if (!undef_hook_registered) {
1479 register_undef_hook(&ssbs_emulation_hook);
1480 undef_hook_registered = true;
1481 }
27e6e7d6 1482 raw_spin_unlock(&hook_lock);
8f04e8e6
WD		 1483
1484 if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
1485 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
1486 arm64_set_ssbd_mitigation(false);
1487 } else {
1488 arm64_set_ssbd_mitigation(true);
1489 }
1490}
1491#endif /* CONFIG_ARM64_SSBD */
1492
b8925ee2
WD		 1493#ifdef CONFIG_ARM64_PAN
1494static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1495{
1496 /*
1497 * We modify PSTATE. This won't work from irq context as the PSTATE
1498 * is discarded once we return from the exception.
1499 */
1500 WARN_ON_ONCE(in_interrupt());
1501
1502 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1503 asm(SET_PSTATE_PAN(1));
1504}
1505#endif /* CONFIG_ARM64_PAN */
1506
1507#ifdef CONFIG_ARM64_RAS_EXTN
1508static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1509{
1510 /* Firmware may have left a deferred SError in this register. */
1511 write_sysreg_s(0, SYS_DISR_EL1);
1512}
1513#endif /* CONFIG_ARM64_RAS_EXTN */
1514
6984eb47 1515#ifdef CONFIG_ARM64_PTR_AUTH
cfef06bd
KM		 1516static bool has_address_auth(const struct arm64_cpu_capabilities *entry,
1517 int __unused)
1518{
1519 return __system_matches_cap(ARM64_HAS_ADDRESS_AUTH_ARCH) ||
1520 __system_matches_cap(ARM64_HAS_ADDRESS_AUTH_IMP_DEF);
1521}
1522
1523static bool has_generic_auth(const struct arm64_cpu_capabilities *entry,
1524 int __unused)
75031975 1525{
cfef06bd
KM		 1526 return __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH) ||
1527 __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF);
75031975 1528}
6984eb47
MR		 1529#endif /* CONFIG_ARM64_PTR_AUTH */
1530
3e6c69a0
MB		 1531#ifdef CONFIG_ARM64_E0PD
1532static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)
1533{
1534 if (this_cpu_has_cap(ARM64_HAS_E0PD))
1535 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1);
1536}
1537#endif /* CONFIG_ARM64_E0PD */
1538
b90d2b22 1539#ifdef CONFIG_ARM64_PSEUDO_NMI
bc3c03cc
JT		 1540static bool enable_pseudo_nmi;
1541
1542static int __init early_enable_pseudo_nmi(char *p)
1543{
1544 return strtobool(p, &enable_pseudo_nmi);
1545}
1546early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1547
b90d2b22
JT		 1548static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1549 int scope)
1550{
bc3c03cc 1551 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
b90d2b22
JT		 1552}
1553#endif
1554
8c176e16
ADK		 1555/* Internal helper functions to match cpu capability type */
1556static bool
1557cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
1558{
1559 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU);
1560}
1561
1562static bool
1563cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap)
1564{
1565 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU);
1566}
1567
deeaac51
KM		 1568static bool
1569cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap)
1570{
1571 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT);
1572}
1573
359b7064 1574static const struct arm64_cpu_capabilities arm64_features[] = {
94a9e04a
MZ		 1575 {
1576 .desc = "GIC system register CPU interface",
1577 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
c9bfdf73 1578 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
963fcd40 1579 .matches = has_useable_gicv3_cpuif,
da8d02d1
SP		 1580 .sys_reg = SYS_ID_AA64PFR0_EL1,
1581 .field_pos = ID_AA64PFR0_GIC_SHIFT,
ff96f7bc 1582 .sign = FTR_UNSIGNED,
18ffa046 1583 .min_field_value = 1,
94a9e04a 1584 },
338d4f49
JM		 1585#ifdef CONFIG_ARM64_PAN
1586 {
1587 .desc = "Privileged Access Never",
1588 .capability = ARM64_HAS_PAN,
5b4747c5 1589 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
da8d02d1
SP		 1590 .matches = has_cpuid_feature,
1591 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1592 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
ff96f7bc 1593 .sign = FTR_UNSIGNED,
338d4f49 1594 .min_field_value = 1,
c0cda3b8 1595 .cpu_enable = cpu_enable_pan,
338d4f49
JM		 1596 },
1597#endif /* CONFIG_ARM64_PAN */
395af861 1598#ifdef CONFIG_ARM64_LSE_ATOMICS
2e94da13
WD		 1599 {
1600 .desc = "LSE atomic instructions",
1601 .capability = ARM64_HAS_LSE_ATOMICS,
5b4747c5 1602 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
da8d02d1
SP		 1603 .matches = has_cpuid_feature,
1604 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1605 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
ff96f7bc 1606 .sign = FTR_UNSIGNED,
2e94da13
WD		 1607 .min_field_value = 2,
1608 },
395af861 1609#endif /* CONFIG_ARM64_LSE_ATOMICS */
d5370f75
WD		 1610 {
1611 .desc = "Software prefetching using PRFM",
1612 .capability = ARM64_HAS_NO_HW_PREFETCH,
5c137714 1613 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
d5370f75
WD		 1614 .matches = has_no_hw_prefetch,
1615 },
57f4959b
JM		 1616#ifdef CONFIG_ARM64_UAO
1617 {
1618 .desc = "User Access Override",
1619 .capability = ARM64_HAS_UAO,
5b4747c5 1620 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
57f4959b
JM		 1621 .matches = has_cpuid_feature,
1622 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1623 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1624 .min_field_value = 1,
c8b06e3f
JM		 1625 /*
1626 * We rely on stop_machine() calling uao_thread_switch() to set
1627 * UAO immediately after patching.
1628 */
57f4959b
JM		 1629 },
1630#endif /* CONFIG_ARM64_UAO */
70544196
JM		 1631#ifdef CONFIG_ARM64_PAN
1632 {
1633 .capability = ARM64_ALT_PAN_NOT_UAO,
5b4747c5 1634 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
70544196
JM		 1635 .matches = cpufeature_pan_not_uao,
1636 },
1637#endif /* CONFIG_ARM64_PAN */
830dcc9f 1638#ifdef CONFIG_ARM64_VHE
d88701be
MZ		 1639 {
1640 .desc = "Virtualization Host Extensions",
1641 .capability = ARM64_HAS_VIRT_HOST_EXTN,
830dcc9f 1642 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
d88701be 1643 .matches = runs_at_el2,
c0cda3b8 1644 .cpu_enable = cpu_copy_el2regs,
d88701be 1645 },
830dcc9f 1646#endif /* CONFIG_ARM64_VHE */
042446a3
SP		 1647 {
1648 .desc = "32-bit EL0 Support",
1649 .capability = ARM64_HAS_32BIT_EL0,
5b4747c5 1650 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
042446a3
SP		 1651 .matches = has_cpuid_feature,
1652 .sys_reg = SYS_ID_AA64PFR0_EL1,
1653 .sign = FTR_UNSIGNED,
1654 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1655 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1656 },
540f76d1
WD		 1657#ifdef CONFIG_KVM
1658 {
1659 .desc = "32-bit EL1 Support",
1660 .capability = ARM64_HAS_32BIT_EL1,
1661 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1662 .matches = has_cpuid_feature,
1663 .sys_reg = SYS_ID_AA64PFR0_EL1,
1664 .sign = FTR_UNSIGNED,
1665 .field_pos = ID_AA64PFR0_EL1_SHIFT,
1666 .min_field_value = ID_AA64PFR0_EL1_32BIT_64BIT,
1667 },
1668#endif
ea1e3de8 1669 {
179a56f6 1670 .desc = "Kernel page table isolation (KPTI)",
ea1e3de8 1671 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
d3aec8a2
SP		 1672 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1673 /*
1674 * The ID feature fields below are used to indicate that
1675 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1676 * more details.
1677 */
1678 .sys_reg = SYS_ID_AA64PFR0_EL1,
1679 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1680 .min_field_value = 1,
ea1e3de8 1681 .matches = unmap_kernel_at_el0,
c0cda3b8 1682 .cpu_enable = kpti_install_ng_mappings,
ea1e3de8 1683 },
82e0191a
SP		 1684 {
1685 /* FP/SIMD is not implemented */
1686 .capability = ARM64_HAS_NO_FPSIMD,
449443c0 1687 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
82e0191a
SP		 1688 .min_field_value = 0,
1689 .matches = has_no_fpsimd,
1690 },
d50e071f
RM		 1691#ifdef CONFIG_ARM64_PMEM
1692 {
1693 .desc = "Data cache clean to Point of Persistence",
1694 .capability = ARM64_HAS_DCPOP,
5b4747c5 1695 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
d50e071f
RM		 1696 .matches = has_cpuid_feature,
1697 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1698 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1699 .min_field_value = 1,
1700 },
b9585f53
AM		 1701 {
1702 .desc = "Data cache clean to Point of Deep Persistence",
1703 .capability = ARM64_HAS_DCPODP,
1704 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1705 .matches = has_cpuid_feature,
1706 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1707 .sign = FTR_UNSIGNED,
1708 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1709 .min_field_value = 2,
1710 },
d50e071f 1711#endif
43994d82
DM		 1712#ifdef CONFIG_ARM64_SVE
1713 {
1714 .desc = "Scalable Vector Extension",
5b4747c5 1715 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
43994d82 1716 .capability = ARM64_SVE,
43994d82
DM		 1717 .sys_reg = SYS_ID_AA64PFR0_EL1,
1718 .sign = FTR_UNSIGNED,
1719 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1720 .min_field_value = ID_AA64PFR0_SVE,
1721 .matches = has_cpuid_feature,
c0cda3b8 1722 .cpu_enable = sve_kernel_enable,
43994d82
DM		 1723 },
1724#endif /* CONFIG_ARM64_SVE */
64c02720
XX		 1725#ifdef CONFIG_ARM64_RAS_EXTN
1726 {
1727 .desc = "RAS Extension Support",
1728 .capability = ARM64_HAS_RAS_EXTN,
5b4747c5 1729 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
64c02720
XX		 1730 .matches = has_cpuid_feature,
1731 .sys_reg = SYS_ID_AA64PFR0_EL1,
1732 .sign = FTR_UNSIGNED,
1733 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1734 .min_field_value = ID_AA64PFR0_RAS_V1,
c0cda3b8 1735 .cpu_enable = cpu_clear_disr,
64c02720
XX		 1736 },
1737#endif /* CONFIG_ARM64_RAS_EXTN */
2c9d45b4
IV		 1738#ifdef CONFIG_ARM64_AMU_EXTN
1739 {
1740 /*
1741 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y.
1742 * Therefore, don't provide .desc as we don't want the detection
1743 * message to be shown until at least one CPU is detected to
1744 * support the feature.
1745 */
1746 .capability = ARM64_HAS_AMU_EXTN,
1747 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1748 .matches = has_amu,
1749 .sys_reg = SYS_ID_AA64PFR0_EL1,
1750 .sign = FTR_UNSIGNED,
1751 .field_pos = ID_AA64PFR0_AMU_SHIFT,
1752 .min_field_value = ID_AA64PFR0_AMU,
1753 .cpu_enable = cpu_amu_enable,
1754 },
1755#endif /* CONFIG_ARM64_AMU_EXTN */
6ae4b6e0
SD		 1756 {
1757 .desc = "Data cache clean to the PoU not required for I/D coherence",
1758 .capability = ARM64_HAS_CACHE_IDC,
5b4747c5 1759 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
6ae4b6e0 1760 .matches = has_cache_idc,
1602df02 1761 .cpu_enable = cpu_emulate_effective_ctr,
6ae4b6e0
SD		 1762 },
1763 {
1764 .desc = "Instruction cache invalidation not required for I/D coherence",
1765 .capability = ARM64_HAS_CACHE_DIC,
5b4747c5 1766 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
6ae4b6e0
SD		 1767 .matches = has_cache_dic,
1768 },
e48d53a9
MZ		 1769 {
1770 .desc = "Stage-2 Force Write-Back",
1771 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1772 .capability = ARM64_HAS_STAGE2_FWB,
1773 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1774 .sign = FTR_UNSIGNED,
1775 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
1776 .min_field_value = 1,
1777 .matches = has_cpuid_feature,
1778 .cpu_enable = cpu_has_fwb,
1779 },
05abb595
SP		 1780#ifdef CONFIG_ARM64_HW_AFDBM
1781 {
1782 /*
1783 * Since we turn this on always, we don't want the user to
1784 * think that the feature is available when it may not be.
1785 * So hide the description.
1786 *
1787 * .desc = "Hardware pagetable Dirty Bit Management",
1788 *
1789 */
1790 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1791 .capability = ARM64_HW_DBM,
1792 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1793 .sign = FTR_UNSIGNED,
1794 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
1795 .min_field_value = 2,
1796 .matches = has_hw_dbm,
1797 .cpu_enable = cpu_enable_hw_dbm,
1798 },
1799#endif
86d0dd34
AB		 1800 {
1801 .desc = "CRC32 instructions",
1802 .capability = ARM64_HAS_CRC32,
1803 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1804 .matches = has_cpuid_feature,
1805 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1806 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
1807 .min_field_value = 1,
1808 },
4f9f4964 1809#ifdef CONFIG_ARM64_SSBD
d71be2b6
WD		 1810 {
1811 .desc = "Speculative Store Bypassing Safe (SSBS)",
1812 .capability = ARM64_SSBS,
1813 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1814 .matches = has_cpuid_feature,
1815 .sys_reg = SYS_ID_AA64PFR1_EL1,
1816 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
1817 .sign = FTR_UNSIGNED,
1818 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
8f04e8e6 1819 .cpu_enable = cpu_enable_ssbs,
d71be2b6 1820 },
5ffdfaed
VM		 1821#endif
1822#ifdef CONFIG_ARM64_CNP
1823 {
1824 .desc = "Common not Private translations",
1825 .capability = ARM64_HAS_CNP,
1826 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1827 .matches = has_useable_cnp,
1828 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1829 .sign = FTR_UNSIGNED,
1830 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
1831 .min_field_value = 1,
1832 .cpu_enable = cpu_enable_cnp,
1833 },
8f04e8e6 1834#endif
bd4fb6d2
WD		 1835 {
1836 .desc = "Speculation barrier (SB)",
1837 .capability = ARM64_HAS_SB,
1838 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1839 .matches = has_cpuid_feature,
1840 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1841 .field_pos = ID_AA64ISAR1_SB_SHIFT,
1842 .sign = FTR_UNSIGNED,
1843 .min_field_value = 1,
1844 },
6984eb47
MR		 1845#ifdef CONFIG_ARM64_PTR_AUTH
1846 {
1847 .desc = "Address authentication (architected algorithm)",
1848 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
6982934e 1849 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
6984eb47
MR		 1850 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1851 .sign = FTR_UNSIGNED,
1852 .field_pos = ID_AA64ISAR1_APA_SHIFT,
1853 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
1854 .matches = has_cpuid_feature,
1855 },
1856 {
1857 .desc = "Address authentication (IMP DEF algorithm)",
1858 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
6982934e 1859 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
6984eb47
MR		 1860 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1861 .sign = FTR_UNSIGNED,
1862 .field_pos = ID_AA64ISAR1_API_SHIFT,
1863 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
1864 .matches = has_cpuid_feature,
cfef06bd
KM		 1865 },
1866 {
1867 .capability = ARM64_HAS_ADDRESS_AUTH,
6982934e 1868 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
cfef06bd 1869 .matches = has_address_auth,
6984eb47
MR		 1870 },
1871 {
1872 .desc = "Generic authentication (architected algorithm)",
1873 .capability = ARM64_HAS_GENERIC_AUTH_ARCH,
1874 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1875 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1876 .sign = FTR_UNSIGNED,
1877 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
1878 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
1879 .matches = has_cpuid_feature,
1880 },
1881 {
1882 .desc = "Generic authentication (IMP DEF algorithm)",
1883 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
1884 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1885 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1886 .sign = FTR_UNSIGNED,
1887 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
1888 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
1889 .matches = has_cpuid_feature,
1890 },
cfef06bd
KM		 1891 {
1892 .capability = ARM64_HAS_GENERIC_AUTH,
1893 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1894 .matches = has_generic_auth,
1895 },
6984eb47 1896#endif /* CONFIG_ARM64_PTR_AUTH */
b90d2b22
JT		 1897#ifdef CONFIG_ARM64_PSEUDO_NMI
1898 {
1899 /*
1900 * Depends on having GICv3
1901 */
1902 .desc = "IRQ priority masking",
1903 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
1904 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1905 .matches = can_use_gic_priorities,
1906 .sys_reg = SYS_ID_AA64PFR0_EL1,
1907 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1908 .sign = FTR_UNSIGNED,
1909 .min_field_value = 1,
1910 },
3e6c69a0
MB		 1911#endif
1912#ifdef CONFIG_ARM64_E0PD
1913 {
1914 .desc = "E0PD",
1915 .capability = ARM64_HAS_E0PD,
1916 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1917 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1918 .sign = FTR_UNSIGNED,
1919 .field_pos = ID_AA64MMFR2_E0PD_SHIFT,
1920 .matches = has_cpuid_feature,
1921 .min_field_value = 1,
1922 .cpu_enable = cpu_enable_e0pd,
1923 },
bc206065 1924#endif
1a50ec0b
RH		 1925#ifdef CONFIG_ARCH_RANDOM
1926 {
1927 .desc = "Random Number Generator",
1928 .capability = ARM64_HAS_RNG,
1929 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1930 .matches = has_cpuid_feature,
1931 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1932 .field_pos = ID_AA64ISAR0_RNDR_SHIFT,
1933 .sign = FTR_UNSIGNED,
1934 .min_field_value = 1,
1935 },
b90d2b22 1936#endif
359b7064
MZ		 1937 {},
1938};
1939
1e013d06
WD		 1940#define HWCAP_CPUID_MATCH(reg, field, s, min_value) \
1941 .matches = has_cpuid_feature, \
1942 .sys_reg = reg, \
1943 .field_pos = field, \
1944 .sign = s, \
1945 .min_field_value = min_value,
1946
1947#define __HWCAP_CAP(name, cap_type, cap) \
1948 .desc = name, \
1949 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
1950 .hwcap_type = cap_type, \
1951 .hwcap = cap, \
1952
1953#define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \
1954 { \
1955 __HWCAP_CAP(#cap, cap_type, cap) \
1956 HWCAP_CPUID_MATCH(reg, field, s, min_value) \
37b01d53
SP		 1957 }
1958
1e013d06
WD		 1959#define HWCAP_MULTI_CAP(list, cap_type, cap) \
1960 { \
1961 __HWCAP_CAP(#cap, cap_type, cap) \
1962 .matches = cpucap_multi_entry_cap_matches, \
1963 .match_list = list, \
1964 }
1965
7559950a
SP		 1966#define HWCAP_CAP_MATCH(match, cap_type, cap) \
1967 { \
1968 __HWCAP_CAP(#cap, cap_type, cap) \
1969 .matches = match, \
1970 }
1971
1e013d06
WD		 1972#ifdef CONFIG_ARM64_PTR_AUTH
1973static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
1974 {
1975 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
1976 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
1977 },
1978 {
1979 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
1980 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
1981 },
1982 {},
1983};
1984
1985static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
1986 {
1987 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
1988 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
1989 },
1990 {
1991 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
1992 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
1993 },
1994 {},
1995};
1996#endif
1997
f3efb675 1998static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
aaba098f
AM		 1999 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
2000 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
2001 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
2002 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
2003 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
2004 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
2005 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
2006 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
2007 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
2008 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
2009 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
2010 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
2011 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
2012 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
12019374 2013 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
1a50ec0b 2014 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG),
aaba098f
AM		 2015 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
2016 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
2017 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
2018 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
2019 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
2020 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
671db581 2021 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
aaba098f
AM		 2022 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
2023 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
2024 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
2025 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
ca9503fc 2026 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
aaba098f 2027 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
d4209d8b
SP		 2028 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16),
2029 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH),
2030 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM),
aaba098f 2031 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
43994d82 2032#ifdef CONFIG_ARM64_SVE
aaba098f 2033 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
06a916fe
DM		 2034 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
2035 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
2036 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
2037 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
d4209d8b 2038 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
06a916fe
DM		 2039 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
2040 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
d4209d8b
SP		 2041 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
2042 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
2043 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
43994d82 2044#endif
aaba098f 2045 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
75031975 2046#ifdef CONFIG_ARM64_PTR_AUTH
aaba098f
AM		 2047 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
2048 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
75031975 2049#endif
75283501
SP		 2050 {},
2051};
2052
7559950a
SP		 2053#ifdef CONFIG_COMPAT
2054static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
2055{
2056 /*
2057 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
2058 * in line with that of arm32 as in vfp_init(). We make sure that the
2059 * check is future proof, by making sure value is non-zero.
2060 */
2061 u32 mvfr1;
2062
2063 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
2064 if (scope == SCOPE_SYSTEM)
2065 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
2066 else
2067 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
2068
2069 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
2070 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
2071 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
2072}
2073#endif
2074
75283501 2075static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
37b01d53 2076#ifdef CONFIG_COMPAT
7559950a
SP		 2077 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
2078 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
2079 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
2080 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
2081 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
ff96f7bc
SP		 2082 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
2083 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
2084 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
2085 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
2086 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
37b01d53
SP		 2087#endif
2088 {},
2089};
2090
f3efb675 2091static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 2092{
2093 switch (cap->hwcap_type) {
2094 case CAP_HWCAP:
aaba098f 2095 cpu_set_feature(cap->hwcap);
37b01d53
SP		 2096 break;
2097#ifdef CONFIG_COMPAT
2098 case CAP_COMPAT_HWCAP:
2099 compat_elf_hwcap |= (u32)cap->hwcap;
2100 break;
2101 case CAP_COMPAT_HWCAP2:
2102 compat_elf_hwcap2 |= (u32)cap->hwcap;
2103 break;
2104#endif
2105 default:
2106 WARN_ON(1);
2107 break;
2108 }
2109}
2110
2111/* Check if we have a particular HWCAP enabled */
f3efb675 2112static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 2113{
2114 bool rc;
2115
2116 switch (cap->hwcap_type) {
2117 case CAP_HWCAP:
aaba098f 2118 rc = cpu_have_feature(cap->hwcap);
37b01d53
SP		 2119 break;
2120#ifdef CONFIG_COMPAT
2121 case CAP_COMPAT_HWCAP:
2122 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
2123 break;
2124 case CAP_COMPAT_HWCAP2:
2125 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
2126 break;
2127#endif
2128 default:
2129 WARN_ON(1);
2130 rc = false;
2131 }
2132
2133 return rc;
2134}
2135
75283501 2136static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
37b01d53 2137{
77c97b4e 2138 /* We support emulation of accesses to CPU ID feature registers */
aaba098f 2139 cpu_set_named_feature(CPUID);
75283501 2140 for (; hwcaps->matches; hwcaps++)
143ba05d 2141 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
75283501 2142 cap_set_elf_hwcap(hwcaps);
37b01d53
SP		 2143}
2144
606f8e7b 2145static void update_cpu_capabilities(u16 scope_mask)
67948af4 2146{
606f8e7b 2147 int i;
67948af4
SP		 2148 const struct arm64_cpu_capabilities *caps;
2149
cce360b5 2150 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
606f8e7b
SP		 2151 for (i = 0; i < ARM64_NCAPS; i++) {
2152 caps = cpu_hwcaps_ptrs[i];
2153 if (!caps || !(caps->type & scope_mask) ||
2154 cpus_have_cap(caps->capability) ||
cce360b5 2155 !caps->matches(caps, cpucap_default_scope(caps)))
359b7064
MZ		 2156 continue;
2157
606f8e7b
SP		 2158 if (caps->desc)
2159 pr_info("detected: %s\n", caps->desc);
75283501 2160 cpus_set_cap(caps->capability);
0ceb0d56
DT		 2161
2162 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
2163 set_bit(caps->capability, boot_capabilities);
359b7064 2164 }
ce8b602c
SP		 2165}
2166
0b587c84
SP		 2167/*
2168 * Enable all the available capabilities on this CPU. The capabilities
2169 * with BOOT_CPU scope are handled separately and hence skipped here.
2170 */
2171static int cpu_enable_non_boot_scope_capabilities(void *__unused)
ed478b3f 2172{
0b587c84
SP		 2173 int i;
2174 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
ed478b3f 2175
0b587c84
SP		 2176 for_each_available_cap(i) {
2177 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
2178
2179 if (WARN_ON(!cap))
2180 continue;
c0cda3b8 2181
0b587c84
SP		 2182 if (!(cap->type & non_boot_scope))
2183 continue;
2184
2185 if (cap->cpu_enable)
2186 cap->cpu_enable(cap);
2187 }
c0cda3b8
DM		 2188 return 0;
2189}
2190
ce8b602c 2191/*
dbb4e152
SP		 2192 * Run through the enabled capabilities and enable() it on all active
2193 * CPUs
ce8b602c 2194 */
0b587c84 2195static void __init enable_cpu_capabilities(u16 scope_mask)
ce8b602c 2196{
0b587c84
SP		 2197 int i;
2198 const struct arm64_cpu_capabilities *caps;
2199 bool boot_scope;
2200
cce360b5 2201 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
0b587c84 2202 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
63a1e1c9 2203
0b587c84
SP		 2204 for (i = 0; i < ARM64_NCAPS; i++) {
2205 unsigned int num;
2206
2207 caps = cpu_hwcaps_ptrs[i];
2208 if (!caps || !(caps->type & scope_mask))
2209 continue;
2210 num = caps->capability;
2211 if (!cpus_have_cap(num))
63a1e1c9
MR		 2212 continue;
2213
2214 /* Ensure cpus_have_const_cap(num) works */
2215 static_branch_enable(&cpu_hwcap_keys[num]);
2216
0b587c84 2217 if (boot_scope && caps->cpu_enable)
2a6dcb2b 2218 /*
fd9d63da
SP		 2219 * Capabilities with SCOPE_BOOT_CPU scope are finalised
2220 * before any secondary CPU boots. Thus, each secondary
2221 * will enable the capability as appropriate via
2222 * check_local_cpu_capabilities(). The only exception is
2223 * the boot CPU, for which the capability must be
2224 * enabled here. This approach avoids costly
2225 * stop_machine() calls for this case.
2a6dcb2b 2226 */
0b587c84 2227 caps->cpu_enable(caps);
63a1e1c9 2228 }
dbb4e152 2229
0b587c84
SP		 2230 /*
2231 * For all non-boot scope capabilities, use stop_machine()
2232 * as it schedules the work allowing us to modify PSTATE,
2233 * instead of on_each_cpu() which uses an IPI, giving us a
2234 * PSTATE that disappears when we return.
2235 */
2236 if (!boot_scope)
2237 stop_machine(cpu_enable_non_boot_scope_capabilities,
2238 NULL, cpu_online_mask);
ed478b3f
SP		 2239}
2240
eaac4d83
SP		 2241/*
2242 * Run through the list of capabilities to check for conflicts.
2243 * If the system has already detected a capability, take necessary
2244 * action on this CPU.
eaac4d83 2245 */
deeaac51 2246static void verify_local_cpu_caps(u16 scope_mask)
eaac4d83 2247{
606f8e7b 2248 int i;
eaac4d83 2249 bool cpu_has_cap, system_has_cap;
606f8e7b 2250 const struct arm64_cpu_capabilities *caps;
eaac4d83 2251
cce360b5
SP		 2252 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2253
606f8e7b
SP		 2254 for (i = 0; i < ARM64_NCAPS; i++) {
2255 caps = cpu_hwcaps_ptrs[i];
2256 if (!caps || !(caps->type & scope_mask))
cce360b5
SP		 2257 continue;
2258
ba7d9233 2259 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
eaac4d83
SP		 2260 system_has_cap = cpus_have_cap(caps->capability);
2261
2262 if (system_has_cap) {
2263 /*
2264 * Check if the new CPU misses an advertised feature,
2265 * which is not safe to miss.
2266 */
2267 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
2268 break;
2269 /*
2270 * We have to issue cpu_enable() irrespective of
2271 * whether the CPU has it or not, as it is enabeld
2272 * system wide. It is upto the call back to take
2273 * appropriate action on this CPU.
2274 */
2275 if (caps->cpu_enable)
2276 caps->cpu_enable(caps);
2277 } else {
2278 /*
2279 * Check if the CPU has this capability if it isn't
2280 * safe to have when the system doesn't.
2281 */
2282 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
2283 break;
2284 }
2285 }
2286
606f8e7b 2287 if (i < ARM64_NCAPS) {
eaac4d83
SP		 2288 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
2289 smp_processor_id(), caps->capability,
2290 caps->desc, system_has_cap, cpu_has_cap);
eaac4d83 2291
deeaac51
KM		 2292 if (cpucap_panic_on_conflict(caps))
2293 cpu_panic_kernel();
2294 else
2295 cpu_die_early();
2296 }
eaac4d83
SP		 2297}
2298
dbb4e152 2299/*
13f417f3
SP		 2300 * Check for CPU features that are used in early boot
2301 * based on the Boot CPU value.
dbb4e152 2302 */
13f417f3 2303static void check_early_cpu_features(void)
dbb4e152 2304{
13f417f3 2305 verify_cpu_asid_bits();
deeaac51
KM		 2306
2307 verify_local_cpu_caps(SCOPE_BOOT_CPU);
dbb4e152 2308}
1c076303 2309
75283501
SP		 2310static void
2311verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
2312{
2313
92406f0c
SP		 2314 for (; caps->matches; caps++)
2315 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
75283501
SP		 2316 pr_crit("CPU%d: missing HWCAP: %s\n",
2317 smp_processor_id(), caps->desc);
2318 cpu_die_early();
2319 }
75283501
SP		 2320}
2321
2e0f2478
DM		 2322static void verify_sve_features(void)
2323{
2324 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
2325 u64 zcr = read_zcr_features();
2326
2327 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
2328 unsigned int len = zcr & ZCR_ELx_LEN_MASK;
2329
2330 if (len < safe_len || sve_verify_vq_map()) {
d06b76be 2331 pr_crit("CPU%d: SVE: vector length support mismatch\n",
2e0f2478
DM		 2332 smp_processor_id());
2333 cpu_die_early();
2334 }
2335
2336 /* Add checks on other ZCR bits here if necessary */
2337}
2338
c73433fc
AK		 2339static void verify_hyp_capabilities(void)
2340{
2341 u64 safe_mmfr1, mmfr0, mmfr1;
2342 int parange, ipa_max;
2343 unsigned int safe_vmid_bits, vmid_bits;
2344
2345 if (!IS_ENABLED(CONFIG_KVM) || !IS_ENABLED(CONFIG_KVM_ARM_HOST))
2346 return;
2347
2348 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
2349 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
2350 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
2351
2352 /* Verify VMID bits */
2353 safe_vmid_bits = get_vmid_bits(safe_mmfr1);
2354 vmid_bits = get_vmid_bits(mmfr1);
2355 if (vmid_bits < safe_vmid_bits) {
2356 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id());
2357 cpu_die_early();
2358 }
2359
2360 /* Verify IPA range */
f73531f0
AK		 2361 parange = cpuid_feature_extract_unsigned_field(mmfr0,
2362 ID_AA64MMFR0_PARANGE_SHIFT);
c73433fc
AK		 2363 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange);
2364 if (ipa_max < get_kvm_ipa_limit()) {
2365 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id());
2366 cpu_die_early();
2367 }
2368}
1e89baed 2369
dbb4e152
SP		 2370/*
2371 * Run through the enabled system capabilities and enable() it on this CPU.
2372 * The capabilities were decided based on the available CPUs at the boot time.
2373 * Any new CPU should match the system wide status of the capability. If the
2374 * new CPU doesn't have a capability which the system now has enabled, we
2375 * cannot do anything to fix it up and could cause unexpected failures. So
2376 * we park the CPU.
2377 */
c47a1900 2378static void verify_local_cpu_capabilities(void)
dbb4e152 2379{
fd9d63da
SP		 2380 /*
2381 * The capabilities with SCOPE_BOOT_CPU are checked from
2382 * check_early_cpu_features(), as they need to be verified
2383 * on all secondary CPUs.
2384 */
deeaac51 2385 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU);
ed478b3f 2386
c47a1900 2387 verify_local_elf_hwcaps(arm64_elf_hwcaps);
2e0f2478 2388
c47a1900
SP		 2389 if (system_supports_32bit_el0())
2390 verify_local_elf_hwcaps(compat_elf_hwcaps);
2e0f2478
DM		 2391
2392 if (system_supports_sve())
2393 verify_sve_features();
c73433fc
AK		 2394
2395 if (is_hyp_mode_available())
2396 verify_hyp_capabilities();
c47a1900 2397}
dbb4e152 2398
c47a1900
SP		 2399void check_local_cpu_capabilities(void)
2400{
2401 /*
2402 * All secondary CPUs should conform to the early CPU features
2403 * in use by the kernel based on boot CPU.
2404 */
13f417f3
SP		 2405 check_early_cpu_features();
2406
dbb4e152 2407 /*
c47a1900 2408 * If we haven't finalised the system capabilities, this CPU gets
fbd890b9 2409 * a chance to update the errata work arounds and local features.
c47a1900
SP		 2410 * Otherwise, this CPU should verify that it has all the system
2411 * advertised capabilities.
dbb4e152 2412 */
b51c6ac2 2413 if (!system_capabilities_finalized())
ed478b3f
SP		 2414 update_cpu_capabilities(SCOPE_LOCAL_CPU);
2415 else
c47a1900 2416 verify_local_cpu_capabilities();
359b7064
MZ		 2417}
2418
fd9d63da
SP		 2419static void __init setup_boot_cpu_capabilities(void)
2420{
2421 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
2422 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
2423 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
2424 enable_cpu_capabilities(SCOPE_BOOT_CPU);
2425}
2426
f7bfc14a 2427bool this_cpu_has_cap(unsigned int n)
8f413758 2428{
f7bfc14a
SP		 2429 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
2430 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2431
2432 if (cap)
2433 return cap->matches(cap, SCOPE_LOCAL_CPU);
2434 }
2435
2436 return false;
8f413758
MZ		 2437}
2438
3ff047f6
ADK		 2439/*
2440 * This helper function is used in a narrow window when,
2441 * - The system wide safe registers are set with all the SMP CPUs and,
2442 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set.
2443 * In all other cases cpus_have_{const_}cap() should be used.
2444 */
2445static bool __system_matches_cap(unsigned int n)
2446{
2447 if (n < ARM64_NCAPS) {
2448 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2449
2450 if (cap)
2451 return cap->matches(cap, SCOPE_SYSTEM);
2452 }
2453 return false;
2454}
2455
aec0bff7
AM		 2456void cpu_set_feature(unsigned int num)
2457{
2458 WARN_ON(num >= MAX_CPU_FEATURES);
2459 elf_hwcap |= BIT(num);
2460}
2461EXPORT_SYMBOL_GPL(cpu_set_feature);
2462
2463bool cpu_have_feature(unsigned int num)
2464{
2465 WARN_ON(num >= MAX_CPU_FEATURES);
2466 return elf_hwcap & BIT(num);
2467}
2468EXPORT_SYMBOL_GPL(cpu_have_feature);
2469
2470unsigned long cpu_get_elf_hwcap(void)
2471{
2472 /*
2473 * We currently only populate the first 32 bits of AT_HWCAP. Please
2474 * note that for userspace compatibility we guarantee that bits 62
2475 * and 63 will always be returned as 0.
2476 */
2477 return lower_32_bits(elf_hwcap);
2478}
2479
2480unsigned long cpu_get_elf_hwcap2(void)
2481{
2482 return upper_32_bits(elf_hwcap);
2483}
2484
ed478b3f
SP		 2485static void __init setup_system_capabilities(void)
2486{
2487 /*
2488 * We have finalised the system-wide safe feature
2489 * registers, finalise the capabilities that depend
fd9d63da
SP		 2490 * on it. Also enable all the available capabilities,
2491 * that are not enabled already.
ed478b3f
SP		 2492 */
2493 update_cpu_capabilities(SCOPE_SYSTEM);
fd9d63da 2494 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
ed478b3f
SP		 2495}
2496
9cdf8ec4 2497void __init setup_cpu_features(void)
359b7064 2498{
9cdf8ec4 2499 u32 cwg;
9cdf8ec4 2500
ed478b3f 2501 setup_system_capabilities();
75283501 2502 setup_elf_hwcaps(arm64_elf_hwcaps);
643d703d
SP		 2503
2504 if (system_supports_32bit_el0())
2505 setup_elf_hwcaps(compat_elf_hwcaps);
dbb4e152 2506
2e6f549f
KC		 2507 if (system_uses_ttbr0_pan())
2508 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
2509
2e0f2478 2510 sve_setup();
94b07c1f 2511 minsigstksz_setup();
2e0f2478 2512
dbb4e152 2513 /* Advertise that we have computed the system capabilities */
b51c6ac2 2514 finalize_system_capabilities();
dbb4e152 2515
9cdf8ec4
SP		 2516 /*
2517 * Check for sane CTR_EL0.CWG value.
2518 */
2519 cwg = cache_type_cwg();
9cdf8ec4 2520 if (!cwg)
ebc7e21e
CM		 2521 pr_warn("No Cache Writeback Granule information, assuming %d\n",
2522 ARCH_DMA_MINALIGN);
359b7064 2523}
70544196
JM		 2524
2525static bool __maybe_unused
92406f0c 2526cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
70544196 2527{
3ff047f6 2528 return (__system_matches_cap(ARM64_HAS_PAN) && !__system_matches_cap(ARM64_HAS_UAO));
70544196 2529}
77c97b4e 2530
5ffdfaed
VM		 2531static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
2532{
2533 cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
2534}
2535
77c97b4e
SP		 2536/*
2537 * We emulate only the following system register space.
2538 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
2539 * See Table C5-6 System instruction encodings for System register accesses,
2540 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
2541 */
2542static inline bool __attribute_const__ is_emulated(u32 id)
2543{
2544 return (sys_reg_Op0(id) == 0x3 &&
2545 sys_reg_CRn(id) == 0x0 &&
2546 sys_reg_Op1(id) == 0x0 &&
2547 (sys_reg_CRm(id) == 0 ||
2548 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
2549}
2550
2551/*
2552 * With CRm == 0, reg should be one of :
2553 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
2554 */
2555static inline int emulate_id_reg(u32 id, u64 *valp)
2556{
2557 switch (id) {
2558 case SYS_MIDR_EL1:
2559 *valp = read_cpuid_id();
2560 break;
2561 case SYS_MPIDR_EL1:
2562 *valp = SYS_MPIDR_SAFE_VAL;
2563 break;
2564 case SYS_REVIDR_EL1:
2565 /* IMPLEMENTATION DEFINED values are emulated with 0 */
2566 *valp = 0;
2567 break;
2568 default:
2569 return -EINVAL;
2570 }
2571
2572 return 0;
2573}
2574
2575static int emulate_sys_reg(u32 id, u64 *valp)
2576{
2577 struct arm64_ftr_reg *regp;
2578
2579 if (!is_emulated(id))
2580 return -EINVAL;
2581
2582 if (sys_reg_CRm(id) == 0)
2583 return emulate_id_reg(id, valp);
2584
2585 regp = get_arm64_ftr_reg(id);
2586 if (regp)
2587 *valp = arm64_ftr_reg_user_value(regp);
2588 else
2589 /*
2590 * The untracked registers are either IMPLEMENTATION DEFINED
2591 * (e.g, ID_AFR0_EL1) or reserved RAZ.
2592 */
2593 *valp = 0;
2594 return 0;
2595}
2596
520ad988 2597int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
77c97b4e
SP		 2598{
2599 int rc;
77c97b4e
SP		 2600 u64 val;
2601
77c97b4e
SP		 2602 rc = emulate_sys_reg(sys_reg, &val);
2603 if (!rc) {
520ad988 2604 pt_regs_write_reg(regs, rt, val);
6436beee 2605 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
77c97b4e 2606 }
77c97b4e
SP		 2607 return rc;
2608}
2609
520ad988
AK		 2610static int emulate_mrs(struct pt_regs *regs, u32 insn)
2611{
2612 u32 sys_reg, rt;
2613
2614 /*
2615 * sys_reg values are defined as used in mrs/msr instruction.
2616 * shift the imm value to get the encoding.
2617 */
2618 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
2619 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
2620 return do_emulate_mrs(regs, sys_reg, rt);
2621}
2622
77c97b4e
SP		 2623static struct undef_hook mrs_hook = {
2624 .instr_mask = 0xfff00000,
2625 .instr_val = 0xd5300000,
d64567f6 2626 .pstate_mask = PSR_AA32_MODE_MASK,
77c97b4e
SP		 2627 .pstate_val = PSR_MODE_EL0t,
2628 .fn = emulate_mrs,
2629};
2630
2631static int __init enable_mrs_emulation(void)
2632{
2633 register_undef_hook(&mrs_hook);
2634 return 0;
2635}
2636
c0d8832e 2637core_initcall(enable_mrs_emulation);
1b3ccf4b
JL		 2638
2639ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
2640 char *buf)
2641{
2642 if (__meltdown_safe)
2643 return sprintf(buf, "Not affected\n");
2644
2645 if (arm64_kernel_unmapped_at_el0())
2646 return sprintf(buf, "Mitigation: PTI\n");
2647
2648 return sprintf(buf, "Vulnerable\n");
2649}
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