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359b7064 MZ |
1 | /* |
2 | * Contains CPU feature definitions | |
3 | * | |
4 | * Copyright (C) 2015 ARM Ltd. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
9cdf8ec4 | 19 | #define pr_fmt(fmt) "CPU features: " fmt |
359b7064 | 20 | |
3c739b57 | 21 | #include <linux/bsearch.h> |
2a6dcb2b | 22 | #include <linux/cpumask.h> |
3c739b57 | 23 | #include <linux/sort.h> |
2a6dcb2b | 24 | #include <linux/stop_machine.h> |
359b7064 | 25 | #include <linux/types.h> |
2077be67 | 26 | #include <linux/mm.h> |
359b7064 MZ |
27 | #include <asm/cpu.h> |
28 | #include <asm/cpufeature.h> | |
dbb4e152 | 29 | #include <asm/cpu_ops.h> |
2e0f2478 | 30 | #include <asm/fpsimd.h> |
13f417f3 | 31 | #include <asm/mmu_context.h> |
338d4f49 | 32 | #include <asm/processor.h> |
cdcf817b | 33 | #include <asm/sysreg.h> |
77c97b4e | 34 | #include <asm/traps.h> |
d88701be | 35 | #include <asm/virt.h> |
359b7064 | 36 | |
9cdf8ec4 SP |
37 | unsigned long elf_hwcap __read_mostly; |
38 | EXPORT_SYMBOL_GPL(elf_hwcap); | |
39 | ||
40 | #ifdef CONFIG_COMPAT | |
41 | #define COMPAT_ELF_HWCAP_DEFAULT \ | |
42 | (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ | |
43 | COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ | |
44 | COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\ | |
45 | COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\ | |
46 | COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\ | |
47 | COMPAT_HWCAP_LPAE) | |
48 | unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; | |
49 | unsigned int compat_elf_hwcap2 __read_mostly; | |
50 | #endif | |
51 | ||
52 | DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); | |
4b65a5db | 53 | EXPORT_SYMBOL(cpu_hwcaps); |
9cdf8ec4 | 54 | |
8f1eec57 DM |
55 | /* |
56 | * Flag to indicate if we have computed the system wide | |
57 | * capabilities based on the boot time active CPUs. This | |
58 | * will be used to determine if a new booting CPU should | |
59 | * go through the verification process to make sure that it | |
60 | * supports the system capabilities, without using a hotplug | |
61 | * notifier. | |
62 | */ | |
63 | static bool sys_caps_initialised; | |
64 | ||
65 | static inline void set_sys_caps_initialised(void) | |
66 | { | |
67 | sys_caps_initialised = true; | |
68 | } | |
69 | ||
8effeaaf MR |
70 | static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p) |
71 | { | |
72 | /* file-wide pr_fmt adds "CPU features: " prefix */ | |
73 | pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps); | |
74 | return 0; | |
75 | } | |
76 | ||
77 | static struct notifier_block cpu_hwcaps_notifier = { | |
78 | .notifier_call = dump_cpu_hwcaps | |
79 | }; | |
80 | ||
81 | static int __init register_cpu_hwcaps_dumper(void) | |
82 | { | |
83 | atomic_notifier_chain_register(&panic_notifier_list, | |
84 | &cpu_hwcaps_notifier); | |
85 | return 0; | |
86 | } | |
87 | __initcall(register_cpu_hwcaps_dumper); | |
88 | ||
efd9e03f CM |
89 | DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS); |
90 | EXPORT_SYMBOL(cpu_hwcap_keys); | |
91 | ||
fe4fbdbc | 92 | #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ |
3c739b57 | 93 | { \ |
4f0a606b | 94 | .sign = SIGNED, \ |
fe4fbdbc | 95 | .visible = VISIBLE, \ |
3c739b57 SP |
96 | .strict = STRICT, \ |
97 | .type = TYPE, \ | |
98 | .shift = SHIFT, \ | |
99 | .width = WIDTH, \ | |
100 | .safe_val = SAFE_VAL, \ | |
101 | } | |
102 | ||
0710cfdb | 103 | /* Define a feature with unsigned values */ |
fe4fbdbc SP |
104 | #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ |
105 | __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) | |
4f0a606b | 106 | |
0710cfdb | 107 | /* Define a feature with a signed value */ |
fe4fbdbc SP |
108 | #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ |
109 | __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) | |
0710cfdb | 110 | |
3c739b57 SP |
111 | #define ARM64_FTR_END \ |
112 | { \ | |
113 | .width = 0, \ | |
114 | } | |
115 | ||
70544196 JM |
116 | /* meta feature for alternatives */ |
117 | static bool __maybe_unused | |
92406f0c SP |
118 | cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused); |
119 | ||
70544196 | 120 | |
4aa8a472 SP |
121 | /* |
122 | * NOTE: Any changes to the visibility of features should be kept in | |
123 | * sync with the documentation of the CPU feature register ABI. | |
124 | */ | |
5e49d73c | 125 | static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { |
3b3b6810 | 126 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0), |
5bdecb79 SP |
127 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0), |
128 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0), | |
129 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0), | |
130 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0), | |
131 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0), | |
fe4fbdbc SP |
132 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), |
133 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0), | |
134 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0), | |
135 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0), | |
136 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0), | |
3c739b57 SP |
137 | ARM64_FTR_END, |
138 | }; | |
139 | ||
c8c3798d | 140 | static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { |
5bdecb79 SP |
141 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0), |
142 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), | |
143 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), | |
144 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0), | |
c8c3798d SP |
145 | ARM64_FTR_END, |
146 | }; | |
147 | ||
5e49d73c | 148 | static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { |
179a56f6 | 149 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), |
0f15adbb | 150 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), |
43994d82 | 151 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0), |
64c02720 | 152 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0), |
5bdecb79 | 153 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0), |
fe4fbdbc SP |
154 | S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), |
155 | S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), | |
3c739b57 | 156 | /* Linux doesn't care about the EL3 */ |
5bdecb79 SP |
157 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0), |
158 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0), | |
159 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY), | |
160 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY), | |
3c739b57 SP |
161 | ARM64_FTR_END, |
162 | }; | |
163 | ||
5e49d73c | 164 | static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { |
5bdecb79 SP |
165 | S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), |
166 | S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), | |
167 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI), | |
168 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0), | |
3c739b57 | 169 | /* Linux shouldn't care about secure memory */ |
5bdecb79 SP |
170 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0), |
171 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0), | |
172 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0), | |
3c739b57 SP |
173 | /* |
174 | * Differing PARange is fine as long as all peripherals and memory are mapped | |
175 | * within the minimum PARange of all CPUs | |
176 | */ | |
fe4fbdbc | 177 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0), |
3c739b57 SP |
178 | ARM64_FTR_END, |
179 | }; | |
180 | ||
5e49d73c | 181 | static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { |
fe4fbdbc | 182 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0), |
5bdecb79 SP |
183 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0), |
184 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0), | |
185 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0), | |
186 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0), | |
187 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0), | |
3c739b57 SP |
188 | ARM64_FTR_END, |
189 | }; | |
190 | ||
5e49d73c | 191 | static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { |
5bdecb79 SP |
192 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0), |
193 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0), | |
194 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0), | |
195 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0), | |
196 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0), | |
406e3087 JM |
197 | ARM64_FTR_END, |
198 | }; | |
199 | ||
5e49d73c | 200 | static const struct arm64_ftr_bits ftr_ctr[] = { |
fe4fbdbc SP |
201 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */ |
202 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */ | |
203 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */ | |
204 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */ | |
3c739b57 SP |
205 | /* |
206 | * Linux can handle differing I-cache policies. Userspace JITs will | |
ee7bc638 | 207 | * make use of *minLine. |
155433cb | 208 | * If we have differing I-cache policies, report it as the weakest - VIPT. |
3c739b57 | 209 | */ |
155433cb | 210 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */ |
fe4fbdbc | 211 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */ |
3c739b57 SP |
212 | ARM64_FTR_END, |
213 | }; | |
214 | ||
675b0563 AB |
215 | struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { |
216 | .name = "SYS_CTR_EL0", | |
217 | .ftr_bits = ftr_ctr | |
218 | }; | |
219 | ||
5e49d73c | 220 | static const struct arm64_ftr_bits ftr_id_mmfr0[] = { |
5bdecb79 SP |
221 | S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf), /* InnerShr */ |
222 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), /* FCSE */ | |
fe4fbdbc | 223 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */ |
5bdecb79 SP |
224 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), /* TCM */ |
225 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* ShareLvl */ | |
226 | S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf), /* OuterShr */ | |
227 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* PMSA */ | |
228 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* VMSA */ | |
3c739b57 SP |
229 | ARM64_FTR_END, |
230 | }; | |
231 | ||
5e49d73c | 232 | static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { |
fe4fbdbc SP |
233 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0), |
234 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0), | |
235 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0), | |
236 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0), | |
237 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0), | |
b20d1ba3 WD |
238 | /* |
239 | * We can instantiate multiple PMU instances with different levels | |
240 | * of support. | |
fe4fbdbc SP |
241 | */ |
242 | S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0), | |
243 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0), | |
244 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6), | |
3c739b57 SP |
245 | ARM64_FTR_END, |
246 | }; | |
247 | ||
5e49d73c | 248 | static const struct arm64_ftr_bits ftr_mvfr2[] = { |
5bdecb79 SP |
249 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* FPMisc */ |
250 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* SIMDMisc */ | |
3c739b57 SP |
251 | ARM64_FTR_END, |
252 | }; | |
253 | ||
5e49d73c | 254 | static const struct arm64_ftr_bits ftr_dczid[] = { |
fe4fbdbc SP |
255 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */ |
256 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */ | |
3c739b57 SP |
257 | ARM64_FTR_END, |
258 | }; | |
259 | ||
260 | ||
5e49d73c | 261 | static const struct arm64_ftr_bits ftr_id_isar5[] = { |
5bdecb79 SP |
262 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0), |
263 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0), | |
264 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0), | |
265 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0), | |
266 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0), | |
267 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0), | |
3c739b57 SP |
268 | ARM64_FTR_END, |
269 | }; | |
270 | ||
5e49d73c | 271 | static const struct arm64_ftr_bits ftr_id_mmfr4[] = { |
5bdecb79 | 272 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* ac2 */ |
3c739b57 SP |
273 | ARM64_FTR_END, |
274 | }; | |
275 | ||
5e49d73c | 276 | static const struct arm64_ftr_bits ftr_id_pfr0[] = { |
5bdecb79 SP |
277 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* State3 */ |
278 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), /* State2 */ | |
279 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* State1 */ | |
280 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* State0 */ | |
3c739b57 SP |
281 | ARM64_FTR_END, |
282 | }; | |
283 | ||
5e49d73c | 284 | static const struct arm64_ftr_bits ftr_id_dfr0[] = { |
fe4fbdbc SP |
285 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), |
286 | S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */ | |
287 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), | |
288 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), | |
289 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), | |
290 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), | |
291 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), | |
292 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), | |
e5343503 SP |
293 | ARM64_FTR_END, |
294 | }; | |
295 | ||
2e0f2478 DM |
296 | static const struct arm64_ftr_bits ftr_zcr[] = { |
297 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, | |
298 | ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */ | |
299 | ARM64_FTR_END, | |
300 | }; | |
301 | ||
3c739b57 SP |
302 | /* |
303 | * Common ftr bits for a 32bit register with all hidden, strict | |
304 | * attributes, with 4bit feature fields and a default safe value of | |
305 | * 0. Covers the following 32bit registers: | |
306 | * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1] | |
307 | */ | |
5e49d73c | 308 | static const struct arm64_ftr_bits ftr_generic_32bits[] = { |
fe4fbdbc SP |
309 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), |
310 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), | |
311 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), | |
312 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), | |
313 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), | |
314 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), | |
315 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), | |
316 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), | |
3c739b57 SP |
317 | ARM64_FTR_END, |
318 | }; | |
319 | ||
eab43e88 SP |
320 | /* Table for a single 32bit feature value */ |
321 | static const struct arm64_ftr_bits ftr_single32[] = { | |
fe4fbdbc | 322 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), |
3c739b57 SP |
323 | ARM64_FTR_END, |
324 | }; | |
325 | ||
eab43e88 | 326 | static const struct arm64_ftr_bits ftr_raz[] = { |
3c739b57 SP |
327 | ARM64_FTR_END, |
328 | }; | |
329 | ||
6f2b7eef AB |
330 | #define ARM64_FTR_REG(id, table) { \ |
331 | .sys_id = id, \ | |
332 | .reg = &(struct arm64_ftr_reg){ \ | |
3c739b57 SP |
333 | .name = #id, \ |
334 | .ftr_bits = &((table)[0]), \ | |
6f2b7eef | 335 | }} |
3c739b57 | 336 | |
6f2b7eef AB |
337 | static const struct __ftr_reg_entry { |
338 | u32 sys_id; | |
339 | struct arm64_ftr_reg *reg; | |
340 | } arm64_ftr_regs[] = { | |
3c739b57 SP |
341 | |
342 | /* Op1 = 0, CRn = 0, CRm = 1 */ | |
343 | ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), | |
344 | ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits), | |
e5343503 | 345 | ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), |
3c739b57 SP |
346 | ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), |
347 | ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), | |
348 | ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), | |
349 | ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), | |
350 | ||
351 | /* Op1 = 0, CRn = 0, CRm = 2 */ | |
352 | ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits), | |
353 | ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), | |
354 | ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), | |
355 | ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), | |
356 | ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits), | |
357 | ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), | |
358 | ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), | |
359 | ||
360 | /* Op1 = 0, CRn = 0, CRm = 3 */ | |
361 | ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits), | |
362 | ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits), | |
363 | ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), | |
364 | ||
365 | /* Op1 = 0, CRn = 0, CRm = 4 */ | |
366 | ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), | |
eab43e88 | 367 | ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_raz), |
2e0f2478 | 368 | ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_raz), |
3c739b57 SP |
369 | |
370 | /* Op1 = 0, CRn = 0, CRm = 5 */ | |
371 | ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), | |
eab43e88 | 372 | ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), |
3c739b57 SP |
373 | |
374 | /* Op1 = 0, CRn = 0, CRm = 6 */ | |
375 | ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), | |
c8c3798d | 376 | ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1), |
3c739b57 SP |
377 | |
378 | /* Op1 = 0, CRn = 0, CRm = 7 */ | |
379 | ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), | |
380 | ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1), | |
406e3087 | 381 | ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), |
3c739b57 | 382 | |
2e0f2478 DM |
383 | /* Op1 = 0, CRn = 1, CRm = 2 */ |
384 | ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr), | |
385 | ||
3c739b57 | 386 | /* Op1 = 3, CRn = 0, CRm = 0 */ |
675b0563 | 387 | { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, |
3c739b57 SP |
388 | ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), |
389 | ||
390 | /* Op1 = 3, CRn = 14, CRm = 0 */ | |
eab43e88 | 391 | ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), |
3c739b57 SP |
392 | }; |
393 | ||
394 | static int search_cmp_ftr_reg(const void *id, const void *regp) | |
395 | { | |
6f2b7eef | 396 | return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; |
3c739b57 SP |
397 | } |
398 | ||
399 | /* | |
400 | * get_arm64_ftr_reg - Lookup a feature register entry using its | |
401 | * sys_reg() encoding. With the array arm64_ftr_regs sorted in the | |
402 | * ascending order of sys_id , we use binary search to find a matching | |
403 | * entry. | |
404 | * | |
405 | * returns - Upon success, matching ftr_reg entry for id. | |
406 | * - NULL on failure. It is upto the caller to decide | |
407 | * the impact of a failure. | |
408 | */ | |
409 | static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) | |
410 | { | |
6f2b7eef AB |
411 | const struct __ftr_reg_entry *ret; |
412 | ||
413 | ret = bsearch((const void *)(unsigned long)sys_id, | |
3c739b57 SP |
414 | arm64_ftr_regs, |
415 | ARRAY_SIZE(arm64_ftr_regs), | |
416 | sizeof(arm64_ftr_regs[0]), | |
417 | search_cmp_ftr_reg); | |
6f2b7eef AB |
418 | if (ret) |
419 | return ret->reg; | |
420 | return NULL; | |
3c739b57 SP |
421 | } |
422 | ||
5e49d73c AB |
423 | static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, |
424 | s64 ftr_val) | |
3c739b57 SP |
425 | { |
426 | u64 mask = arm64_ftr_mask(ftrp); | |
427 | ||
428 | reg &= ~mask; | |
429 | reg |= (ftr_val << ftrp->shift) & mask; | |
430 | return reg; | |
431 | } | |
432 | ||
5e49d73c AB |
433 | static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, |
434 | s64 cur) | |
3c739b57 SP |
435 | { |
436 | s64 ret = 0; | |
437 | ||
438 | switch (ftrp->type) { | |
439 | case FTR_EXACT: | |
440 | ret = ftrp->safe_val; | |
441 | break; | |
442 | case FTR_LOWER_SAFE: | |
443 | ret = new < cur ? new : cur; | |
444 | break; | |
445 | case FTR_HIGHER_SAFE: | |
446 | ret = new > cur ? new : cur; | |
447 | break; | |
448 | default: | |
449 | BUG(); | |
450 | } | |
451 | ||
452 | return ret; | |
453 | } | |
454 | ||
3c739b57 SP |
455 | static void __init sort_ftr_regs(void) |
456 | { | |
6f2b7eef AB |
457 | int i; |
458 | ||
459 | /* Check that the array is sorted so that we can do the binary search */ | |
460 | for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++) | |
461 | BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id); | |
3c739b57 SP |
462 | } |
463 | ||
464 | /* | |
465 | * Initialise the CPU feature register from Boot CPU values. | |
466 | * Also initiliases the strict_mask for the register. | |
b389d799 MR |
467 | * Any bits that are not covered by an arm64_ftr_bits entry are considered |
468 | * RES0 for the system-wide value, and must strictly match. | |
3c739b57 SP |
469 | */ |
470 | static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new) | |
471 | { | |
472 | u64 val = 0; | |
473 | u64 strict_mask = ~0x0ULL; | |
fe4fbdbc | 474 | u64 user_mask = 0; |
b389d799 MR |
475 | u64 valid_mask = 0; |
476 | ||
5e49d73c | 477 | const struct arm64_ftr_bits *ftrp; |
3c739b57 SP |
478 | struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); |
479 | ||
480 | BUG_ON(!reg); | |
481 | ||
482 | for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { | |
b389d799 | 483 | u64 ftr_mask = arm64_ftr_mask(ftrp); |
3c739b57 SP |
484 | s64 ftr_new = arm64_ftr_value(ftrp, new); |
485 | ||
486 | val = arm64_ftr_set_value(ftrp, val, ftr_new); | |
b389d799 MR |
487 | |
488 | valid_mask |= ftr_mask; | |
3c739b57 | 489 | if (!ftrp->strict) |
b389d799 | 490 | strict_mask &= ~ftr_mask; |
fe4fbdbc SP |
491 | if (ftrp->visible) |
492 | user_mask |= ftr_mask; | |
493 | else | |
494 | reg->user_val = arm64_ftr_set_value(ftrp, | |
495 | reg->user_val, | |
496 | ftrp->safe_val); | |
3c739b57 | 497 | } |
b389d799 MR |
498 | |
499 | val &= valid_mask; | |
500 | ||
3c739b57 SP |
501 | reg->sys_val = val; |
502 | reg->strict_mask = strict_mask; | |
fe4fbdbc | 503 | reg->user_mask = user_mask; |
3c739b57 SP |
504 | } |
505 | ||
506 | void __init init_cpu_features(struct cpuinfo_arm64 *info) | |
507 | { | |
508 | /* Before we start using the tables, make sure it is sorted */ | |
509 | sort_ftr_regs(); | |
510 | ||
511 | init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); | |
512 | init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); | |
513 | init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); | |
514 | init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); | |
515 | init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); | |
516 | init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); | |
517 | init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); | |
518 | init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); | |
519 | init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); | |
406e3087 | 520 | init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); |
3c739b57 SP |
521 | init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); |
522 | init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); | |
2e0f2478 | 523 | init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); |
a6dc3cd7 SP |
524 | |
525 | if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { | |
526 | init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); | |
527 | init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); | |
528 | init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); | |
529 | init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); | |
530 | init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); | |
531 | init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); | |
532 | init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); | |
533 | init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); | |
534 | init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); | |
535 | init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); | |
536 | init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); | |
537 | init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); | |
538 | init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); | |
539 | init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); | |
540 | init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); | |
541 | init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); | |
542 | } | |
543 | ||
2e0f2478 DM |
544 | if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { |
545 | init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr); | |
546 | sve_init_vq_map(); | |
547 | } | |
3c739b57 SP |
548 | } |
549 | ||
3086d391 | 550 | static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) |
3c739b57 | 551 | { |
5e49d73c | 552 | const struct arm64_ftr_bits *ftrp; |
3c739b57 SP |
553 | |
554 | for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { | |
555 | s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); | |
556 | s64 ftr_new = arm64_ftr_value(ftrp, new); | |
557 | ||
558 | if (ftr_cur == ftr_new) | |
559 | continue; | |
560 | /* Find a safe value */ | |
561 | ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); | |
562 | reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); | |
563 | } | |
564 | ||
565 | } | |
566 | ||
3086d391 | 567 | static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) |
cdcf817b | 568 | { |
3086d391 SP |
569 | struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); |
570 | ||
571 | BUG_ON(!regp); | |
572 | update_cpu_ftr_reg(regp, val); | |
573 | if ((boot & regp->strict_mask) == (val & regp->strict_mask)) | |
574 | return 0; | |
575 | pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", | |
576 | regp->name, boot, cpu, val); | |
577 | return 1; | |
578 | } | |
579 | ||
580 | /* | |
581 | * Update system wide CPU feature registers with the values from a | |
582 | * non-boot CPU. Also performs SANITY checks to make sure that there | |
583 | * aren't any insane variations from that of the boot CPU. | |
584 | */ | |
585 | void update_cpu_features(int cpu, | |
586 | struct cpuinfo_arm64 *info, | |
587 | struct cpuinfo_arm64 *boot) | |
588 | { | |
589 | int taint = 0; | |
590 | ||
591 | /* | |
592 | * The kernel can handle differing I-cache policies, but otherwise | |
593 | * caches should look identical. Userspace JITs will make use of | |
594 | * *minLine. | |
595 | */ | |
596 | taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, | |
597 | info->reg_ctr, boot->reg_ctr); | |
598 | ||
599 | /* | |
600 | * Userspace may perform DC ZVA instructions. Mismatched block sizes | |
601 | * could result in too much or too little memory being zeroed if a | |
602 | * process is preempted and migrated between CPUs. | |
603 | */ | |
604 | taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, | |
605 | info->reg_dczid, boot->reg_dczid); | |
606 | ||
607 | /* If different, timekeeping will be broken (especially with KVM) */ | |
608 | taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, | |
609 | info->reg_cntfrq, boot->reg_cntfrq); | |
610 | ||
611 | /* | |
612 | * The kernel uses self-hosted debug features and expects CPUs to | |
613 | * support identical debug features. We presently need CTX_CMPs, WRPs, | |
614 | * and BRPs to be identical. | |
615 | * ID_AA64DFR1 is currently RES0. | |
616 | */ | |
617 | taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, | |
618 | info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); | |
619 | taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, | |
620 | info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); | |
621 | /* | |
622 | * Even in big.LITTLE, processors should be identical instruction-set | |
623 | * wise. | |
624 | */ | |
625 | taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, | |
626 | info->reg_id_aa64isar0, boot->reg_id_aa64isar0); | |
627 | taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, | |
628 | info->reg_id_aa64isar1, boot->reg_id_aa64isar1); | |
629 | ||
630 | /* | |
631 | * Differing PARange support is fine as long as all peripherals and | |
632 | * memory are mapped within the minimum PARange of all CPUs. | |
633 | * Linux should not care about secure memory. | |
634 | */ | |
635 | taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, | |
636 | info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); | |
637 | taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, | |
638 | info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); | |
406e3087 JM |
639 | taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, |
640 | info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); | |
3086d391 SP |
641 | |
642 | /* | |
643 | * EL3 is not our concern. | |
644 | * ID_AA64PFR1 is currently RES0. | |
645 | */ | |
646 | taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, | |
647 | info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); | |
648 | taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, | |
649 | info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); | |
650 | ||
2e0f2478 DM |
651 | taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, |
652 | info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); | |
653 | ||
3086d391 | 654 | /* |
a6dc3cd7 SP |
655 | * If we have AArch32, we care about 32-bit features for compat. |
656 | * If the system doesn't support AArch32, don't update them. | |
3086d391 | 657 | */ |
46823dd1 | 658 | if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) && |
a6dc3cd7 SP |
659 | id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { |
660 | ||
661 | taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, | |
3086d391 | 662 | info->reg_id_dfr0, boot->reg_id_dfr0); |
a6dc3cd7 | 663 | taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, |
3086d391 | 664 | info->reg_id_isar0, boot->reg_id_isar0); |
a6dc3cd7 | 665 | taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, |
3086d391 | 666 | info->reg_id_isar1, boot->reg_id_isar1); |
a6dc3cd7 | 667 | taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, |
3086d391 | 668 | info->reg_id_isar2, boot->reg_id_isar2); |
a6dc3cd7 | 669 | taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, |
3086d391 | 670 | info->reg_id_isar3, boot->reg_id_isar3); |
a6dc3cd7 | 671 | taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, |
3086d391 | 672 | info->reg_id_isar4, boot->reg_id_isar4); |
a6dc3cd7 | 673 | taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, |
3086d391 SP |
674 | info->reg_id_isar5, boot->reg_id_isar5); |
675 | ||
a6dc3cd7 SP |
676 | /* |
677 | * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and | |
678 | * ACTLR formats could differ across CPUs and therefore would have to | |
679 | * be trapped for virtualization anyway. | |
680 | */ | |
681 | taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, | |
3086d391 | 682 | info->reg_id_mmfr0, boot->reg_id_mmfr0); |
a6dc3cd7 | 683 | taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, |
3086d391 | 684 | info->reg_id_mmfr1, boot->reg_id_mmfr1); |
a6dc3cd7 | 685 | taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, |
3086d391 | 686 | info->reg_id_mmfr2, boot->reg_id_mmfr2); |
a6dc3cd7 | 687 | taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, |
3086d391 | 688 | info->reg_id_mmfr3, boot->reg_id_mmfr3); |
a6dc3cd7 | 689 | taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, |
3086d391 | 690 | info->reg_id_pfr0, boot->reg_id_pfr0); |
a6dc3cd7 | 691 | taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, |
3086d391 | 692 | info->reg_id_pfr1, boot->reg_id_pfr1); |
a6dc3cd7 | 693 | taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, |
3086d391 | 694 | info->reg_mvfr0, boot->reg_mvfr0); |
a6dc3cd7 | 695 | taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, |
3086d391 | 696 | info->reg_mvfr1, boot->reg_mvfr1); |
a6dc3cd7 | 697 | taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, |
3086d391 | 698 | info->reg_mvfr2, boot->reg_mvfr2); |
a6dc3cd7 | 699 | } |
3086d391 | 700 | |
2e0f2478 DM |
701 | if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { |
702 | taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu, | |
703 | info->reg_zcr, boot->reg_zcr); | |
704 | ||
705 | /* Probe vector lengths, unless we already gave up on SVE */ | |
706 | if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) && | |
707 | !sys_caps_initialised) | |
708 | sve_update_vq_map(); | |
709 | } | |
710 | ||
3086d391 SP |
711 | /* |
712 | * Mismatched CPU features are a recipe for disaster. Don't even | |
713 | * pretend to support them. | |
714 | */ | |
8dd0ee65 WD |
715 | if (taint) { |
716 | pr_warn_once("Unsupported CPU feature variation detected.\n"); | |
717 | add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); | |
718 | } | |
cdcf817b SP |
719 | } |
720 | ||
46823dd1 | 721 | u64 read_sanitised_ftr_reg(u32 id) |
b3f15378 SP |
722 | { |
723 | struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); | |
724 | ||
725 | /* We shouldn't get a request for an unsupported register */ | |
726 | BUG_ON(!regp); | |
727 | return regp->sys_val; | |
728 | } | |
359b7064 | 729 | |
965861d6 MR |
730 | #define read_sysreg_case(r) \ |
731 | case r: return read_sysreg_s(r) | |
732 | ||
92406f0c | 733 | /* |
46823dd1 | 734 | * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. |
92406f0c SP |
735 | * Read the system register on the current CPU |
736 | */ | |
46823dd1 | 737 | static u64 __read_sysreg_by_encoding(u32 sys_id) |
92406f0c SP |
738 | { |
739 | switch (sys_id) { | |
965861d6 MR |
740 | read_sysreg_case(SYS_ID_PFR0_EL1); |
741 | read_sysreg_case(SYS_ID_PFR1_EL1); | |
742 | read_sysreg_case(SYS_ID_DFR0_EL1); | |
743 | read_sysreg_case(SYS_ID_MMFR0_EL1); | |
744 | read_sysreg_case(SYS_ID_MMFR1_EL1); | |
745 | read_sysreg_case(SYS_ID_MMFR2_EL1); | |
746 | read_sysreg_case(SYS_ID_MMFR3_EL1); | |
747 | read_sysreg_case(SYS_ID_ISAR0_EL1); | |
748 | read_sysreg_case(SYS_ID_ISAR1_EL1); | |
749 | read_sysreg_case(SYS_ID_ISAR2_EL1); | |
750 | read_sysreg_case(SYS_ID_ISAR3_EL1); | |
751 | read_sysreg_case(SYS_ID_ISAR4_EL1); | |
752 | read_sysreg_case(SYS_ID_ISAR5_EL1); | |
753 | read_sysreg_case(SYS_MVFR0_EL1); | |
754 | read_sysreg_case(SYS_MVFR1_EL1); | |
755 | read_sysreg_case(SYS_MVFR2_EL1); | |
756 | ||
757 | read_sysreg_case(SYS_ID_AA64PFR0_EL1); | |
758 | read_sysreg_case(SYS_ID_AA64PFR1_EL1); | |
759 | read_sysreg_case(SYS_ID_AA64DFR0_EL1); | |
760 | read_sysreg_case(SYS_ID_AA64DFR1_EL1); | |
761 | read_sysreg_case(SYS_ID_AA64MMFR0_EL1); | |
762 | read_sysreg_case(SYS_ID_AA64MMFR1_EL1); | |
763 | read_sysreg_case(SYS_ID_AA64MMFR2_EL1); | |
764 | read_sysreg_case(SYS_ID_AA64ISAR0_EL1); | |
765 | read_sysreg_case(SYS_ID_AA64ISAR1_EL1); | |
766 | ||
767 | read_sysreg_case(SYS_CNTFRQ_EL0); | |
768 | read_sysreg_case(SYS_CTR_EL0); | |
769 | read_sysreg_case(SYS_DCZID_EL0); | |
770 | ||
92406f0c SP |
771 | default: |
772 | BUG(); | |
773 | return 0; | |
774 | } | |
775 | } | |
776 | ||
963fcd40 MZ |
777 | #include <linux/irqchip/arm-gic-v3.h> |
778 | ||
18ffa046 JM |
779 | static bool |
780 | feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) | |
781 | { | |
28c5dcb2 | 782 | int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign); |
18ffa046 JM |
783 | |
784 | return val >= entry->min_field_value; | |
785 | } | |
786 | ||
da8d02d1 | 787 | static bool |
92406f0c | 788 | has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) |
da8d02d1 SP |
789 | { |
790 | u64 val; | |
94a9e04a | 791 | |
92406f0c SP |
792 | WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); |
793 | if (scope == SCOPE_SYSTEM) | |
46823dd1 | 794 | val = read_sanitised_ftr_reg(entry->sys_reg); |
92406f0c | 795 | else |
46823dd1 | 796 | val = __read_sysreg_by_encoding(entry->sys_reg); |
92406f0c | 797 | |
da8d02d1 SP |
798 | return feature_matches(val, entry); |
799 | } | |
338d4f49 | 800 | |
92406f0c | 801 | static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) |
963fcd40 MZ |
802 | { |
803 | bool has_sre; | |
804 | ||
92406f0c | 805 | if (!has_cpuid_feature(entry, scope)) |
963fcd40 MZ |
806 | return false; |
807 | ||
808 | has_sre = gic_enable_sre(); | |
809 | if (!has_sre) | |
810 | pr_warn_once("%s present but disabled by higher exception level\n", | |
811 | entry->desc); | |
812 | ||
813 | return has_sre; | |
814 | } | |
815 | ||
92406f0c | 816 | static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) |
d5370f75 WD |
817 | { |
818 | u32 midr = read_cpuid_id(); | |
d5370f75 WD |
819 | |
820 | /* Cavium ThunderX pass 1.x and 2.x */ | |
fa5ce3d1 RR |
821 | return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, |
822 | MIDR_CPU_VAR_REV(0, 0), | |
823 | MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); | |
d5370f75 WD |
824 | } |
825 | ||
92406f0c | 826 | static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) |
d88701be MZ |
827 | { |
828 | return is_kernel_in_hyp_mode(); | |
829 | } | |
830 | ||
d1745910 MZ |
831 | static bool hyp_offset_low(const struct arm64_cpu_capabilities *entry, |
832 | int __unused) | |
833 | { | |
2077be67 | 834 | phys_addr_t idmap_addr = __pa_symbol(__hyp_idmap_text_start); |
d1745910 MZ |
835 | |
836 | /* | |
837 | * Activate the lower HYP offset only if: | |
838 | * - the idmap doesn't clash with it, | |
839 | * - the kernel is not running at EL2. | |
840 | */ | |
841 | return idmap_addr > GENMASK(VA_BITS - 2, 0) && !is_kernel_in_hyp_mode(); | |
842 | } | |
843 | ||
82e0191a SP |
844 | static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused) |
845 | { | |
46823dd1 | 846 | u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); |
82e0191a SP |
847 | |
848 | return cpuid_feature_extract_signed_field(pfr0, | |
849 | ID_AA64PFR0_FP_SHIFT) < 0; | |
850 | } | |
851 | ||
ea1e3de8 WD |
852 | #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 |
853 | static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ | |
854 | ||
855 | static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, | |
856 | int __unused) | |
857 | { | |
179a56f6 WD |
858 | u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); |
859 | ||
ea1e3de8 WD |
860 | /* Forced on command line? */ |
861 | if (__kpti_forced) { | |
862 | pr_info_once("kernel page table isolation forced %s by command line option\n", | |
863 | __kpti_forced > 0 ? "ON" : "OFF"); | |
864 | return __kpti_forced > 0; | |
865 | } | |
866 | ||
867 | /* Useful for KASLR robustness */ | |
868 | if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) | |
869 | return true; | |
870 | ||
0ba2e29c J |
871 | /* Don't force KPTI for CPUs that are not vulnerable */ |
872 | switch (read_cpuid_id() & MIDR_CPU_MODEL_MASK) { | |
873 | case MIDR_CAVIUM_THUNDERX2: | |
874 | case MIDR_BRCM_VULCAN: | |
875 | return false; | |
876 | } | |
877 | ||
179a56f6 WD |
878 | /* Defer to CPU feature registers */ |
879 | return !cpuid_feature_extract_unsigned_field(pfr0, | |
880 | ID_AA64PFR0_CSV3_SHIFT); | |
ea1e3de8 WD |
881 | } |
882 | ||
883 | static int __init parse_kpti(char *str) | |
884 | { | |
885 | bool enabled; | |
886 | int ret = strtobool(str, &enabled); | |
887 | ||
888 | if (ret) | |
889 | return ret; | |
890 | ||
891 | __kpti_forced = enabled ? 1 : -1; | |
892 | return 0; | |
893 | } | |
894 | __setup("kpti=", parse_kpti); | |
895 | #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ | |
896 | ||
6d99b689 JM |
897 | static int cpu_copy_el2regs(void *__unused) |
898 | { | |
899 | /* | |
900 | * Copy register values that aren't redirected by hardware. | |
901 | * | |
902 | * Before code patching, we only set tpidr_el1, all CPUs need to copy | |
903 | * this value to tpidr_el2 before we patch the code. Once we've done | |
904 | * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to | |
905 | * do anything here. | |
906 | */ | |
907 | if (!alternatives_applied) | |
908 | write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); | |
909 | ||
910 | return 0; | |
911 | } | |
912 | ||
359b7064 | 913 | static const struct arm64_cpu_capabilities arm64_features[] = { |
94a9e04a MZ |
914 | { |
915 | .desc = "GIC system register CPU interface", | |
916 | .capability = ARM64_HAS_SYSREG_GIC_CPUIF, | |
92406f0c | 917 | .def_scope = SCOPE_SYSTEM, |
963fcd40 | 918 | .matches = has_useable_gicv3_cpuif, |
da8d02d1 SP |
919 | .sys_reg = SYS_ID_AA64PFR0_EL1, |
920 | .field_pos = ID_AA64PFR0_GIC_SHIFT, | |
ff96f7bc | 921 | .sign = FTR_UNSIGNED, |
18ffa046 | 922 | .min_field_value = 1, |
94a9e04a | 923 | }, |
338d4f49 JM |
924 | #ifdef CONFIG_ARM64_PAN |
925 | { | |
926 | .desc = "Privileged Access Never", | |
927 | .capability = ARM64_HAS_PAN, | |
92406f0c | 928 | .def_scope = SCOPE_SYSTEM, |
da8d02d1 SP |
929 | .matches = has_cpuid_feature, |
930 | .sys_reg = SYS_ID_AA64MMFR1_EL1, | |
931 | .field_pos = ID_AA64MMFR1_PAN_SHIFT, | |
ff96f7bc | 932 | .sign = FTR_UNSIGNED, |
338d4f49 JM |
933 | .min_field_value = 1, |
934 | .enable = cpu_enable_pan, | |
935 | }, | |
936 | #endif /* CONFIG_ARM64_PAN */ | |
2e94da13 WD |
937 | #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS) |
938 | { | |
939 | .desc = "LSE atomic instructions", | |
940 | .capability = ARM64_HAS_LSE_ATOMICS, | |
92406f0c | 941 | .def_scope = SCOPE_SYSTEM, |
da8d02d1 SP |
942 | .matches = has_cpuid_feature, |
943 | .sys_reg = SYS_ID_AA64ISAR0_EL1, | |
944 | .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, | |
ff96f7bc | 945 | .sign = FTR_UNSIGNED, |
2e94da13 WD |
946 | .min_field_value = 2, |
947 | }, | |
948 | #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */ | |
d5370f75 WD |
949 | { |
950 | .desc = "Software prefetching using PRFM", | |
951 | .capability = ARM64_HAS_NO_HW_PREFETCH, | |
92406f0c | 952 | .def_scope = SCOPE_SYSTEM, |
d5370f75 WD |
953 | .matches = has_no_hw_prefetch, |
954 | }, | |
57f4959b JM |
955 | #ifdef CONFIG_ARM64_UAO |
956 | { | |
957 | .desc = "User Access Override", | |
958 | .capability = ARM64_HAS_UAO, | |
92406f0c | 959 | .def_scope = SCOPE_SYSTEM, |
57f4959b JM |
960 | .matches = has_cpuid_feature, |
961 | .sys_reg = SYS_ID_AA64MMFR2_EL1, | |
962 | .field_pos = ID_AA64MMFR2_UAO_SHIFT, | |
963 | .min_field_value = 1, | |
c8b06e3f JM |
964 | /* |
965 | * We rely on stop_machine() calling uao_thread_switch() to set | |
966 | * UAO immediately after patching. | |
967 | */ | |
57f4959b JM |
968 | }, |
969 | #endif /* CONFIG_ARM64_UAO */ | |
70544196 JM |
970 | #ifdef CONFIG_ARM64_PAN |
971 | { | |
972 | .capability = ARM64_ALT_PAN_NOT_UAO, | |
92406f0c | 973 | .def_scope = SCOPE_SYSTEM, |
70544196 JM |
974 | .matches = cpufeature_pan_not_uao, |
975 | }, | |
976 | #endif /* CONFIG_ARM64_PAN */ | |
d88701be MZ |
977 | { |
978 | .desc = "Virtualization Host Extensions", | |
979 | .capability = ARM64_HAS_VIRT_HOST_EXTN, | |
92406f0c | 980 | .def_scope = SCOPE_SYSTEM, |
d88701be | 981 | .matches = runs_at_el2, |
6d99b689 | 982 | .enable = cpu_copy_el2regs, |
d88701be | 983 | }, |
042446a3 SP |
984 | { |
985 | .desc = "32-bit EL0 Support", | |
986 | .capability = ARM64_HAS_32BIT_EL0, | |
92406f0c | 987 | .def_scope = SCOPE_SYSTEM, |
042446a3 SP |
988 | .matches = has_cpuid_feature, |
989 | .sys_reg = SYS_ID_AA64PFR0_EL1, | |
990 | .sign = FTR_UNSIGNED, | |
991 | .field_pos = ID_AA64PFR0_EL0_SHIFT, | |
992 | .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT, | |
993 | }, | |
d1745910 MZ |
994 | { |
995 | .desc = "Reduced HYP mapping offset", | |
996 | .capability = ARM64_HYP_OFFSET_LOW, | |
997 | .def_scope = SCOPE_SYSTEM, | |
998 | .matches = hyp_offset_low, | |
999 | }, | |
ea1e3de8 WD |
1000 | #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 |
1001 | { | |
179a56f6 | 1002 | .desc = "Kernel page table isolation (KPTI)", |
ea1e3de8 WD |
1003 | .capability = ARM64_UNMAP_KERNEL_AT_EL0, |
1004 | .def_scope = SCOPE_SYSTEM, | |
1005 | .matches = unmap_kernel_at_el0, | |
1006 | }, | |
1007 | #endif | |
82e0191a SP |
1008 | { |
1009 | /* FP/SIMD is not implemented */ | |
1010 | .capability = ARM64_HAS_NO_FPSIMD, | |
1011 | .def_scope = SCOPE_SYSTEM, | |
1012 | .min_field_value = 0, | |
1013 | .matches = has_no_fpsimd, | |
1014 | }, | |
d50e071f RM |
1015 | #ifdef CONFIG_ARM64_PMEM |
1016 | { | |
1017 | .desc = "Data cache clean to Point of Persistence", | |
1018 | .capability = ARM64_HAS_DCPOP, | |
1019 | .def_scope = SCOPE_SYSTEM, | |
1020 | .matches = has_cpuid_feature, | |
1021 | .sys_reg = SYS_ID_AA64ISAR1_EL1, | |
1022 | .field_pos = ID_AA64ISAR1_DPB_SHIFT, | |
1023 | .min_field_value = 1, | |
1024 | }, | |
1025 | #endif | |
43994d82 DM |
1026 | #ifdef CONFIG_ARM64_SVE |
1027 | { | |
1028 | .desc = "Scalable Vector Extension", | |
1029 | .capability = ARM64_SVE, | |
1030 | .def_scope = SCOPE_SYSTEM, | |
1031 | .sys_reg = SYS_ID_AA64PFR0_EL1, | |
1032 | .sign = FTR_UNSIGNED, | |
1033 | .field_pos = ID_AA64PFR0_SVE_SHIFT, | |
1034 | .min_field_value = ID_AA64PFR0_SVE, | |
1035 | .matches = has_cpuid_feature, | |
1036 | .enable = sve_kernel_enable, | |
1037 | }, | |
1038 | #endif /* CONFIG_ARM64_SVE */ | |
64c02720 XX |
1039 | #ifdef CONFIG_ARM64_RAS_EXTN |
1040 | { | |
1041 | .desc = "RAS Extension Support", | |
1042 | .capability = ARM64_HAS_RAS_EXTN, | |
1043 | .def_scope = SCOPE_SYSTEM, | |
1044 | .matches = has_cpuid_feature, | |
1045 | .sys_reg = SYS_ID_AA64PFR0_EL1, | |
1046 | .sign = FTR_UNSIGNED, | |
1047 | .field_pos = ID_AA64PFR0_RAS_SHIFT, | |
1048 | .min_field_value = ID_AA64PFR0_RAS_V1, | |
68ddbf09 | 1049 | .enable = cpu_clear_disr, |
64c02720 XX |
1050 | }, |
1051 | #endif /* CONFIG_ARM64_RAS_EXTN */ | |
359b7064 MZ |
1052 | {}, |
1053 | }; | |
1054 | ||
ff96f7bc | 1055 | #define HWCAP_CAP(reg, field, s, min_value, type, cap) \ |
37b01d53 SP |
1056 | { \ |
1057 | .desc = #cap, \ | |
92406f0c | 1058 | .def_scope = SCOPE_SYSTEM, \ |
37b01d53 SP |
1059 | .matches = has_cpuid_feature, \ |
1060 | .sys_reg = reg, \ | |
1061 | .field_pos = field, \ | |
ff96f7bc | 1062 | .sign = s, \ |
37b01d53 SP |
1063 | .min_field_value = min_value, \ |
1064 | .hwcap_type = type, \ | |
1065 | .hwcap = cap, \ | |
1066 | } | |
1067 | ||
f3efb675 | 1068 | static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { |
ff96f7bc SP |
1069 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL), |
1070 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES), | |
1071 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1), | |
1072 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2), | |
f5e035f8 | 1073 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_SHA512), |
ff96f7bc SP |
1074 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32), |
1075 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS), | |
f92f5ce0 | 1076 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM), |
f5e035f8 SP |
1077 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA3), |
1078 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM3), | |
1079 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM4), | |
1080 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDDP), | |
3b3b6810 | 1081 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDFHM), |
ff96f7bc | 1082 | HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP), |
bf500618 | 1083 | HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP), |
ff96f7bc | 1084 | HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD), |
bf500618 | 1085 | HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP), |
7aac405e | 1086 | HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_DCPOP), |
c8c3798d | 1087 | HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT), |
cb567e79 | 1088 | HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA), |
c651aae5 | 1089 | HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC), |
43994d82 DM |
1090 | #ifdef CONFIG_ARM64_SVE |
1091 | HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, HWCAP_SVE), | |
1092 | #endif | |
75283501 SP |
1093 | {}, |
1094 | }; | |
1095 | ||
1096 | static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { | |
37b01d53 | 1097 | #ifdef CONFIG_COMPAT |
ff96f7bc SP |
1098 | HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), |
1099 | HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), | |
1100 | HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), | |
1101 | HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), | |
1102 | HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), | |
37b01d53 SP |
1103 | #endif |
1104 | {}, | |
1105 | }; | |
1106 | ||
f3efb675 | 1107 | static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) |
37b01d53 SP |
1108 | { |
1109 | switch (cap->hwcap_type) { | |
1110 | case CAP_HWCAP: | |
1111 | elf_hwcap |= cap->hwcap; | |
1112 | break; | |
1113 | #ifdef CONFIG_COMPAT | |
1114 | case CAP_COMPAT_HWCAP: | |
1115 | compat_elf_hwcap |= (u32)cap->hwcap; | |
1116 | break; | |
1117 | case CAP_COMPAT_HWCAP2: | |
1118 | compat_elf_hwcap2 |= (u32)cap->hwcap; | |
1119 | break; | |
1120 | #endif | |
1121 | default: | |
1122 | WARN_ON(1); | |
1123 | break; | |
1124 | } | |
1125 | } | |
1126 | ||
1127 | /* Check if we have a particular HWCAP enabled */ | |
f3efb675 | 1128 | static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) |
37b01d53 SP |
1129 | { |
1130 | bool rc; | |
1131 | ||
1132 | switch (cap->hwcap_type) { | |
1133 | case CAP_HWCAP: | |
1134 | rc = (elf_hwcap & cap->hwcap) != 0; | |
1135 | break; | |
1136 | #ifdef CONFIG_COMPAT | |
1137 | case CAP_COMPAT_HWCAP: | |
1138 | rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; | |
1139 | break; | |
1140 | case CAP_COMPAT_HWCAP2: | |
1141 | rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; | |
1142 | break; | |
1143 | #endif | |
1144 | default: | |
1145 | WARN_ON(1); | |
1146 | rc = false; | |
1147 | } | |
1148 | ||
1149 | return rc; | |
1150 | } | |
1151 | ||
75283501 | 1152 | static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) |
37b01d53 | 1153 | { |
77c97b4e SP |
1154 | /* We support emulation of accesses to CPU ID feature registers */ |
1155 | elf_hwcap |= HWCAP_CPUID; | |
75283501 | 1156 | for (; hwcaps->matches; hwcaps++) |
92406f0c | 1157 | if (hwcaps->matches(hwcaps, hwcaps->def_scope)) |
75283501 | 1158 | cap_set_elf_hwcap(hwcaps); |
37b01d53 SP |
1159 | } |
1160 | ||
67948af4 SP |
1161 | /* |
1162 | * Check if the current CPU has a given feature capability. | |
1163 | * Should be called from non-preemptible context. | |
1164 | */ | |
1165 | static bool __this_cpu_has_cap(const struct arm64_cpu_capabilities *cap_array, | |
1166 | unsigned int cap) | |
1167 | { | |
1168 | const struct arm64_cpu_capabilities *caps; | |
1169 | ||
1170 | if (WARN_ON(preemptible())) | |
1171 | return false; | |
1172 | ||
edf298cf | 1173 | for (caps = cap_array; caps->matches; caps++) |
67948af4 | 1174 | if (caps->capability == cap && |
67948af4 SP |
1175 | caps->matches(caps, SCOPE_LOCAL_CPU)) |
1176 | return true; | |
1177 | return false; | |
1178 | } | |
1179 | ||
ce8b602c | 1180 | void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps, |
359b7064 MZ |
1181 | const char *info) |
1182 | { | |
75283501 | 1183 | for (; caps->matches; caps++) { |
92406f0c | 1184 | if (!caps->matches(caps, caps->def_scope)) |
359b7064 MZ |
1185 | continue; |
1186 | ||
75283501 SP |
1187 | if (!cpus_have_cap(caps->capability) && caps->desc) |
1188 | pr_info("%s %s\n", info, caps->desc); | |
1189 | cpus_set_cap(caps->capability); | |
359b7064 | 1190 | } |
ce8b602c SP |
1191 | } |
1192 | ||
1193 | /* | |
dbb4e152 SP |
1194 | * Run through the enabled capabilities and enable() it on all active |
1195 | * CPUs | |
ce8b602c | 1196 | */ |
8e231852 | 1197 | void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps) |
ce8b602c | 1198 | { |
63a1e1c9 MR |
1199 | for (; caps->matches; caps++) { |
1200 | unsigned int num = caps->capability; | |
1201 | ||
1202 | if (!cpus_have_cap(num)) | |
1203 | continue; | |
1204 | ||
1205 | /* Ensure cpus_have_const_cap(num) works */ | |
1206 | static_branch_enable(&cpu_hwcap_keys[num]); | |
1207 | ||
1208 | if (caps->enable) { | |
2a6dcb2b JM |
1209 | /* |
1210 | * Use stop_machine() as it schedules the work allowing | |
1211 | * us to modify PSTATE, instead of on_each_cpu() which | |
1212 | * uses an IPI, giving us a PSTATE that disappears when | |
1213 | * we return. | |
1214 | */ | |
0a0d111d | 1215 | stop_machine(caps->enable, (void *)caps, cpu_online_mask); |
63a1e1c9 MR |
1216 | } |
1217 | } | |
dbb4e152 SP |
1218 | } |
1219 | ||
dbb4e152 | 1220 | /* |
13f417f3 SP |
1221 | * Check for CPU features that are used in early boot |
1222 | * based on the Boot CPU value. | |
dbb4e152 | 1223 | */ |
13f417f3 | 1224 | static void check_early_cpu_features(void) |
dbb4e152 | 1225 | { |
ac1ad20f | 1226 | verify_cpu_run_el(); |
13f417f3 | 1227 | verify_cpu_asid_bits(); |
dbb4e152 | 1228 | } |
1c076303 | 1229 | |
75283501 SP |
1230 | static void |
1231 | verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) | |
1232 | { | |
1233 | ||
92406f0c SP |
1234 | for (; caps->matches; caps++) |
1235 | if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { | |
75283501 SP |
1236 | pr_crit("CPU%d: missing HWCAP: %s\n", |
1237 | smp_processor_id(), caps->desc); | |
1238 | cpu_die_early(); | |
1239 | } | |
75283501 SP |
1240 | } |
1241 | ||
1242 | static void | |
67948af4 | 1243 | verify_local_cpu_features(const struct arm64_cpu_capabilities *caps_list) |
75283501 | 1244 | { |
67948af4 | 1245 | const struct arm64_cpu_capabilities *caps = caps_list; |
75283501 | 1246 | for (; caps->matches; caps++) { |
92406f0c | 1247 | if (!cpus_have_cap(caps->capability)) |
75283501 SP |
1248 | continue; |
1249 | /* | |
1250 | * If the new CPU misses an advertised feature, we cannot proceed | |
1251 | * further, park the cpu. | |
1252 | */ | |
67948af4 | 1253 | if (!__this_cpu_has_cap(caps_list, caps->capability)) { |
75283501 SP |
1254 | pr_crit("CPU%d: missing feature: %s\n", |
1255 | smp_processor_id(), caps->desc); | |
1256 | cpu_die_early(); | |
1257 | } | |
1258 | if (caps->enable) | |
0a0d111d | 1259 | caps->enable((void *)caps); |
75283501 SP |
1260 | } |
1261 | } | |
1262 | ||
2e0f2478 DM |
1263 | static void verify_sve_features(void) |
1264 | { | |
1265 | u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); | |
1266 | u64 zcr = read_zcr_features(); | |
1267 | ||
1268 | unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK; | |
1269 | unsigned int len = zcr & ZCR_ELx_LEN_MASK; | |
1270 | ||
1271 | if (len < safe_len || sve_verify_vq_map()) { | |
1272 | pr_crit("CPU%d: SVE: required vector length(s) missing\n", | |
1273 | smp_processor_id()); | |
1274 | cpu_die_early(); | |
1275 | } | |
1276 | ||
1277 | /* Add checks on other ZCR bits here if necessary */ | |
1278 | } | |
1279 | ||
dbb4e152 SP |
1280 | /* |
1281 | * Run through the enabled system capabilities and enable() it on this CPU. | |
1282 | * The capabilities were decided based on the available CPUs at the boot time. | |
1283 | * Any new CPU should match the system wide status of the capability. If the | |
1284 | * new CPU doesn't have a capability which the system now has enabled, we | |
1285 | * cannot do anything to fix it up and could cause unexpected failures. So | |
1286 | * we park the CPU. | |
1287 | */ | |
c47a1900 | 1288 | static void verify_local_cpu_capabilities(void) |
dbb4e152 | 1289 | { |
c47a1900 SP |
1290 | verify_local_cpu_errata_workarounds(); |
1291 | verify_local_cpu_features(arm64_features); | |
1292 | verify_local_elf_hwcaps(arm64_elf_hwcaps); | |
2e0f2478 | 1293 | |
c47a1900 SP |
1294 | if (system_supports_32bit_el0()) |
1295 | verify_local_elf_hwcaps(compat_elf_hwcaps); | |
2e0f2478 DM |
1296 | |
1297 | if (system_supports_sve()) | |
1298 | verify_sve_features(); | |
894cfd14 SB |
1299 | |
1300 | if (system_uses_ttbr0_pan()) | |
1301 | pr_info("Emulating Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); | |
c47a1900 | 1302 | } |
dbb4e152 | 1303 | |
c47a1900 SP |
1304 | void check_local_cpu_capabilities(void) |
1305 | { | |
1306 | /* | |
1307 | * All secondary CPUs should conform to the early CPU features | |
1308 | * in use by the kernel based on boot CPU. | |
1309 | */ | |
13f417f3 SP |
1310 | check_early_cpu_features(); |
1311 | ||
dbb4e152 | 1312 | /* |
c47a1900 SP |
1313 | * If we haven't finalised the system capabilities, this CPU gets |
1314 | * a chance to update the errata work arounds. | |
1315 | * Otherwise, this CPU should verify that it has all the system | |
1316 | * advertised capabilities. | |
dbb4e152 SP |
1317 | */ |
1318 | if (!sys_caps_initialised) | |
c47a1900 SP |
1319 | update_cpu_errata_workarounds(); |
1320 | else | |
1321 | verify_local_cpu_capabilities(); | |
359b7064 MZ |
1322 | } |
1323 | ||
a7c61a34 | 1324 | static void __init setup_feature_capabilities(void) |
359b7064 | 1325 | { |
ce8b602c SP |
1326 | update_cpu_capabilities(arm64_features, "detected feature:"); |
1327 | enable_cpu_capabilities(arm64_features); | |
359b7064 MZ |
1328 | } |
1329 | ||
63a1e1c9 MR |
1330 | DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready); |
1331 | EXPORT_SYMBOL(arm64_const_caps_ready); | |
1332 | ||
1333 | static void __init mark_const_caps_ready(void) | |
1334 | { | |
1335 | static_branch_enable(&arm64_const_caps_ready); | |
1336 | } | |
1337 | ||
8f413758 MZ |
1338 | extern const struct arm64_cpu_capabilities arm64_errata[]; |
1339 | ||
1340 | bool this_cpu_has_cap(unsigned int cap) | |
1341 | { | |
1342 | return (__this_cpu_has_cap(arm64_features, cap) || | |
1343 | __this_cpu_has_cap(arm64_errata, cap)); | |
1344 | } | |
1345 | ||
9cdf8ec4 | 1346 | void __init setup_cpu_features(void) |
359b7064 | 1347 | { |
9cdf8ec4 SP |
1348 | u32 cwg; |
1349 | int cls; | |
1350 | ||
dbb4e152 SP |
1351 | /* Set the CPU feature capabilies */ |
1352 | setup_feature_capabilities(); | |
8e231852 | 1353 | enable_errata_workarounds(); |
63a1e1c9 | 1354 | mark_const_caps_ready(); |
75283501 | 1355 | setup_elf_hwcaps(arm64_elf_hwcaps); |
643d703d SP |
1356 | |
1357 | if (system_supports_32bit_el0()) | |
1358 | setup_elf_hwcaps(compat_elf_hwcaps); | |
dbb4e152 | 1359 | |
2e0f2478 DM |
1360 | sve_setup(); |
1361 | ||
dbb4e152 SP |
1362 | /* Advertise that we have computed the system capabilities */ |
1363 | set_sys_caps_initialised(); | |
1364 | ||
9cdf8ec4 SP |
1365 | /* |
1366 | * Check for sane CTR_EL0.CWG value. | |
1367 | */ | |
1368 | cwg = cache_type_cwg(); | |
1369 | cls = cache_line_size(); | |
1370 | if (!cwg) | |
1371 | pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n", | |
1372 | cls); | |
1373 | if (L1_CACHE_BYTES < cls) | |
1374 | pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n", | |
1375 | L1_CACHE_BYTES, cls); | |
359b7064 | 1376 | } |
70544196 JM |
1377 | |
1378 | static bool __maybe_unused | |
92406f0c | 1379 | cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused) |
70544196 | 1380 | { |
a4023f68 | 1381 | return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO)); |
70544196 | 1382 | } |
77c97b4e SP |
1383 | |
1384 | /* | |
1385 | * We emulate only the following system register space. | |
1386 | * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7] | |
1387 | * See Table C5-6 System instruction encodings for System register accesses, | |
1388 | * ARMv8 ARM(ARM DDI 0487A.f) for more details. | |
1389 | */ | |
1390 | static inline bool __attribute_const__ is_emulated(u32 id) | |
1391 | { | |
1392 | return (sys_reg_Op0(id) == 0x3 && | |
1393 | sys_reg_CRn(id) == 0x0 && | |
1394 | sys_reg_Op1(id) == 0x0 && | |
1395 | (sys_reg_CRm(id) == 0 || | |
1396 | ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7)))); | |
1397 | } | |
1398 | ||
1399 | /* | |
1400 | * With CRm == 0, reg should be one of : | |
1401 | * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. | |
1402 | */ | |
1403 | static inline int emulate_id_reg(u32 id, u64 *valp) | |
1404 | { | |
1405 | switch (id) { | |
1406 | case SYS_MIDR_EL1: | |
1407 | *valp = read_cpuid_id(); | |
1408 | break; | |
1409 | case SYS_MPIDR_EL1: | |
1410 | *valp = SYS_MPIDR_SAFE_VAL; | |
1411 | break; | |
1412 | case SYS_REVIDR_EL1: | |
1413 | /* IMPLEMENTATION DEFINED values are emulated with 0 */ | |
1414 | *valp = 0; | |
1415 | break; | |
1416 | default: | |
1417 | return -EINVAL; | |
1418 | } | |
1419 | ||
1420 | return 0; | |
1421 | } | |
1422 | ||
1423 | static int emulate_sys_reg(u32 id, u64 *valp) | |
1424 | { | |
1425 | struct arm64_ftr_reg *regp; | |
1426 | ||
1427 | if (!is_emulated(id)) | |
1428 | return -EINVAL; | |
1429 | ||
1430 | if (sys_reg_CRm(id) == 0) | |
1431 | return emulate_id_reg(id, valp); | |
1432 | ||
1433 | regp = get_arm64_ftr_reg(id); | |
1434 | if (regp) | |
1435 | *valp = arm64_ftr_reg_user_value(regp); | |
1436 | else | |
1437 | /* | |
1438 | * The untracked registers are either IMPLEMENTATION DEFINED | |
1439 | * (e.g, ID_AFR0_EL1) or reserved RAZ. | |
1440 | */ | |
1441 | *valp = 0; | |
1442 | return 0; | |
1443 | } | |
1444 | ||
1445 | static int emulate_mrs(struct pt_regs *regs, u32 insn) | |
1446 | { | |
1447 | int rc; | |
1448 | u32 sys_reg, dst; | |
1449 | u64 val; | |
1450 | ||
1451 | /* | |
1452 | * sys_reg values are defined as used in mrs/msr instruction. | |
1453 | * shift the imm value to get the encoding. | |
1454 | */ | |
1455 | sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; | |
1456 | rc = emulate_sys_reg(sys_reg, &val); | |
1457 | if (!rc) { | |
1458 | dst = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); | |
521c6461 | 1459 | pt_regs_write_reg(regs, dst, val); |
6436beee | 1460 | arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); |
77c97b4e SP |
1461 | } |
1462 | ||
1463 | return rc; | |
1464 | } | |
1465 | ||
1466 | static struct undef_hook mrs_hook = { | |
1467 | .instr_mask = 0xfff00000, | |
1468 | .instr_val = 0xd5300000, | |
1469 | .pstate_mask = COMPAT_PSR_MODE_MASK, | |
1470 | .pstate_val = PSR_MODE_EL0t, | |
1471 | .fn = emulate_mrs, | |
1472 | }; | |
1473 | ||
1474 | static int __init enable_mrs_emulation(void) | |
1475 | { | |
1476 | register_undef_hook(&mrs_hook); | |
1477 | return 0; | |
1478 | } | |
1479 | ||
c0d8832e | 1480 | core_initcall(enable_mrs_emulation); |
68ddbf09 JM |
1481 | |
1482 | int cpu_clear_disr(void *__unused) | |
1483 | { | |
1484 | /* Firmware may have left a deferred SError in this register. */ | |
1485 | write_sysreg_s(0, SYS_DISR_EL1); | |
1486 | ||
1487 | return 0; | |
1488 | } |