]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - arch/arm64/kernel/cpufeature.c
projects / mirror_ubuntu-jammy-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
arm64: cpufeature: ctr: Fix cpu capability check for late CPUs
[mirror_ubuntu-jammy-kernel.git] / arch / arm64 / kernel / cpufeature.c
CommitLineData
359b7064
MZ		 1/*
2 * Contains CPU feature definitions
3 *
4 * Copyright (C) 2015 ARM Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
9cdf8ec4 19#define pr_fmt(fmt) "CPU features: " fmt
359b7064 20
3c739b57 21#include <linux/bsearch.h>
2a6dcb2b 22#include <linux/cpumask.h>
5ffdfaed 23#include <linux/crash_dump.h>
3c739b57 24#include <linux/sort.h>
2a6dcb2b 25#include <linux/stop_machine.h>
359b7064 26#include <linux/types.h>
2077be67 27#include <linux/mm.h>
359b7064
MZ		 28#include <asm/cpu.h>
29#include <asm/cpufeature.h>
dbb4e152 30#include <asm/cpu_ops.h>
2e0f2478 31#include <asm/fpsimd.h>
13f417f3 32#include <asm/mmu_context.h>
338d4f49 33#include <asm/processor.h>
cdcf817b 34#include <asm/sysreg.h>
77c97b4e 35#include <asm/traps.h>
d88701be 36#include <asm/virt.h>
359b7064 37
9cdf8ec4
SP		 38unsigned long elf_hwcap __read_mostly;
39EXPORT_SYMBOL_GPL(elf_hwcap);
40
41#ifdef CONFIG_COMPAT
42#define COMPAT_ELF_HWCAP_DEFAULT \
43 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
44 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
45 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
46 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
47 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
48 COMPAT_HWCAP_LPAE)
49unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
50unsigned int compat_elf_hwcap2 __read_mostly;
51#endif
52
53DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
4b65a5db 54EXPORT_SYMBOL(cpu_hwcaps);
9cdf8ec4 55
8f1eec57
DM		 56/*
57 * Flag to indicate if we have computed the system wide
58 * capabilities based on the boot time active CPUs. This
59 * will be used to determine if a new booting CPU should
60 * go through the verification process to make sure that it
61 * supports the system capabilities, without using a hotplug
62 * notifier.
63 */
64static bool sys_caps_initialised;
65
66static inline void set_sys_caps_initialised(void)
67{
68 sys_caps_initialised = true;
69}
70
8effeaaf
MR		 71static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
72{
73 /* file-wide pr_fmt adds "CPU features: " prefix */
74 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
75 return 0;
76}
77
78static struct notifier_block cpu_hwcaps_notifier = {
79 .notifier_call = dump_cpu_hwcaps
80};
81
82static int __init register_cpu_hwcaps_dumper(void)
83{
84 atomic_notifier_chain_register(&panic_notifier_list,
85 &cpu_hwcaps_notifier);
86 return 0;
87}
88__initcall(register_cpu_hwcaps_dumper);
89
efd9e03f
CM		 90DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
91EXPORT_SYMBOL(cpu_hwcap_keys);
92
fe4fbdbc 93#define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
3c739b57 94 { \
4f0a606b 95 .sign = SIGNED, \
fe4fbdbc 96 .visible = VISIBLE, \
3c739b57
SP		 97 .strict = STRICT, \
98 .type = TYPE, \
99 .shift = SHIFT, \
100 .width = WIDTH, \
101 .safe_val = SAFE_VAL, \
102 }
103
0710cfdb 104/* Define a feature with unsigned values */
fe4fbdbc
SP		 105#define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
106 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
4f0a606b 107
0710cfdb 108/* Define a feature with a signed value */
fe4fbdbc
SP		 109#define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
110 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
0710cfdb 111
3c739b57
SP		 112#define ARM64_FTR_END \
113 { \
114 .width = 0, \
115 }
116
70544196
JM		 117/* meta feature for alternatives */
118static bool __maybe_unused
92406f0c
SP		 119cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
120
5ffdfaed 121static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
70544196 122
4aa8a472
SP		 123/*
124 * NOTE: Any changes to the visibility of features should be kept in
125 * sync with the documentation of the CPU feature register ABI.
126 */
5e49d73c 127static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
7206dc93 128 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
3b3b6810 129 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
5bdecb79
SP		 130 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
131 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
132 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
133 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
134 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
fe4fbdbc
SP		 135 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
136 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
137 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
138 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
139 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
3c739b57
SP		 140 ARM64_FTR_END,
141};
142
c8c3798d 143static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
5bdecb79
SP		 144 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
145 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
146 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
147 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
c8c3798d
SP		 148 ARM64_FTR_END,
149};
150
5e49d73c 151static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
179a56f6 152 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
0f15adbb 153 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
7206dc93 154 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
3fab3999
DM		 155 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
156 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
64c02720 157 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
5bdecb79 158 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
fe4fbdbc
SP		 159 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
160 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
3c739b57 161 /* Linux doesn't care about the EL3 */
5bdecb79
SP		 162 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
163 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
164 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
165 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
3c739b57
SP		 166 ARM64_FTR_END,
167};
168
d71be2b6
WD		 169static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
170 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
171 ARM64_FTR_END,
172};
173
5e49d73c 174static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
5bdecb79
SP		 175 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
176 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
177 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
178 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
3c739b57 179 /* Linux shouldn't care about secure memory */
5bdecb79
SP		 180 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
181 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
182 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
3c739b57
SP		 183 /*
184 * Differing PARange is fine as long as all peripherals and memory are mapped
185 * within the minimum PARange of all CPUs
186 */
fe4fbdbc 187 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
3c739b57
SP		 188 ARM64_FTR_END,
189};
190
5e49d73c 191static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
fe4fbdbc 192 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
5bdecb79
SP		 193 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
194 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
195 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
196 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
197 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
3c739b57
SP		 198 ARM64_FTR_END,
199};
200
5e49d73c 201static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
e48d53a9 202 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
7206dc93 203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
5bdecb79
SP		 204 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
205 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
206 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
207 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
208 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
406e3087
JM		 209 ARM64_FTR_END,
210};
211
5e49d73c 212static const struct arm64_ftr_bits ftr_ctr[] = {
6ae4b6e0
SD		 213 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
214 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
215 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
216 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_CWG_SHIFT, 4, 0),
217 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_ERG_SHIFT, 4, 0),
218 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
3c739b57
SP		 219 /*
220 * Linux can handle differing I-cache policies. Userspace JITs will
ee7bc638 221 * make use of *minLine.
155433cb 222 * If we have differing I-cache policies, report it as the weakest - VIPT.
3c739b57 223 */
155433cb 224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */
4c4a39dd 225 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
3c739b57
SP		 226 ARM64_FTR_END,
227};
228
675b0563
AB		 229struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
230 .name = "SYS_CTR_EL0",
231 .ftr_bits = ftr_ctr
232};
233
5e49d73c 234static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
5bdecb79
SP		 235 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf), /* InnerShr */
236 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), /* FCSE */
fe4fbdbc 237 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
5bdecb79
SP		 238 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), /* TCM */
239 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* ShareLvl */
240 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf), /* OuterShr */
241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* PMSA */
242 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* VMSA */
3c739b57
SP		 243 ARM64_FTR_END,
244};
245
5e49d73c 246static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
fe4fbdbc
SP		 247 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
248 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
249 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
250 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
251 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
b20d1ba3
WD		 252 /*
253 * We can instantiate multiple PMU instances with different levels
254 * of support.
fe4fbdbc
SP		 255 */
256 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
257 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
258 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
3c739b57
SP		 259 ARM64_FTR_END,
260};
261
5e49d73c 262static const struct arm64_ftr_bits ftr_mvfr2[] = {
5bdecb79
SP		 263 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* FPMisc */
264 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* SIMDMisc */
3c739b57
SP		 265 ARM64_FTR_END,
266};
267
5e49d73c 268static const struct arm64_ftr_bits ftr_dczid[] = {
fe4fbdbc
SP		 269 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
270 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
3c739b57
SP		 271 ARM64_FTR_END,
272};
273
274
5e49d73c 275static const struct arm64_ftr_bits ftr_id_isar5[] = {
5bdecb79
SP		 276 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
277 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
278 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
279 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
280 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
281 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
3c739b57
SP		 282 ARM64_FTR_END,
283};
284
5e49d73c 285static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
5bdecb79 286 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* ac2 */
3c739b57
SP		 287 ARM64_FTR_END,
288};
289
5e49d73c 290static const struct arm64_ftr_bits ftr_id_pfr0[] = {
5bdecb79
SP		 291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* State3 */
292 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), /* State2 */
293 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* State1 */
294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* State0 */
3c739b57
SP		 295 ARM64_FTR_END,
296};
297
5e49d73c 298static const struct arm64_ftr_bits ftr_id_dfr0[] = {
fe4fbdbc
SP		 299 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
300 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */
301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
302 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
303 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
304 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
305 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
306 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
e5343503
SP		 307 ARM64_FTR_END,
308};
309
2e0f2478
DM		 310static const struct arm64_ftr_bits ftr_zcr[] = {
311 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
312 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */
313 ARM64_FTR_END,
314};
315
3c739b57
SP		 316/*
317 * Common ftr bits for a 32bit register with all hidden, strict
318 * attributes, with 4bit feature fields and a default safe value of
319 * 0. Covers the following 32bit registers:
320 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
321 */
5e49d73c 322static const struct arm64_ftr_bits ftr_generic_32bits[] = {
fe4fbdbc
SP		 323 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
324 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
325 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
326 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
327 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
328 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
329 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
330 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
3c739b57
SP		 331 ARM64_FTR_END,
332};
333
eab43e88
SP		 334/* Table for a single 32bit feature value */
335static const struct arm64_ftr_bits ftr_single32[] = {
fe4fbdbc 336 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
3c739b57
SP		 337 ARM64_FTR_END,
338};
339
eab43e88 340static const struct arm64_ftr_bits ftr_raz[] = {
3c739b57
SP		 341 ARM64_FTR_END,
342};
343
6f2b7eef
AB		 344#define ARM64_FTR_REG(id, table) { \
345 .sys_id = id, \
346 .reg = &(struct arm64_ftr_reg){ \
3c739b57
SP		 347 .name = #id, \
348 .ftr_bits = &((table)[0]), \
6f2b7eef 349 }}
3c739b57 350
6f2b7eef
AB		 351static const struct __ftr_reg_entry {
352 u32 sys_id;
353 struct arm64_ftr_reg *reg;
354} arm64_ftr_regs[] = {
3c739b57
SP		 355
356 /* Op1 = 0, CRn = 0, CRm = 1 */
357 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
358 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
e5343503 359 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
3c739b57
SP		 360 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
361 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
362 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
363 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
364
365 /* Op1 = 0, CRn = 0, CRm = 2 */
366 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
367 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
368 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
369 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
370 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
371 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
372 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
373
374 /* Op1 = 0, CRn = 0, CRm = 3 */
375 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
376 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
377 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
378
379 /* Op1 = 0, CRn = 0, CRm = 4 */
380 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
d71be2b6 381 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
2e0f2478 382 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_raz),
3c739b57
SP		 383
384 /* Op1 = 0, CRn = 0, CRm = 5 */
385 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
eab43e88 386 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
3c739b57
SP		 387
388 /* Op1 = 0, CRn = 0, CRm = 6 */
389 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
c8c3798d 390 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
3c739b57
SP		 391
392 /* Op1 = 0, CRn = 0, CRm = 7 */
393 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
394 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
406e3087 395 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
3c739b57 396
2e0f2478
DM		 397 /* Op1 = 0, CRn = 1, CRm = 2 */
398 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
399
3c739b57 400 /* Op1 = 3, CRn = 0, CRm = 0 */
675b0563 401 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
3c739b57
SP		 402 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
403
404 /* Op1 = 3, CRn = 14, CRm = 0 */
eab43e88 405 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
3c739b57
SP		 406};
407
408static int search_cmp_ftr_reg(const void *id, const void *regp)
409{
6f2b7eef 410 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
3c739b57
SP		 411}
412
413/*
414 * get_arm64_ftr_reg - Lookup a feature register entry using its
415 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
416 * ascending order of sys_id , we use binary search to find a matching
417 * entry.
418 *
419 * returns - Upon success, matching ftr_reg entry for id.
420 * - NULL on failure. It is upto the caller to decide
421 * the impact of a failure.
422 */
423static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
424{
6f2b7eef
AB		 425 const struct __ftr_reg_entry *ret;
426
427 ret = bsearch((const void *)(unsigned long)sys_id,
3c739b57
SP		 428 arm64_ftr_regs,
429 ARRAY_SIZE(arm64_ftr_regs),
430 sizeof(arm64_ftr_regs[0]),
431 search_cmp_ftr_reg);
6f2b7eef
AB		 432 if (ret)
433 return ret->reg;
434 return NULL;
3c739b57
SP		 435}
436
5e49d73c
AB		 437static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
438 s64 ftr_val)
3c739b57
SP		 439{
440 u64 mask = arm64_ftr_mask(ftrp);
441
442 reg &= ~mask;
443 reg |= (ftr_val << ftrp->shift) & mask;
444 return reg;
445}
446
5e49d73c
AB		 447static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
448 s64 cur)
3c739b57
SP		 449{
450 s64 ret = 0;
451
452 switch (ftrp->type) {
453 case FTR_EXACT:
454 ret = ftrp->safe_val;
455 break;
456 case FTR_LOWER_SAFE:
457 ret = new < cur ? new : cur;
458 break;
459 case FTR_HIGHER_SAFE:
460 ret = new > cur ? new : cur;
461 break;
462 default:
463 BUG();
464 }
465
466 return ret;
467}
468
3c739b57
SP		 469static void __init sort_ftr_regs(void)
470{
6f2b7eef
AB		 471 int i;
472
473 /* Check that the array is sorted so that we can do the binary search */
474 for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
475 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
3c739b57
SP		 476}
477
478/*
479 * Initialise the CPU feature register from Boot CPU values.
480 * Also initiliases the strict_mask for the register.
b389d799
MR		 481 * Any bits that are not covered by an arm64_ftr_bits entry are considered
482 * RES0 for the system-wide value, and must strictly match.
3c739b57
SP		 483 */
484static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
485{
486 u64 val = 0;
487 u64 strict_mask = ~0x0ULL;
fe4fbdbc 488 u64 user_mask = 0;
b389d799
MR		 489 u64 valid_mask = 0;
490
5e49d73c 491 const struct arm64_ftr_bits *ftrp;
3c739b57
SP		 492 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
493
494 BUG_ON(!reg);
495
496 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
b389d799 497 u64 ftr_mask = arm64_ftr_mask(ftrp);
3c739b57
SP		 498 s64 ftr_new = arm64_ftr_value(ftrp, new);
499
500 val = arm64_ftr_set_value(ftrp, val, ftr_new);
b389d799
MR		 501
502 valid_mask |= ftr_mask;
3c739b57 503 if (!ftrp->strict)
b389d799 504 strict_mask &= ~ftr_mask;
fe4fbdbc
SP		 505 if (ftrp->visible)
506 user_mask |= ftr_mask;
507 else
508 reg->user_val = arm64_ftr_set_value(ftrp,
509 reg->user_val,
510 ftrp->safe_val);
3c739b57 511 }
b389d799
MR		 512
513 val &= valid_mask;
514
3c739b57
SP		 515 reg->sys_val = val;
516 reg->strict_mask = strict_mask;
fe4fbdbc 517 reg->user_mask = user_mask;
3c739b57
SP		 518}
519
1e89baed 520extern const struct arm64_cpu_capabilities arm64_errata[];
fd9d63da 521static void __init setup_boot_cpu_capabilities(void);
1e89baed 522
3c739b57
SP		 523void __init init_cpu_features(struct cpuinfo_arm64 *info)
524{
525 /* Before we start using the tables, make sure it is sorted */
526 sort_ftr_regs();
527
528 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
529 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
530 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
531 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
532 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
533 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
534 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
535 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
536 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
406e3087 537 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
3c739b57
SP		 538 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
539 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
2e0f2478 540 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
a6dc3cd7
SP		 541
542 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
543 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
544 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
545 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
546 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
547 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
548 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
549 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
550 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
551 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
552 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
553 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
554 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
555 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
556 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
557 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
558 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
559 }
560
2e0f2478
DM		 561 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
562 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
563 sve_init_vq_map();
564 }
5e91107b
SP		 565
566 /*
fd9d63da
SP		 567 * Detect and enable early CPU capabilities based on the boot CPU,
568 * after we have initialised the CPU feature infrastructure.
5e91107b 569 */
fd9d63da 570 setup_boot_cpu_capabilities();
3c739b57
SP		 571}
572
3086d391 573static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
3c739b57 574{
5e49d73c 575 const struct arm64_ftr_bits *ftrp;
3c739b57
SP		 576
577 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
578 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
579 s64 ftr_new = arm64_ftr_value(ftrp, new);
580
581 if (ftr_cur == ftr_new)
582 continue;
583 /* Find a safe value */
584 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
585 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
586 }
587
588}
589
3086d391 590static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
cdcf817b 591{
3086d391
SP		 592 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
593
594 BUG_ON(!regp);
595 update_cpu_ftr_reg(regp, val);
596 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
597 return 0;
598 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
599 regp->name, boot, cpu, val);
600 return 1;
601}
602
603/*
604 * Update system wide CPU feature registers with the values from a
605 * non-boot CPU. Also performs SANITY checks to make sure that there
606 * aren't any insane variations from that of the boot CPU.
607 */
608void update_cpu_features(int cpu,
609 struct cpuinfo_arm64 *info,
610 struct cpuinfo_arm64 *boot)
611{
612 int taint = 0;
613
614 /*
615 * The kernel can handle differing I-cache policies, but otherwise
616 * caches should look identical. Userspace JITs will make use of
617 * *minLine.
618 */
619 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
620 info->reg_ctr, boot->reg_ctr);
621
622 /*
623 * Userspace may perform DC ZVA instructions. Mismatched block sizes
624 * could result in too much or too little memory being zeroed if a
625 * process is preempted and migrated between CPUs.
626 */
627 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
628 info->reg_dczid, boot->reg_dczid);
629
630 /* If different, timekeeping will be broken (especially with KVM) */
631 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
632 info->reg_cntfrq, boot->reg_cntfrq);
633
634 /*
635 * The kernel uses self-hosted debug features and expects CPUs to
636 * support identical debug features. We presently need CTX_CMPs, WRPs,
637 * and BRPs to be identical.
638 * ID_AA64DFR1 is currently RES0.
639 */
640 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
641 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
642 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
643 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
644 /*
645 * Even in big.LITTLE, processors should be identical instruction-set
646 * wise.
647 */
648 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
649 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
650 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
651 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
652
653 /*
654 * Differing PARange support is fine as long as all peripherals and
655 * memory are mapped within the minimum PARange of all CPUs.
656 * Linux should not care about secure memory.
657 */
658 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
659 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
660 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
661 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
406e3087
JM		 662 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
663 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
3086d391
SP		 664
665 /*
666 * EL3 is not our concern.
3086d391
SP		 667 */
668 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
669 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
670 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
671 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
672
2e0f2478
DM		 673 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
674 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
675
3086d391 676 /*
a6dc3cd7
SP		 677 * If we have AArch32, we care about 32-bit features for compat.
678 * If the system doesn't support AArch32, don't update them.
3086d391 679 */
46823dd1 680 if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
a6dc3cd7
SP		 681 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
682
683 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
3086d391 684 info->reg_id_dfr0, boot->reg_id_dfr0);
a6dc3cd7 685 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
3086d391 686 info->reg_id_isar0, boot->reg_id_isar0);
a6dc3cd7 687 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
3086d391 688 info->reg_id_isar1, boot->reg_id_isar1);
a6dc3cd7 689 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
3086d391 690 info->reg_id_isar2, boot->reg_id_isar2);
a6dc3cd7 691 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
3086d391 692 info->reg_id_isar3, boot->reg_id_isar3);
a6dc3cd7 693 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
3086d391 694 info->reg_id_isar4, boot->reg_id_isar4);
a6dc3cd7 695 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
3086d391
SP		 696 info->reg_id_isar5, boot->reg_id_isar5);
697
a6dc3cd7
SP		 698 /*
699 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
700 * ACTLR formats could differ across CPUs and therefore would have to
701 * be trapped for virtualization anyway.
702 */
703 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
3086d391 704 info->reg_id_mmfr0, boot->reg_id_mmfr0);
a6dc3cd7 705 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
3086d391 706 info->reg_id_mmfr1, boot->reg_id_mmfr1);
a6dc3cd7 707 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
3086d391 708 info->reg_id_mmfr2, boot->reg_id_mmfr2);
a6dc3cd7 709 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
3086d391 710 info->reg_id_mmfr3, boot->reg_id_mmfr3);
a6dc3cd7 711 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
3086d391 712 info->reg_id_pfr0, boot->reg_id_pfr0);
a6dc3cd7 713 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
3086d391 714 info->reg_id_pfr1, boot->reg_id_pfr1);
a6dc3cd7 715 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
3086d391 716 info->reg_mvfr0, boot->reg_mvfr0);
a6dc3cd7 717 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
3086d391 718 info->reg_mvfr1, boot->reg_mvfr1);
a6dc3cd7 719 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
3086d391 720 info->reg_mvfr2, boot->reg_mvfr2);
a6dc3cd7 721 }
3086d391 722
2e0f2478
DM		 723 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
724 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
725 info->reg_zcr, boot->reg_zcr);
726
727 /* Probe vector lengths, unless we already gave up on SVE */
728 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
729 !sys_caps_initialised)
730 sve_update_vq_map();
731 }
732
3086d391
SP		 733 /*
734 * Mismatched CPU features are a recipe for disaster. Don't even
735 * pretend to support them.
736 */
8dd0ee65
WD		 737 if (taint) {
738 pr_warn_once("Unsupported CPU feature variation detected.\n");
739 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
740 }
cdcf817b
SP		 741}
742
46823dd1 743u64 read_sanitised_ftr_reg(u32 id)
b3f15378
SP		 744{
745 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
746
747 /* We shouldn't get a request for an unsupported register */
748 BUG_ON(!regp);
749 return regp->sys_val;
750}
359b7064 751
965861d6
MR		 752#define read_sysreg_case(r) \
753 case r: return read_sysreg_s(r)
754
92406f0c 755/*
46823dd1 756 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
92406f0c
SP		 757 * Read the system register on the current CPU
758 */
46823dd1 759static u64 __read_sysreg_by_encoding(u32 sys_id)
92406f0c
SP		 760{
761 switch (sys_id) {
965861d6
MR		 762 read_sysreg_case(SYS_ID_PFR0_EL1);
763 read_sysreg_case(SYS_ID_PFR1_EL1);
764 read_sysreg_case(SYS_ID_DFR0_EL1);
765 read_sysreg_case(SYS_ID_MMFR0_EL1);
766 read_sysreg_case(SYS_ID_MMFR1_EL1);
767 read_sysreg_case(SYS_ID_MMFR2_EL1);
768 read_sysreg_case(SYS_ID_MMFR3_EL1);
769 read_sysreg_case(SYS_ID_ISAR0_EL1);
770 read_sysreg_case(SYS_ID_ISAR1_EL1);
771 read_sysreg_case(SYS_ID_ISAR2_EL1);
772 read_sysreg_case(SYS_ID_ISAR3_EL1);
773 read_sysreg_case(SYS_ID_ISAR4_EL1);
774 read_sysreg_case(SYS_ID_ISAR5_EL1);
775 read_sysreg_case(SYS_MVFR0_EL1);
776 read_sysreg_case(SYS_MVFR1_EL1);
777 read_sysreg_case(SYS_MVFR2_EL1);
778
779 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
780 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
781 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
782 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
783 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
784 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
785 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
786 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
787 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
788
789 read_sysreg_case(SYS_CNTFRQ_EL0);
790 read_sysreg_case(SYS_CTR_EL0);
791 read_sysreg_case(SYS_DCZID_EL0);
792
92406f0c
SP		 793 default:
794 BUG();
795 return 0;
796 }
797}
798
963fcd40
MZ		 799#include <linux/irqchip/arm-gic-v3.h>
800
18ffa046
JM		 801static bool
802feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
803{
28c5dcb2 804 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
18ffa046
JM		 805
806 return val >= entry->min_field_value;
807}
808
da8d02d1 809static bool
92406f0c 810has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
da8d02d1
SP		 811{
812 u64 val;
94a9e04a 813
92406f0c
SP		 814 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
815 if (scope == SCOPE_SYSTEM)
46823dd1 816 val = read_sanitised_ftr_reg(entry->sys_reg);
92406f0c 817 else
46823dd1 818 val = __read_sysreg_by_encoding(entry->sys_reg);
92406f0c 819
da8d02d1
SP		 820 return feature_matches(val, entry);
821}
338d4f49 822
92406f0c 823static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
963fcd40
MZ		 824{
825 bool has_sre;
826
92406f0c 827 if (!has_cpuid_feature(entry, scope))
963fcd40
MZ		 828 return false;
829
830 has_sre = gic_enable_sre();
831 if (!has_sre)
832 pr_warn_once("%s present but disabled by higher exception level\n",
833 entry->desc);
834
835 return has_sre;
836}
837
92406f0c 838static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
d5370f75
WD		 839{
840 u32 midr = read_cpuid_id();
d5370f75
WD		 841
842 /* Cavium ThunderX pass 1.x and 2.x */
fa5ce3d1
RR		 843 return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX,
844 MIDR_CPU_VAR_REV(0, 0),
845 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
d5370f75
WD		 846}
847
82e0191a
SP		 848static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
849{
46823dd1 850 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
82e0191a
SP		 851
852 return cpuid_feature_extract_signed_field(pfr0,
853 ID_AA64PFR0_FP_SHIFT) < 0;
854}
855
6ae4b6e0 856static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
8ab66cbe 857 int scope)
6ae4b6e0 858{
8ab66cbe
SP		 859 u64 ctr;
860
861 if (scope == SCOPE_SYSTEM)
862 ctr = arm64_ftr_reg_ctrel0.sys_val;
863 else
864 ctr = read_cpuid_cachetype();
865
866 return ctr & BIT(CTR_IDC_SHIFT);
6ae4b6e0
SD		 867}
868
869static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
8ab66cbe 870 int scope)
6ae4b6e0 871{
8ab66cbe
SP		 872 u64 ctr;
873
874 if (scope == SCOPE_SYSTEM)
875 ctr = arm64_ftr_reg_ctrel0.sys_val;
876 else
877 ctr = read_cpuid_cachetype();
878
879 return ctr & BIT(CTR_DIC_SHIFT);
6ae4b6e0
SD		 880}
881
5ffdfaed
VM		 882static bool __maybe_unused
883has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
884{
885 /*
886 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
887 * may share TLB entries with a CPU stuck in the crashed
888 * kernel.
889 */
890 if (is_kdump_kernel())
891 return false;
892
893 return has_cpuid_feature(entry, scope);
894}
895
ea1e3de8
WD		 896#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
897static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
898
899static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
d3aec8a2 900 int scope)
ea1e3de8 901{
be5b2998
SP		 902 /* List of CPUs that are not vulnerable and don't need KPTI */
903 static const struct midr_range kpti_safe_list[] = {
904 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
905 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
71c751f2 906 { /* sentinel */ }
be5b2998 907 };
6dc52b15 908 char const *str = "command line option";
179a56f6 909
6dc52b15
MZ		 910 /*
911 * For reasons that aren't entirely clear, enabling KPTI on Cavium
912 * ThunderX leads to apparent I-cache corruption of kernel text, which
913 * ends as well as you might imagine. Don't even try.
914 */
915 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
916 str = "ARM64_WORKAROUND_CAVIUM_27456";
917 __kpti_forced = -1;
918 }
919
920 /* Forced? */
ea1e3de8 921 if (__kpti_forced) {
6dc52b15
MZ		 922 pr_info_once("kernel page table isolation forced %s by %s\n",
923 __kpti_forced > 0 ? "ON" : "OFF", str);
ea1e3de8
WD		 924 return __kpti_forced > 0;
925 }
926
927 /* Useful for KASLR robustness */
928 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE))
929 return true;
930
0ba2e29c 931 /* Don't force KPTI for CPUs that are not vulnerable */
be5b2998 932 if (is_midr_in_range_list(read_cpuid_id(), kpti_safe_list))
0ba2e29c 933 return false;
0ba2e29c 934
179a56f6 935 /* Defer to CPU feature registers */
d3aec8a2 936 return !has_cpuid_feature(entry, scope);
ea1e3de8
WD		 937}
938
c0cda3b8
DM		 939static void
940kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
f992b4df
WD		 941{
942 typedef void (kpti_remap_fn)(int, int, phys_addr_t);
943 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
944 kpti_remap_fn *remap_fn;
945
946 static bool kpti_applied = false;
947 int cpu = smp_processor_id();
948
949 if (kpti_applied)
c0cda3b8 950 return;
f992b4df
WD		 951
952 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
953
954 cpu_install_idmap();
955 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
956 cpu_uninstall_idmap();
957
958 if (!cpu)
959 kpti_applied = true;
960
c0cda3b8 961 return;
f992b4df
WD		 962}
963
ea1e3de8
WD		 964static int __init parse_kpti(char *str)
965{
966 bool enabled;
967 int ret = strtobool(str, &enabled);
968
969 if (ret)
970 return ret;
971
972 __kpti_forced = enabled ? 1 : -1;
973 return 0;
974}
b5b7dd64 975early_param("kpti", parse_kpti);
ea1e3de8
WD		 976#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
977
05abb595
SP		 978#ifdef CONFIG_ARM64_HW_AFDBM
979static inline void __cpu_enable_hw_dbm(void)
980{
981 u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
982
983 write_sysreg(tcr, tcr_el1);
984 isb();
985}
986
ece1397c
SP		 987static bool cpu_has_broken_dbm(void)
988{
989 /* List of CPUs which have broken DBM support. */
990 static const struct midr_range cpus[] = {
991#ifdef CONFIG_ARM64_ERRATUM_1024718
992 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0
993#endif
994 {},
995 };
996
997 return is_midr_in_range_list(read_cpuid_id(), cpus);
998}
999
05abb595
SP		 1000static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1001{
ece1397c
SP		 1002 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1003 !cpu_has_broken_dbm();
05abb595
SP		 1004}
1005
1006static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1007{
1008 if (cpu_can_use_dbm(cap))
1009 __cpu_enable_hw_dbm();
1010}
1011
1012static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1013 int __unused)
1014{
1015 static bool detected = false;
1016 /*
1017 * DBM is a non-conflicting feature. i.e, the kernel can safely
1018 * run a mix of CPUs with and without the feature. So, we
1019 * unconditionally enable the capability to allow any late CPU
1020 * to use the feature. We only enable the control bits on the
1021 * CPU, if it actually supports.
1022 *
1023 * We have to make sure we print the "feature" detection only
1024 * when at least one CPU actually uses it. So check if this CPU
1025 * can actually use it and print the message exactly once.
1026 *
1027 * This is safe as all CPUs (including secondary CPUs - due to the
1028 * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1029 * goes through the "matches" check exactly once. Also if a CPU
1030 * matches the criteria, it is guaranteed that the CPU will turn
1031 * the DBM on, as the capability is unconditionally enabled.
1032 */
1033 if (!detected && cpu_can_use_dbm(cap)) {
1034 detected = true;
1035 pr_info("detected: Hardware dirty bit management\n");
1036 }
1037
1038 return true;
1039}
1040
1041#endif
1042
12eb3691
WD		 1043#ifdef CONFIG_ARM64_VHE
1044static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1045{
1046 return is_kernel_in_hyp_mode();
1047}
1048
c0cda3b8 1049static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
6d99b689
JM		 1050{
1051 /*
1052 * Copy register values that aren't redirected by hardware.
1053 *
1054 * Before code patching, we only set tpidr_el1, all CPUs need to copy
1055 * this value to tpidr_el2 before we patch the code. Once we've done
1056 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1057 * do anything here.
1058 */
1059 if (!alternatives_applied)
1060 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
6d99b689 1061}
12eb3691 1062#endif
6d99b689 1063
e48d53a9
MZ		 1064static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1065{
1066 u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1067
1068 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1069 WARN_ON(val & (7 << 27 | 7 << 21));
1070}
1071
8f04e8e6
WD		 1072#ifdef CONFIG_ARM64_SSBD
1073static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
1074{
1075 if (user_mode(regs))
1076 return 1;
1077
74e24828 1078 if (instr & BIT(PSTATE_Imm_shift))
8f04e8e6
WD		 1079 regs->pstate |= PSR_SSBS_BIT;
1080 else
1081 regs->pstate &= ~PSR_SSBS_BIT;
1082
1083 arm64_skip_faulting_instruction(regs, 4);
1084 return 0;
1085}
1086
1087static struct undef_hook ssbs_emulation_hook = {
74e24828
SP		 1088 .instr_mask = ~(1U << PSTATE_Imm_shift),
1089 .instr_val = 0xd500401f | PSTATE_SSBS,
8f04e8e6
WD		 1090 .fn = ssbs_emulation_handler,
1091};
1092
1093static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
1094{
1095 static bool undef_hook_registered = false;
1096 static DEFINE_SPINLOCK(hook_lock);
1097
1098 spin_lock(&hook_lock);
1099 if (!undef_hook_registered) {
1100 register_undef_hook(&ssbs_emulation_hook);
1101 undef_hook_registered = true;
1102 }
1103 spin_unlock(&hook_lock);
1104
1105 if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
1106 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
1107 arm64_set_ssbd_mitigation(false);
1108 } else {
1109 arm64_set_ssbd_mitigation(true);
1110 }
1111}
1112#endif /* CONFIG_ARM64_SSBD */
1113
b8925ee2
WD		 1114#ifdef CONFIG_ARM64_PAN
1115static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1116{
1117 /*
1118 * We modify PSTATE. This won't work from irq context as the PSTATE
1119 * is discarded once we return from the exception.
1120 */
1121 WARN_ON_ONCE(in_interrupt());
1122
1123 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1124 asm(SET_PSTATE_PAN(1));
1125}
1126#endif /* CONFIG_ARM64_PAN */
1127
1128#ifdef CONFIG_ARM64_RAS_EXTN
1129static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1130{
1131 /* Firmware may have left a deferred SError in this register. */
1132 write_sysreg_s(0, SYS_DISR_EL1);
1133}
1134#endif /* CONFIG_ARM64_RAS_EXTN */
1135
359b7064 1136static const struct arm64_cpu_capabilities arm64_features[] = {
94a9e04a
MZ		 1137 {
1138 .desc = "GIC system register CPU interface",
1139 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
5b4747c5 1140 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
963fcd40 1141 .matches = has_useable_gicv3_cpuif,
da8d02d1
SP		 1142 .sys_reg = SYS_ID_AA64PFR0_EL1,
1143 .field_pos = ID_AA64PFR0_GIC_SHIFT,
ff96f7bc 1144 .sign = FTR_UNSIGNED,
18ffa046 1145 .min_field_value = 1,
94a9e04a 1146 },
338d4f49
JM		 1147#ifdef CONFIG_ARM64_PAN
1148 {
1149 .desc = "Privileged Access Never",
1150 .capability = ARM64_HAS_PAN,
5b4747c5 1151 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
da8d02d1
SP		 1152 .matches = has_cpuid_feature,
1153 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1154 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
ff96f7bc 1155 .sign = FTR_UNSIGNED,
338d4f49 1156 .min_field_value = 1,
c0cda3b8 1157 .cpu_enable = cpu_enable_pan,
338d4f49
JM		 1158 },
1159#endif /* CONFIG_ARM64_PAN */
2e94da13
WD		 1160#if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
1161 {
1162 .desc = "LSE atomic instructions",
1163 .capability = ARM64_HAS_LSE_ATOMICS,
5b4747c5 1164 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
da8d02d1
SP		 1165 .matches = has_cpuid_feature,
1166 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1167 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
ff96f7bc 1168 .sign = FTR_UNSIGNED,
2e94da13
WD		 1169 .min_field_value = 2,
1170 },
1171#endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
d5370f75
WD		 1172 {
1173 .desc = "Software prefetching using PRFM",
1174 .capability = ARM64_HAS_NO_HW_PREFETCH,
5c137714 1175 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
d5370f75
WD		 1176 .matches = has_no_hw_prefetch,
1177 },
57f4959b
JM		 1178#ifdef CONFIG_ARM64_UAO
1179 {
1180 .desc = "User Access Override",
1181 .capability = ARM64_HAS_UAO,
5b4747c5 1182 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
57f4959b
JM		 1183 .matches = has_cpuid_feature,
1184 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1185 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1186 .min_field_value = 1,
c8b06e3f
JM		 1187 /*
1188 * We rely on stop_machine() calling uao_thread_switch() to set
1189 * UAO immediately after patching.
1190 */
57f4959b
JM		 1191 },
1192#endif /* CONFIG_ARM64_UAO */
70544196
JM		 1193#ifdef CONFIG_ARM64_PAN
1194 {
1195 .capability = ARM64_ALT_PAN_NOT_UAO,
5b4747c5 1196 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
70544196
JM		 1197 .matches = cpufeature_pan_not_uao,
1198 },
1199#endif /* CONFIG_ARM64_PAN */
830dcc9f 1200#ifdef CONFIG_ARM64_VHE
d88701be
MZ		 1201 {
1202 .desc = "Virtualization Host Extensions",
1203 .capability = ARM64_HAS_VIRT_HOST_EXTN,
830dcc9f 1204 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
d88701be 1205 .matches = runs_at_el2,
c0cda3b8 1206 .cpu_enable = cpu_copy_el2regs,
d88701be 1207 },
830dcc9f 1208#endif /* CONFIG_ARM64_VHE */
042446a3
SP		 1209 {
1210 .desc = "32-bit EL0 Support",
1211 .capability = ARM64_HAS_32BIT_EL0,
5b4747c5 1212 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
042446a3
SP		 1213 .matches = has_cpuid_feature,
1214 .sys_reg = SYS_ID_AA64PFR0_EL1,
1215 .sign = FTR_UNSIGNED,
1216 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1217 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1218 },
ea1e3de8
WD		 1219#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1220 {
179a56f6 1221 .desc = "Kernel page table isolation (KPTI)",
ea1e3de8 1222 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
d3aec8a2
SP		 1223 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1224 /*
1225 * The ID feature fields below are used to indicate that
1226 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1227 * more details.
1228 */
1229 .sys_reg = SYS_ID_AA64PFR0_EL1,
1230 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1231 .min_field_value = 1,
ea1e3de8 1232 .matches = unmap_kernel_at_el0,
c0cda3b8 1233 .cpu_enable = kpti_install_ng_mappings,
ea1e3de8
WD		 1234 },
1235#endif
82e0191a
SP		 1236 {
1237 /* FP/SIMD is not implemented */
1238 .capability = ARM64_HAS_NO_FPSIMD,
5b4747c5 1239 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
82e0191a
SP		 1240 .min_field_value = 0,
1241 .matches = has_no_fpsimd,
1242 },
d50e071f
RM		 1243#ifdef CONFIG_ARM64_PMEM
1244 {
1245 .desc = "Data cache clean to Point of Persistence",
1246 .capability = ARM64_HAS_DCPOP,
5b4747c5 1247 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
d50e071f
RM		 1248 .matches = has_cpuid_feature,
1249 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1250 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1251 .min_field_value = 1,
1252 },
1253#endif
43994d82
DM		 1254#ifdef CONFIG_ARM64_SVE
1255 {
1256 .desc = "Scalable Vector Extension",
5b4747c5 1257 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
43994d82 1258 .capability = ARM64_SVE,
43994d82
DM		 1259 .sys_reg = SYS_ID_AA64PFR0_EL1,
1260 .sign = FTR_UNSIGNED,
1261 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1262 .min_field_value = ID_AA64PFR0_SVE,
1263 .matches = has_cpuid_feature,
c0cda3b8 1264 .cpu_enable = sve_kernel_enable,
43994d82
DM		 1265 },
1266#endif /* CONFIG_ARM64_SVE */
64c02720
XX		 1267#ifdef CONFIG_ARM64_RAS_EXTN
1268 {
1269 .desc = "RAS Extension Support",
1270 .capability = ARM64_HAS_RAS_EXTN,
5b4747c5 1271 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
64c02720
XX		 1272 .matches = has_cpuid_feature,
1273 .sys_reg = SYS_ID_AA64PFR0_EL1,
1274 .sign = FTR_UNSIGNED,
1275 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1276 .min_field_value = ID_AA64PFR0_RAS_V1,
c0cda3b8 1277 .cpu_enable = cpu_clear_disr,
64c02720
XX		 1278 },
1279#endif /* CONFIG_ARM64_RAS_EXTN */
6ae4b6e0
SD		 1280 {
1281 .desc = "Data cache clean to the PoU not required for I/D coherence",
1282 .capability = ARM64_HAS_CACHE_IDC,
5b4747c5 1283 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
6ae4b6e0
SD		 1284 .matches = has_cache_idc,
1285 },
1286 {
1287 .desc = "Instruction cache invalidation not required for I/D coherence",
1288 .capability = ARM64_HAS_CACHE_DIC,
5b4747c5 1289 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
6ae4b6e0
SD		 1290 .matches = has_cache_dic,
1291 },
e48d53a9
MZ		 1292 {
1293 .desc = "Stage-2 Force Write-Back",
1294 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1295 .capability = ARM64_HAS_STAGE2_FWB,
1296 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1297 .sign = FTR_UNSIGNED,
1298 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
1299 .min_field_value = 1,
1300 .matches = has_cpuid_feature,
1301 .cpu_enable = cpu_has_fwb,
1302 },
05abb595
SP		 1303#ifdef CONFIG_ARM64_HW_AFDBM
1304 {
1305 /*
1306 * Since we turn this on always, we don't want the user to
1307 * think that the feature is available when it may not be.
1308 * So hide the description.
1309 *
1310 * .desc = "Hardware pagetable Dirty Bit Management",
1311 *
1312 */
1313 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1314 .capability = ARM64_HW_DBM,
1315 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1316 .sign = FTR_UNSIGNED,
1317 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
1318 .min_field_value = 2,
1319 .matches = has_hw_dbm,
1320 .cpu_enable = cpu_enable_hw_dbm,
1321 },
1322#endif
8f04e8e6 1323#ifdef CONFIG_ARM64_SSBD
86d0dd34
AB		 1324 {
1325 .desc = "CRC32 instructions",
1326 .capability = ARM64_HAS_CRC32,
1327 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1328 .matches = has_cpuid_feature,
1329 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1330 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
1331 .min_field_value = 1,
1332 },
d71be2b6
WD		 1333 {
1334 .desc = "Speculative Store Bypassing Safe (SSBS)",
1335 .capability = ARM64_SSBS,
1336 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1337 .matches = has_cpuid_feature,
1338 .sys_reg = SYS_ID_AA64PFR1_EL1,
1339 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
1340 .sign = FTR_UNSIGNED,
1341 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
8f04e8e6 1342 .cpu_enable = cpu_enable_ssbs,
d71be2b6 1343 },
5ffdfaed
VM		 1344#endif
1345#ifdef CONFIG_ARM64_CNP
1346 {
1347 .desc = "Common not Private translations",
1348 .capability = ARM64_HAS_CNP,
1349 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1350 .matches = has_useable_cnp,
1351 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1352 .sign = FTR_UNSIGNED,
1353 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
1354 .min_field_value = 1,
1355 .cpu_enable = cpu_enable_cnp,
1356 },
8f04e8e6 1357#endif
359b7064
MZ		 1358 {},
1359};
1360
143ba05d 1361#define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \
37b01d53
SP		 1362 { \
1363 .desc = #cap, \
5b4747c5 1364 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
37b01d53
SP		 1365 .matches = has_cpuid_feature, \
1366 .sys_reg = reg, \
1367 .field_pos = field, \
ff96f7bc 1368 .sign = s, \
37b01d53 1369 .min_field_value = min_value, \
143ba05d 1370 .hwcap_type = cap_type, \
37b01d53
SP		 1371 .hwcap = cap, \
1372 }
1373
f3efb675 1374static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
ff96f7bc
SP		 1375 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
1376 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
1377 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
1378 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
f5e035f8 1379 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_SHA512),
ff96f7bc
SP		 1380 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
1381 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
f92f5ce0 1382 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM),
f5e035f8
SP		 1383 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA3),
1384 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM3),
1385 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM4),
1386 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDDP),
3b3b6810 1387 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDFHM),
7206dc93 1388 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FLAGM),
ff96f7bc 1389 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
bf500618 1390 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
ff96f7bc 1391 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
bf500618 1392 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
7206dc93 1393 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_DIT),
7aac405e 1394 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_DCPOP),
c8c3798d 1395 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),
cb567e79 1396 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA),
c651aae5 1397 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC),
7206dc93
SP		 1398 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ILRCPC),
1399 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_USCAT),
43994d82
DM		 1400#ifdef CONFIG_ARM64_SVE
1401 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, HWCAP_SVE),
1402#endif
d71be2b6 1403 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, HWCAP_SSBS),
75283501
SP		 1404 {},
1405};
1406
1407static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
37b01d53 1408#ifdef CONFIG_COMPAT
ff96f7bc
SP		 1409 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
1410 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
1411 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
1412 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
1413 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
37b01d53
SP		 1414#endif
1415 {},
1416};
1417
f3efb675 1418static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 1419{
1420 switch (cap->hwcap_type) {
1421 case CAP_HWCAP:
1422 elf_hwcap |= cap->hwcap;
1423 break;
1424#ifdef CONFIG_COMPAT
1425 case CAP_COMPAT_HWCAP:
1426 compat_elf_hwcap |= (u32)cap->hwcap;
1427 break;
1428 case CAP_COMPAT_HWCAP2:
1429 compat_elf_hwcap2 |= (u32)cap->hwcap;
1430 break;
1431#endif
1432 default:
1433 WARN_ON(1);
1434 break;
1435 }
1436}
1437
1438/* Check if we have a particular HWCAP enabled */
f3efb675 1439static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 1440{
1441 bool rc;
1442
1443 switch (cap->hwcap_type) {
1444 case CAP_HWCAP:
1445 rc = (elf_hwcap & cap->hwcap) != 0;
1446 break;
1447#ifdef CONFIG_COMPAT
1448 case CAP_COMPAT_HWCAP:
1449 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1450 break;
1451 case CAP_COMPAT_HWCAP2:
1452 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1453 break;
1454#endif
1455 default:
1456 WARN_ON(1);
1457 rc = false;
1458 }
1459
1460 return rc;
1461}
1462
75283501 1463static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
37b01d53 1464{
77c97b4e
SP		 1465 /* We support emulation of accesses to CPU ID feature registers */
1466 elf_hwcap |= HWCAP_CPUID;
75283501 1467 for (; hwcaps->matches; hwcaps++)
143ba05d 1468 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
75283501 1469 cap_set_elf_hwcap(hwcaps);
37b01d53
SP		 1470}
1471
67948af4
SP		 1472/*
1473 * Check if the current CPU has a given feature capability.
1474 * Should be called from non-preemptible context.
1475 */
1476static bool __this_cpu_has_cap(const struct arm64_cpu_capabilities *cap_array,
1477 unsigned int cap)
1478{
1479 const struct arm64_cpu_capabilities *caps;
1480
1481 if (WARN_ON(preemptible()))
1482 return false;
1483
edf298cf 1484 for (caps = cap_array; caps->matches; caps++)
ba7d9233
SP		 1485 if (caps->capability == cap)
1486 return caps->matches(caps, SCOPE_LOCAL_CPU);
1487
67948af4
SP		 1488 return false;
1489}
1490
ed478b3f
SP		 1491static void __update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
1492 u16 scope_mask, const char *info)
359b7064 1493{
cce360b5 1494 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
75283501 1495 for (; caps->matches; caps++) {
cce360b5
SP		 1496 if (!(caps->type & scope_mask) ||
1497 !caps->matches(caps, cpucap_default_scope(caps)))
359b7064
MZ		 1498 continue;
1499
75283501
SP		 1500 if (!cpus_have_cap(caps->capability) && caps->desc)
1501 pr_info("%s %s\n", info, caps->desc);
1502 cpus_set_cap(caps->capability);
359b7064 1503 }
ce8b602c
SP		 1504}
1505
ed478b3f
SP		 1506static void update_cpu_capabilities(u16 scope_mask)
1507{
ed478b3f
SP		 1508 __update_cpu_capabilities(arm64_errata, scope_mask,
1509 "enabling workaround for");
dc0e3658 1510 __update_cpu_capabilities(arm64_features, scope_mask, "detected:");
ed478b3f
SP		 1511}
1512
c0cda3b8
DM		 1513static int __enable_cpu_capability(void *arg)
1514{
1515 const struct arm64_cpu_capabilities *cap = arg;
1516
1517 cap->cpu_enable(cap);
1518 return 0;
1519}
1520
ce8b602c 1521/*
dbb4e152
SP		 1522 * Run through the enabled capabilities and enable() it on all active
1523 * CPUs
ce8b602c 1524 */
1e89baed 1525static void __init
ed478b3f
SP		 1526__enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
1527 u16 scope_mask)
ce8b602c 1528{
cce360b5 1529 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
63a1e1c9
MR		 1530 for (; caps->matches; caps++) {
1531 unsigned int num = caps->capability;
1532
cce360b5 1533 if (!(caps->type & scope_mask) || !cpus_have_cap(num))
63a1e1c9
MR		 1534 continue;
1535
1536 /* Ensure cpus_have_const_cap(num) works */
1537 static_branch_enable(&cpu_hwcap_keys[num]);
1538
c0cda3b8 1539 if (caps->cpu_enable) {
2a6dcb2b 1540 /*
fd9d63da
SP		 1541 * Capabilities with SCOPE_BOOT_CPU scope are finalised
1542 * before any secondary CPU boots. Thus, each secondary
1543 * will enable the capability as appropriate via
1544 * check_local_cpu_capabilities(). The only exception is
1545 * the boot CPU, for which the capability must be
1546 * enabled here. This approach avoids costly
1547 * stop_machine() calls for this case.
1548 *
1549 * Otherwise, use stop_machine() as it schedules the
1550 * work allowing us to modify PSTATE, instead of
1551 * on_each_cpu() which uses an IPI, giving us a PSTATE
1552 * that disappears when we return.
2a6dcb2b 1553 */
fd9d63da
SP		 1554 if (scope_mask & SCOPE_BOOT_CPU)
1555 caps->cpu_enable(caps);
1556 else
1557 stop_machine(__enable_cpu_capability,
1558 (void *)caps, cpu_online_mask);
63a1e1c9
MR		 1559 }
1560 }
dbb4e152
SP		 1561}
1562
ed478b3f
SP		 1563static void __init enable_cpu_capabilities(u16 scope_mask)
1564{
ed478b3f 1565 __enable_cpu_capabilities(arm64_errata, scope_mask);
dc0e3658 1566 __enable_cpu_capabilities(arm64_features, scope_mask);
ed478b3f
SP		 1567}
1568
eaac4d83
SP		 1569/*
1570 * Run through the list of capabilities to check for conflicts.
1571 * If the system has already detected a capability, take necessary
1572 * action on this CPU.
1573 *
1574 * Returns "false" on conflicts.
1575 */
1576static bool
ba7d9233 1577__verify_local_cpu_caps(const struct arm64_cpu_capabilities *caps,
cce360b5 1578 u16 scope_mask)
eaac4d83
SP		 1579{
1580 bool cpu_has_cap, system_has_cap;
eaac4d83 1581
cce360b5
SP		 1582 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1583
ba7d9233 1584 for (; caps->matches; caps++) {
cce360b5
SP		 1585 if (!(caps->type & scope_mask))
1586 continue;
1587
ba7d9233 1588 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
eaac4d83
SP		 1589 system_has_cap = cpus_have_cap(caps->capability);
1590
1591 if (system_has_cap) {
1592 /*
1593 * Check if the new CPU misses an advertised feature,
1594 * which is not safe to miss.
1595 */
1596 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
1597 break;
1598 /*
1599 * We have to issue cpu_enable() irrespective of
1600 * whether the CPU has it or not, as it is enabeld
1601 * system wide. It is upto the call back to take
1602 * appropriate action on this CPU.
1603 */
1604 if (caps->cpu_enable)
1605 caps->cpu_enable(caps);
1606 } else {
1607 /*
1608 * Check if the CPU has this capability if it isn't
1609 * safe to have when the system doesn't.
1610 */
1611 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
1612 break;
1613 }
1614 }
1615
1616 if (caps->matches) {
1617 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
1618 smp_processor_id(), caps->capability,
1619 caps->desc, system_has_cap, cpu_has_cap);
1620 return false;
1621 }
1622
1623 return true;
1624}
1625
ed478b3f
SP		 1626static bool verify_local_cpu_caps(u16 scope_mask)
1627{
1628 return __verify_local_cpu_caps(arm64_errata, scope_mask) &&
1629 __verify_local_cpu_caps(arm64_features, scope_mask);
1630}
1631
dbb4e152 1632/*
13f417f3
SP		 1633 * Check for CPU features that are used in early boot
1634 * based on the Boot CPU value.
dbb4e152 1635 */
13f417f3 1636static void check_early_cpu_features(void)
dbb4e152 1637{
13f417f3 1638 verify_cpu_asid_bits();
fd9d63da
SP		 1639 /*
1640 * Early features are used by the kernel already. If there
1641 * is a conflict, we cannot proceed further.
1642 */
1643 if (!verify_local_cpu_caps(SCOPE_BOOT_CPU))
1644 cpu_panic_kernel();
dbb4e152 1645}
1c076303 1646
75283501
SP		 1647static void
1648verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1649{
1650
92406f0c
SP		 1651 for (; caps->matches; caps++)
1652 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
75283501
SP		 1653 pr_crit("CPU%d: missing HWCAP: %s\n",
1654 smp_processor_id(), caps->desc);
1655 cpu_die_early();
1656 }
75283501
SP		 1657}
1658
2e0f2478
DM		 1659static void verify_sve_features(void)
1660{
1661 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
1662 u64 zcr = read_zcr_features();
1663
1664 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
1665 unsigned int len = zcr & ZCR_ELx_LEN_MASK;
1666
1667 if (len < safe_len || sve_verify_vq_map()) {
1668 pr_crit("CPU%d: SVE: required vector length(s) missing\n",
1669 smp_processor_id());
1670 cpu_die_early();
1671 }
1672
1673 /* Add checks on other ZCR bits here if necessary */
1674}
1675
1e89baed 1676
dbb4e152
SP		 1677/*
1678 * Run through the enabled system capabilities and enable() it on this CPU.
1679 * The capabilities were decided based on the available CPUs at the boot time.
1680 * Any new CPU should match the system wide status of the capability. If the
1681 * new CPU doesn't have a capability which the system now has enabled, we
1682 * cannot do anything to fix it up and could cause unexpected failures. So
1683 * we park the CPU.
1684 */
c47a1900 1685static void verify_local_cpu_capabilities(void)
dbb4e152 1686{
fd9d63da
SP		 1687 /*
1688 * The capabilities with SCOPE_BOOT_CPU are checked from
1689 * check_early_cpu_features(), as they need to be verified
1690 * on all secondary CPUs.
1691 */
1692 if (!verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU))
600b9c91 1693 cpu_die_early();
ed478b3f 1694
c47a1900 1695 verify_local_elf_hwcaps(arm64_elf_hwcaps);
2e0f2478 1696
c47a1900
SP		 1697 if (system_supports_32bit_el0())
1698 verify_local_elf_hwcaps(compat_elf_hwcaps);
2e0f2478
DM		 1699
1700 if (system_supports_sve())
1701 verify_sve_features();
c47a1900 1702}
dbb4e152 1703
c47a1900
SP		 1704void check_local_cpu_capabilities(void)
1705{
1706 /*
1707 * All secondary CPUs should conform to the early CPU features
1708 * in use by the kernel based on boot CPU.
1709 */
13f417f3
SP		 1710 check_early_cpu_features();
1711
dbb4e152 1712 /*
c47a1900 1713 * If we haven't finalised the system capabilities, this CPU gets
fbd890b9 1714 * a chance to update the errata work arounds and local features.
c47a1900
SP		 1715 * Otherwise, this CPU should verify that it has all the system
1716 * advertised capabilities.
dbb4e152 1717 */
ed478b3f
SP		 1718 if (!sys_caps_initialised)
1719 update_cpu_capabilities(SCOPE_LOCAL_CPU);
1720 else
c47a1900 1721 verify_local_cpu_capabilities();
359b7064
MZ		 1722}
1723
fd9d63da
SP		 1724static void __init setup_boot_cpu_capabilities(void)
1725{
1726 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
1727 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
1728 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
1729 enable_cpu_capabilities(SCOPE_BOOT_CPU);
1730}
1731
63a1e1c9
MR		 1732DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
1733EXPORT_SYMBOL(arm64_const_caps_ready);
1734
1735static void __init mark_const_caps_ready(void)
1736{
1737 static_branch_enable(&arm64_const_caps_ready);
1738}
1739
8f413758
MZ		 1740extern const struct arm64_cpu_capabilities arm64_errata[];
1741
1742bool this_cpu_has_cap(unsigned int cap)
1743{
1744 return (__this_cpu_has_cap(arm64_features, cap) ||
1745 __this_cpu_has_cap(arm64_errata, cap));
1746}
1747
ed478b3f
SP		 1748static void __init setup_system_capabilities(void)
1749{
1750 /*
1751 * We have finalised the system-wide safe feature
1752 * registers, finalise the capabilities that depend
fd9d63da
SP		 1753 * on it. Also enable all the available capabilities,
1754 * that are not enabled already.
ed478b3f
SP		 1755 */
1756 update_cpu_capabilities(SCOPE_SYSTEM);
fd9d63da 1757 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
ed478b3f
SP		 1758}
1759
9cdf8ec4 1760void __init setup_cpu_features(void)
359b7064 1761{
9cdf8ec4 1762 u32 cwg;
9cdf8ec4 1763
ed478b3f 1764 setup_system_capabilities();
63a1e1c9 1765 mark_const_caps_ready();
75283501 1766 setup_elf_hwcaps(arm64_elf_hwcaps);
643d703d
SP		 1767
1768 if (system_supports_32bit_el0())
1769 setup_elf_hwcaps(compat_elf_hwcaps);
dbb4e152 1770
2e6f549f
KC		 1771 if (system_uses_ttbr0_pan())
1772 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
1773
2e0f2478 1774 sve_setup();
94b07c1f 1775 minsigstksz_setup();
2e0f2478 1776
dbb4e152
SP		 1777 /* Advertise that we have computed the system capabilities */
1778 set_sys_caps_initialised();
1779
9cdf8ec4
SP		 1780 /*
1781 * Check for sane CTR_EL0.CWG value.
1782 */
1783 cwg = cache_type_cwg();
9cdf8ec4 1784 if (!cwg)
ebc7e21e
CM		 1785 pr_warn("No Cache Writeback Granule information, assuming %d\n",
1786 ARCH_DMA_MINALIGN);
359b7064 1787}
70544196
JM		 1788
1789static bool __maybe_unused
92406f0c 1790cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
70544196 1791{
a4023f68 1792 return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
70544196 1793}
77c97b4e 1794
5ffdfaed
VM		 1795static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
1796{
1797 cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
1798}
1799
77c97b4e
SP		 1800/*
1801 * We emulate only the following system register space.
1802 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
1803 * See Table C5-6 System instruction encodings for System register accesses,
1804 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
1805 */
1806static inline bool __attribute_const__ is_emulated(u32 id)
1807{
1808 return (sys_reg_Op0(id) == 0x3 &&
1809 sys_reg_CRn(id) == 0x0 &&
1810 sys_reg_Op1(id) == 0x0 &&
1811 (sys_reg_CRm(id) == 0 ||
1812 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
1813}
1814
1815/*
1816 * With CRm == 0, reg should be one of :
1817 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
1818 */
1819static inline int emulate_id_reg(u32 id, u64 *valp)
1820{
1821 switch (id) {
1822 case SYS_MIDR_EL1:
1823 *valp = read_cpuid_id();
1824 break;
1825 case SYS_MPIDR_EL1:
1826 *valp = SYS_MPIDR_SAFE_VAL;
1827 break;
1828 case SYS_REVIDR_EL1:
1829 /* IMPLEMENTATION DEFINED values are emulated with 0 */
1830 *valp = 0;
1831 break;
1832 default:
1833 return -EINVAL;
1834 }
1835
1836 return 0;
1837}
1838
1839static int emulate_sys_reg(u32 id, u64 *valp)
1840{
1841 struct arm64_ftr_reg *regp;
1842
1843 if (!is_emulated(id))
1844 return -EINVAL;
1845
1846 if (sys_reg_CRm(id) == 0)
1847 return emulate_id_reg(id, valp);
1848
1849 regp = get_arm64_ftr_reg(id);
1850 if (regp)
1851 *valp = arm64_ftr_reg_user_value(regp);
1852 else
1853 /*
1854 * The untracked registers are either IMPLEMENTATION DEFINED
1855 * (e.g, ID_AFR0_EL1) or reserved RAZ.
1856 */
1857 *valp = 0;
1858 return 0;
1859}
1860
520ad988 1861int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
77c97b4e
SP		 1862{
1863 int rc;
77c97b4e
SP		 1864 u64 val;
1865
77c97b4e
SP		 1866 rc = emulate_sys_reg(sys_reg, &val);
1867 if (!rc) {
520ad988 1868 pt_regs_write_reg(regs, rt, val);
6436beee 1869 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
77c97b4e 1870 }
77c97b4e
SP		 1871 return rc;
1872}
1873
520ad988
AK		 1874static int emulate_mrs(struct pt_regs *regs, u32 insn)
1875{
1876 u32 sys_reg, rt;
1877
1878 /*
1879 * sys_reg values are defined as used in mrs/msr instruction.
1880 * shift the imm value to get the encoding.
1881 */
1882 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
1883 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
1884 return do_emulate_mrs(regs, sys_reg, rt);
1885}
1886
77c97b4e
SP		 1887static struct undef_hook mrs_hook = {
1888 .instr_mask = 0xfff00000,
1889 .instr_val = 0xd5300000,
d64567f6 1890 .pstate_mask = PSR_AA32_MODE_MASK,
77c97b4e
SP		 1891 .pstate_val = PSR_MODE_EL0t,
1892 .fn = emulate_mrs,
1893};
1894
1895static int __init enable_mrs_emulation(void)
1896{
1897 register_undef_hook(&mrs_hook);
1898 return 0;
1899}
1900
c0d8832e 1901core_initcall(enable_mrs_emulation);
Ubuntu Jammy Linux kernel mirror