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359b7064
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1/*
2 * Contains CPU feature definitions
3 *
4 * Copyright (C) 2015 ARM Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
9cdf8ec4 19#define pr_fmt(fmt) "CPU features: " fmt
359b7064 20
3c739b57 21#include <linux/bsearch.h>
2a6dcb2b 22#include <linux/cpumask.h>
3c739b57 23#include <linux/sort.h>
2a6dcb2b 24#include <linux/stop_machine.h>
359b7064 25#include <linux/types.h>
2077be67 26#include <linux/mm.h>
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27#include <asm/cpu.h>
28#include <asm/cpufeature.h>
dbb4e152 29#include <asm/cpu_ops.h>
13f417f3 30#include <asm/mmu_context.h>
338d4f49 31#include <asm/processor.h>
cdcf817b 32#include <asm/sysreg.h>
77c97b4e 33#include <asm/traps.h>
d88701be 34#include <asm/virt.h>
359b7064 35
9cdf8ec4
SP
36unsigned long elf_hwcap __read_mostly;
37EXPORT_SYMBOL_GPL(elf_hwcap);
38
39#ifdef CONFIG_COMPAT
40#define COMPAT_ELF_HWCAP_DEFAULT \
41 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
42 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
43 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
44 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
45 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
46 COMPAT_HWCAP_LPAE)
47unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
48unsigned int compat_elf_hwcap2 __read_mostly;
49#endif
50
51DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
4b65a5db 52EXPORT_SYMBOL(cpu_hwcaps);
9cdf8ec4 53
efd9e03f
CM
54DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
55EXPORT_SYMBOL(cpu_hwcap_keys);
56
fe4fbdbc 57#define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
3c739b57 58 { \
4f0a606b 59 .sign = SIGNED, \
fe4fbdbc 60 .visible = VISIBLE, \
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61 .strict = STRICT, \
62 .type = TYPE, \
63 .shift = SHIFT, \
64 .width = WIDTH, \
65 .safe_val = SAFE_VAL, \
66 }
67
0710cfdb 68/* Define a feature with unsigned values */
fe4fbdbc
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69#define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
70 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
4f0a606b 71
0710cfdb 72/* Define a feature with a signed value */
fe4fbdbc
SP
73#define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
74 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
0710cfdb 75
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76#define ARM64_FTR_END \
77 { \
78 .width = 0, \
79 }
80
70544196
JM
81/* meta feature for alternatives */
82static bool __maybe_unused
92406f0c
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83cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
84
70544196 85
4aa8a472
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86/*
87 * NOTE: Any changes to the visibility of features should be kept in
88 * sync with the documentation of the CPU feature register ABI.
89 */
5e49d73c 90static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
fe4fbdbc
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91 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
92 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
93 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
94 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
95 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
96 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
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97 ARM64_FTR_END,
98};
99
c8c3798d 100static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
c651aae5 101 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
cb567e79 102 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
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103 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
104 ARM64_FTR_END,
105};
106
5e49d73c 107static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
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108 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),
109 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
110 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
3c739b57 111 /* Linux doesn't care about the EL3 */
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112 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0),
113 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0),
114 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
115 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
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116 ARM64_FTR_END,
117};
118
5e49d73c 119static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
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120 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
121 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
122 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
123 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
3c739b57 124 /* Linux shouldn't care about secure memory */
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SP
125 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
126 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
127 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
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128 /*
129 * Differing PARange is fine as long as all peripherals and memory are mapped
130 * within the minimum PARange of all CPUs
131 */
fe4fbdbc 132 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
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133 ARM64_FTR_END,
134};
135
5e49d73c 136static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
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137 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
138 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
139 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
140 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
141 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
142 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
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143 ARM64_FTR_END,
144};
145
5e49d73c 146static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
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147 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
148 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
149 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
150 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
151 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
406e3087
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152 ARM64_FTR_END,
153};
154
5e49d73c 155static const struct arm64_ftr_bits ftr_ctr[] = {
fe4fbdbc
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156 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */
157 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */
158 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */
159 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */
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160 /*
161 * Linux can handle differing I-cache policies. Userspace JITs will
ee7bc638 162 * make use of *minLine.
155433cb 163 * If we have differing I-cache policies, report it as the weakest - VIPT.
3c739b57 164 */
155433cb 165 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */
fe4fbdbc 166 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */
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167 ARM64_FTR_END,
168};
169
675b0563
AB
170struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
171 .name = "SYS_CTR_EL0",
172 .ftr_bits = ftr_ctr
173};
174
5e49d73c 175static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
fe4fbdbc
SP
176 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 28, 4, 0xf), /* InnerShr */
177 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 24, 4, 0), /* FCSE */
178 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
179 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 16, 4, 0), /* TCM */
180 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 12, 4, 0), /* ShareLvl */
181 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 8, 4, 0xf), /* OuterShr */
182 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */
183 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */
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184 ARM64_FTR_END,
185};
186
5e49d73c 187static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
fe4fbdbc
SP
188 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
189 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
190 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
191 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
192 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
b20d1ba3
WD
193 /*
194 * We can instantiate multiple PMU instances with different levels
195 * of support.
fe4fbdbc
SP
196 */
197 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
198 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
199 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
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200 ARM64_FTR_END,
201};
202
5e49d73c 203static const struct arm64_ftr_bits ftr_mvfr2[] = {
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204 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0), /* FPMisc */
205 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 4, 0), /* SIMDMisc */
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206 ARM64_FTR_END,
207};
208
5e49d73c 209static const struct arm64_ftr_bits ftr_dczid[] = {
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210 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
211 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
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212 ARM64_FTR_END,
213};
214
215
5e49d73c 216static const struct arm64_ftr_bits ftr_id_isar5[] = {
fe4fbdbc
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217 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0),
218 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0),
219 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0),
220 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0),
221 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0),
222 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0),
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223 ARM64_FTR_END,
224};
225
5e49d73c 226static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
fe4fbdbc 227 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0), /* ac2 */
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228 ARM64_FTR_END,
229};
230
5e49d73c 231static const struct arm64_ftr_bits ftr_id_pfr0[] = {
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232 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 12, 4, 0), /* State3 */
233 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 8, 4, 0), /* State2 */
234 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0), /* State1 */
235 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 4, 0), /* State0 */
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236 ARM64_FTR_END,
237};
238
5e49d73c 239static const struct arm64_ftr_bits ftr_id_dfr0[] = {
fe4fbdbc
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240 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
241 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */
242 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
243 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
244 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
245 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
246 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
247 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
e5343503
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248 ARM64_FTR_END,
249};
250
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251/*
252 * Common ftr bits for a 32bit register with all hidden, strict
253 * attributes, with 4bit feature fields and a default safe value of
254 * 0. Covers the following 32bit registers:
255 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
256 */
5e49d73c 257static const struct arm64_ftr_bits ftr_generic_32bits[] = {
fe4fbdbc
SP
258 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
259 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
260 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
261 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
262 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
263 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
264 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
265 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
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266 ARM64_FTR_END,
267};
268
eab43e88
SP
269/* Table for a single 32bit feature value */
270static const struct arm64_ftr_bits ftr_single32[] = {
fe4fbdbc 271 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
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272 ARM64_FTR_END,
273};
274
eab43e88 275static const struct arm64_ftr_bits ftr_raz[] = {
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276 ARM64_FTR_END,
277};
278
6f2b7eef
AB
279#define ARM64_FTR_REG(id, table) { \
280 .sys_id = id, \
281 .reg = &(struct arm64_ftr_reg){ \
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282 .name = #id, \
283 .ftr_bits = &((table)[0]), \
6f2b7eef 284 }}
3c739b57 285
6f2b7eef
AB
286static const struct __ftr_reg_entry {
287 u32 sys_id;
288 struct arm64_ftr_reg *reg;
289} arm64_ftr_regs[] = {
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290
291 /* Op1 = 0, CRn = 0, CRm = 1 */
292 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
293 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
e5343503 294 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
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295 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
296 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
297 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
298 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
299
300 /* Op1 = 0, CRn = 0, CRm = 2 */
301 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
302 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
303 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
304 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
305 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
306 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
307 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
308
309 /* Op1 = 0, CRn = 0, CRm = 3 */
310 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
311 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
312 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
313
314 /* Op1 = 0, CRn = 0, CRm = 4 */
315 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
eab43e88 316 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_raz),
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317
318 /* Op1 = 0, CRn = 0, CRm = 5 */
319 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
eab43e88 320 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
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321
322 /* Op1 = 0, CRn = 0, CRm = 6 */
323 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
c8c3798d 324 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
3c739b57
SP
325
326 /* Op1 = 0, CRn = 0, CRm = 7 */
327 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
328 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
406e3087 329 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
3c739b57
SP
330
331 /* Op1 = 3, CRn = 0, CRm = 0 */
675b0563 332 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
3c739b57
SP
333 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
334
335 /* Op1 = 3, CRn = 14, CRm = 0 */
eab43e88 336 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
3c739b57
SP
337};
338
339static int search_cmp_ftr_reg(const void *id, const void *regp)
340{
6f2b7eef 341 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
3c739b57
SP
342}
343
344/*
345 * get_arm64_ftr_reg - Lookup a feature register entry using its
346 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
347 * ascending order of sys_id , we use binary search to find a matching
348 * entry.
349 *
350 * returns - Upon success, matching ftr_reg entry for id.
351 * - NULL on failure. It is upto the caller to decide
352 * the impact of a failure.
353 */
354static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
355{
6f2b7eef
AB
356 const struct __ftr_reg_entry *ret;
357
358 ret = bsearch((const void *)(unsigned long)sys_id,
3c739b57
SP
359 arm64_ftr_regs,
360 ARRAY_SIZE(arm64_ftr_regs),
361 sizeof(arm64_ftr_regs[0]),
362 search_cmp_ftr_reg);
6f2b7eef
AB
363 if (ret)
364 return ret->reg;
365 return NULL;
3c739b57
SP
366}
367
5e49d73c
AB
368static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
369 s64 ftr_val)
3c739b57
SP
370{
371 u64 mask = arm64_ftr_mask(ftrp);
372
373 reg &= ~mask;
374 reg |= (ftr_val << ftrp->shift) & mask;
375 return reg;
376}
377
5e49d73c
AB
378static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
379 s64 cur)
3c739b57
SP
380{
381 s64 ret = 0;
382
383 switch (ftrp->type) {
384 case FTR_EXACT:
385 ret = ftrp->safe_val;
386 break;
387 case FTR_LOWER_SAFE:
388 ret = new < cur ? new : cur;
389 break;
390 case FTR_HIGHER_SAFE:
391 ret = new > cur ? new : cur;
392 break;
393 default:
394 BUG();
395 }
396
397 return ret;
398}
399
3c739b57
SP
400static void __init sort_ftr_regs(void)
401{
6f2b7eef
AB
402 int i;
403
404 /* Check that the array is sorted so that we can do the binary search */
405 for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
406 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
3c739b57
SP
407}
408
409/*
410 * Initialise the CPU feature register from Boot CPU values.
411 * Also initiliases the strict_mask for the register.
b389d799
MR
412 * Any bits that are not covered by an arm64_ftr_bits entry are considered
413 * RES0 for the system-wide value, and must strictly match.
3c739b57
SP
414 */
415static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
416{
417 u64 val = 0;
418 u64 strict_mask = ~0x0ULL;
fe4fbdbc 419 u64 user_mask = 0;
b389d799
MR
420 u64 valid_mask = 0;
421
5e49d73c 422 const struct arm64_ftr_bits *ftrp;
3c739b57
SP
423 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
424
425 BUG_ON(!reg);
426
427 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
b389d799 428 u64 ftr_mask = arm64_ftr_mask(ftrp);
3c739b57
SP
429 s64 ftr_new = arm64_ftr_value(ftrp, new);
430
431 val = arm64_ftr_set_value(ftrp, val, ftr_new);
b389d799
MR
432
433 valid_mask |= ftr_mask;
3c739b57 434 if (!ftrp->strict)
b389d799 435 strict_mask &= ~ftr_mask;
fe4fbdbc
SP
436 if (ftrp->visible)
437 user_mask |= ftr_mask;
438 else
439 reg->user_val = arm64_ftr_set_value(ftrp,
440 reg->user_val,
441 ftrp->safe_val);
3c739b57 442 }
b389d799
MR
443
444 val &= valid_mask;
445
3c739b57
SP
446 reg->sys_val = val;
447 reg->strict_mask = strict_mask;
fe4fbdbc 448 reg->user_mask = user_mask;
3c739b57
SP
449}
450
451void __init init_cpu_features(struct cpuinfo_arm64 *info)
452{
453 /* Before we start using the tables, make sure it is sorted */
454 sort_ftr_regs();
455
456 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
457 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
458 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
459 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
460 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
461 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
462 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
463 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
464 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
406e3087 465 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
3c739b57
SP
466 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
467 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
a6dc3cd7
SP
468
469 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
470 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
471 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
472 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
473 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
474 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
475 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
476 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
477 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
478 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
479 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
480 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
481 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
482 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
483 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
484 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
485 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
486 }
487
3c739b57
SP
488}
489
3086d391 490static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
3c739b57 491{
5e49d73c 492 const struct arm64_ftr_bits *ftrp;
3c739b57
SP
493
494 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
495 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
496 s64 ftr_new = arm64_ftr_value(ftrp, new);
497
498 if (ftr_cur == ftr_new)
499 continue;
500 /* Find a safe value */
501 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
502 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
503 }
504
505}
506
3086d391 507static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
cdcf817b 508{
3086d391
SP
509 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
510
511 BUG_ON(!regp);
512 update_cpu_ftr_reg(regp, val);
513 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
514 return 0;
515 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
516 regp->name, boot, cpu, val);
517 return 1;
518}
519
520/*
521 * Update system wide CPU feature registers with the values from a
522 * non-boot CPU. Also performs SANITY checks to make sure that there
523 * aren't any insane variations from that of the boot CPU.
524 */
525void update_cpu_features(int cpu,
526 struct cpuinfo_arm64 *info,
527 struct cpuinfo_arm64 *boot)
528{
529 int taint = 0;
530
531 /*
532 * The kernel can handle differing I-cache policies, but otherwise
533 * caches should look identical. Userspace JITs will make use of
534 * *minLine.
535 */
536 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
537 info->reg_ctr, boot->reg_ctr);
538
539 /*
540 * Userspace may perform DC ZVA instructions. Mismatched block sizes
541 * could result in too much or too little memory being zeroed if a
542 * process is preempted and migrated between CPUs.
543 */
544 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
545 info->reg_dczid, boot->reg_dczid);
546
547 /* If different, timekeeping will be broken (especially with KVM) */
548 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
549 info->reg_cntfrq, boot->reg_cntfrq);
550
551 /*
552 * The kernel uses self-hosted debug features and expects CPUs to
553 * support identical debug features. We presently need CTX_CMPs, WRPs,
554 * and BRPs to be identical.
555 * ID_AA64DFR1 is currently RES0.
556 */
557 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
558 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
559 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
560 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
561 /*
562 * Even in big.LITTLE, processors should be identical instruction-set
563 * wise.
564 */
565 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
566 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
567 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
568 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
569
570 /*
571 * Differing PARange support is fine as long as all peripherals and
572 * memory are mapped within the minimum PARange of all CPUs.
573 * Linux should not care about secure memory.
574 */
575 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
576 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
577 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
578 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
406e3087
JM
579 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
580 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
3086d391
SP
581
582 /*
583 * EL3 is not our concern.
584 * ID_AA64PFR1 is currently RES0.
585 */
586 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
587 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
588 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
589 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
590
591 /*
a6dc3cd7
SP
592 * If we have AArch32, we care about 32-bit features for compat.
593 * If the system doesn't support AArch32, don't update them.
3086d391 594 */
46823dd1 595 if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
a6dc3cd7
SP
596 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
597
598 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
3086d391 599 info->reg_id_dfr0, boot->reg_id_dfr0);
a6dc3cd7 600 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
3086d391 601 info->reg_id_isar0, boot->reg_id_isar0);
a6dc3cd7 602 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
3086d391 603 info->reg_id_isar1, boot->reg_id_isar1);
a6dc3cd7 604 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
3086d391 605 info->reg_id_isar2, boot->reg_id_isar2);
a6dc3cd7 606 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
3086d391 607 info->reg_id_isar3, boot->reg_id_isar3);
a6dc3cd7 608 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
3086d391 609 info->reg_id_isar4, boot->reg_id_isar4);
a6dc3cd7 610 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
3086d391
SP
611 info->reg_id_isar5, boot->reg_id_isar5);
612
a6dc3cd7
SP
613 /*
614 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
615 * ACTLR formats could differ across CPUs and therefore would have to
616 * be trapped for virtualization anyway.
617 */
618 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
3086d391 619 info->reg_id_mmfr0, boot->reg_id_mmfr0);
a6dc3cd7 620 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
3086d391 621 info->reg_id_mmfr1, boot->reg_id_mmfr1);
a6dc3cd7 622 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
3086d391 623 info->reg_id_mmfr2, boot->reg_id_mmfr2);
a6dc3cd7 624 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
3086d391 625 info->reg_id_mmfr3, boot->reg_id_mmfr3);
a6dc3cd7 626 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
3086d391 627 info->reg_id_pfr0, boot->reg_id_pfr0);
a6dc3cd7 628 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
3086d391 629 info->reg_id_pfr1, boot->reg_id_pfr1);
a6dc3cd7 630 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
3086d391 631 info->reg_mvfr0, boot->reg_mvfr0);
a6dc3cd7 632 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
3086d391 633 info->reg_mvfr1, boot->reg_mvfr1);
a6dc3cd7 634 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
3086d391 635 info->reg_mvfr2, boot->reg_mvfr2);
a6dc3cd7 636 }
3086d391
SP
637
638 /*
639 * Mismatched CPU features are a recipe for disaster. Don't even
640 * pretend to support them.
641 */
8dd0ee65
WD
642 if (taint) {
643 pr_warn_once("Unsupported CPU feature variation detected.\n");
644 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
645 }
cdcf817b
SP
646}
647
46823dd1 648u64 read_sanitised_ftr_reg(u32 id)
b3f15378
SP
649{
650 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
651
652 /* We shouldn't get a request for an unsupported register */
653 BUG_ON(!regp);
654 return regp->sys_val;
655}
359b7064 656
965861d6
MR
657#define read_sysreg_case(r) \
658 case r: return read_sysreg_s(r)
659
92406f0c 660/*
46823dd1 661 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
92406f0c
SP
662 * Read the system register on the current CPU
663 */
46823dd1 664static u64 __read_sysreg_by_encoding(u32 sys_id)
92406f0c
SP
665{
666 switch (sys_id) {
965861d6
MR
667 read_sysreg_case(SYS_ID_PFR0_EL1);
668 read_sysreg_case(SYS_ID_PFR1_EL1);
669 read_sysreg_case(SYS_ID_DFR0_EL1);
670 read_sysreg_case(SYS_ID_MMFR0_EL1);
671 read_sysreg_case(SYS_ID_MMFR1_EL1);
672 read_sysreg_case(SYS_ID_MMFR2_EL1);
673 read_sysreg_case(SYS_ID_MMFR3_EL1);
674 read_sysreg_case(SYS_ID_ISAR0_EL1);
675 read_sysreg_case(SYS_ID_ISAR1_EL1);
676 read_sysreg_case(SYS_ID_ISAR2_EL1);
677 read_sysreg_case(SYS_ID_ISAR3_EL1);
678 read_sysreg_case(SYS_ID_ISAR4_EL1);
679 read_sysreg_case(SYS_ID_ISAR5_EL1);
680 read_sysreg_case(SYS_MVFR0_EL1);
681 read_sysreg_case(SYS_MVFR1_EL1);
682 read_sysreg_case(SYS_MVFR2_EL1);
683
684 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
685 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
686 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
687 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
688 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
689 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
690 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
691 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
692 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
693
694 read_sysreg_case(SYS_CNTFRQ_EL0);
695 read_sysreg_case(SYS_CTR_EL0);
696 read_sysreg_case(SYS_DCZID_EL0);
697
92406f0c
SP
698 default:
699 BUG();
700 return 0;
701 }
702}
703
963fcd40
MZ
704#include <linux/irqchip/arm-gic-v3.h>
705
18ffa046
JM
706static bool
707feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
708{
28c5dcb2 709 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
18ffa046
JM
710
711 return val >= entry->min_field_value;
712}
713
da8d02d1 714static bool
92406f0c 715has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
da8d02d1
SP
716{
717 u64 val;
94a9e04a 718
92406f0c
SP
719 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
720 if (scope == SCOPE_SYSTEM)
46823dd1 721 val = read_sanitised_ftr_reg(entry->sys_reg);
92406f0c 722 else
46823dd1 723 val = __read_sysreg_by_encoding(entry->sys_reg);
92406f0c 724
da8d02d1
SP
725 return feature_matches(val, entry);
726}
338d4f49 727
92406f0c 728static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
963fcd40
MZ
729{
730 bool has_sre;
731
92406f0c 732 if (!has_cpuid_feature(entry, scope))
963fcd40
MZ
733 return false;
734
735 has_sre = gic_enable_sre();
736 if (!has_sre)
737 pr_warn_once("%s present but disabled by higher exception level\n",
738 entry->desc);
739
740 return has_sre;
741}
742
92406f0c 743static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
d5370f75
WD
744{
745 u32 midr = read_cpuid_id();
d5370f75
WD
746
747 /* Cavium ThunderX pass 1.x and 2.x */
fa5ce3d1
RR
748 return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX,
749 MIDR_CPU_VAR_REV(0, 0),
750 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
d5370f75
WD
751}
752
92406f0c 753static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
d88701be
MZ
754{
755 return is_kernel_in_hyp_mode();
756}
757
d1745910
MZ
758static bool hyp_offset_low(const struct arm64_cpu_capabilities *entry,
759 int __unused)
760{
2077be67 761 phys_addr_t idmap_addr = __pa_symbol(__hyp_idmap_text_start);
d1745910
MZ
762
763 /*
764 * Activate the lower HYP offset only if:
765 * - the idmap doesn't clash with it,
766 * - the kernel is not running at EL2.
767 */
768 return idmap_addr > GENMASK(VA_BITS - 2, 0) && !is_kernel_in_hyp_mode();
769}
770
82e0191a
SP
771static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
772{
46823dd1 773 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
82e0191a
SP
774
775 return cpuid_feature_extract_signed_field(pfr0,
776 ID_AA64PFR0_FP_SHIFT) < 0;
777}
778
359b7064 779static const struct arm64_cpu_capabilities arm64_features[] = {
94a9e04a
MZ
780 {
781 .desc = "GIC system register CPU interface",
782 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
92406f0c 783 .def_scope = SCOPE_SYSTEM,
963fcd40 784 .matches = has_useable_gicv3_cpuif,
da8d02d1
SP
785 .sys_reg = SYS_ID_AA64PFR0_EL1,
786 .field_pos = ID_AA64PFR0_GIC_SHIFT,
ff96f7bc 787 .sign = FTR_UNSIGNED,
18ffa046 788 .min_field_value = 1,
94a9e04a 789 },
338d4f49
JM
790#ifdef CONFIG_ARM64_PAN
791 {
792 .desc = "Privileged Access Never",
793 .capability = ARM64_HAS_PAN,
92406f0c 794 .def_scope = SCOPE_SYSTEM,
da8d02d1
SP
795 .matches = has_cpuid_feature,
796 .sys_reg = SYS_ID_AA64MMFR1_EL1,
797 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
ff96f7bc 798 .sign = FTR_UNSIGNED,
338d4f49
JM
799 .min_field_value = 1,
800 .enable = cpu_enable_pan,
801 },
802#endif /* CONFIG_ARM64_PAN */
2e94da13
WD
803#if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
804 {
805 .desc = "LSE atomic instructions",
806 .capability = ARM64_HAS_LSE_ATOMICS,
92406f0c 807 .def_scope = SCOPE_SYSTEM,
da8d02d1
SP
808 .matches = has_cpuid_feature,
809 .sys_reg = SYS_ID_AA64ISAR0_EL1,
810 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
ff96f7bc 811 .sign = FTR_UNSIGNED,
2e94da13
WD
812 .min_field_value = 2,
813 },
814#endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
d5370f75
WD
815 {
816 .desc = "Software prefetching using PRFM",
817 .capability = ARM64_HAS_NO_HW_PREFETCH,
92406f0c 818 .def_scope = SCOPE_SYSTEM,
d5370f75
WD
819 .matches = has_no_hw_prefetch,
820 },
57f4959b
JM
821#ifdef CONFIG_ARM64_UAO
822 {
823 .desc = "User Access Override",
824 .capability = ARM64_HAS_UAO,
92406f0c 825 .def_scope = SCOPE_SYSTEM,
57f4959b
JM
826 .matches = has_cpuid_feature,
827 .sys_reg = SYS_ID_AA64MMFR2_EL1,
828 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
829 .min_field_value = 1,
c8b06e3f
JM
830 /*
831 * We rely on stop_machine() calling uao_thread_switch() to set
832 * UAO immediately after patching.
833 */
57f4959b
JM
834 },
835#endif /* CONFIG_ARM64_UAO */
70544196
JM
836#ifdef CONFIG_ARM64_PAN
837 {
838 .capability = ARM64_ALT_PAN_NOT_UAO,
92406f0c 839 .def_scope = SCOPE_SYSTEM,
70544196
JM
840 .matches = cpufeature_pan_not_uao,
841 },
842#endif /* CONFIG_ARM64_PAN */
d88701be
MZ
843 {
844 .desc = "Virtualization Host Extensions",
845 .capability = ARM64_HAS_VIRT_HOST_EXTN,
92406f0c 846 .def_scope = SCOPE_SYSTEM,
d88701be
MZ
847 .matches = runs_at_el2,
848 },
042446a3
SP
849 {
850 .desc = "32-bit EL0 Support",
851 .capability = ARM64_HAS_32BIT_EL0,
92406f0c 852 .def_scope = SCOPE_SYSTEM,
042446a3
SP
853 .matches = has_cpuid_feature,
854 .sys_reg = SYS_ID_AA64PFR0_EL1,
855 .sign = FTR_UNSIGNED,
856 .field_pos = ID_AA64PFR0_EL0_SHIFT,
857 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
858 },
d1745910
MZ
859 {
860 .desc = "Reduced HYP mapping offset",
861 .capability = ARM64_HYP_OFFSET_LOW,
862 .def_scope = SCOPE_SYSTEM,
863 .matches = hyp_offset_low,
864 },
82e0191a
SP
865 {
866 /* FP/SIMD is not implemented */
867 .capability = ARM64_HAS_NO_FPSIMD,
868 .def_scope = SCOPE_SYSTEM,
869 .min_field_value = 0,
870 .matches = has_no_fpsimd,
871 },
359b7064
MZ
872 {},
873};
874
ff96f7bc 875#define HWCAP_CAP(reg, field, s, min_value, type, cap) \
37b01d53
SP
876 { \
877 .desc = #cap, \
92406f0c 878 .def_scope = SCOPE_SYSTEM, \
37b01d53
SP
879 .matches = has_cpuid_feature, \
880 .sys_reg = reg, \
881 .field_pos = field, \
ff96f7bc 882 .sign = s, \
37b01d53
SP
883 .min_field_value = min_value, \
884 .hwcap_type = type, \
885 .hwcap = cap, \
886 }
887
f3efb675 888static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
ff96f7bc
SP
889 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
890 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
891 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
892 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
893 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
894 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
f92f5ce0 895 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM),
ff96f7bc 896 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
bf500618 897 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
ff96f7bc 898 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
bf500618 899 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
c8c3798d 900 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),
cb567e79 901 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA),
c651aae5 902 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC),
75283501
SP
903 {},
904};
905
906static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
37b01d53 907#ifdef CONFIG_COMPAT
ff96f7bc
SP
908 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
909 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
910 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
911 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
912 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
37b01d53
SP
913#endif
914 {},
915};
916
f3efb675 917static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP
918{
919 switch (cap->hwcap_type) {
920 case CAP_HWCAP:
921 elf_hwcap |= cap->hwcap;
922 break;
923#ifdef CONFIG_COMPAT
924 case CAP_COMPAT_HWCAP:
925 compat_elf_hwcap |= (u32)cap->hwcap;
926 break;
927 case CAP_COMPAT_HWCAP2:
928 compat_elf_hwcap2 |= (u32)cap->hwcap;
929 break;
930#endif
931 default:
932 WARN_ON(1);
933 break;
934 }
935}
936
937/* Check if we have a particular HWCAP enabled */
f3efb675 938static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP
939{
940 bool rc;
941
942 switch (cap->hwcap_type) {
943 case CAP_HWCAP:
944 rc = (elf_hwcap & cap->hwcap) != 0;
945 break;
946#ifdef CONFIG_COMPAT
947 case CAP_COMPAT_HWCAP:
948 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
949 break;
950 case CAP_COMPAT_HWCAP2:
951 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
952 break;
953#endif
954 default:
955 WARN_ON(1);
956 rc = false;
957 }
958
959 return rc;
960}
961
75283501 962static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
37b01d53 963{
77c97b4e
SP
964 /* We support emulation of accesses to CPU ID feature registers */
965 elf_hwcap |= HWCAP_CPUID;
75283501 966 for (; hwcaps->matches; hwcaps++)
92406f0c 967 if (hwcaps->matches(hwcaps, hwcaps->def_scope))
75283501 968 cap_set_elf_hwcap(hwcaps);
37b01d53
SP
969}
970
ce8b602c 971void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
359b7064
MZ
972 const char *info)
973{
75283501 974 for (; caps->matches; caps++) {
92406f0c 975 if (!caps->matches(caps, caps->def_scope))
359b7064
MZ
976 continue;
977
75283501
SP
978 if (!cpus_have_cap(caps->capability) && caps->desc)
979 pr_info("%s %s\n", info, caps->desc);
980 cpus_set_cap(caps->capability);
359b7064 981 }
ce8b602c
SP
982}
983
984/*
dbb4e152
SP
985 * Run through the enabled capabilities and enable() it on all active
986 * CPUs
ce8b602c 987 */
8e231852 988void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
ce8b602c 989{
63a1e1c9
MR
990 for (; caps->matches; caps++) {
991 unsigned int num = caps->capability;
992
993 if (!cpus_have_cap(num))
994 continue;
995
996 /* Ensure cpus_have_const_cap(num) works */
997 static_branch_enable(&cpu_hwcap_keys[num]);
998
999 if (caps->enable) {
2a6dcb2b
JM
1000 /*
1001 * Use stop_machine() as it schedules the work allowing
1002 * us to modify PSTATE, instead of on_each_cpu() which
1003 * uses an IPI, giving us a PSTATE that disappears when
1004 * we return.
1005 */
1006 stop_machine(caps->enable, NULL, cpu_online_mask);
63a1e1c9
MR
1007 }
1008 }
dbb4e152
SP
1009}
1010
dbb4e152
SP
1011/*
1012 * Flag to indicate if we have computed the system wide
1013 * capabilities based on the boot time active CPUs. This
1014 * will be used to determine if a new booting CPU should
1015 * go through the verification process to make sure that it
1016 * supports the system capabilities, without using a hotplug
1017 * notifier.
1018 */
1019static bool sys_caps_initialised;
1020
1021static inline void set_sys_caps_initialised(void)
1022{
1023 sys_caps_initialised = true;
1024}
1025
1026/*
13f417f3
SP
1027 * Check for CPU features that are used in early boot
1028 * based on the Boot CPU value.
dbb4e152 1029 */
13f417f3 1030static void check_early_cpu_features(void)
dbb4e152 1031{
ac1ad20f 1032 verify_cpu_run_el();
13f417f3 1033 verify_cpu_asid_bits();
dbb4e152 1034}
1c076303 1035
75283501
SP
1036static void
1037verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1038{
1039
92406f0c
SP
1040 for (; caps->matches; caps++)
1041 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
75283501
SP
1042 pr_crit("CPU%d: missing HWCAP: %s\n",
1043 smp_processor_id(), caps->desc);
1044 cpu_die_early();
1045 }
75283501
SP
1046}
1047
1048static void
1049verify_local_cpu_features(const struct arm64_cpu_capabilities *caps)
1050{
1051 for (; caps->matches; caps++) {
92406f0c 1052 if (!cpus_have_cap(caps->capability))
75283501
SP
1053 continue;
1054 /*
1055 * If the new CPU misses an advertised feature, we cannot proceed
1056 * further, park the cpu.
1057 */
92406f0c 1058 if (!caps->matches(caps, SCOPE_LOCAL_CPU)) {
75283501
SP
1059 pr_crit("CPU%d: missing feature: %s\n",
1060 smp_processor_id(), caps->desc);
1061 cpu_die_early();
1062 }
1063 if (caps->enable)
1064 caps->enable(NULL);
1065 }
1066}
1067
dbb4e152
SP
1068/*
1069 * Run through the enabled system capabilities and enable() it on this CPU.
1070 * The capabilities were decided based on the available CPUs at the boot time.
1071 * Any new CPU should match the system wide status of the capability. If the
1072 * new CPU doesn't have a capability which the system now has enabled, we
1073 * cannot do anything to fix it up and could cause unexpected failures. So
1074 * we park the CPU.
1075 */
c47a1900 1076static void verify_local_cpu_capabilities(void)
dbb4e152 1077{
c47a1900
SP
1078 verify_local_cpu_errata_workarounds();
1079 verify_local_cpu_features(arm64_features);
1080 verify_local_elf_hwcaps(arm64_elf_hwcaps);
1081 if (system_supports_32bit_el0())
1082 verify_local_elf_hwcaps(compat_elf_hwcaps);
1083}
dbb4e152 1084
c47a1900
SP
1085void check_local_cpu_capabilities(void)
1086{
1087 /*
1088 * All secondary CPUs should conform to the early CPU features
1089 * in use by the kernel based on boot CPU.
1090 */
13f417f3
SP
1091 check_early_cpu_features();
1092
dbb4e152 1093 /*
c47a1900
SP
1094 * If we haven't finalised the system capabilities, this CPU gets
1095 * a chance to update the errata work arounds.
1096 * Otherwise, this CPU should verify that it has all the system
1097 * advertised capabilities.
dbb4e152
SP
1098 */
1099 if (!sys_caps_initialised)
c47a1900
SP
1100 update_cpu_errata_workarounds();
1101 else
1102 verify_local_cpu_capabilities();
359b7064
MZ
1103}
1104
a7c61a34 1105static void __init setup_feature_capabilities(void)
359b7064 1106{
ce8b602c
SP
1107 update_cpu_capabilities(arm64_features, "detected feature:");
1108 enable_cpu_capabilities(arm64_features);
359b7064
MZ
1109}
1110
63a1e1c9
MR
1111DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
1112EXPORT_SYMBOL(arm64_const_caps_ready);
1113
1114static void __init mark_const_caps_ready(void)
1115{
1116 static_branch_enable(&arm64_const_caps_ready);
1117}
1118
e3661b12
MZ
1119/*
1120 * Check if the current CPU has a given feature capability.
1121 * Should be called from non-preemptible context.
1122 */
8f413758
MZ
1123static bool __this_cpu_has_cap(const struct arm64_cpu_capabilities *cap_array,
1124 unsigned int cap)
e3661b12
MZ
1125{
1126 const struct arm64_cpu_capabilities *caps;
1127
1128 if (WARN_ON(preemptible()))
1129 return false;
1130
8f413758 1131 for (caps = cap_array; caps->desc; caps++)
e3661b12
MZ
1132 if (caps->capability == cap && caps->matches)
1133 return caps->matches(caps, SCOPE_LOCAL_CPU);
1134
1135 return false;
1136}
1137
8f413758
MZ
1138extern const struct arm64_cpu_capabilities arm64_errata[];
1139
1140bool this_cpu_has_cap(unsigned int cap)
1141{
1142 return (__this_cpu_has_cap(arm64_features, cap) ||
1143 __this_cpu_has_cap(arm64_errata, cap));
1144}
1145
9cdf8ec4 1146void __init setup_cpu_features(void)
359b7064 1147{
9cdf8ec4
SP
1148 u32 cwg;
1149 int cls;
1150
dbb4e152
SP
1151 /* Set the CPU feature capabilies */
1152 setup_feature_capabilities();
8e231852 1153 enable_errata_workarounds();
63a1e1c9 1154 mark_const_caps_ready();
75283501 1155 setup_elf_hwcaps(arm64_elf_hwcaps);
643d703d
SP
1156
1157 if (system_supports_32bit_el0())
1158 setup_elf_hwcaps(compat_elf_hwcaps);
dbb4e152
SP
1159
1160 /* Advertise that we have computed the system capabilities */
1161 set_sys_caps_initialised();
1162
9cdf8ec4
SP
1163 /*
1164 * Check for sane CTR_EL0.CWG value.
1165 */
1166 cwg = cache_type_cwg();
1167 cls = cache_line_size();
1168 if (!cwg)
1169 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
1170 cls);
1171 if (L1_CACHE_BYTES < cls)
1172 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
1173 L1_CACHE_BYTES, cls);
359b7064 1174}
70544196
JM
1175
1176static bool __maybe_unused
92406f0c 1177cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
70544196 1178{
a4023f68 1179 return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
70544196 1180}
77c97b4e
SP
1181
1182/*
1183 * We emulate only the following system register space.
1184 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
1185 * See Table C5-6 System instruction encodings for System register accesses,
1186 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
1187 */
1188static inline bool __attribute_const__ is_emulated(u32 id)
1189{
1190 return (sys_reg_Op0(id) == 0x3 &&
1191 sys_reg_CRn(id) == 0x0 &&
1192 sys_reg_Op1(id) == 0x0 &&
1193 (sys_reg_CRm(id) == 0 ||
1194 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
1195}
1196
1197/*
1198 * With CRm == 0, reg should be one of :
1199 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
1200 */
1201static inline int emulate_id_reg(u32 id, u64 *valp)
1202{
1203 switch (id) {
1204 case SYS_MIDR_EL1:
1205 *valp = read_cpuid_id();
1206 break;
1207 case SYS_MPIDR_EL1:
1208 *valp = SYS_MPIDR_SAFE_VAL;
1209 break;
1210 case SYS_REVIDR_EL1:
1211 /* IMPLEMENTATION DEFINED values are emulated with 0 */
1212 *valp = 0;
1213 break;
1214 default:
1215 return -EINVAL;
1216 }
1217
1218 return 0;
1219}
1220
1221static int emulate_sys_reg(u32 id, u64 *valp)
1222{
1223 struct arm64_ftr_reg *regp;
1224
1225 if (!is_emulated(id))
1226 return -EINVAL;
1227
1228 if (sys_reg_CRm(id) == 0)
1229 return emulate_id_reg(id, valp);
1230
1231 regp = get_arm64_ftr_reg(id);
1232 if (regp)
1233 *valp = arm64_ftr_reg_user_value(regp);
1234 else
1235 /*
1236 * The untracked registers are either IMPLEMENTATION DEFINED
1237 * (e.g, ID_AFR0_EL1) or reserved RAZ.
1238 */
1239 *valp = 0;
1240 return 0;
1241}
1242
1243static int emulate_mrs(struct pt_regs *regs, u32 insn)
1244{
1245 int rc;
1246 u32 sys_reg, dst;
1247 u64 val;
1248
1249 /*
1250 * sys_reg values are defined as used in mrs/msr instruction.
1251 * shift the imm value to get the encoding.
1252 */
1253 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
1254 rc = emulate_sys_reg(sys_reg, &val);
1255 if (!rc) {
1256 dst = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
521c6461 1257 pt_regs_write_reg(regs, dst, val);
77c97b4e
SP
1258 regs->pc += 4;
1259 }
1260
1261 return rc;
1262}
1263
1264static struct undef_hook mrs_hook = {
1265 .instr_mask = 0xfff00000,
1266 .instr_val = 0xd5300000,
1267 .pstate_mask = COMPAT_PSR_MODE_MASK,
1268 .pstate_val = PSR_MODE_EL0t,
1269 .fn = emulate_mrs,
1270};
1271
1272static int __init enable_mrs_emulation(void)
1273{
1274 register_undef_hook(&mrs_hook);
1275 return 0;
1276}
1277
1278late_initcall(enable_mrs_emulation);