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arm64: make dt_scan_depth1_nodes more readable
[mirror_ubuntu-artful-kernel.git] / arch / arm64 / kernel / cpufeature.c
CommitLineData
359b7064
MZ		 1/*
2 * Contains CPU feature definitions
3 *
4 * Copyright (C) 2015 ARM Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
9cdf8ec4 19#define pr_fmt(fmt) "CPU features: " fmt
359b7064 20
3c739b57
SP		 21#include <linux/bsearch.h>
22#include <linux/sort.h>
359b7064
MZ		 23#include <linux/types.h>
24#include <asm/cpu.h>
25#include <asm/cpufeature.h>
dbb4e152 26#include <asm/cpu_ops.h>
13f417f3 27#include <asm/mmu_context.h>
338d4f49 28#include <asm/processor.h>
cdcf817b 29#include <asm/sysreg.h>
d88701be 30#include <asm/virt.h>
359b7064 31
9cdf8ec4
SP		 32unsigned long elf_hwcap __read_mostly;
33EXPORT_SYMBOL_GPL(elf_hwcap);
34
35#ifdef CONFIG_COMPAT
36#define COMPAT_ELF_HWCAP_DEFAULT \
37 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
38 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
39 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
40 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
41 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
42 COMPAT_HWCAP_LPAE)
43unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
44unsigned int compat_elf_hwcap2 __read_mostly;
45#endif
46
47DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
48
4f0a606b 49#define __ARM64_FTR_BITS(SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
3c739b57 50 { \
4f0a606b 51 .sign = SIGNED, \
3c739b57
SP		 52 .strict = STRICT, \
53 .type = TYPE, \
54 .shift = SHIFT, \
55 .width = WIDTH, \
56 .safe_val = SAFE_VAL, \
57 }
58
0710cfdb 59/* Define a feature with unsigned values */
4f0a606b 60#define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
4f0a606b
SP		 61 __ARM64_FTR_BITS(FTR_UNSIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
62
0710cfdb
SP		 63/* Define a feature with a signed value */
64#define S_ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
65 __ARM64_FTR_BITS(FTR_SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
66
3c739b57
SP		 67#define ARM64_FTR_END \
68 { \
69 .width = 0, \
70 }
71
70544196
JM		 72/* meta feature for alternatives */
73static bool __maybe_unused
74cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry);
75
3c739b57
SP		 76static struct arm64_ftr_bits ftr_id_aa64isar0[] = {
77 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
78 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
79 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),
80 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
81 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
82 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
83 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
84 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
85 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
86 ARM64_FTR_END,
87};
88
89static struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
90 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
91 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),
92 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),
0710cfdb
SP		 93 S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
94 S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
3c739b57
SP		 95 /* Linux doesn't care about the EL3 */
96 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0),
97 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0),
98 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
99 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
100 ARM64_FTR_END,
101};
102
103static struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
104 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
0710cfdb
SP		 105 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
106 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
3c739b57
SP		 107 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
108 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
109 /* Linux shouldn't care about secure memory */
110 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
111 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
112 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
113 /*
114 * Differing PARange is fine as long as all peripherals and memory are mapped
115 * within the minimum PARange of all CPUs
116 */
0710cfdb 117 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
3c739b57
SP		 118 ARM64_FTR_END,
119};
120
121static struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
122 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
123 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
124 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
125 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
126 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
127 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
128 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
129 ARM64_FTR_END,
130};
131
406e3087 132static struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
7d7b4ae4
KW		 133 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
134 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
135 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
406e3087 136 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
7d7b4ae4 137 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
406e3087
JM		 138 ARM64_FTR_END,
139};
140
3c739b57 141static struct arm64_ftr_bits ftr_ctr[] = {
0710cfdb 142 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */
3c739b57 143 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0),
0710cfdb
SP		 144 ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */
145 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */
146 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */
3c739b57
SP		 147 /*
148 * Linux can handle differing I-cache policies. Userspace JITs will
149 * make use of *minLine
150 */
0710cfdb 151 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, 0), /* L1Ip */
3c739b57 152 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0), /* RAZ */
0710cfdb 153 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */
3c739b57
SP		 154 ARM64_FTR_END,
155};
156
157static struct arm64_ftr_bits ftr_id_mmfr0[] = {
0710cfdb 158 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0xf), /* InnerShr */
3c739b57
SP		 159 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0), /* FCSE */
160 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
161 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 4, 0), /* TCM */
162 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* ShareLvl */
0710cfdb 163 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0xf), /* OuterShr */
3c739b57
SP		 164 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */
165 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */
166 ARM64_FTR_END,
167};
168
169static struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
170 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
0710cfdb
SP		 171 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
172 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
173 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
174 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
175 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
176 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
3c739b57
SP		 177 ARM64_FTR_END,
178};
179
180static struct arm64_ftr_bits ftr_mvfr2[] = {
181 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
182 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* FPMisc */
183 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* SIMDMisc */
184 ARM64_FTR_END,
185};
186
187static struct arm64_ftr_bits ftr_dczid[] = {
188 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 5, 27, 0), /* RAZ */
189 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
190 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
191 ARM64_FTR_END,
192};
193
194
195static struct arm64_ftr_bits ftr_id_isar5[] = {
196 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0),
197 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 20, 4, 0), /* RAZ */
198 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0),
199 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0),
200 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0),
201 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0),
202 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0),
203 ARM64_FTR_END,
204};
205
206static struct arm64_ftr_bits ftr_id_mmfr4[] = {
207 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
208 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* ac2 */
209 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
210 ARM64_FTR_END,
211};
212
213static struct arm64_ftr_bits ftr_id_pfr0[] = {
214 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 16, 0), /* RAZ */
215 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* State3 */
216 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* State2 */
217 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* State1 */
218 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* State0 */
219 ARM64_FTR_END,
220};
221
e5343503
SP		 222static struct arm64_ftr_bits ftr_id_dfr0[] = {
223 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
0710cfdb 224 S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */
e5343503
SP		 225 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
226 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
227 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
228 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
229 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
230 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
231 ARM64_FTR_END,
232};
233
3c739b57
SP		 234/*
235 * Common ftr bits for a 32bit register with all hidden, strict
236 * attributes, with 4bit feature fields and a default safe value of
237 * 0. Covers the following 32bit registers:
238 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
239 */
240static struct arm64_ftr_bits ftr_generic_32bits[] = {
241 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
242 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
243 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
244 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
245 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
246 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
247 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
248 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
249 ARM64_FTR_END,
250};
251
252static struct arm64_ftr_bits ftr_generic[] = {
253 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
254 ARM64_FTR_END,
255};
256
257static struct arm64_ftr_bits ftr_generic32[] = {
258 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 32, 0),
259 ARM64_FTR_END,
260};
261
262static struct arm64_ftr_bits ftr_aa64raz[] = {
263 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
264 ARM64_FTR_END,
265};
266
267#define ARM64_FTR_REG(id, table) \
268 { \
269 .sys_id = id, \
270 .name = #id, \
271 .ftr_bits = &((table)[0]), \
272 }
273
274static struct arm64_ftr_reg arm64_ftr_regs[] = {
275
276 /* Op1 = 0, CRn = 0, CRm = 1 */
277 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
278 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
e5343503 279 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
3c739b57
SP		 280 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
281 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
282 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
283 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
284
285 /* Op1 = 0, CRn = 0, CRm = 2 */
286 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
287 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
288 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
289 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
290 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
291 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
292 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
293
294 /* Op1 = 0, CRn = 0, CRm = 3 */
295 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
296 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
297 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
298
299 /* Op1 = 0, CRn = 0, CRm = 4 */
300 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
301 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_aa64raz),
302
303 /* Op1 = 0, CRn = 0, CRm = 5 */
304 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
305 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_generic),
306
307 /* Op1 = 0, CRn = 0, CRm = 6 */
308 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
309 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_aa64raz),
310
311 /* Op1 = 0, CRn = 0, CRm = 7 */
312 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
313 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
406e3087 314 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
3c739b57
SP		 315
316 /* Op1 = 3, CRn = 0, CRm = 0 */
317 ARM64_FTR_REG(SYS_CTR_EL0, ftr_ctr),
318 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
319
320 /* Op1 = 3, CRn = 14, CRm = 0 */
321 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_generic32),
322};
323
324static int search_cmp_ftr_reg(const void *id, const void *regp)
325{
326 return (int)(unsigned long)id - (int)((const struct arm64_ftr_reg *)regp)->sys_id;
327}
328
329/*
330 * get_arm64_ftr_reg - Lookup a feature register entry using its
331 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
332 * ascending order of sys_id , we use binary search to find a matching
333 * entry.
334 *
335 * returns - Upon success, matching ftr_reg entry for id.
336 * - NULL on failure. It is upto the caller to decide
337 * the impact of a failure.
338 */
339static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
340{
341 return bsearch((const void *)(unsigned long)sys_id,
342 arm64_ftr_regs,
343 ARRAY_SIZE(arm64_ftr_regs),
344 sizeof(arm64_ftr_regs[0]),
345 search_cmp_ftr_reg);
346}
347
348static u64 arm64_ftr_set_value(struct arm64_ftr_bits *ftrp, s64 reg, s64 ftr_val)
349{
350 u64 mask = arm64_ftr_mask(ftrp);
351
352 reg &= ~mask;
353 reg |= (ftr_val << ftrp->shift) & mask;
354 return reg;
355}
356
357static s64 arm64_ftr_safe_value(struct arm64_ftr_bits *ftrp, s64 new, s64 cur)
358{
359 s64 ret = 0;
360
361 switch (ftrp->type) {
362 case FTR_EXACT:
363 ret = ftrp->safe_val;
364 break;
365 case FTR_LOWER_SAFE:
366 ret = new < cur ? new : cur;
367 break;
368 case FTR_HIGHER_SAFE:
369 ret = new > cur ? new : cur;
370 break;
371 default:
372 BUG();
373 }
374
375 return ret;
376}
377
378static int __init sort_cmp_ftr_regs(const void *a, const void *b)
379{
380 return ((const struct arm64_ftr_reg *)a)->sys_id -
381 ((const struct arm64_ftr_reg *)b)->sys_id;
382}
383
384static void __init swap_ftr_regs(void *a, void *b, int size)
385{
386 struct arm64_ftr_reg tmp = *(struct arm64_ftr_reg *)a;
387 *(struct arm64_ftr_reg *)a = *(struct arm64_ftr_reg *)b;
388 *(struct arm64_ftr_reg *)b = tmp;
389}
390
391static void __init sort_ftr_regs(void)
392{
393 /* Keep the array sorted so that we can do the binary search */
394 sort(arm64_ftr_regs,
395 ARRAY_SIZE(arm64_ftr_regs),
396 sizeof(arm64_ftr_regs[0]),
397 sort_cmp_ftr_regs,
398 swap_ftr_regs);
399}
400
401/*
402 * Initialise the CPU feature register from Boot CPU values.
403 * Also initiliases the strict_mask for the register.
404 */
405static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
406{
407 u64 val = 0;
408 u64 strict_mask = ~0x0ULL;
409 struct arm64_ftr_bits *ftrp;
410 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
411
412 BUG_ON(!reg);
413
414 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
415 s64 ftr_new = arm64_ftr_value(ftrp, new);
416
417 val = arm64_ftr_set_value(ftrp, val, ftr_new);
418 if (!ftrp->strict)
419 strict_mask &= ~arm64_ftr_mask(ftrp);
420 }
421 reg->sys_val = val;
422 reg->strict_mask = strict_mask;
423}
424
425void __init init_cpu_features(struct cpuinfo_arm64 *info)
426{
427 /* Before we start using the tables, make sure it is sorted */
428 sort_ftr_regs();
429
430 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
431 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
432 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
433 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
434 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
435 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
436 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
437 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
438 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
406e3087 439 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
3c739b57
SP		 440 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
441 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
a6dc3cd7
SP		 442
443 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
444 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
445 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
446 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
447 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
448 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
449 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
450 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
451 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
452 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
453 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
454 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
455 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
456 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
457 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
458 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
459 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
460 }
461
3c739b57
SP		 462}
463
3086d391 464static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
3c739b57
SP		 465{
466 struct arm64_ftr_bits *ftrp;
3c739b57
SP		 467
468 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
469 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
470 s64 ftr_new = arm64_ftr_value(ftrp, new);
471
472 if (ftr_cur == ftr_new)
473 continue;
474 /* Find a safe value */
475 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
476 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
477 }
478
479}
480
3086d391 481static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
cdcf817b 482{
3086d391
SP		 483 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
484
485 BUG_ON(!regp);
486 update_cpu_ftr_reg(regp, val);
487 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
488 return 0;
489 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
490 regp->name, boot, cpu, val);
491 return 1;
492}
493
494/*
495 * Update system wide CPU feature registers with the values from a
496 * non-boot CPU. Also performs SANITY checks to make sure that there
497 * aren't any insane variations from that of the boot CPU.
498 */
499void update_cpu_features(int cpu,
500 struct cpuinfo_arm64 *info,
501 struct cpuinfo_arm64 *boot)
502{
503 int taint = 0;
504
505 /*
506 * The kernel can handle differing I-cache policies, but otherwise
507 * caches should look identical. Userspace JITs will make use of
508 * *minLine.
509 */
510 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
511 info->reg_ctr, boot->reg_ctr);
512
513 /*
514 * Userspace may perform DC ZVA instructions. Mismatched block sizes
515 * could result in too much or too little memory being zeroed if a
516 * process is preempted and migrated between CPUs.
517 */
518 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
519 info->reg_dczid, boot->reg_dczid);
520
521 /* If different, timekeeping will be broken (especially with KVM) */
522 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
523 info->reg_cntfrq, boot->reg_cntfrq);
524
525 /*
526 * The kernel uses self-hosted debug features and expects CPUs to
527 * support identical debug features. We presently need CTX_CMPs, WRPs,
528 * and BRPs to be identical.
529 * ID_AA64DFR1 is currently RES0.
530 */
531 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
532 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
533 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
534 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
535 /*
536 * Even in big.LITTLE, processors should be identical instruction-set
537 * wise.
538 */
539 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
540 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
541 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
542 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
543
544 /*
545 * Differing PARange support is fine as long as all peripherals and
546 * memory are mapped within the minimum PARange of all CPUs.
547 * Linux should not care about secure memory.
548 */
549 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
550 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
551 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
552 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
406e3087
JM		 553 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
554 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
3086d391
SP		 555
556 /*
557 * EL3 is not our concern.
558 * ID_AA64PFR1 is currently RES0.
559 */
560 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
561 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
562 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
563 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
564
565 /*
a6dc3cd7
SP		 566 * If we have AArch32, we care about 32-bit features for compat.
567 * If the system doesn't support AArch32, don't update them.
3086d391 568 */
a6dc3cd7
SP		 569 if (id_aa64pfr0_32bit_el0(read_system_reg(SYS_ID_AA64PFR0_EL1)) &&
570 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
571
572 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
3086d391 573 info->reg_id_dfr0, boot->reg_id_dfr0);
a6dc3cd7 574 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
3086d391 575 info->reg_id_isar0, boot->reg_id_isar0);
a6dc3cd7 576 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
3086d391 577 info->reg_id_isar1, boot->reg_id_isar1);
a6dc3cd7 578 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
3086d391 579 info->reg_id_isar2, boot->reg_id_isar2);
a6dc3cd7 580 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
3086d391 581 info->reg_id_isar3, boot->reg_id_isar3);
a6dc3cd7 582 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
3086d391 583 info->reg_id_isar4, boot->reg_id_isar4);
a6dc3cd7 584 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
3086d391
SP		 585 info->reg_id_isar5, boot->reg_id_isar5);
586
a6dc3cd7
SP		 587 /*
588 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
589 * ACTLR formats could differ across CPUs and therefore would have to
590 * be trapped for virtualization anyway.
591 */
592 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
3086d391 593 info->reg_id_mmfr0, boot->reg_id_mmfr0);
a6dc3cd7 594 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
3086d391 595 info->reg_id_mmfr1, boot->reg_id_mmfr1);
a6dc3cd7 596 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
3086d391 597 info->reg_id_mmfr2, boot->reg_id_mmfr2);
a6dc3cd7 598 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
3086d391 599 info->reg_id_mmfr3, boot->reg_id_mmfr3);
a6dc3cd7 600 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
3086d391 601 info->reg_id_pfr0, boot->reg_id_pfr0);
a6dc3cd7 602 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
3086d391 603 info->reg_id_pfr1, boot->reg_id_pfr1);
a6dc3cd7 604 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
3086d391 605 info->reg_mvfr0, boot->reg_mvfr0);
a6dc3cd7 606 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
3086d391 607 info->reg_mvfr1, boot->reg_mvfr1);
a6dc3cd7 608 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
3086d391 609 info->reg_mvfr2, boot->reg_mvfr2);
a6dc3cd7 610 }
3086d391
SP		 611
612 /*
613 * Mismatched CPU features are a recipe for disaster. Don't even
614 * pretend to support them.
615 */
616 WARN_TAINT_ONCE(taint, TAINT_CPU_OUT_OF_SPEC,
617 "Unsupported CPU feature variation.\n");
cdcf817b
SP		 618}
619
b3f15378
SP		 620u64 read_system_reg(u32 id)
621{
622 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
623
624 /* We shouldn't get a request for an unsupported register */
625 BUG_ON(!regp);
626 return regp->sys_val;
627}
359b7064 628
963fcd40
MZ		 629#include <linux/irqchip/arm-gic-v3.h>
630
18ffa046
JM		 631static bool
632feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
633{
28c5dcb2 634 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
18ffa046
JM		 635
636 return val >= entry->min_field_value;
637}
638
da8d02d1
SP		 639static bool
640has_cpuid_feature(const struct arm64_cpu_capabilities *entry)
641{
642 u64 val;
94a9e04a 643
da8d02d1
SP		 644 val = read_system_reg(entry->sys_reg);
645 return feature_matches(val, entry);
646}
338d4f49 647
963fcd40
MZ		 648static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry)
649{
650 bool has_sre;
651
2dc10ad8 652 if (!has_cpuid_feature(entry))
963fcd40
MZ		 653 return false;
654
655 has_sre = gic_enable_sre();
656 if (!has_sre)
657 pr_warn_once("%s present but disabled by higher exception level\n",
658 entry->desc);
659
660 return has_sre;
661}
662
d5370f75
WD		 663static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry)
664{
665 u32 midr = read_cpuid_id();
666 u32 rv_min, rv_max;
667
668 /* Cavium ThunderX pass 1.x and 2.x */
669 rv_min = 0;
670 rv_max = (1 << MIDR_VARIANT_SHIFT) | MIDR_REVISION_MASK;
671
672 return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, rv_min, rv_max);
673}
674
d88701be
MZ		 675static bool runs_at_el2(const struct arm64_cpu_capabilities *entry)
676{
677 return is_kernel_in_hyp_mode();
678}
679
359b7064 680static const struct arm64_cpu_capabilities arm64_features[] = {
94a9e04a
MZ		 681 {
682 .desc = "GIC system register CPU interface",
683 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
963fcd40 684 .matches = has_useable_gicv3_cpuif,
da8d02d1
SP		 685 .sys_reg = SYS_ID_AA64PFR0_EL1,
686 .field_pos = ID_AA64PFR0_GIC_SHIFT,
ff96f7bc 687 .sign = FTR_UNSIGNED,
18ffa046 688 .min_field_value = 1,
94a9e04a 689 },
338d4f49
JM		 690#ifdef CONFIG_ARM64_PAN
691 {
692 .desc = "Privileged Access Never",
693 .capability = ARM64_HAS_PAN,
da8d02d1
SP		 694 .matches = has_cpuid_feature,
695 .sys_reg = SYS_ID_AA64MMFR1_EL1,
696 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
ff96f7bc 697 .sign = FTR_UNSIGNED,
338d4f49
JM		 698 .min_field_value = 1,
699 .enable = cpu_enable_pan,
700 },
701#endif /* CONFIG_ARM64_PAN */
2e94da13
WD		 702#if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
703 {
704 .desc = "LSE atomic instructions",
705 .capability = ARM64_HAS_LSE_ATOMICS,
da8d02d1
SP		 706 .matches = has_cpuid_feature,
707 .sys_reg = SYS_ID_AA64ISAR0_EL1,
708 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
ff96f7bc 709 .sign = FTR_UNSIGNED,
2e94da13
WD		 710 .min_field_value = 2,
711 },
712#endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
d5370f75
WD		 713 {
714 .desc = "Software prefetching using PRFM",
715 .capability = ARM64_HAS_NO_HW_PREFETCH,
716 .matches = has_no_hw_prefetch,
717 },
57f4959b
JM		 718#ifdef CONFIG_ARM64_UAO
719 {
720 .desc = "User Access Override",
721 .capability = ARM64_HAS_UAO,
722 .matches = has_cpuid_feature,
723 .sys_reg = SYS_ID_AA64MMFR2_EL1,
724 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
725 .min_field_value = 1,
726 .enable = cpu_enable_uao,
727 },
728#endif /* CONFIG_ARM64_UAO */
70544196
JM		 729#ifdef CONFIG_ARM64_PAN
730 {
731 .capability = ARM64_ALT_PAN_NOT_UAO,
732 .matches = cpufeature_pan_not_uao,
733 },
734#endif /* CONFIG_ARM64_PAN */
d88701be
MZ		 735 {
736 .desc = "Virtualization Host Extensions",
737 .capability = ARM64_HAS_VIRT_HOST_EXTN,
738 .matches = runs_at_el2,
739 },
042446a3
SP		 740 {
741 .desc = "32-bit EL0 Support",
742 .capability = ARM64_HAS_32BIT_EL0,
743 .matches = has_cpuid_feature,
744 .sys_reg = SYS_ID_AA64PFR0_EL1,
745 .sign = FTR_UNSIGNED,
746 .field_pos = ID_AA64PFR0_EL0_SHIFT,
747 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
748 },
359b7064
MZ		 749 {},
750};
751
ff96f7bc 752#define HWCAP_CAP(reg, field, s, min_value, type, cap) \
37b01d53
SP		 753 { \
754 .desc = #cap, \
755 .matches = has_cpuid_feature, \
756 .sys_reg = reg, \
757 .field_pos = field, \
ff96f7bc 758 .sign = s, \
37b01d53
SP		 759 .min_field_value = min_value, \
760 .hwcap_type = type, \
761 .hwcap = cap, \
762 }
763
f3efb675 764static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
ff96f7bc
SP		 765 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
766 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
767 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
768 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
769 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
770 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
771 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
bf500618 772 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
ff96f7bc 773 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
bf500618 774 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
75283501
SP		 775 {},
776};
777
778static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
37b01d53 779#ifdef CONFIG_COMPAT
ff96f7bc
SP		 780 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
781 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
782 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
783 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
784 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
37b01d53
SP		 785#endif
786 {},
787};
788
f3efb675 789static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 790{
791 switch (cap->hwcap_type) {
792 case CAP_HWCAP:
793 elf_hwcap |= cap->hwcap;
794 break;
795#ifdef CONFIG_COMPAT
796 case CAP_COMPAT_HWCAP:
797 compat_elf_hwcap |= (u32)cap->hwcap;
798 break;
799 case CAP_COMPAT_HWCAP2:
800 compat_elf_hwcap2 |= (u32)cap->hwcap;
801 break;
802#endif
803 default:
804 WARN_ON(1);
805 break;
806 }
807}
808
809/* Check if we have a particular HWCAP enabled */
f3efb675 810static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 811{
812 bool rc;
813
814 switch (cap->hwcap_type) {
815 case CAP_HWCAP:
816 rc = (elf_hwcap & cap->hwcap) != 0;
817 break;
818#ifdef CONFIG_COMPAT
819 case CAP_COMPAT_HWCAP:
820 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
821 break;
822 case CAP_COMPAT_HWCAP2:
823 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
824 break;
825#endif
826 default:
827 WARN_ON(1);
828 rc = false;
829 }
830
831 return rc;
832}
833
75283501 834static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
37b01d53 835{
75283501
SP		 836 for (; hwcaps->matches; hwcaps++)
837 if (hwcaps->matches(hwcaps))
838 cap_set_elf_hwcap(hwcaps);
37b01d53
SP		 839}
840
ce8b602c 841void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
359b7064
MZ		 842 const char *info)
843{
75283501
SP		 844 for (; caps->matches; caps++) {
845 if (!caps->matches(caps))
359b7064
MZ		 846 continue;
847
75283501
SP		 848 if (!cpus_have_cap(caps->capability) && caps->desc)
849 pr_info("%s %s\n", info, caps->desc);
850 cpus_set_cap(caps->capability);
359b7064 851 }
ce8b602c
SP		 852}
853
854/*
dbb4e152
SP		 855 * Run through the enabled capabilities and enable() it on all active
856 * CPUs
ce8b602c 857 */
a7c61a34
JZ		 858static void __init
859enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
ce8b602c 860{
75283501
SP		 861 for (; caps->matches; caps++)
862 if (caps->enable && cpus_have_cap(caps->capability))
863 on_each_cpu(caps->enable, NULL, true);
dbb4e152
SP		 864}
865
dbb4e152
SP		 866/*
867 * Flag to indicate if we have computed the system wide
868 * capabilities based on the boot time active CPUs. This
869 * will be used to determine if a new booting CPU should
870 * go through the verification process to make sure that it
871 * supports the system capabilities, without using a hotplug
872 * notifier.
873 */
874static bool sys_caps_initialised;
875
876static inline void set_sys_caps_initialised(void)
877{
878 sys_caps_initialised = true;
879}
880
da8d02d1
SP		 881/*
882 * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated.
883 */
884static u64 __raw_read_system_reg(u32 sys_id)
885{
886 switch (sys_id) {
1cc6ed90
MR		 887 case SYS_ID_PFR0_EL1: return read_cpuid(ID_PFR0_EL1);
888 case SYS_ID_PFR1_EL1: return read_cpuid(ID_PFR1_EL1);
889 case SYS_ID_DFR0_EL1: return read_cpuid(ID_DFR0_EL1);
890 case SYS_ID_MMFR0_EL1: return read_cpuid(ID_MMFR0_EL1);
891 case SYS_ID_MMFR1_EL1: return read_cpuid(ID_MMFR1_EL1);
892 case SYS_ID_MMFR2_EL1: return read_cpuid(ID_MMFR2_EL1);
893 case SYS_ID_MMFR3_EL1: return read_cpuid(ID_MMFR3_EL1);
894 case SYS_ID_ISAR0_EL1: return read_cpuid(ID_ISAR0_EL1);
895 case SYS_ID_ISAR1_EL1: return read_cpuid(ID_ISAR1_EL1);
896 case SYS_ID_ISAR2_EL1: return read_cpuid(ID_ISAR2_EL1);
897 case SYS_ID_ISAR3_EL1: return read_cpuid(ID_ISAR3_EL1);
898 case SYS_ID_ISAR4_EL1: return read_cpuid(ID_ISAR4_EL1);
899 case SYS_ID_ISAR5_EL1: return read_cpuid(ID_ISAR4_EL1);
900 case SYS_MVFR0_EL1: return read_cpuid(MVFR0_EL1);
901 case SYS_MVFR1_EL1: return read_cpuid(MVFR1_EL1);
902 case SYS_MVFR2_EL1: return read_cpuid(MVFR2_EL1);
903
904 case SYS_ID_AA64PFR0_EL1: return read_cpuid(ID_AA64PFR0_EL1);
905 case SYS_ID_AA64PFR1_EL1: return read_cpuid(ID_AA64PFR0_EL1);
906 case SYS_ID_AA64DFR0_EL1: return read_cpuid(ID_AA64DFR0_EL1);
907 case SYS_ID_AA64DFR1_EL1: return read_cpuid(ID_AA64DFR0_EL1);
908 case SYS_ID_AA64MMFR0_EL1: return read_cpuid(ID_AA64MMFR0_EL1);
909 case SYS_ID_AA64MMFR1_EL1: return read_cpuid(ID_AA64MMFR1_EL1);
910 case SYS_ID_AA64MMFR2_EL1: return read_cpuid(ID_AA64MMFR2_EL1);
911 case SYS_ID_AA64ISAR0_EL1: return read_cpuid(ID_AA64ISAR0_EL1);
912 case SYS_ID_AA64ISAR1_EL1: return read_cpuid(ID_AA64ISAR1_EL1);
913
914 case SYS_CNTFRQ_EL0: return read_cpuid(CNTFRQ_EL0);
915 case SYS_CTR_EL0: return read_cpuid(CTR_EL0);
916 case SYS_DCZID_EL0: return read_cpuid(DCZID_EL0);
da8d02d1
SP		 917 default:
918 BUG();
919 return 0;
920 }
921}
922
dbb4e152 923/*
13f417f3
SP		 924 * Check for CPU features that are used in early boot
925 * based on the Boot CPU value.
dbb4e152 926 */
13f417f3 927static void check_early_cpu_features(void)
dbb4e152 928{
ac1ad20f 929 verify_cpu_run_el();
13f417f3 930 verify_cpu_asid_bits();
dbb4e152 931}
1c076303 932
75283501
SP		 933static void
934verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
935{
936
937 for (; caps->matches; caps++) {
938 if (!cpus_have_elf_hwcap(caps))
939 continue;
940 if (!feature_matches(__raw_read_system_reg(caps->sys_reg), caps)) {
941 pr_crit("CPU%d: missing HWCAP: %s\n",
942 smp_processor_id(), caps->desc);
943 cpu_die_early();
944 }
945 }
946}
947
948static void
949verify_local_cpu_features(const struct arm64_cpu_capabilities *caps)
950{
951 for (; caps->matches; caps++) {
952 if (!cpus_have_cap(caps->capability) || !caps->sys_reg)
953 continue;
954 /*
955 * If the new CPU misses an advertised feature, we cannot proceed
956 * further, park the cpu.
957 */
958 if (!feature_matches(__raw_read_system_reg(caps->sys_reg), caps)) {
959 pr_crit("CPU%d: missing feature: %s\n",
960 smp_processor_id(), caps->desc);
961 cpu_die_early();
962 }
963 if (caps->enable)
964 caps->enable(NULL);
965 }
966}
967
dbb4e152
SP		 968/*
969 * Run through the enabled system capabilities and enable() it on this CPU.
970 * The capabilities were decided based on the available CPUs at the boot time.
971 * Any new CPU should match the system wide status of the capability. If the
972 * new CPU doesn't have a capability which the system now has enabled, we
973 * cannot do anything to fix it up and could cause unexpected failures. So
974 * we park the CPU.
975 */
976void verify_local_cpu_capabilities(void)
977{
dbb4e152 978
13f417f3
SP		 979 check_early_cpu_features();
980
dbb4e152
SP		 981 /*
982 * If we haven't computed the system capabilities, there is nothing
983 * to verify.
984 */
985 if (!sys_caps_initialised)
986 return;
987
75283501
SP		 988 verify_local_cpu_features(arm64_features);
989 verify_local_elf_hwcaps(arm64_elf_hwcaps);
643d703d
SP		 990 if (system_supports_32bit_el0())
991 verify_local_elf_hwcaps(compat_elf_hwcaps);
359b7064
MZ		 992}
993
a7c61a34 994static void __init setup_feature_capabilities(void)
359b7064 995{
ce8b602c
SP		 996 update_cpu_capabilities(arm64_features, "detected feature:");
997 enable_cpu_capabilities(arm64_features);
359b7064
MZ		 998}
999
9cdf8ec4 1000void __init setup_cpu_features(void)
359b7064 1001{
9cdf8ec4
SP		 1002 u32 cwg;
1003 int cls;
1004
dbb4e152
SP		 1005 /* Set the CPU feature capabilies */
1006 setup_feature_capabilities();
75283501 1007 setup_elf_hwcaps(arm64_elf_hwcaps);
643d703d
SP		 1008
1009 if (system_supports_32bit_el0())
1010 setup_elf_hwcaps(compat_elf_hwcaps);
dbb4e152
SP		 1011
1012 /* Advertise that we have computed the system capabilities */
1013 set_sys_caps_initialised();
1014
9cdf8ec4
SP		 1015 /*
1016 * Check for sane CTR_EL0.CWG value.
1017 */
1018 cwg = cache_type_cwg();
1019 cls = cache_line_size();
1020 if (!cwg)
1021 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
1022 cls);
1023 if (L1_CACHE_BYTES < cls)
1024 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
1025 L1_CACHE_BYTES, cls);
359b7064 1026}
70544196
JM		 1027
1028static bool __maybe_unused
1029cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry)
1030{
1031 return (cpus_have_cap(ARM64_HAS_PAN) && !cpus_have_cap(ARM64_HAS_UAO));
1032}
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