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arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR0 register
[mirror_ubuntu-jammy-kernel.git] / arch / arm64 / kernel / cpufeature.c
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caab277b 1// SPDX-License-Identifier: GPL-2.0-only
359b7064
MZ		 2/*
3 * Contains CPU feature definitions
4 *
5 * Copyright (C) 2015 ARM Ltd.
a2a69963
WD		 6 *
7 * A note for the weary kernel hacker: the code here is confusing and hard to
8 * follow! That's partly because it's solving a nasty problem, but also because
9 * there's a little bit of over-abstraction that tends to obscure what's going
10 * on behind a maze of helper functions and macros.
11 *
12 * The basic problem is that hardware folks have started gluing together CPUs
13 * with distinct architectural features; in some cases even creating SoCs where
14 * user-visible instructions are available only on a subset of the available
15 * cores. We try to address this by snapshotting the feature registers of the
16 * boot CPU and comparing these with the feature registers of each secondary
17 * CPU when bringing them up. If there is a mismatch, then we update the
18 * snapshot state to indicate the lowest-common denominator of the feature,
19 * known as the "safe" value. This snapshot state can be queried to view the
20 * "sanitised" value of a feature register.
21 *
22 * The sanitised register values are used to decide which capabilities we
23 * have in the system. These may be in the form of traditional "hwcaps"
24 * advertised to userspace or internal "cpucaps" which are used to configure
25 * things like alternative patching and static keys. While a feature mismatch
26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch
27 * may prevent a CPU from being onlined at all.
28 *
29 * Some implementation details worth remembering:
30 *
31 * - Mismatched features are *always* sanitised to a "safe" value, which
32 * usually indicates that the feature is not supported.
33 *
34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
35 * warning when onlining an offending CPU and the kernel will be tainted
36 * with TAINT_CPU_OUT_OF_SPEC.
37 *
38 * - Features marked as FTR_VISIBLE have their sanitised value visible to
39 * userspace. FTR_VISIBLE features in registers that are only visible
40 * to EL0 by trapping *must* have a corresponding HWCAP so that late
41 * onlining of CPUs cannot lead to features disappearing at runtime.
42 *
43 * - A "feature" is typically a 4-bit register field. A "capability" is the
44 * high-level description derived from the sanitised field value.
45 *
46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID
47 * scheme for fields in ID registers") to understand when feature fields
48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly).
49 *
50 * - KVM exposes its own view of the feature registers to guest operating
51 * systems regardless of FTR_VISIBLE. This is typically driven from the
52 * sanitised register values to allow virtual CPUs to be migrated between
53 * arbitrary physical CPUs, but some features not present on the host are
54 * also advertised and emulated. Look at sys_reg_descs[] for the gory
55 * details.
433022b5
WD		 56 *
57 * - If the arm64_ftr_bits[] for a register has a missing field, then this
58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg().
59 * This is stronger than FTR_HIDDEN and can be used to hide features from
60 * KVM guests.
359b7064
MZ		 61 */
62
9cdf8ec4 63#define pr_fmt(fmt) "CPU features: " fmt
359b7064 64
3c739b57 65#include <linux/bsearch.h>
2a6dcb2b 66#include <linux/cpumask.h>
5ffdfaed 67#include <linux/crash_dump.h>
3c739b57 68#include <linux/sort.h>
2a6dcb2b 69#include <linux/stop_machine.h>
359b7064 70#include <linux/types.h>
2077be67 71#include <linux/mm.h>
a111b7c0 72#include <linux/cpu.h>
359b7064
MZ		 73#include <asm/cpu.h>
74#include <asm/cpufeature.h>
dbb4e152 75#include <asm/cpu_ops.h>
2e0f2478 76#include <asm/fpsimd.h>
13f417f3 77#include <asm/mmu_context.h>
338d4f49 78#include <asm/processor.h>
cdcf817b 79#include <asm/sysreg.h>
77c97b4e 80#include <asm/traps.h>
d88701be 81#include <asm/virt.h>
359b7064 82
aec0bff7
AM		 83/* Kernel representation of AT_HWCAP and AT_HWCAP2 */
84static unsigned long elf_hwcap __read_mostly;
9cdf8ec4
SP		 85
86#ifdef CONFIG_COMPAT
87#define COMPAT_ELF_HWCAP_DEFAULT \
88 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
89 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
7559950a 90 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
9cdf8ec4
SP		 91 COMPAT_HWCAP_LPAE)
92unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
93unsigned int compat_elf_hwcap2 __read_mostly;
94#endif
95
96DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
4b65a5db 97EXPORT_SYMBOL(cpu_hwcaps);
82a3a21b 98static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
9cdf8ec4 99
0ceb0d56
DT		 100/* Need also bit for ARM64_CB_PATCH */
101DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
102
09e3c22a
MB		 103bool arm64_use_ng_mappings = false;
104EXPORT_SYMBOL(arm64_use_ng_mappings);
105
8f1eec57
DM		 106/*
107 * Flag to indicate if we have computed the system wide
108 * capabilities based on the boot time active CPUs. This
109 * will be used to determine if a new booting CPU should
110 * go through the verification process to make sure that it
111 * supports the system capabilities, without using a hotplug
b51c6ac2
SP		 112 * notifier. This is also used to decide if we could use
113 * the fast path for checking constant CPU caps.
8f1eec57 114 */
b51c6ac2
SP		 115DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
116EXPORT_SYMBOL(arm64_const_caps_ready);
117static inline void finalize_system_capabilities(void)
8f1eec57 118{
b51c6ac2 119 static_branch_enable(&arm64_const_caps_ready);
8f1eec57
DM		 120}
121
8effeaaf
MR		 122static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
123{
124 /* file-wide pr_fmt adds "CPU features: " prefix */
125 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
126 return 0;
127}
128
129static struct notifier_block cpu_hwcaps_notifier = {
130 .notifier_call = dump_cpu_hwcaps
131};
132
133static int __init register_cpu_hwcaps_dumper(void)
134{
135 atomic_notifier_chain_register(&panic_notifier_list,
136 &cpu_hwcaps_notifier);
137 return 0;
138}
139__initcall(register_cpu_hwcaps_dumper);
140
efd9e03f
CM		 141DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
142EXPORT_SYMBOL(cpu_hwcap_keys);
143
fe4fbdbc 144#define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
3c739b57 145 { \
4f0a606b 146 .sign = SIGNED, \
fe4fbdbc 147 .visible = VISIBLE, \
3c739b57
SP		 148 .strict = STRICT, \
149 .type = TYPE, \
150 .shift = SHIFT, \
151 .width = WIDTH, \
152 .safe_val = SAFE_VAL, \
153 }
154
0710cfdb 155/* Define a feature with unsigned values */
fe4fbdbc
SP		 156#define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
157 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
4f0a606b 158
0710cfdb 159/* Define a feature with a signed value */
fe4fbdbc
SP		 160#define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
161 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
0710cfdb 162
3c739b57
SP		 163#define ARM64_FTR_END \
164 { \
165 .width = 0, \
166 }
167
70544196
JM		 168/* meta feature for alternatives */
169static bool __maybe_unused
92406f0c
SP		 170cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
171
5ffdfaed 172static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
70544196 173
3ff047f6
ADK		 174static bool __system_matches_cap(unsigned int n);
175
4aa8a472
SP		 176/*
177 * NOTE: Any changes to the visibility of features should be kept in
178 * sync with the documentation of the CPU feature register ABI.
179 */
5e49d73c 180static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
1a50ec0b 181 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0),
7cd51a5a 182 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TLB_SHIFT, 4, 0),
7206dc93 183 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
3b3b6810 184 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
5bdecb79
SP		 185 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
186 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
187 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
188 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
189 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
fe4fbdbc
SP		 190 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
191 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
192 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
193 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
194 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
3c739b57
SP		 195 ARM64_FTR_END,
196};
197
c8c3798d 198static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
d4209d8b
SP		 199 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0),
200 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0),
201 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0),
202 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0),
bd4fb6d2 203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
7230f7e9 204 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
6984eb47
MR		 205 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
206 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
207 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
208 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
5bdecb79
SP		 209 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
210 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
211 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
6984eb47
MR		 212 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
213 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0),
214 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
215 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0),
5bdecb79 216 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
c8c3798d
SP		 217 ARM64_FTR_END,
218};
219
5e49d73c 220static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
179a56f6 221 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
0f15adbb 222 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
7206dc93 223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
2c9d45b4 224 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0),
011e5f5b
AK		 225 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0),
226 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0),
3fab3999
DM		 227 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
228 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
64c02720 229 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
5bdecb79 230 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
fe4fbdbc
SP		 231 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
232 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
5bdecb79 233 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
98448cdf
WD		 234 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
235 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
236 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
3c739b57
SP		 237 ARM64_FTR_END,
238};
239
d71be2b6 240static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
14e270fa
AK		 241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0),
242 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0),
d71be2b6 243 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
8ef8f360
DM		 244 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI),
245 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0),
d71be2b6
WD		 246 ARM64_FTR_END,
247};
248
06a916fe 249static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
d4209d8b
SP		 250 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
251 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0),
252 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
253 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0),
254 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
255 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0),
ec52c713
JG		 256 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
257 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
258 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
259 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
d4209d8b
SP		 260 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
261 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0),
ec52c713
JG		 262 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
263 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
264 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
265 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
266 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
267 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
06a916fe
DM		 268 ARM64_FTR_END,
269};
270
5e49d73c 271static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
bc67f10a
AK		 272 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0),
273 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0),
274 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0),
b130a8f7
MZ		 275 /*
276 * Page size not being supported at Stage-2 is not fatal. You
277 * just give up KVM if PAGE_SIZE isn't supported there. Go fix
278 * your favourite nesting hypervisor.
279 *
280 * There is a small corner case where the hypervisor explicitly
281 * advertises a given granule size at Stage-2 (value 2) on some
282 * vCPUs, and uses the fallback to Stage-1 (value 0) for other
283 * vCPUs. Although this is not forbidden by the architecture, it
284 * indicates that the hypervisor is being silly (or buggy).
285 *
286 * We make no effort to cope with this and pretend that if these
287 * fields are inconsistent across vCPUs, then it isn't worth
288 * trying to bring KVM up.
289 */
290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, 1),
291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, 1),
292 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, 1),
5717fe5a
WD		 293 /*
294 * We already refuse to boot CPUs that don't support our configured
295 * page size, so we can only detect mismatches for a page size other
296 * than the one we're currently using. Unfortunately, SoCs like this
297 * exist in the wild so, even though we don't like it, we'll have to go
298 * along with it and treat them as non-strict.
299 */
300 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
301 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
302 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
303
5bdecb79 304 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
3c739b57 305 /* Linux shouldn't care about secure memory */
5bdecb79
SP		 306 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
307 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
308 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
3c739b57
SP		 309 /*
310 * Differing PARange is fine as long as all peripherals and memory are mapped
311 * within the minimum PARange of all CPUs
312 */
fe4fbdbc 313 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
3c739b57
SP		 314 ARM64_FTR_END,
315};
316
5e49d73c 317static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
fe4fbdbc 318 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
5bdecb79
SP		 319 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
320 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
322 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
323 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
3c739b57
SP		 324 ARM64_FTR_END,
325};
326
5e49d73c 327static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
3e6c69a0 328 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0),
e48d53a9 329 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
7206dc93 330 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
5bdecb79 331 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
9d3f8881 332 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
5bdecb79
SP		 333 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
334 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
335 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
406e3087
JM		 336 ARM64_FTR_END,
337};
338
5e49d73c 339static const struct arm64_ftr_bits ftr_ctr[] = {
6ae4b6e0
SD		 340 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
341 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
342 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
147b9635
WD		 343 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
344 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
6ae4b6e0 345 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
3c739b57
SP		 346 /*
347 * Linux can handle differing I-cache policies. Userspace JITs will
ee7bc638 348 * make use of *minLine.
155433cb 349 * If we have differing I-cache policies, report it as the weakest - VIPT.
3c739b57 350 */
155433cb 351 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */
4c4a39dd 352 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
3c739b57
SP		 353 ARM64_FTR_END,
354};
355
675b0563
AB		 356struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
357 .name = "SYS_CTR_EL0",
358 .ftr_bits = ftr_ctr
359};
360
5e49d73c 361static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
5bdecb79
SP		 362 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf), /* InnerShr */
363 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), /* FCSE */
fe4fbdbc 364 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
5bdecb79
SP		 365 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), /* TCM */
366 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* ShareLvl */
367 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf), /* OuterShr */
368 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* PMSA */
369 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* VMSA */
3c739b57
SP		 370 ARM64_FTR_END,
371};
372
5e49d73c 373static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
e965bcb0 374 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 36, 4, 0),
fe4fbdbc
SP		 375 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
376 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
377 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
378 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
b20d1ba3
WD		 379 /*
380 * We can instantiate multiple PMU instances with different levels
381 * of support.
fe4fbdbc
SP		 382 */
383 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
384 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
385 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
3c739b57
SP		 386 ARM64_FTR_END,
387};
388
5e49d73c 389static const struct arm64_ftr_bits ftr_mvfr2[] = {
5bdecb79
SP		 390 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* FPMisc */
391 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* SIMDMisc */
3c739b57
SP		 392 ARM64_FTR_END,
393};
394
5e49d73c 395static const struct arm64_ftr_bits ftr_dczid[] = {
fe4fbdbc
SP		 396 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
397 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
3c739b57
SP		 398 ARM64_FTR_END,
399};
400
2a5bc6c4
AK		 401static const struct arm64_ftr_bits ftr_id_isar0[] = {
402 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0),
403 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0),
404 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0),
405 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0),
406 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0),
407 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0),
408 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0),
409 ARM64_FTR_END,
410};
3c739b57 411
5e49d73c 412static const struct arm64_ftr_bits ftr_id_isar5[] = {
5bdecb79
SP		 413 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
414 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
415 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
416 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
417 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
418 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
3c739b57
SP		 419 ARM64_FTR_END,
420};
421
5e49d73c 422static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
fcd65353
AK		 423 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0),
424 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0),
425 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0),
426 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0),
427 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0),
428 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0),
5bdecb79 429 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* ac2 */
fcd65353
AK		 430 /*
431 * SpecSEI = 1 indicates that the PE might generate an SError on an
432 * external abort on speculative read. It is safe to assume that an
433 * SError might be generated than it will not be. Hence it has been
434 * classified as FTR_HIGHER_SAFE.
435 */
436 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0),
3c739b57
SP		 437 ARM64_FTR_END,
438};
439
0113340e
WD		 440static const struct arm64_ftr_bits ftr_id_isar4[] = {
441 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0),
442 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0),
443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0),
444 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0),
445 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0),
446 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0),
447 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0),
448 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0),
449 ARM64_FTR_END,
450};
451
152accf8
AK		 452static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
453 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0),
454 ARM64_FTR_END,
455};
456
8e3747be
AK		 457static const struct arm64_ftr_bits ftr_id_isar6[] = {
458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),
459 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
460 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),
461 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),
462 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),
463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0),
464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0),
465 ARM64_FTR_END,
466};
467
5e49d73c 468static const struct arm64_ftr_bits ftr_id_pfr0[] = {
0ae43a99
AK		 469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0),
470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0),
5bdecb79
SP		 471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* State3 */
472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), /* State2 */
473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* State1 */
474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* State0 */
3c739b57
SP		 475 ARM64_FTR_END,
476};
477
0113340e
WD		 478static const struct arm64_ftr_bits ftr_id_pfr1[] = {
479 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0),
480 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0),
481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0),
482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0),
483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0),
484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0),
485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0),
486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0),
487 ARM64_FTR_END,
488};
489
16824085
AK		 490static const struct arm64_ftr_bits ftr_id_pfr2[] = {
491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0),
492 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0),
493 ARM64_FTR_END,
494};
495
5e49d73c 496static const struct arm64_ftr_bits ftr_id_dfr0[] = {
1ed1b90a 497 /* [31:28] TraceFilt */
fe4fbdbc
SP		 498 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */
499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
500 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
503 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
504 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
e5343503
SP		 505 ARM64_FTR_END,
506};
507
dd35ec07
AK		 508static const struct arm64_ftr_bits ftr_id_dfr1[] = {
509 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0),
510 ARM64_FTR_END,
511};
512
2e0f2478
DM		 513static const struct arm64_ftr_bits ftr_zcr[] = {
514 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
515 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */
516 ARM64_FTR_END,
517};
518
3c739b57
SP		 519/*
520 * Common ftr bits for a 32bit register with all hidden, strict
521 * attributes, with 4bit feature fields and a default safe value of
522 * 0. Covers the following 32bit registers:
2a5bc6c4 523 * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
3c739b57 524 */
5e49d73c 525static const struct arm64_ftr_bits ftr_generic_32bits[] = {
fe4fbdbc
SP		 526 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
527 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
528 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
529 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
530 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
531 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
532 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
533 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
3c739b57
SP		 534 ARM64_FTR_END,
535};
536
eab43e88
SP		 537/* Table for a single 32bit feature value */
538static const struct arm64_ftr_bits ftr_single32[] = {
fe4fbdbc 539 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
3c739b57
SP		 540 ARM64_FTR_END,
541};
542
eab43e88 543static const struct arm64_ftr_bits ftr_raz[] = {
3c739b57
SP		 544 ARM64_FTR_END,
545};
546
6f2b7eef
AB		 547#define ARM64_FTR_REG(id, table) { \
548 .sys_id = id, \
549 .reg = &(struct arm64_ftr_reg){ \
3c739b57
SP		 550 .name = #id, \
551 .ftr_bits = &((table)[0]), \
6f2b7eef 552 }}
3c739b57 553
6f2b7eef
AB		 554static const struct __ftr_reg_entry {
555 u32 sys_id;
556 struct arm64_ftr_reg *reg;
557} arm64_ftr_regs[] = {
3c739b57
SP		 558
559 /* Op1 = 0, CRn = 0, CRm = 1 */
560 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
0113340e 561 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1),
e5343503 562 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
3c739b57
SP		 563 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
564 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
565 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
566 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
567
568 /* Op1 = 0, CRn = 0, CRm = 2 */
2a5bc6c4 569 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0),
3c739b57
SP		 570 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
571 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
572 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
0113340e 573 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4),
3c739b57
SP		 574 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
575 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
8e3747be 576 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),
3c739b57
SP		 577
578 /* Op1 = 0, CRn = 0, CRm = 3 */
579 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
580 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
581 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
16824085 582 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
dd35ec07 583 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1),
152accf8 584 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5),
3c739b57
SP		 585
586 /* Op1 = 0, CRn = 0, CRm = 4 */
587 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
d71be2b6 588 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
06a916fe 589 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
3c739b57
SP		 590
591 /* Op1 = 0, CRn = 0, CRm = 5 */
592 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
eab43e88 593 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
3c739b57
SP		 594
595 /* Op1 = 0, CRn = 0, CRm = 6 */
596 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
c8c3798d 597 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
3c739b57
SP		 598
599 /* Op1 = 0, CRn = 0, CRm = 7 */
600 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
601 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
406e3087 602 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
3c739b57 603
2e0f2478
DM		 604 /* Op1 = 0, CRn = 1, CRm = 2 */
605 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
606
3c739b57 607 /* Op1 = 3, CRn = 0, CRm = 0 */
675b0563 608 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
3c739b57
SP		 609 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
610
611 /* Op1 = 3, CRn = 14, CRm = 0 */
eab43e88 612 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
3c739b57
SP		 613};
614
615static int search_cmp_ftr_reg(const void *id, const void *regp)
616{
6f2b7eef 617 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
3c739b57
SP		 618}
619
620/*
3577dd37
AK		 621 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using
622 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the
623 * ascending order of sys_id, we use binary search to find a matching
3c739b57
SP		 624 * entry.
625 *
626 * returns - Upon success, matching ftr_reg entry for id.
627 * - NULL on failure. It is upto the caller to decide
628 * the impact of a failure.
629 */
3577dd37 630static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id)
3c739b57 631{
6f2b7eef
AB		 632 const struct __ftr_reg_entry *ret;
633
634 ret = bsearch((const void *)(unsigned long)sys_id,
3c739b57
SP		 635 arm64_ftr_regs,
636 ARRAY_SIZE(arm64_ftr_regs),
637 sizeof(arm64_ftr_regs[0]),
638 search_cmp_ftr_reg);
6f2b7eef
AB		 639 if (ret)
640 return ret->reg;
641 return NULL;
3c739b57
SP		 642}
643
3577dd37
AK		 644/*
645 * get_arm64_ftr_reg - Looks up a feature register entry using
646 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn().
647 *
648 * returns - Upon success, matching ftr_reg entry for id.
649 * - NULL on failure but with an WARN_ON().
650 */
651static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
652{
653 struct arm64_ftr_reg *reg;
654
655 reg = get_arm64_ftr_reg_nowarn(sys_id);
656
657 /*
658 * Requesting a non-existent register search is an error. Warn
659 * and let the caller handle it.
660 */
661 WARN_ON(!reg);
662 return reg;
663}
664
5e49d73c
AB		 665static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
666 s64 ftr_val)
3c739b57
SP		 667{
668 u64 mask = arm64_ftr_mask(ftrp);
669
670 reg &= ~mask;
671 reg |= (ftr_val << ftrp->shift) & mask;
672 return reg;
673}
674
5e49d73c
AB		 675static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
676 s64 cur)
3c739b57
SP		 677{
678 s64 ret = 0;
679
680 switch (ftrp->type) {
681 case FTR_EXACT:
682 ret = ftrp->safe_val;
683 break;
684 case FTR_LOWER_SAFE:
685 ret = new < cur ? new : cur;
686 break;
147b9635
WD		 687 case FTR_HIGHER_OR_ZERO_SAFE:
688 if (!cur || !new)
689 break;
690 /* Fallthrough */
3c739b57
SP		 691 case FTR_HIGHER_SAFE:
692 ret = new > cur ? new : cur;
693 break;
694 default:
695 BUG();
696 }
697
698 return ret;
699}
700
3c739b57
SP		 701static void __init sort_ftr_regs(void)
702{
6f2b7eef
AB		 703 int i;
704
705 /* Check that the array is sorted so that we can do the binary search */
706 for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
707 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
3c739b57
SP		 708}
709
710/*
711 * Initialise the CPU feature register from Boot CPU values.
712 * Also initiliases the strict_mask for the register.
b389d799
MR		 713 * Any bits that are not covered by an arm64_ftr_bits entry are considered
714 * RES0 for the system-wide value, and must strictly match.
3c739b57
SP		 715 */
716static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
717{
718 u64 val = 0;
719 u64 strict_mask = ~0x0ULL;
fe4fbdbc 720 u64 user_mask = 0;
b389d799
MR		 721 u64 valid_mask = 0;
722
5e49d73c 723 const struct arm64_ftr_bits *ftrp;
3c739b57
SP		 724 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
725
3577dd37
AK		 726 if (!reg)
727 return;
3c739b57 728
24b2cce9 729 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
b389d799 730 u64 ftr_mask = arm64_ftr_mask(ftrp);
3c739b57
SP		 731 s64 ftr_new = arm64_ftr_value(ftrp, new);
732
733 val = arm64_ftr_set_value(ftrp, val, ftr_new);
b389d799
MR		 734
735 valid_mask |= ftr_mask;
3c739b57 736 if (!ftrp->strict)
b389d799 737 strict_mask &= ~ftr_mask;
fe4fbdbc
SP		 738 if (ftrp->visible)
739 user_mask |= ftr_mask;
740 else
741 reg->user_val = arm64_ftr_set_value(ftrp,
742 reg->user_val,
743 ftrp->safe_val);
3c739b57 744 }
b389d799
MR		 745
746 val &= valid_mask;
747
3c739b57
SP		 748 reg->sys_val = val;
749 reg->strict_mask = strict_mask;
fe4fbdbc 750 reg->user_mask = user_mask;
3c739b57
SP		 751}
752
1e89baed 753extern const struct arm64_cpu_capabilities arm64_errata[];
82a3a21b
SP		 754static const struct arm64_cpu_capabilities arm64_features[];
755
756static void __init
757init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
758{
759 for (; caps->matches; caps++) {
760 if (WARN(caps->capability >= ARM64_NCAPS,
761 "Invalid capability %d\n", caps->capability))
762 continue;
763 if (WARN(cpu_hwcaps_ptrs[caps->capability],
764 "Duplicate entry for capability %d\n",
765 caps->capability))
766 continue;
767 cpu_hwcaps_ptrs[caps->capability] = caps;
768 }
769}
770
771static void __init init_cpu_hwcaps_indirect_list(void)
772{
773 init_cpu_hwcaps_indirect_list_from_array(arm64_features);
774 init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
775}
776
fd9d63da 777static void __init setup_boot_cpu_capabilities(void);
1e89baed 778
3c739b57
SP		 779void __init init_cpu_features(struct cpuinfo_arm64 *info)
780{
781 /* Before we start using the tables, make sure it is sorted */
782 sort_ftr_regs();
783
784 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
785 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
786 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
787 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
788 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
789 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
790 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
791 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
792 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
406e3087 793 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
3c739b57
SP		 794 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
795 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
2e0f2478 796 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
a6dc3cd7
SP		 797
798 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
799 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
dd35ec07 800 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1);
a6dc3cd7
SP		 801 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
802 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
803 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
804 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
805 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
806 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
8e3747be 807 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6);
a6dc3cd7
SP		 808 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
809 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
810 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
811 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
858b8a80 812 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4);
152accf8 813 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5);
a6dc3cd7
SP		 814 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
815 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
16824085 816 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2);
a6dc3cd7
SP		 817 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
818 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
819 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
820 }
821
2e0f2478
DM		 822 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
823 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
824 sve_init_vq_map();
825 }
5e91107b 826
82a3a21b
SP		 827 /*
828 * Initialize the indirect array of CPU hwcaps capabilities pointers
829 * before we handle the boot CPU below.
830 */
831 init_cpu_hwcaps_indirect_list();
832
5e91107b 833 /*
fd9d63da
SP		 834 * Detect and enable early CPU capabilities based on the boot CPU,
835 * after we have initialised the CPU feature infrastructure.
5e91107b 836 */
fd9d63da 837 setup_boot_cpu_capabilities();
3c739b57
SP		 838}
839
3086d391 840static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
3c739b57 841{
5e49d73c 842 const struct arm64_ftr_bits *ftrp;
3c739b57
SP		 843
844 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
845 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
846 s64 ftr_new = arm64_ftr_value(ftrp, new);
847
848 if (ftr_cur == ftr_new)
849 continue;
850 /* Find a safe value */
851 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
852 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
853 }
854
855}
856
3086d391 857static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
cdcf817b 858{
3086d391
SP		 859 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
860
3577dd37
AK		 861 if (!regp)
862 return 0;
863
3086d391
SP		 864 update_cpu_ftr_reg(regp, val);
865 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
866 return 0;
867 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
868 regp->name, boot, cpu, val);
869 return 1;
870}
871
eab2f926
WD		 872static void relax_cpu_ftr_reg(u32 sys_id, int field)
873{
874 const struct arm64_ftr_bits *ftrp;
875 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
876
3577dd37 877 if (!regp)
eab2f926
WD		 878 return;
879
880 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) {
881 if (ftrp->shift == field) {
882 regp->strict_mask &= ~arm64_ftr_mask(ftrp);
883 break;
884 }
885 }
886
887 /* Bogus field? */
888 WARN_ON(!ftrp->width);
889}
890
1efcfe79
WD		 891static int update_32bit_cpu_features(int cpu, struct cpuinfo_arm64 *info,
892 struct cpuinfo_arm64 *boot)
893{
894 int taint = 0;
895 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
896
897 /*
898 * If we don't have AArch32 at all then skip the checks entirely
899 * as the register values may be UNKNOWN and we're not going to be
900 * using them for anything.
901 */
902 if (!id_aa64pfr0_32bit_el0(pfr0))
903 return taint;
904
eab2f926
WD		 905 /*
906 * If we don't have AArch32 at EL1, then relax the strictness of
907 * EL1-dependent register fields to avoid spurious sanity check fails.
908 */
909 if (!id_aa64pfr0_32bit_el1(pfr0)) {
910 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT);
911 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT);
912 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT);
913 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT);
914 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT);
915 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT);
916 }
917
1efcfe79
WD		 918 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
919 info->reg_id_dfr0, boot->reg_id_dfr0);
dd35ec07
AK		 920 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu,
921 info->reg_id_dfr1, boot->reg_id_dfr1);
1efcfe79
WD		 922 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
923 info->reg_id_isar0, boot->reg_id_isar0);
924 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
925 info->reg_id_isar1, boot->reg_id_isar1);
926 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
927 info->reg_id_isar2, boot->reg_id_isar2);
928 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
929 info->reg_id_isar3, boot->reg_id_isar3);
930 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
931 info->reg_id_isar4, boot->reg_id_isar4);
932 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
933 info->reg_id_isar5, boot->reg_id_isar5);
934 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu,
935 info->reg_id_isar6, boot->reg_id_isar6);
936
937 /*
938 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
939 * ACTLR formats could differ across CPUs and therefore would have to
940 * be trapped for virtualization anyway.
941 */
942 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
943 info->reg_id_mmfr0, boot->reg_id_mmfr0);
944 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
945 info->reg_id_mmfr1, boot->reg_id_mmfr1);
946 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
947 info->reg_id_mmfr2, boot->reg_id_mmfr2);
948 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
949 info->reg_id_mmfr3, boot->reg_id_mmfr3);
858b8a80
AK		 950 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu,
951 info->reg_id_mmfr4, boot->reg_id_mmfr4);
152accf8
AK		 952 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu,
953 info->reg_id_mmfr5, boot->reg_id_mmfr5);
1efcfe79
WD		 954 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
955 info->reg_id_pfr0, boot->reg_id_pfr0);
956 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
957 info->reg_id_pfr1, boot->reg_id_pfr1);
16824085
AK		 958 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu,
959 info->reg_id_pfr2, boot->reg_id_pfr2);
1efcfe79
WD		 960 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
961 info->reg_mvfr0, boot->reg_mvfr0);
962 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
963 info->reg_mvfr1, boot->reg_mvfr1);
964 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
965 info->reg_mvfr2, boot->reg_mvfr2);
966
967 return taint;
968}
969
3086d391
SP		 970/*
971 * Update system wide CPU feature registers with the values from a
972 * non-boot CPU. Also performs SANITY checks to make sure that there
973 * aren't any insane variations from that of the boot CPU.
974 */
975void update_cpu_features(int cpu,
976 struct cpuinfo_arm64 *info,
977 struct cpuinfo_arm64 *boot)
978{
979 int taint = 0;
980
981 /*
982 * The kernel can handle differing I-cache policies, but otherwise
983 * caches should look identical. Userspace JITs will make use of
984 * *minLine.
985 */
986 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
987 info->reg_ctr, boot->reg_ctr);
988
989 /*
990 * Userspace may perform DC ZVA instructions. Mismatched block sizes
991 * could result in too much or too little memory being zeroed if a
992 * process is preempted and migrated between CPUs.
993 */
994 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
995 info->reg_dczid, boot->reg_dczid);
996
997 /* If different, timekeeping will be broken (especially with KVM) */
998 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
999 info->reg_cntfrq, boot->reg_cntfrq);
1000
1001 /*
1002 * The kernel uses self-hosted debug features and expects CPUs to
1003 * support identical debug features. We presently need CTX_CMPs, WRPs,
1004 * and BRPs to be identical.
1005 * ID_AA64DFR1 is currently RES0.
1006 */
1007 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
1008 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
1009 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
1010 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
1011 /*
1012 * Even in big.LITTLE, processors should be identical instruction-set
1013 * wise.
1014 */
1015 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
1016 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
1017 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
1018 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
1019
1020 /*
1021 * Differing PARange support is fine as long as all peripherals and
1022 * memory are mapped within the minimum PARange of all CPUs.
1023 * Linux should not care about secure memory.
1024 */
1025 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
1026 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
1027 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
1028 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
406e3087
JM		 1029 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
1030 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
3086d391 1031
3086d391
SP		 1032 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
1033 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
1034 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
1035 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
1036
2e0f2478
DM		 1037 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
1038 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
1039
2e0f2478
DM		 1040 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
1041 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
1042 info->reg_zcr, boot->reg_zcr);
1043
1044 /* Probe vector lengths, unless we already gave up on SVE */
1045 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
b51c6ac2 1046 !system_capabilities_finalized())
2e0f2478
DM		 1047 sve_update_vq_map();
1048 }
1049
1efcfe79
WD		 1050 /*
1051 * This relies on a sanitised view of the AArch64 ID registers
1052 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last.
1053 */
1054 taint |= update_32bit_cpu_features(cpu, info, boot);
1055
3086d391
SP		 1056 /*
1057 * Mismatched CPU features are a recipe for disaster. Don't even
1058 * pretend to support them.
1059 */
8dd0ee65
WD		 1060 if (taint) {
1061 pr_warn_once("Unsupported CPU feature variation detected.\n");
1062 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1063 }
cdcf817b
SP		 1064}
1065
46823dd1 1066u64 read_sanitised_ftr_reg(u32 id)
b3f15378
SP		 1067{
1068 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
1069
3577dd37
AK		 1070 if (!regp)
1071 return 0;
b3f15378
SP		 1072 return regp->sys_val;
1073}
359b7064 1074
965861d6
MR		 1075#define read_sysreg_case(r) \
1076 case r: return read_sysreg_s(r)
1077
92406f0c 1078/*
46823dd1 1079 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
92406f0c
SP		 1080 * Read the system register on the current CPU
1081 */
46823dd1 1082static u64 __read_sysreg_by_encoding(u32 sys_id)
92406f0c
SP		 1083{
1084 switch (sys_id) {
965861d6
MR		 1085 read_sysreg_case(SYS_ID_PFR0_EL1);
1086 read_sysreg_case(SYS_ID_PFR1_EL1);
16824085 1087 read_sysreg_case(SYS_ID_PFR2_EL1);
965861d6 1088 read_sysreg_case(SYS_ID_DFR0_EL1);
dd35ec07 1089 read_sysreg_case(SYS_ID_DFR1_EL1);
965861d6
MR		 1090 read_sysreg_case(SYS_ID_MMFR0_EL1);
1091 read_sysreg_case(SYS_ID_MMFR1_EL1);
1092 read_sysreg_case(SYS_ID_MMFR2_EL1);
1093 read_sysreg_case(SYS_ID_MMFR3_EL1);
858b8a80 1094 read_sysreg_case(SYS_ID_MMFR4_EL1);
152accf8 1095 read_sysreg_case(SYS_ID_MMFR5_EL1);
965861d6
MR		 1096 read_sysreg_case(SYS_ID_ISAR0_EL1);
1097 read_sysreg_case(SYS_ID_ISAR1_EL1);
1098 read_sysreg_case(SYS_ID_ISAR2_EL1);
1099 read_sysreg_case(SYS_ID_ISAR3_EL1);
1100 read_sysreg_case(SYS_ID_ISAR4_EL1);
1101 read_sysreg_case(SYS_ID_ISAR5_EL1);
8e3747be 1102 read_sysreg_case(SYS_ID_ISAR6_EL1);
965861d6
MR		 1103 read_sysreg_case(SYS_MVFR0_EL1);
1104 read_sysreg_case(SYS_MVFR1_EL1);
1105 read_sysreg_case(SYS_MVFR2_EL1);
1106
1107 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
1108 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
78ed70bf 1109 read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
965861d6
MR		 1110 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
1111 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
1112 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
1113 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
1114 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
1115 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
1116 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
1117
1118 read_sysreg_case(SYS_CNTFRQ_EL0);
1119 read_sysreg_case(SYS_CTR_EL0);
1120 read_sysreg_case(SYS_DCZID_EL0);
1121
92406f0c
SP		 1122 default:
1123 BUG();
1124 return 0;
1125 }
1126}
1127
963fcd40
MZ		 1128#include <linux/irqchip/arm-gic-v3.h>
1129
18ffa046
JM		 1130static bool
1131feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
1132{
28c5dcb2 1133 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
18ffa046
JM		 1134
1135 return val >= entry->min_field_value;
1136}
1137
da8d02d1 1138static bool
92406f0c 1139has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
da8d02d1
SP		 1140{
1141 u64 val;
94a9e04a 1142
92406f0c
SP		 1143 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1144 if (scope == SCOPE_SYSTEM)
46823dd1 1145 val = read_sanitised_ftr_reg(entry->sys_reg);
92406f0c 1146 else
46823dd1 1147 val = __read_sysreg_by_encoding(entry->sys_reg);
92406f0c 1148
da8d02d1
SP		 1149 return feature_matches(val, entry);
1150}
338d4f49 1151
92406f0c 1152static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
963fcd40
MZ		 1153{
1154 bool has_sre;
1155
92406f0c 1156 if (!has_cpuid_feature(entry, scope))
963fcd40
MZ		 1157 return false;
1158
1159 has_sre = gic_enable_sre();
1160 if (!has_sre)
1161 pr_warn_once("%s present but disabled by higher exception level\n",
1162 entry->desc);
1163
1164 return has_sre;
1165}
1166
92406f0c 1167static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
d5370f75
WD		 1168{
1169 u32 midr = read_cpuid_id();
d5370f75
WD		 1170
1171 /* Cavium ThunderX pass 1.x and 2.x */
b99286b0 1172 return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
fa5ce3d1
RR		 1173 MIDR_CPU_VAR_REV(0, 0),
1174 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
d5370f75
WD		 1175}
1176
82e0191a
SP		 1177static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
1178{
46823dd1 1179 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
82e0191a
SP		 1180
1181 return cpuid_feature_extract_signed_field(pfr0,
1182 ID_AA64PFR0_FP_SHIFT) < 0;
1183}
1184
6ae4b6e0 1185static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
8ab66cbe 1186 int scope)
6ae4b6e0 1187{
8ab66cbe
SP		 1188 u64 ctr;
1189
1190 if (scope == SCOPE_SYSTEM)
1191 ctr = arm64_ftr_reg_ctrel0.sys_val;
1192 else
1602df02 1193 ctr = read_cpuid_effective_cachetype();
8ab66cbe
SP		 1194
1195 return ctr & BIT(CTR_IDC_SHIFT);
6ae4b6e0
SD		 1196}
1197
1602df02
SP		 1198static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
1199{
1200 /*
1201 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
1202 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
1203 * to the CTR_EL0 on this CPU and emulate it with the real/safe
1204 * value.
1205 */
1206 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
1207 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
1208}
1209
6ae4b6e0 1210static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
8ab66cbe 1211 int scope)
6ae4b6e0 1212{
8ab66cbe
SP		 1213 u64 ctr;
1214
1215 if (scope == SCOPE_SYSTEM)
1216 ctr = arm64_ftr_reg_ctrel0.sys_val;
1217 else
1218 ctr = read_cpuid_cachetype();
1219
1220 return ctr & BIT(CTR_DIC_SHIFT);
6ae4b6e0
SD		 1221}
1222
5ffdfaed
VM		 1223static bool __maybe_unused
1224has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
1225{
1226 /*
1227 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
1228 * may share TLB entries with a CPU stuck in the crashed
1229 * kernel.
1230 */
1231 if (is_kdump_kernel())
1232 return false;
1233
1234 return has_cpuid_feature(entry, scope);
1235}
1236
09e3c22a
MB		 1237/*
1238 * This check is triggered during the early boot before the cpufeature
1239 * is initialised. Checking the status on the local CPU allows the boot
1240 * CPU to detect the need for non-global mappings and thus avoiding a
1241 * pagetable re-write after all the CPUs are booted. This check will be
1242 * anyway run on individual CPUs, allowing us to get the consistent
1243 * state once the SMP CPUs are up and thus make the switch to non-global
1244 * mappings if required.
1245 */
1246bool kaslr_requires_kpti(void)
1247{
09e3c22a
MB		 1248 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE))
1249 return false;
1250
1251 /*
1252 * E0PD does a similar job to KPTI so can be used instead
1253 * where available.
1254 */
1255 if (IS_ENABLED(CONFIG_ARM64_E0PD)) {
a569f5f3
WD		 1256 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1);
1257 if (cpuid_feature_extract_unsigned_field(mmfr2,
1258 ID_AA64MMFR2_E0PD_SHIFT))
09e3c22a
MB		 1259 return false;
1260 }
1261
1262 /*
1263 * Systems affected by Cavium erratum 24756 are incompatible
1264 * with KPTI.
1265 */
ebac96ed 1266 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) {
09e3c22a
MB		 1267 extern const struct midr_range cavium_erratum_27456_cpus[];
1268
ebac96ed
WD		 1269 if (is_midr_in_range_list(read_cpuid_id(),
1270 cavium_erratum_27456_cpus))
1271 return false;
09e3c22a 1272 }
09e3c22a
MB		 1273
1274 return kaslr_offset() > 0;
1275}
1276
1b3ccf4b 1277static bool __meltdown_safe = true;
ea1e3de8
WD		 1278static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
1279
1280static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
d3aec8a2 1281 int scope)
ea1e3de8 1282{
be5b2998
SP		 1283 /* List of CPUs that are not vulnerable and don't need KPTI */
1284 static const struct midr_range kpti_safe_list[] = {
1285 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
1286 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
31d868c4 1287 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
2a355ec2
WD		 1288 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
1289 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
1290 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1291 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
1292 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
1293 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
0ecc471a 1294 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
918e1946 1295 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
f4617be3
SPR		 1296 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
1297 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
71c751f2 1298 { /* sentinel */ }
be5b2998 1299 };
a111b7c0 1300 char const *str = "kpti command line option";
1b3ccf4b
JL		 1301 bool meltdown_safe;
1302
1303 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
1304
1305 /* Defer to CPU feature registers */
1306 if (has_cpuid_feature(entry, scope))
1307 meltdown_safe = true;
1308
1309 if (!meltdown_safe)
1310 __meltdown_safe = false;
179a56f6 1311
6dc52b15
MZ		 1312 /*
1313 * For reasons that aren't entirely clear, enabling KPTI on Cavium
1314 * ThunderX leads to apparent I-cache corruption of kernel text, which
1315 * ends as well as you might imagine. Don't even try.
1316 */
1317 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1318 str = "ARM64_WORKAROUND_CAVIUM_27456";
1319 __kpti_forced = -1;
1320 }
1321
1b3ccf4b 1322 /* Useful for KASLR robustness */
c2d92353 1323 if (kaslr_requires_kpti()) {
1b3ccf4b
JL		 1324 if (!__kpti_forced) {
1325 str = "KASLR";
1326 __kpti_forced = 1;
1327 }
1328 }
1329
a111b7c0
JP		 1330 if (cpu_mitigations_off() && !__kpti_forced) {
1331 str = "mitigations=off";
1332 __kpti_forced = -1;
1333 }
1334
1b3ccf4b
JL		 1335 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1336 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1337 return false;
1338 }
1339
6dc52b15 1340 /* Forced? */
ea1e3de8 1341 if (__kpti_forced) {
6dc52b15
MZ		 1342 pr_info_once("kernel page table isolation forced %s by %s\n",
1343 __kpti_forced > 0 ? "ON" : "OFF", str);
ea1e3de8
WD		 1344 return __kpti_forced > 0;
1345 }
1346
1b3ccf4b 1347 return !meltdown_safe;
ea1e3de8
WD		 1348}
1349
1b3ccf4b 1350#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
c0cda3b8
DM		 1351static void
1352kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
f992b4df
WD		 1353{
1354 typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1355 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1356 kpti_remap_fn *remap_fn;
1357
f992b4df
WD		 1358 int cpu = smp_processor_id();
1359
b89d82ef
WD		 1360 /*
1361 * We don't need to rewrite the page-tables if either we've done
1362 * it already or we have KASLR enabled and therefore have not
1363 * created any global mappings at all.
1364 */
09e3c22a 1365 if (arm64_use_ng_mappings)
c0cda3b8 1366 return;
f992b4df
WD		 1367
1368 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
1369
1370 cpu_install_idmap();
1371 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1372 cpu_uninstall_idmap();
1373
1374 if (!cpu)
09e3c22a 1375 arm64_use_ng_mappings = true;
f992b4df 1376
c0cda3b8 1377 return;
f992b4df 1378}
1b3ccf4b
JL		 1379#else
1380static void
1381kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1382{
1383}
1384#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
f992b4df 1385
ea1e3de8
WD		 1386static int __init parse_kpti(char *str)
1387{
1388 bool enabled;
1389 int ret = strtobool(str, &enabled);
1390
1391 if (ret)
1392 return ret;
1393
1394 __kpti_forced = enabled ? 1 : -1;
1395 return 0;
1396}
b5b7dd64 1397early_param("kpti", parse_kpti);
ea1e3de8 1398
05abb595
SP		 1399#ifdef CONFIG_ARM64_HW_AFDBM
1400static inline void __cpu_enable_hw_dbm(void)
1401{
1402 u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1403
1404 write_sysreg(tcr, tcr_el1);
1405 isb();
1406}
1407
ece1397c
SP		 1408static bool cpu_has_broken_dbm(void)
1409{
1410 /* List of CPUs which have broken DBM support. */
1411 static const struct midr_range cpus[] = {
1412#ifdef CONFIG_ARM64_ERRATUM_1024718
1413 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0
1414#endif
1415 {},
1416 };
1417
1418 return is_midr_in_range_list(read_cpuid_id(), cpus);
1419}
1420
05abb595
SP		 1421static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1422{
ece1397c
SP		 1423 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1424 !cpu_has_broken_dbm();
05abb595
SP		 1425}
1426
1427static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1428{
1429 if (cpu_can_use_dbm(cap))
1430 __cpu_enable_hw_dbm();
1431}
1432
1433static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1434 int __unused)
1435{
1436 static bool detected = false;
1437 /*
1438 * DBM is a non-conflicting feature. i.e, the kernel can safely
1439 * run a mix of CPUs with and without the feature. So, we
1440 * unconditionally enable the capability to allow any late CPU
1441 * to use the feature. We only enable the control bits on the
1442 * CPU, if it actually supports.
1443 *
1444 * We have to make sure we print the "feature" detection only
1445 * when at least one CPU actually uses it. So check if this CPU
1446 * can actually use it and print the message exactly once.
1447 *
1448 * This is safe as all CPUs (including secondary CPUs - due to the
1449 * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1450 * goes through the "matches" check exactly once. Also if a CPU
1451 * matches the criteria, it is guaranteed that the CPU will turn
1452 * the DBM on, as the capability is unconditionally enabled.
1453 */
1454 if (!detected && cpu_can_use_dbm(cap)) {
1455 detected = true;
1456 pr_info("detected: Hardware dirty bit management\n");
1457 }
1458
1459 return true;
1460}
1461
1462#endif
1463
2c9d45b4
IV		 1464#ifdef CONFIG_ARM64_AMU_EXTN
1465
1466/*
1467 * The "amu_cpus" cpumask only signals that the CPU implementation for the
1468 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide
1469 * information regarding all the events that it supports. When a CPU bit is
1470 * set in the cpumask, the user of this feature can only rely on the presence
1471 * of the 4 fixed counters for that CPU. But this does not guarantee that the
1472 * counters are enabled or access to these counters is enabled by code
1473 * executed at higher exception levels (firmware).
1474 */
1475static struct cpumask amu_cpus __read_mostly;
1476
1477bool cpu_has_amu_feat(int cpu)
1478{
1479 return cpumask_test_cpu(cpu, &amu_cpus);
1480}
1481
cd0ed03a
IV		 1482/* Initialize the use of AMU counters for frequency invariance */
1483extern void init_cpu_freq_invariance_counters(void);
1484
2c9d45b4
IV		 1485static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)
1486{
1487 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) {
1488 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n",
1489 smp_processor_id());
1490 cpumask_set_cpu(smp_processor_id(), &amu_cpus);
cd0ed03a 1491 init_cpu_freq_invariance_counters();
2c9d45b4
IV		 1492 }
1493}
1494
1495static bool has_amu(const struct arm64_cpu_capabilities *cap,
1496 int __unused)
1497{
1498 /*
1499 * The AMU extension is a non-conflicting feature: the kernel can
1500 * safely run a mix of CPUs with and without support for the
1501 * activity monitors extension. Therefore, unconditionally enable
1502 * the capability to allow any late CPU to use the feature.
1503 *
1504 * With this feature unconditionally enabled, the cpu_enable
1505 * function will be called for all CPUs that match the criteria,
1506 * including secondary and hotplugged, marking this feature as
1507 * present on that respective CPU. The enable function will also
1508 * print a detection message.
1509 */
1510
1511 return true;
1512}
1513#endif
1514
12eb3691
WD		 1515#ifdef CONFIG_ARM64_VHE
1516static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1517{
1518 return is_kernel_in_hyp_mode();
1519}
1520
c0cda3b8 1521static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
6d99b689
JM		 1522{
1523 /*
1524 * Copy register values that aren't redirected by hardware.
1525 *
1526 * Before code patching, we only set tpidr_el1, all CPUs need to copy
1527 * this value to tpidr_el2 before we patch the code. Once we've done
1528 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1529 * do anything here.
1530 */
e9ab7a2e 1531 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
6d99b689 1532 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
6d99b689 1533}
12eb3691 1534#endif
6d99b689 1535
e48d53a9
MZ		 1536static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1537{
1538 u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1539
1540 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1541 WARN_ON(val & (7 << 27 | 7 << 21));
1542}
1543
8f04e8e6
WD		 1544#ifdef CONFIG_ARM64_SSBD
1545static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
1546{
1547 if (user_mode(regs))
1548 return 1;
1549
74e24828 1550 if (instr & BIT(PSTATE_Imm_shift))
8f04e8e6
WD		 1551 regs->pstate |= PSR_SSBS_BIT;
1552 else
1553 regs->pstate &= ~PSR_SSBS_BIT;
1554
1555 arm64_skip_faulting_instruction(regs, 4);
1556 return 0;
1557}
1558
1559static struct undef_hook ssbs_emulation_hook = {
74e24828
SP		 1560 .instr_mask = ~(1U << PSTATE_Imm_shift),
1561 .instr_val = 0xd500401f | PSTATE_SSBS,
8f04e8e6
WD		 1562 .fn = ssbs_emulation_handler,
1563};
1564
1565static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
1566{
1567 static bool undef_hook_registered = false;
27e6e7d6 1568 static DEFINE_RAW_SPINLOCK(hook_lock);
8f04e8e6 1569
27e6e7d6 1570 raw_spin_lock(&hook_lock);
8f04e8e6
WD		 1571 if (!undef_hook_registered) {
1572 register_undef_hook(&ssbs_emulation_hook);
1573 undef_hook_registered = true;
1574 }
27e6e7d6 1575 raw_spin_unlock(&hook_lock);
8f04e8e6
WD		 1576
1577 if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
1578 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
1579 arm64_set_ssbd_mitigation(false);
1580 } else {
1581 arm64_set_ssbd_mitigation(true);
1582 }
1583}
1584#endif /* CONFIG_ARM64_SSBD */
1585
b8925ee2
WD		 1586#ifdef CONFIG_ARM64_PAN
1587static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1588{
1589 /*
1590 * We modify PSTATE. This won't work from irq context as the PSTATE
1591 * is discarded once we return from the exception.
1592 */
1593 WARN_ON_ONCE(in_interrupt());
1594
1595 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1596 asm(SET_PSTATE_PAN(1));
1597}
1598#endif /* CONFIG_ARM64_PAN */
1599
1600#ifdef CONFIG_ARM64_RAS_EXTN
1601static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1602{
1603 /* Firmware may have left a deferred SError in this register. */
1604 write_sysreg_s(0, SYS_DISR_EL1);
1605}
1606#endif /* CONFIG_ARM64_RAS_EXTN */
1607
6984eb47 1608#ifdef CONFIG_ARM64_PTR_AUTH
cfef06bd
KM		 1609static bool has_address_auth(const struct arm64_cpu_capabilities *entry,
1610 int __unused)
1611{
1612 return __system_matches_cap(ARM64_HAS_ADDRESS_AUTH_ARCH) ||
1613 __system_matches_cap(ARM64_HAS_ADDRESS_AUTH_IMP_DEF);
1614}
1615
1616static bool has_generic_auth(const struct arm64_cpu_capabilities *entry,
1617 int __unused)
75031975 1618{
cfef06bd
KM		 1619 return __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH) ||
1620 __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF);
75031975 1621}
6984eb47
MR		 1622#endif /* CONFIG_ARM64_PTR_AUTH */
1623
3e6c69a0
MB		 1624#ifdef CONFIG_ARM64_E0PD
1625static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)
1626{
1627 if (this_cpu_has_cap(ARM64_HAS_E0PD))
1628 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1);
1629}
1630#endif /* CONFIG_ARM64_E0PD */
1631
b90d2b22 1632#ifdef CONFIG_ARM64_PSEUDO_NMI
bc3c03cc
JT		 1633static bool enable_pseudo_nmi;
1634
1635static int __init early_enable_pseudo_nmi(char *p)
1636{
1637 return strtobool(p, &enable_pseudo_nmi);
1638}
1639early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1640
b90d2b22
JT		 1641static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1642 int scope)
1643{
bc3c03cc 1644 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
b90d2b22
JT		 1645}
1646#endif
1647
8ef8f360
DM		 1648#ifdef CONFIG_ARM64_BTI
1649static void bti_enable(const struct arm64_cpu_capabilities *__unused)
1650{
1651 /*
1652 * Use of X16/X17 for tail-calls and trampolines that jump to
1653 * function entry points using BR is a requirement for
1654 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI.
1655 * So, be strict and forbid other BRs using other registers to
1656 * jump onto a PACIxSP instruction:
1657 */
1658 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1);
1659 isb();
1660}
1661#endif /* CONFIG_ARM64_BTI */
1662
8c176e16
ADK		 1663/* Internal helper functions to match cpu capability type */
1664static bool
1665cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
1666{
1667 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU);
1668}
1669
1670static bool
1671cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap)
1672{
1673 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU);
1674}
1675
deeaac51
KM		 1676static bool
1677cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap)
1678{
1679 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT);
1680}
1681
359b7064 1682static const struct arm64_cpu_capabilities arm64_features[] = {
94a9e04a
MZ		 1683 {
1684 .desc = "GIC system register CPU interface",
1685 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
c9bfdf73 1686 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
963fcd40 1687 .matches = has_useable_gicv3_cpuif,
da8d02d1
SP		 1688 .sys_reg = SYS_ID_AA64PFR0_EL1,
1689 .field_pos = ID_AA64PFR0_GIC_SHIFT,
ff96f7bc 1690 .sign = FTR_UNSIGNED,
18ffa046 1691 .min_field_value = 1,
94a9e04a 1692 },
338d4f49
JM		 1693#ifdef CONFIG_ARM64_PAN
1694 {
1695 .desc = "Privileged Access Never",
1696 .capability = ARM64_HAS_PAN,
5b4747c5 1697 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
da8d02d1
SP		 1698 .matches = has_cpuid_feature,
1699 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1700 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
ff96f7bc 1701 .sign = FTR_UNSIGNED,
338d4f49 1702 .min_field_value = 1,
c0cda3b8 1703 .cpu_enable = cpu_enable_pan,
338d4f49
JM		 1704 },
1705#endif /* CONFIG_ARM64_PAN */
395af861 1706#ifdef CONFIG_ARM64_LSE_ATOMICS
2e94da13
WD		 1707 {
1708 .desc = "LSE atomic instructions",
1709 .capability = ARM64_HAS_LSE_ATOMICS,
5b4747c5 1710 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
da8d02d1
SP		 1711 .matches = has_cpuid_feature,
1712 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1713 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
ff96f7bc 1714 .sign = FTR_UNSIGNED,
2e94da13
WD		 1715 .min_field_value = 2,
1716 },
395af861 1717#endif /* CONFIG_ARM64_LSE_ATOMICS */
d5370f75
WD		 1718 {
1719 .desc = "Software prefetching using PRFM",
1720 .capability = ARM64_HAS_NO_HW_PREFETCH,
5c137714 1721 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
d5370f75
WD		 1722 .matches = has_no_hw_prefetch,
1723 },
57f4959b
JM		 1724#ifdef CONFIG_ARM64_UAO
1725 {
1726 .desc = "User Access Override",
1727 .capability = ARM64_HAS_UAO,
5b4747c5 1728 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
57f4959b
JM		 1729 .matches = has_cpuid_feature,
1730 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1731 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1732 .min_field_value = 1,
c8b06e3f
JM		 1733 /*
1734 * We rely on stop_machine() calling uao_thread_switch() to set
1735 * UAO immediately after patching.
1736 */
57f4959b
JM		 1737 },
1738#endif /* CONFIG_ARM64_UAO */
70544196
JM		 1739#ifdef CONFIG_ARM64_PAN
1740 {
1741 .capability = ARM64_ALT_PAN_NOT_UAO,
5b4747c5 1742 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
70544196
JM		 1743 .matches = cpufeature_pan_not_uao,
1744 },
1745#endif /* CONFIG_ARM64_PAN */
830dcc9f 1746#ifdef CONFIG_ARM64_VHE
d88701be
MZ		 1747 {
1748 .desc = "Virtualization Host Extensions",
1749 .capability = ARM64_HAS_VIRT_HOST_EXTN,
830dcc9f 1750 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
d88701be 1751 .matches = runs_at_el2,
c0cda3b8 1752 .cpu_enable = cpu_copy_el2regs,
d88701be 1753 },
830dcc9f 1754#endif /* CONFIG_ARM64_VHE */
042446a3
SP		 1755 {
1756 .desc = "32-bit EL0 Support",
1757 .capability = ARM64_HAS_32BIT_EL0,
5b4747c5 1758 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
042446a3
SP		 1759 .matches = has_cpuid_feature,
1760 .sys_reg = SYS_ID_AA64PFR0_EL1,
1761 .sign = FTR_UNSIGNED,
1762 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1763 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1764 },
540f76d1
WD		 1765#ifdef CONFIG_KVM
1766 {
1767 .desc = "32-bit EL1 Support",
1768 .capability = ARM64_HAS_32BIT_EL1,
1769 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1770 .matches = has_cpuid_feature,
1771 .sys_reg = SYS_ID_AA64PFR0_EL1,
1772 .sign = FTR_UNSIGNED,
1773 .field_pos = ID_AA64PFR0_EL1_SHIFT,
1774 .min_field_value = ID_AA64PFR0_EL1_32BIT_64BIT,
1775 },
1776#endif
ea1e3de8 1777 {
179a56f6 1778 .desc = "Kernel page table isolation (KPTI)",
ea1e3de8 1779 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
d3aec8a2
SP		 1780 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1781 /*
1782 * The ID feature fields below are used to indicate that
1783 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1784 * more details.
1785 */
1786 .sys_reg = SYS_ID_AA64PFR0_EL1,
1787 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1788 .min_field_value = 1,
ea1e3de8 1789 .matches = unmap_kernel_at_el0,
c0cda3b8 1790 .cpu_enable = kpti_install_ng_mappings,
ea1e3de8 1791 },
82e0191a
SP		 1792 {
1793 /* FP/SIMD is not implemented */
1794 .capability = ARM64_HAS_NO_FPSIMD,
449443c0 1795 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
82e0191a
SP		 1796 .min_field_value = 0,
1797 .matches = has_no_fpsimd,
1798 },
d50e071f
RM		 1799#ifdef CONFIG_ARM64_PMEM
1800 {
1801 .desc = "Data cache clean to Point of Persistence",
1802 .capability = ARM64_HAS_DCPOP,
5b4747c5 1803 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
d50e071f
RM		 1804 .matches = has_cpuid_feature,
1805 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1806 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1807 .min_field_value = 1,
1808 },
b9585f53
AM		 1809 {
1810 .desc = "Data cache clean to Point of Deep Persistence",
1811 .capability = ARM64_HAS_DCPODP,
1812 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1813 .matches = has_cpuid_feature,
1814 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1815 .sign = FTR_UNSIGNED,
1816 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1817 .min_field_value = 2,
1818 },
d50e071f 1819#endif
43994d82
DM		 1820#ifdef CONFIG_ARM64_SVE
1821 {
1822 .desc = "Scalable Vector Extension",
5b4747c5 1823 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
43994d82 1824 .capability = ARM64_SVE,
43994d82
DM		 1825 .sys_reg = SYS_ID_AA64PFR0_EL1,
1826 .sign = FTR_UNSIGNED,
1827 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1828 .min_field_value = ID_AA64PFR0_SVE,
1829 .matches = has_cpuid_feature,
c0cda3b8 1830 .cpu_enable = sve_kernel_enable,
43994d82
DM		 1831 },
1832#endif /* CONFIG_ARM64_SVE */
64c02720
XX		 1833#ifdef CONFIG_ARM64_RAS_EXTN
1834 {
1835 .desc = "RAS Extension Support",
1836 .capability = ARM64_HAS_RAS_EXTN,
5b4747c5 1837 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
64c02720
XX		 1838 .matches = has_cpuid_feature,
1839 .sys_reg = SYS_ID_AA64PFR0_EL1,
1840 .sign = FTR_UNSIGNED,
1841 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1842 .min_field_value = ID_AA64PFR0_RAS_V1,
c0cda3b8 1843 .cpu_enable = cpu_clear_disr,
64c02720
XX		 1844 },
1845#endif /* CONFIG_ARM64_RAS_EXTN */
2c9d45b4
IV		 1846#ifdef CONFIG_ARM64_AMU_EXTN
1847 {
1848 /*
1849 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y.
1850 * Therefore, don't provide .desc as we don't want the detection
1851 * message to be shown until at least one CPU is detected to
1852 * support the feature.
1853 */
1854 .capability = ARM64_HAS_AMU_EXTN,
1855 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1856 .matches = has_amu,
1857 .sys_reg = SYS_ID_AA64PFR0_EL1,
1858 .sign = FTR_UNSIGNED,
1859 .field_pos = ID_AA64PFR0_AMU_SHIFT,
1860 .min_field_value = ID_AA64PFR0_AMU,
1861 .cpu_enable = cpu_amu_enable,
1862 },
1863#endif /* CONFIG_ARM64_AMU_EXTN */
6ae4b6e0
SD		 1864 {
1865 .desc = "Data cache clean to the PoU not required for I/D coherence",
1866 .capability = ARM64_HAS_CACHE_IDC,
5b4747c5 1867 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
6ae4b6e0 1868 .matches = has_cache_idc,
1602df02 1869 .cpu_enable = cpu_emulate_effective_ctr,
6ae4b6e0
SD		 1870 },
1871 {
1872 .desc = "Instruction cache invalidation not required for I/D coherence",
1873 .capability = ARM64_HAS_CACHE_DIC,
5b4747c5 1874 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
6ae4b6e0
SD		 1875 .matches = has_cache_dic,
1876 },
e48d53a9
MZ		 1877 {
1878 .desc = "Stage-2 Force Write-Back",
1879 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1880 .capability = ARM64_HAS_STAGE2_FWB,
1881 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1882 .sign = FTR_UNSIGNED,
1883 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
1884 .min_field_value = 1,
1885 .matches = has_cpuid_feature,
1886 .cpu_enable = cpu_has_fwb,
1887 },
05abb595
SP		 1888#ifdef CONFIG_ARM64_HW_AFDBM
1889 {
1890 /*
1891 * Since we turn this on always, we don't want the user to
1892 * think that the feature is available when it may not be.
1893 * So hide the description.
1894 *
1895 * .desc = "Hardware pagetable Dirty Bit Management",
1896 *
1897 */
1898 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1899 .capability = ARM64_HW_DBM,
1900 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1901 .sign = FTR_UNSIGNED,
1902 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
1903 .min_field_value = 2,
1904 .matches = has_hw_dbm,
1905 .cpu_enable = cpu_enable_hw_dbm,
1906 },
1907#endif
86d0dd34
AB		 1908 {
1909 .desc = "CRC32 instructions",
1910 .capability = ARM64_HAS_CRC32,
1911 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1912 .matches = has_cpuid_feature,
1913 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1914 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
1915 .min_field_value = 1,
1916 },
4f9f4964 1917#ifdef CONFIG_ARM64_SSBD
d71be2b6
WD		 1918 {
1919 .desc = "Speculative Store Bypassing Safe (SSBS)",
1920 .capability = ARM64_SSBS,
1921 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1922 .matches = has_cpuid_feature,
1923 .sys_reg = SYS_ID_AA64PFR1_EL1,
1924 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
1925 .sign = FTR_UNSIGNED,
1926 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
8f04e8e6 1927 .cpu_enable = cpu_enable_ssbs,
d71be2b6 1928 },
5ffdfaed
VM		 1929#endif
1930#ifdef CONFIG_ARM64_CNP
1931 {
1932 .desc = "Common not Private translations",
1933 .capability = ARM64_HAS_CNP,
1934 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1935 .matches = has_useable_cnp,
1936 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1937 .sign = FTR_UNSIGNED,
1938 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
1939 .min_field_value = 1,
1940 .cpu_enable = cpu_enable_cnp,
1941 },
8f04e8e6 1942#endif
bd4fb6d2
WD		 1943 {
1944 .desc = "Speculation barrier (SB)",
1945 .capability = ARM64_HAS_SB,
1946 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1947 .matches = has_cpuid_feature,
1948 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1949 .field_pos = ID_AA64ISAR1_SB_SHIFT,
1950 .sign = FTR_UNSIGNED,
1951 .min_field_value = 1,
1952 },
6984eb47
MR		 1953#ifdef CONFIG_ARM64_PTR_AUTH
1954 {
1955 .desc = "Address authentication (architected algorithm)",
1956 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
6982934e 1957 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
6984eb47
MR		 1958 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1959 .sign = FTR_UNSIGNED,
1960 .field_pos = ID_AA64ISAR1_APA_SHIFT,
1961 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
1962 .matches = has_cpuid_feature,
1963 },
1964 {
1965 .desc = "Address authentication (IMP DEF algorithm)",
1966 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
6982934e 1967 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
6984eb47
MR		 1968 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1969 .sign = FTR_UNSIGNED,
1970 .field_pos = ID_AA64ISAR1_API_SHIFT,
1971 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
1972 .matches = has_cpuid_feature,
cfef06bd
KM		 1973 },
1974 {
1975 .capability = ARM64_HAS_ADDRESS_AUTH,
6982934e 1976 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
cfef06bd 1977 .matches = has_address_auth,
6984eb47
MR		 1978 },
1979 {
1980 .desc = "Generic authentication (architected algorithm)",
1981 .capability = ARM64_HAS_GENERIC_AUTH_ARCH,
1982 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1983 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1984 .sign = FTR_UNSIGNED,
1985 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
1986 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
1987 .matches = has_cpuid_feature,
1988 },
1989 {
1990 .desc = "Generic authentication (IMP DEF algorithm)",
1991 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
1992 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1993 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1994 .sign = FTR_UNSIGNED,
1995 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
1996 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
1997 .matches = has_cpuid_feature,
1998 },
cfef06bd
KM		 1999 {
2000 .capability = ARM64_HAS_GENERIC_AUTH,
2001 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2002 .matches = has_generic_auth,
2003 },
6984eb47 2004#endif /* CONFIG_ARM64_PTR_AUTH */
b90d2b22
JT		 2005#ifdef CONFIG_ARM64_PSEUDO_NMI
2006 {
2007 /*
2008 * Depends on having GICv3
2009 */
2010 .desc = "IRQ priority masking",
2011 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
2012 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2013 .matches = can_use_gic_priorities,
2014 .sys_reg = SYS_ID_AA64PFR0_EL1,
2015 .field_pos = ID_AA64PFR0_GIC_SHIFT,
2016 .sign = FTR_UNSIGNED,
2017 .min_field_value = 1,
2018 },
3e6c69a0
MB		 2019#endif
2020#ifdef CONFIG_ARM64_E0PD
2021 {
2022 .desc = "E0PD",
2023 .capability = ARM64_HAS_E0PD,
2024 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2025 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2026 .sign = FTR_UNSIGNED,
2027 .field_pos = ID_AA64MMFR2_E0PD_SHIFT,
2028 .matches = has_cpuid_feature,
2029 .min_field_value = 1,
2030 .cpu_enable = cpu_enable_e0pd,
2031 },
bc206065 2032#endif
1a50ec0b
RH		 2033#ifdef CONFIG_ARCH_RANDOM
2034 {
2035 .desc = "Random Number Generator",
2036 .capability = ARM64_HAS_RNG,
2037 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2038 .matches = has_cpuid_feature,
2039 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2040 .field_pos = ID_AA64ISAR0_RNDR_SHIFT,
2041 .sign = FTR_UNSIGNED,
2042 .min_field_value = 1,
2043 },
8ef8f360
DM		 2044#endif
2045#ifdef CONFIG_ARM64_BTI
2046 {
2047 .desc = "Branch Target Identification",
2048 .capability = ARM64_BTI,
c8027285
MB		 2049#ifdef CONFIG_ARM64_BTI_KERNEL
2050 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2051#else
8ef8f360 2052 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
c8027285 2053#endif
8ef8f360
DM		 2054 .matches = has_cpuid_feature,
2055 .cpu_enable = bti_enable,
2056 .sys_reg = SYS_ID_AA64PFR1_EL1,
2057 .field_pos = ID_AA64PFR1_BT_SHIFT,
2058 .min_field_value = ID_AA64PFR1_BT_BTI,
2059 .sign = FTR_UNSIGNED,
2060 },
b90d2b22 2061#endif
359b7064
MZ		 2062 {},
2063};
2064
1e013d06
WD		 2065#define HWCAP_CPUID_MATCH(reg, field, s, min_value) \
2066 .matches = has_cpuid_feature, \
2067 .sys_reg = reg, \
2068 .field_pos = field, \
2069 .sign = s, \
2070 .min_field_value = min_value,
2071
2072#define __HWCAP_CAP(name, cap_type, cap) \
2073 .desc = name, \
2074 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
2075 .hwcap_type = cap_type, \
2076 .hwcap = cap, \
2077
2078#define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \
2079 { \
2080 __HWCAP_CAP(#cap, cap_type, cap) \
2081 HWCAP_CPUID_MATCH(reg, field, s, min_value) \
37b01d53
SP		 2082 }
2083
1e013d06
WD		 2084#define HWCAP_MULTI_CAP(list, cap_type, cap) \
2085 { \
2086 __HWCAP_CAP(#cap, cap_type, cap) \
2087 .matches = cpucap_multi_entry_cap_matches, \
2088 .match_list = list, \
2089 }
2090
7559950a
SP		 2091#define HWCAP_CAP_MATCH(match, cap_type, cap) \
2092 { \
2093 __HWCAP_CAP(#cap, cap_type, cap) \
2094 .matches = match, \
2095 }
2096
1e013d06
WD		 2097#ifdef CONFIG_ARM64_PTR_AUTH
2098static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
2099 {
2100 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
2101 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
2102 },
2103 {
2104 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
2105 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
2106 },
2107 {},
2108};
2109
2110static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
2111 {
2112 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
2113 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
2114 },
2115 {
2116 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
2117 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
2118 },
2119 {},
2120};
2121#endif
2122
f3efb675 2123static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
aaba098f
AM		 2124 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
2125 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
2126 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
2127 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
2128 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
2129 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
2130 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
2131 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
2132 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
2133 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
2134 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
2135 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
2136 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
2137 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
12019374 2138 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
1a50ec0b 2139 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG),
aaba098f
AM		 2140 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
2141 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
2142 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
2143 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
2144 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
2145 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
671db581 2146 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
aaba098f
AM		 2147 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
2148 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
2149 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
2150 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
ca9503fc 2151 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
aaba098f 2152 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
d4209d8b
SP		 2153 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16),
2154 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH),
2155 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM),
aaba098f 2156 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
43994d82 2157#ifdef CONFIG_ARM64_SVE
aaba098f 2158 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
06a916fe
DM		 2159 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
2160 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
2161 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
2162 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
d4209d8b 2163 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
06a916fe
DM		 2164 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
2165 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
d4209d8b
SP		 2166 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
2167 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
2168 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
43994d82 2169#endif
aaba098f 2170 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
8ef8f360
DM		 2171#ifdef CONFIG_ARM64_BTI
2172 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_BT_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_BT_BTI, CAP_HWCAP, KERNEL_HWCAP_BTI),
2173#endif
75031975 2174#ifdef CONFIG_ARM64_PTR_AUTH
aaba098f
AM		 2175 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
2176 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
75031975 2177#endif
75283501
SP		 2178 {},
2179};
2180
7559950a
SP		 2181#ifdef CONFIG_COMPAT
2182static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
2183{
2184 /*
2185 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
2186 * in line with that of arm32 as in vfp_init(). We make sure that the
2187 * check is future proof, by making sure value is non-zero.
2188 */
2189 u32 mvfr1;
2190
2191 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
2192 if (scope == SCOPE_SYSTEM)
2193 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
2194 else
2195 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
2196
2197 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
2198 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
2199 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
2200}
2201#endif
2202
75283501 2203static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
37b01d53 2204#ifdef CONFIG_COMPAT
7559950a
SP		 2205 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
2206 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
2207 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
2208 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
2209 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
ff96f7bc
SP		 2210 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
2211 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
2212 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
2213 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
2214 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
37b01d53
SP		 2215#endif
2216 {},
2217};
2218
f3efb675 2219static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 2220{
2221 switch (cap->hwcap_type) {
2222 case CAP_HWCAP:
aaba098f 2223 cpu_set_feature(cap->hwcap);
37b01d53
SP		 2224 break;
2225#ifdef CONFIG_COMPAT
2226 case CAP_COMPAT_HWCAP:
2227 compat_elf_hwcap |= (u32)cap->hwcap;
2228 break;
2229 case CAP_COMPAT_HWCAP2:
2230 compat_elf_hwcap2 |= (u32)cap->hwcap;
2231 break;
2232#endif
2233 default:
2234 WARN_ON(1);
2235 break;
2236 }
2237}
2238
2239/* Check if we have a particular HWCAP enabled */
f3efb675 2240static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 2241{
2242 bool rc;
2243
2244 switch (cap->hwcap_type) {
2245 case CAP_HWCAP:
aaba098f 2246 rc = cpu_have_feature(cap->hwcap);
37b01d53
SP		 2247 break;
2248#ifdef CONFIG_COMPAT
2249 case CAP_COMPAT_HWCAP:
2250 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
2251 break;
2252 case CAP_COMPAT_HWCAP2:
2253 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
2254 break;
2255#endif
2256 default:
2257 WARN_ON(1);
2258 rc = false;
2259 }
2260
2261 return rc;
2262}
2263
75283501 2264static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
37b01d53 2265{
77c97b4e 2266 /* We support emulation of accesses to CPU ID feature registers */
aaba098f 2267 cpu_set_named_feature(CPUID);
75283501 2268 for (; hwcaps->matches; hwcaps++)
143ba05d 2269 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
75283501 2270 cap_set_elf_hwcap(hwcaps);
37b01d53
SP		 2271}
2272
606f8e7b 2273static void update_cpu_capabilities(u16 scope_mask)
67948af4 2274{
606f8e7b 2275 int i;
67948af4
SP		 2276 const struct arm64_cpu_capabilities *caps;
2277
cce360b5 2278 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
606f8e7b
SP		 2279 for (i = 0; i < ARM64_NCAPS; i++) {
2280 caps = cpu_hwcaps_ptrs[i];
2281 if (!caps || !(caps->type & scope_mask) ||
2282 cpus_have_cap(caps->capability) ||
cce360b5 2283 !caps->matches(caps, cpucap_default_scope(caps)))
359b7064
MZ		 2284 continue;
2285
606f8e7b
SP		 2286 if (caps->desc)
2287 pr_info("detected: %s\n", caps->desc);
75283501 2288 cpus_set_cap(caps->capability);
0ceb0d56
DT		 2289
2290 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
2291 set_bit(caps->capability, boot_capabilities);
359b7064 2292 }
ce8b602c
SP		 2293}
2294
0b587c84
SP		 2295/*
2296 * Enable all the available capabilities on this CPU. The capabilities
2297 * with BOOT_CPU scope are handled separately and hence skipped here.
2298 */
2299static int cpu_enable_non_boot_scope_capabilities(void *__unused)
ed478b3f 2300{
0b587c84
SP		 2301 int i;
2302 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
ed478b3f 2303
0b587c84
SP		 2304 for_each_available_cap(i) {
2305 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
2306
2307 if (WARN_ON(!cap))
2308 continue;
c0cda3b8 2309
0b587c84
SP		 2310 if (!(cap->type & non_boot_scope))
2311 continue;
2312
2313 if (cap->cpu_enable)
2314 cap->cpu_enable(cap);
2315 }
c0cda3b8
DM		 2316 return 0;
2317}
2318
ce8b602c 2319/*
dbb4e152
SP		 2320 * Run through the enabled capabilities and enable() it on all active
2321 * CPUs
ce8b602c 2322 */
0b587c84 2323static void __init enable_cpu_capabilities(u16 scope_mask)
ce8b602c 2324{
0b587c84
SP		 2325 int i;
2326 const struct arm64_cpu_capabilities *caps;
2327 bool boot_scope;
2328
cce360b5 2329 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
0b587c84 2330 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
63a1e1c9 2331
0b587c84
SP		 2332 for (i = 0; i < ARM64_NCAPS; i++) {
2333 unsigned int num;
2334
2335 caps = cpu_hwcaps_ptrs[i];
2336 if (!caps || !(caps->type & scope_mask))
2337 continue;
2338 num = caps->capability;
2339 if (!cpus_have_cap(num))
63a1e1c9
MR		 2340 continue;
2341
2342 /* Ensure cpus_have_const_cap(num) works */
2343 static_branch_enable(&cpu_hwcap_keys[num]);
2344
0b587c84 2345 if (boot_scope && caps->cpu_enable)
2a6dcb2b 2346 /*
fd9d63da
SP		 2347 * Capabilities with SCOPE_BOOT_CPU scope are finalised
2348 * before any secondary CPU boots. Thus, each secondary
2349 * will enable the capability as appropriate via
2350 * check_local_cpu_capabilities(). The only exception is
2351 * the boot CPU, for which the capability must be
2352 * enabled here. This approach avoids costly
2353 * stop_machine() calls for this case.
2a6dcb2b 2354 */
0b587c84 2355 caps->cpu_enable(caps);
63a1e1c9 2356 }
dbb4e152 2357
0b587c84
SP		 2358 /*
2359 * For all non-boot scope capabilities, use stop_machine()
2360 * as it schedules the work allowing us to modify PSTATE,
2361 * instead of on_each_cpu() which uses an IPI, giving us a
2362 * PSTATE that disappears when we return.
2363 */
2364 if (!boot_scope)
2365 stop_machine(cpu_enable_non_boot_scope_capabilities,
2366 NULL, cpu_online_mask);
ed478b3f
SP		 2367}
2368
eaac4d83
SP		 2369/*
2370 * Run through the list of capabilities to check for conflicts.
2371 * If the system has already detected a capability, take necessary
2372 * action on this CPU.
eaac4d83 2373 */
deeaac51 2374static void verify_local_cpu_caps(u16 scope_mask)
eaac4d83 2375{
606f8e7b 2376 int i;
eaac4d83 2377 bool cpu_has_cap, system_has_cap;
606f8e7b 2378 const struct arm64_cpu_capabilities *caps;
eaac4d83 2379
cce360b5
SP		 2380 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2381
606f8e7b
SP		 2382 for (i = 0; i < ARM64_NCAPS; i++) {
2383 caps = cpu_hwcaps_ptrs[i];
2384 if (!caps || !(caps->type & scope_mask))
cce360b5
SP		 2385 continue;
2386
ba7d9233 2387 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
eaac4d83
SP		 2388 system_has_cap = cpus_have_cap(caps->capability);
2389
2390 if (system_has_cap) {
2391 /*
2392 * Check if the new CPU misses an advertised feature,
2393 * which is not safe to miss.
2394 */
2395 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
2396 break;
2397 /*
2398 * We have to issue cpu_enable() irrespective of
2399 * whether the CPU has it or not, as it is enabeld
2400 * system wide. It is upto the call back to take
2401 * appropriate action on this CPU.
2402 */
2403 if (caps->cpu_enable)
2404 caps->cpu_enable(caps);
2405 } else {
2406 /*
2407 * Check if the CPU has this capability if it isn't
2408 * safe to have when the system doesn't.
2409 */
2410 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
2411 break;
2412 }
2413 }
2414
606f8e7b 2415 if (i < ARM64_NCAPS) {
eaac4d83
SP		 2416 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
2417 smp_processor_id(), caps->capability,
2418 caps->desc, system_has_cap, cpu_has_cap);
eaac4d83 2419
deeaac51
KM		 2420 if (cpucap_panic_on_conflict(caps))
2421 cpu_panic_kernel();
2422 else
2423 cpu_die_early();
2424 }
eaac4d83
SP		 2425}
2426
dbb4e152 2427/*
13f417f3
SP		 2428 * Check for CPU features that are used in early boot
2429 * based on the Boot CPU value.
dbb4e152 2430 */
13f417f3 2431static void check_early_cpu_features(void)
dbb4e152 2432{
13f417f3 2433 verify_cpu_asid_bits();
deeaac51
KM		 2434
2435 verify_local_cpu_caps(SCOPE_BOOT_CPU);
dbb4e152 2436}
1c076303 2437
75283501
SP		 2438static void
2439verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
2440{
2441
92406f0c
SP		 2442 for (; caps->matches; caps++)
2443 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
75283501
SP		 2444 pr_crit("CPU%d: missing HWCAP: %s\n",
2445 smp_processor_id(), caps->desc);
2446 cpu_die_early();
2447 }
75283501
SP		 2448}
2449
2e0f2478
DM		 2450static void verify_sve_features(void)
2451{
2452 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
2453 u64 zcr = read_zcr_features();
2454
2455 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
2456 unsigned int len = zcr & ZCR_ELx_LEN_MASK;
2457
2458 if (len < safe_len || sve_verify_vq_map()) {
d06b76be 2459 pr_crit("CPU%d: SVE: vector length support mismatch\n",
2e0f2478
DM		 2460 smp_processor_id());
2461 cpu_die_early();
2462 }
2463
2464 /* Add checks on other ZCR bits here if necessary */
2465}
2466
c73433fc
AK		 2467static void verify_hyp_capabilities(void)
2468{
2469 u64 safe_mmfr1, mmfr0, mmfr1;
2470 int parange, ipa_max;
2471 unsigned int safe_vmid_bits, vmid_bits;
2472
2473 if (!IS_ENABLED(CONFIG_KVM) || !IS_ENABLED(CONFIG_KVM_ARM_HOST))
2474 return;
2475
2476 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
2477 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
2478 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
2479
2480 /* Verify VMID bits */
2481 safe_vmid_bits = get_vmid_bits(safe_mmfr1);
2482 vmid_bits = get_vmid_bits(mmfr1);
2483 if (vmid_bits < safe_vmid_bits) {
2484 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id());
2485 cpu_die_early();
2486 }
2487
2488 /* Verify IPA range */
f73531f0
AK		 2489 parange = cpuid_feature_extract_unsigned_field(mmfr0,
2490 ID_AA64MMFR0_PARANGE_SHIFT);
c73433fc
AK		 2491 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange);
2492 if (ipa_max < get_kvm_ipa_limit()) {
2493 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id());
2494 cpu_die_early();
2495 }
2496}
1e89baed 2497
dbb4e152
SP		 2498/*
2499 * Run through the enabled system capabilities and enable() it on this CPU.
2500 * The capabilities were decided based on the available CPUs at the boot time.
2501 * Any new CPU should match the system wide status of the capability. If the
2502 * new CPU doesn't have a capability which the system now has enabled, we
2503 * cannot do anything to fix it up and could cause unexpected failures. So
2504 * we park the CPU.
2505 */
c47a1900 2506static void verify_local_cpu_capabilities(void)
dbb4e152 2507{
fd9d63da
SP		 2508 /*
2509 * The capabilities with SCOPE_BOOT_CPU are checked from
2510 * check_early_cpu_features(), as they need to be verified
2511 * on all secondary CPUs.
2512 */
deeaac51 2513 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU);
ed478b3f 2514
c47a1900 2515 verify_local_elf_hwcaps(arm64_elf_hwcaps);
2e0f2478 2516
c47a1900
SP		 2517 if (system_supports_32bit_el0())
2518 verify_local_elf_hwcaps(compat_elf_hwcaps);
2e0f2478
DM		 2519
2520 if (system_supports_sve())
2521 verify_sve_features();
c73433fc
AK		 2522
2523 if (is_hyp_mode_available())
2524 verify_hyp_capabilities();
c47a1900 2525}
dbb4e152 2526
c47a1900
SP		 2527void check_local_cpu_capabilities(void)
2528{
2529 /*
2530 * All secondary CPUs should conform to the early CPU features
2531 * in use by the kernel based on boot CPU.
2532 */
13f417f3
SP		 2533 check_early_cpu_features();
2534
dbb4e152 2535 /*
c47a1900 2536 * If we haven't finalised the system capabilities, this CPU gets
fbd890b9 2537 * a chance to update the errata work arounds and local features.
c47a1900
SP		 2538 * Otherwise, this CPU should verify that it has all the system
2539 * advertised capabilities.
dbb4e152 2540 */
b51c6ac2 2541 if (!system_capabilities_finalized())
ed478b3f
SP		 2542 update_cpu_capabilities(SCOPE_LOCAL_CPU);
2543 else
c47a1900 2544 verify_local_cpu_capabilities();
359b7064
MZ		 2545}
2546
fd9d63da
SP		 2547static void __init setup_boot_cpu_capabilities(void)
2548{
2549 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
2550 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
2551 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
2552 enable_cpu_capabilities(SCOPE_BOOT_CPU);
2553}
2554
f7bfc14a 2555bool this_cpu_has_cap(unsigned int n)
8f413758 2556{
f7bfc14a
SP		 2557 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
2558 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2559
2560 if (cap)
2561 return cap->matches(cap, SCOPE_LOCAL_CPU);
2562 }
2563
2564 return false;
8f413758
MZ		 2565}
2566
3ff047f6
ADK		 2567/*
2568 * This helper function is used in a narrow window when,
2569 * - The system wide safe registers are set with all the SMP CPUs and,
2570 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set.
2571 * In all other cases cpus_have_{const_}cap() should be used.
2572 */
2573static bool __system_matches_cap(unsigned int n)
2574{
2575 if (n < ARM64_NCAPS) {
2576 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2577
2578 if (cap)
2579 return cap->matches(cap, SCOPE_SYSTEM);
2580 }
2581 return false;
2582}
2583
aec0bff7
AM		 2584void cpu_set_feature(unsigned int num)
2585{
2586 WARN_ON(num >= MAX_CPU_FEATURES);
2587 elf_hwcap |= BIT(num);
2588}
2589EXPORT_SYMBOL_GPL(cpu_set_feature);
2590
2591bool cpu_have_feature(unsigned int num)
2592{
2593 WARN_ON(num >= MAX_CPU_FEATURES);
2594 return elf_hwcap & BIT(num);
2595}
2596EXPORT_SYMBOL_GPL(cpu_have_feature);
2597
2598unsigned long cpu_get_elf_hwcap(void)
2599{
2600 /*
2601 * We currently only populate the first 32 bits of AT_HWCAP. Please
2602 * note that for userspace compatibility we guarantee that bits 62
2603 * and 63 will always be returned as 0.
2604 */
2605 return lower_32_bits(elf_hwcap);
2606}
2607
2608unsigned long cpu_get_elf_hwcap2(void)
2609{
2610 return upper_32_bits(elf_hwcap);
2611}
2612
ed478b3f
SP		 2613static void __init setup_system_capabilities(void)
2614{
2615 /*
2616 * We have finalised the system-wide safe feature
2617 * registers, finalise the capabilities that depend
fd9d63da
SP		 2618 * on it. Also enable all the available capabilities,
2619 * that are not enabled already.
ed478b3f
SP		 2620 */
2621 update_cpu_capabilities(SCOPE_SYSTEM);
fd9d63da 2622 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
ed478b3f
SP		 2623}
2624
9cdf8ec4 2625void __init setup_cpu_features(void)
359b7064 2626{
9cdf8ec4 2627 u32 cwg;
9cdf8ec4 2628
ed478b3f 2629 setup_system_capabilities();
75283501 2630 setup_elf_hwcaps(arm64_elf_hwcaps);
643d703d
SP		 2631
2632 if (system_supports_32bit_el0())
2633 setup_elf_hwcaps(compat_elf_hwcaps);
dbb4e152 2634
2e6f549f
KC		 2635 if (system_uses_ttbr0_pan())
2636 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
2637
2e0f2478 2638 sve_setup();
94b07c1f 2639 minsigstksz_setup();
2e0f2478 2640
dbb4e152 2641 /* Advertise that we have computed the system capabilities */
b51c6ac2 2642 finalize_system_capabilities();
dbb4e152 2643
9cdf8ec4
SP		 2644 /*
2645 * Check for sane CTR_EL0.CWG value.
2646 */
2647 cwg = cache_type_cwg();
9cdf8ec4 2648 if (!cwg)
ebc7e21e
CM		 2649 pr_warn("No Cache Writeback Granule information, assuming %d\n",
2650 ARCH_DMA_MINALIGN);
359b7064 2651}
70544196
JM		 2652
2653static bool __maybe_unused
92406f0c 2654cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
70544196 2655{
3ff047f6 2656 return (__system_matches_cap(ARM64_HAS_PAN) && !__system_matches_cap(ARM64_HAS_UAO));
70544196 2657}
77c97b4e 2658
5ffdfaed
VM		 2659static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
2660{
2661 cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
2662}
2663
77c97b4e
SP		 2664/*
2665 * We emulate only the following system register space.
2666 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
2667 * See Table C5-6 System instruction encodings for System register accesses,
2668 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
2669 */
2670static inline bool __attribute_const__ is_emulated(u32 id)
2671{
2672 return (sys_reg_Op0(id) == 0x3 &&
2673 sys_reg_CRn(id) == 0x0 &&
2674 sys_reg_Op1(id) == 0x0 &&
2675 (sys_reg_CRm(id) == 0 ||
2676 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
2677}
2678
2679/*
2680 * With CRm == 0, reg should be one of :
2681 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
2682 */
2683static inline int emulate_id_reg(u32 id, u64 *valp)
2684{
2685 switch (id) {
2686 case SYS_MIDR_EL1:
2687 *valp = read_cpuid_id();
2688 break;
2689 case SYS_MPIDR_EL1:
2690 *valp = SYS_MPIDR_SAFE_VAL;
2691 break;
2692 case SYS_REVIDR_EL1:
2693 /* IMPLEMENTATION DEFINED values are emulated with 0 */
2694 *valp = 0;
2695 break;
2696 default:
2697 return -EINVAL;
2698 }
2699
2700 return 0;
2701}
2702
2703static int emulate_sys_reg(u32 id, u64 *valp)
2704{
2705 struct arm64_ftr_reg *regp;
2706
2707 if (!is_emulated(id))
2708 return -EINVAL;
2709
2710 if (sys_reg_CRm(id) == 0)
2711 return emulate_id_reg(id, valp);
2712
3577dd37 2713 regp = get_arm64_ftr_reg_nowarn(id);
77c97b4e
SP		 2714 if (regp)
2715 *valp = arm64_ftr_reg_user_value(regp);
2716 else
2717 /*
2718 * The untracked registers are either IMPLEMENTATION DEFINED
2719 * (e.g, ID_AFR0_EL1) or reserved RAZ.
2720 */
2721 *valp = 0;
2722 return 0;
2723}
2724
520ad988 2725int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
77c97b4e
SP		 2726{
2727 int rc;
77c97b4e
SP		 2728 u64 val;
2729
77c97b4e
SP		 2730 rc = emulate_sys_reg(sys_reg, &val);
2731 if (!rc) {
520ad988 2732 pt_regs_write_reg(regs, rt, val);
6436beee 2733 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
77c97b4e 2734 }
77c97b4e
SP		 2735 return rc;
2736}
2737
520ad988
AK		 2738static int emulate_mrs(struct pt_regs *regs, u32 insn)
2739{
2740 u32 sys_reg, rt;
2741
2742 /*
2743 * sys_reg values are defined as used in mrs/msr instruction.
2744 * shift the imm value to get the encoding.
2745 */
2746 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
2747 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
2748 return do_emulate_mrs(regs, sys_reg, rt);
2749}
2750
77c97b4e
SP		 2751static struct undef_hook mrs_hook = {
2752 .instr_mask = 0xfff00000,
2753 .instr_val = 0xd5300000,
d64567f6 2754 .pstate_mask = PSR_AA32_MODE_MASK,
77c97b4e
SP		 2755 .pstate_val = PSR_MODE_EL0t,
2756 .fn = emulate_mrs,
2757};
2758
2759static int __init enable_mrs_emulation(void)
2760{
2761 register_undef_hook(&mrs_hook);
2762 return 0;
2763}
2764
c0d8832e 2765core_initcall(enable_mrs_emulation);
1b3ccf4b
JL		 2766
2767ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
2768 char *buf)
2769{
2770 if (__meltdown_safe)
2771 return sprintf(buf, "Not affected\n");
2772
2773 if (arm64_kernel_unmapped_at_el0())
2774 return sprintf(buf, "Mitigation: PTI\n");
2775
2776 return sprintf(buf, "Vulnerable\n");
2777}
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