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arm64: Add helpers for detecting AArch32 support at EL0
[mirror_ubuntu-artful-kernel.git] / arch / arm64 / kernel / cpufeature.c
CommitLineData
359b7064
MZ		 1/*
2 * Contains CPU feature definitions
3 *
4 * Copyright (C) 2015 ARM Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
9cdf8ec4 19#define pr_fmt(fmt) "CPU features: " fmt
359b7064 20
3c739b57
SP		 21#include <linux/bsearch.h>
22#include <linux/sort.h>
359b7064
MZ		 23#include <linux/types.h>
24#include <asm/cpu.h>
25#include <asm/cpufeature.h>
dbb4e152 26#include <asm/cpu_ops.h>
13f417f3 27#include <asm/mmu_context.h>
338d4f49 28#include <asm/processor.h>
cdcf817b 29#include <asm/sysreg.h>
d88701be 30#include <asm/virt.h>
359b7064 31
9cdf8ec4
SP		 32unsigned long elf_hwcap __read_mostly;
33EXPORT_SYMBOL_GPL(elf_hwcap);
34
35#ifdef CONFIG_COMPAT
36#define COMPAT_ELF_HWCAP_DEFAULT \
37 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
38 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
39 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
40 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
41 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
42 COMPAT_HWCAP_LPAE)
43unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
44unsigned int compat_elf_hwcap2 __read_mostly;
45#endif
46
47DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
48
4f0a606b 49#define __ARM64_FTR_BITS(SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
3c739b57 50 { \
4f0a606b 51 .sign = SIGNED, \
3c739b57
SP		 52 .strict = STRICT, \
53 .type = TYPE, \
54 .shift = SHIFT, \
55 .width = WIDTH, \
56 .safe_val = SAFE_VAL, \
57 }
58
0710cfdb 59/* Define a feature with unsigned values */
4f0a606b 60#define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
4f0a606b
SP		 61 __ARM64_FTR_BITS(FTR_UNSIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
62
0710cfdb
SP		 63/* Define a feature with a signed value */
64#define S_ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
65 __ARM64_FTR_BITS(FTR_SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
66
3c739b57
SP		 67#define ARM64_FTR_END \
68 { \
69 .width = 0, \
70 }
71
70544196
JM		 72/* meta feature for alternatives */
73static bool __maybe_unused
74cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry);
75
3c739b57
SP		 76static struct arm64_ftr_bits ftr_id_aa64isar0[] = {
77 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
78 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
79 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),
80 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
81 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
82 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
83 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
84 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
85 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
86 ARM64_FTR_END,
87};
88
89static struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
90 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
91 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),
92 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),
0710cfdb
SP		 93 S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
94 S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
3c739b57
SP		 95 /* Linux doesn't care about the EL3 */
96 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0),
97 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0),
98 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
99 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
100 ARM64_FTR_END,
101};
102
103static struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
104 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
0710cfdb
SP		 105 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
106 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
3c739b57
SP		 107 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
108 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
109 /* Linux shouldn't care about secure memory */
110 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
111 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
112 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
113 /*
114 * Differing PARange is fine as long as all peripherals and memory are mapped
115 * within the minimum PARange of all CPUs
116 */
0710cfdb 117 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
3c739b57
SP		 118 ARM64_FTR_END,
119};
120
121static struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
122 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
123 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
124 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
125 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
126 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
127 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
128 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
129 ARM64_FTR_END,
130};
131
406e3087 132static struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
7d7b4ae4
KW		 133 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
134 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
135 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
406e3087 136 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
7d7b4ae4 137 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
406e3087
JM		 138 ARM64_FTR_END,
139};
140
3c739b57 141static struct arm64_ftr_bits ftr_ctr[] = {
0710cfdb 142 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */
3c739b57 143 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0),
0710cfdb
SP		 144 ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */
145 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */
146 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */
3c739b57
SP		 147 /*
148 * Linux can handle differing I-cache policies. Userspace JITs will
149 * make use of *minLine
150 */
0710cfdb 151 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, 0), /* L1Ip */
3c739b57 152 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0), /* RAZ */
0710cfdb 153 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */
3c739b57
SP		 154 ARM64_FTR_END,
155};
156
157static struct arm64_ftr_bits ftr_id_mmfr0[] = {
0710cfdb 158 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0xf), /* InnerShr */
3c739b57
SP		 159 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0), /* FCSE */
160 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
161 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 4, 0), /* TCM */
162 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* ShareLvl */
0710cfdb 163 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0xf), /* OuterShr */
3c739b57
SP		 164 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */
165 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */
166 ARM64_FTR_END,
167};
168
169static struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
170 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
0710cfdb
SP		 171 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
172 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
173 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
174 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
175 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
176 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
3c739b57
SP		 177 ARM64_FTR_END,
178};
179
180static struct arm64_ftr_bits ftr_mvfr2[] = {
181 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
182 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* FPMisc */
183 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* SIMDMisc */
184 ARM64_FTR_END,
185};
186
187static struct arm64_ftr_bits ftr_dczid[] = {
188 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 5, 27, 0), /* RAZ */
189 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
190 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
191 ARM64_FTR_END,
192};
193
194
195static struct arm64_ftr_bits ftr_id_isar5[] = {
196 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0),
197 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 20, 4, 0), /* RAZ */
198 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0),
199 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0),
200 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0),
201 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0),
202 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0),
203 ARM64_FTR_END,
204};
205
206static struct arm64_ftr_bits ftr_id_mmfr4[] = {
207 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
208 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* ac2 */
209 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
210 ARM64_FTR_END,
211};
212
213static struct arm64_ftr_bits ftr_id_pfr0[] = {
214 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 16, 0), /* RAZ */
215 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* State3 */
216 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* State2 */
217 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* State1 */
218 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* State0 */
219 ARM64_FTR_END,
220};
221
e5343503
SP		 222static struct arm64_ftr_bits ftr_id_dfr0[] = {
223 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
0710cfdb 224 S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */
e5343503
SP		 225 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
226 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
227 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
228 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
229 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
230 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
231 ARM64_FTR_END,
232};
233
3c739b57
SP		 234/*
235 * Common ftr bits for a 32bit register with all hidden, strict
236 * attributes, with 4bit feature fields and a default safe value of
237 * 0. Covers the following 32bit registers:
238 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
239 */
240static struct arm64_ftr_bits ftr_generic_32bits[] = {
241 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
242 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
243 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
244 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
245 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
246 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
247 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
248 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
249 ARM64_FTR_END,
250};
251
252static struct arm64_ftr_bits ftr_generic[] = {
253 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
254 ARM64_FTR_END,
255};
256
257static struct arm64_ftr_bits ftr_generic32[] = {
258 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 32, 0),
259 ARM64_FTR_END,
260};
261
262static struct arm64_ftr_bits ftr_aa64raz[] = {
263 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
264 ARM64_FTR_END,
265};
266
267#define ARM64_FTR_REG(id, table) \
268 { \
269 .sys_id = id, \
270 .name = #id, \
271 .ftr_bits = &((table)[0]), \
272 }
273
274static struct arm64_ftr_reg arm64_ftr_regs[] = {
275
276 /* Op1 = 0, CRn = 0, CRm = 1 */
277 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
278 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
e5343503 279 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
3c739b57
SP		 280 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
281 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
282 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
283 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
284
285 /* Op1 = 0, CRn = 0, CRm = 2 */
286 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
287 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
288 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
289 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
290 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
291 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
292 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
293
294 /* Op1 = 0, CRn = 0, CRm = 3 */
295 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
296 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
297 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
298
299 /* Op1 = 0, CRn = 0, CRm = 4 */
300 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
301 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_aa64raz),
302
303 /* Op1 = 0, CRn = 0, CRm = 5 */
304 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
305 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_generic),
306
307 /* Op1 = 0, CRn = 0, CRm = 6 */
308 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
309 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_aa64raz),
310
311 /* Op1 = 0, CRn = 0, CRm = 7 */
312 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
313 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
406e3087 314 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
3c739b57
SP		 315
316 /* Op1 = 3, CRn = 0, CRm = 0 */
317 ARM64_FTR_REG(SYS_CTR_EL0, ftr_ctr),
318 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
319
320 /* Op1 = 3, CRn = 14, CRm = 0 */
321 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_generic32),
322};
323
324static int search_cmp_ftr_reg(const void *id, const void *regp)
325{
326 return (int)(unsigned long)id - (int)((const struct arm64_ftr_reg *)regp)->sys_id;
327}
328
329/*
330 * get_arm64_ftr_reg - Lookup a feature register entry using its
331 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
332 * ascending order of sys_id , we use binary search to find a matching
333 * entry.
334 *
335 * returns - Upon success, matching ftr_reg entry for id.
336 * - NULL on failure. It is upto the caller to decide
337 * the impact of a failure.
338 */
339static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
340{
341 return bsearch((const void *)(unsigned long)sys_id,
342 arm64_ftr_regs,
343 ARRAY_SIZE(arm64_ftr_regs),
344 sizeof(arm64_ftr_regs[0]),
345 search_cmp_ftr_reg);
346}
347
348static u64 arm64_ftr_set_value(struct arm64_ftr_bits *ftrp, s64 reg, s64 ftr_val)
349{
350 u64 mask = arm64_ftr_mask(ftrp);
351
352 reg &= ~mask;
353 reg |= (ftr_val << ftrp->shift) & mask;
354 return reg;
355}
356
357static s64 arm64_ftr_safe_value(struct arm64_ftr_bits *ftrp, s64 new, s64 cur)
358{
359 s64 ret = 0;
360
361 switch (ftrp->type) {
362 case FTR_EXACT:
363 ret = ftrp->safe_val;
364 break;
365 case FTR_LOWER_SAFE:
366 ret = new < cur ? new : cur;
367 break;
368 case FTR_HIGHER_SAFE:
369 ret = new > cur ? new : cur;
370 break;
371 default:
372 BUG();
373 }
374
375 return ret;
376}
377
378static int __init sort_cmp_ftr_regs(const void *a, const void *b)
379{
380 return ((const struct arm64_ftr_reg *)a)->sys_id -
381 ((const struct arm64_ftr_reg *)b)->sys_id;
382}
383
384static void __init swap_ftr_regs(void *a, void *b, int size)
385{
386 struct arm64_ftr_reg tmp = *(struct arm64_ftr_reg *)a;
387 *(struct arm64_ftr_reg *)a = *(struct arm64_ftr_reg *)b;
388 *(struct arm64_ftr_reg *)b = tmp;
389}
390
391static void __init sort_ftr_regs(void)
392{
393 /* Keep the array sorted so that we can do the binary search */
394 sort(arm64_ftr_regs,
395 ARRAY_SIZE(arm64_ftr_regs),
396 sizeof(arm64_ftr_regs[0]),
397 sort_cmp_ftr_regs,
398 swap_ftr_regs);
399}
400
401/*
402 * Initialise the CPU feature register from Boot CPU values.
403 * Also initiliases the strict_mask for the register.
404 */
405static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
406{
407 u64 val = 0;
408 u64 strict_mask = ~0x0ULL;
409 struct arm64_ftr_bits *ftrp;
410 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
411
412 BUG_ON(!reg);
413
414 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
415 s64 ftr_new = arm64_ftr_value(ftrp, new);
416
417 val = arm64_ftr_set_value(ftrp, val, ftr_new);
418 if (!ftrp->strict)
419 strict_mask &= ~arm64_ftr_mask(ftrp);
420 }
421 reg->sys_val = val;
422 reg->strict_mask = strict_mask;
423}
424
425void __init init_cpu_features(struct cpuinfo_arm64 *info)
426{
427 /* Before we start using the tables, make sure it is sorted */
428 sort_ftr_regs();
429
430 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
431 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
432 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
433 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
434 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
435 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
436 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
437 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
438 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
406e3087 439 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
3c739b57
SP		 440 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
441 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
442 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
443 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
444 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
445 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
446 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
447 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
448 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
449 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
450 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
451 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
452 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
453 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
454 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
455 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
456 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
457 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
3c739b57
SP		 458}
459
3086d391 460static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
3c739b57
SP		 461{
462 struct arm64_ftr_bits *ftrp;
3c739b57
SP		 463
464 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
465 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
466 s64 ftr_new = arm64_ftr_value(ftrp, new);
467
468 if (ftr_cur == ftr_new)
469 continue;
470 /* Find a safe value */
471 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
472 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
473 }
474
475}
476
3086d391 477static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
cdcf817b 478{
3086d391
SP		 479 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
480
481 BUG_ON(!regp);
482 update_cpu_ftr_reg(regp, val);
483 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
484 return 0;
485 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
486 regp->name, boot, cpu, val);
487 return 1;
488}
489
490/*
491 * Update system wide CPU feature registers with the values from a
492 * non-boot CPU. Also performs SANITY checks to make sure that there
493 * aren't any insane variations from that of the boot CPU.
494 */
495void update_cpu_features(int cpu,
496 struct cpuinfo_arm64 *info,
497 struct cpuinfo_arm64 *boot)
498{
499 int taint = 0;
500
501 /*
502 * The kernel can handle differing I-cache policies, but otherwise
503 * caches should look identical. Userspace JITs will make use of
504 * *minLine.
505 */
506 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
507 info->reg_ctr, boot->reg_ctr);
508
509 /*
510 * Userspace may perform DC ZVA instructions. Mismatched block sizes
511 * could result in too much or too little memory being zeroed if a
512 * process is preempted and migrated between CPUs.
513 */
514 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
515 info->reg_dczid, boot->reg_dczid);
516
517 /* If different, timekeeping will be broken (especially with KVM) */
518 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
519 info->reg_cntfrq, boot->reg_cntfrq);
520
521 /*
522 * The kernel uses self-hosted debug features and expects CPUs to
523 * support identical debug features. We presently need CTX_CMPs, WRPs,
524 * and BRPs to be identical.
525 * ID_AA64DFR1 is currently RES0.
526 */
527 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
528 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
529 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
530 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
531 /*
532 * Even in big.LITTLE, processors should be identical instruction-set
533 * wise.
534 */
535 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
536 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
537 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
538 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
539
540 /*
541 * Differing PARange support is fine as long as all peripherals and
542 * memory are mapped within the minimum PARange of all CPUs.
543 * Linux should not care about secure memory.
544 */
545 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
546 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
547 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
548 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
406e3087
JM		 549 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
550 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
3086d391
SP		 551
552 /*
553 * EL3 is not our concern.
554 * ID_AA64PFR1 is currently RES0.
555 */
556 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
557 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
558 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
559 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
560
561 /*
562 * If we have AArch32, we care about 32-bit features for compat. These
563 * registers should be RES0 otherwise.
564 */
565 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
566 info->reg_id_dfr0, boot->reg_id_dfr0);
567 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
568 info->reg_id_isar0, boot->reg_id_isar0);
569 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
570 info->reg_id_isar1, boot->reg_id_isar1);
571 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
572 info->reg_id_isar2, boot->reg_id_isar2);
573 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
574 info->reg_id_isar3, boot->reg_id_isar3);
575 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
576 info->reg_id_isar4, boot->reg_id_isar4);
577 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
578 info->reg_id_isar5, boot->reg_id_isar5);
579
580 /*
581 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
582 * ACTLR formats could differ across CPUs and therefore would have to
583 * be trapped for virtualization anyway.
584 */
585 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
586 info->reg_id_mmfr0, boot->reg_id_mmfr0);
587 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
588 info->reg_id_mmfr1, boot->reg_id_mmfr1);
589 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
590 info->reg_id_mmfr2, boot->reg_id_mmfr2);
591 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
592 info->reg_id_mmfr3, boot->reg_id_mmfr3);
593 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
594 info->reg_id_pfr0, boot->reg_id_pfr0);
595 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
596 info->reg_id_pfr1, boot->reg_id_pfr1);
597 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
598 info->reg_mvfr0, boot->reg_mvfr0);
599 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
600 info->reg_mvfr1, boot->reg_mvfr1);
601 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
602 info->reg_mvfr2, boot->reg_mvfr2);
603
604 /*
605 * Mismatched CPU features are a recipe for disaster. Don't even
606 * pretend to support them.
607 */
608 WARN_TAINT_ONCE(taint, TAINT_CPU_OUT_OF_SPEC,
609 "Unsupported CPU feature variation.\n");
cdcf817b
SP		 610}
611
b3f15378
SP		 612u64 read_system_reg(u32 id)
613{
614 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
615
616 /* We shouldn't get a request for an unsupported register */
617 BUG_ON(!regp);
618 return regp->sys_val;
619}
359b7064 620
963fcd40
MZ		 621#include <linux/irqchip/arm-gic-v3.h>
622
18ffa046
JM		 623static bool
624feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
625{
28c5dcb2 626 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
18ffa046
JM		 627
628 return val >= entry->min_field_value;
629}
630
da8d02d1
SP		 631static bool
632has_cpuid_feature(const struct arm64_cpu_capabilities *entry)
633{
634 u64 val;
94a9e04a 635
da8d02d1
SP		 636 val = read_system_reg(entry->sys_reg);
637 return feature_matches(val, entry);
638}
338d4f49 639
963fcd40
MZ		 640static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry)
641{
642 bool has_sre;
643
2dc10ad8 644 if (!has_cpuid_feature(entry))
963fcd40
MZ		 645 return false;
646
647 has_sre = gic_enable_sre();
648 if (!has_sre)
649 pr_warn_once("%s present but disabled by higher exception level\n",
650 entry->desc);
651
652 return has_sre;
653}
654
d5370f75
WD		 655static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry)
656{
657 u32 midr = read_cpuid_id();
658 u32 rv_min, rv_max;
659
660 /* Cavium ThunderX pass 1.x and 2.x */
661 rv_min = 0;
662 rv_max = (1 << MIDR_VARIANT_SHIFT) | MIDR_REVISION_MASK;
663
664 return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, rv_min, rv_max);
665}
666
d88701be
MZ		 667static bool runs_at_el2(const struct arm64_cpu_capabilities *entry)
668{
669 return is_kernel_in_hyp_mode();
670}
671
359b7064 672static const struct arm64_cpu_capabilities arm64_features[] = {
94a9e04a
MZ		 673 {
674 .desc = "GIC system register CPU interface",
675 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
963fcd40 676 .matches = has_useable_gicv3_cpuif,
da8d02d1
SP		 677 .sys_reg = SYS_ID_AA64PFR0_EL1,
678 .field_pos = ID_AA64PFR0_GIC_SHIFT,
ff96f7bc 679 .sign = FTR_UNSIGNED,
18ffa046 680 .min_field_value = 1,
94a9e04a 681 },
338d4f49
JM		 682#ifdef CONFIG_ARM64_PAN
683 {
684 .desc = "Privileged Access Never",
685 .capability = ARM64_HAS_PAN,
da8d02d1
SP		 686 .matches = has_cpuid_feature,
687 .sys_reg = SYS_ID_AA64MMFR1_EL1,
688 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
ff96f7bc 689 .sign = FTR_UNSIGNED,
338d4f49
JM		 690 .min_field_value = 1,
691 .enable = cpu_enable_pan,
692 },
693#endif /* CONFIG_ARM64_PAN */
2e94da13
WD		 694#if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
695 {
696 .desc = "LSE atomic instructions",
697 .capability = ARM64_HAS_LSE_ATOMICS,
da8d02d1
SP		 698 .matches = has_cpuid_feature,
699 .sys_reg = SYS_ID_AA64ISAR0_EL1,
700 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
ff96f7bc 701 .sign = FTR_UNSIGNED,
2e94da13
WD		 702 .min_field_value = 2,
703 },
704#endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
d5370f75
WD		 705 {
706 .desc = "Software prefetching using PRFM",
707 .capability = ARM64_HAS_NO_HW_PREFETCH,
708 .matches = has_no_hw_prefetch,
709 },
57f4959b
JM		 710#ifdef CONFIG_ARM64_UAO
711 {
712 .desc = "User Access Override",
713 .capability = ARM64_HAS_UAO,
714 .matches = has_cpuid_feature,
715 .sys_reg = SYS_ID_AA64MMFR2_EL1,
716 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
717 .min_field_value = 1,
718 .enable = cpu_enable_uao,
719 },
720#endif /* CONFIG_ARM64_UAO */
70544196
JM		 721#ifdef CONFIG_ARM64_PAN
722 {
723 .capability = ARM64_ALT_PAN_NOT_UAO,
724 .matches = cpufeature_pan_not_uao,
725 },
726#endif /* CONFIG_ARM64_PAN */
d88701be
MZ		 727 {
728 .desc = "Virtualization Host Extensions",
729 .capability = ARM64_HAS_VIRT_HOST_EXTN,
730 .matches = runs_at_el2,
731 },
359b7064
MZ		 732 {},
733};
734
ff96f7bc 735#define HWCAP_CAP(reg, field, s, min_value, type, cap) \
37b01d53
SP		 736 { \
737 .desc = #cap, \
738 .matches = has_cpuid_feature, \
739 .sys_reg = reg, \
740 .field_pos = field, \
ff96f7bc 741 .sign = s, \
37b01d53
SP		 742 .min_field_value = min_value, \
743 .hwcap_type = type, \
744 .hwcap = cap, \
745 }
746
f3efb675 747static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
ff96f7bc
SP		 748 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
749 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
750 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
751 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
752 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
753 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
754 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
bf500618 755 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
ff96f7bc 756 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
bf500618 757 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
75283501
SP		 758 {},
759};
760
761static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
37b01d53 762#ifdef CONFIG_COMPAT
ff96f7bc
SP		 763 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
764 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
765 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
766 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
767 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
37b01d53
SP		 768#endif
769 {},
770};
771
f3efb675 772static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 773{
774 switch (cap->hwcap_type) {
775 case CAP_HWCAP:
776 elf_hwcap |= cap->hwcap;
777 break;
778#ifdef CONFIG_COMPAT
779 case CAP_COMPAT_HWCAP:
780 compat_elf_hwcap |= (u32)cap->hwcap;
781 break;
782 case CAP_COMPAT_HWCAP2:
783 compat_elf_hwcap2 |= (u32)cap->hwcap;
784 break;
785#endif
786 default:
787 WARN_ON(1);
788 break;
789 }
790}
791
792/* Check if we have a particular HWCAP enabled */
f3efb675 793static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 794{
795 bool rc;
796
797 switch (cap->hwcap_type) {
798 case CAP_HWCAP:
799 rc = (elf_hwcap & cap->hwcap) != 0;
800 break;
801#ifdef CONFIG_COMPAT
802 case CAP_COMPAT_HWCAP:
803 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
804 break;
805 case CAP_COMPAT_HWCAP2:
806 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
807 break;
808#endif
809 default:
810 WARN_ON(1);
811 rc = false;
812 }
813
814 return rc;
815}
816
75283501 817static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
37b01d53 818{
75283501
SP		 819 for (; hwcaps->matches; hwcaps++)
820 if (hwcaps->matches(hwcaps))
821 cap_set_elf_hwcap(hwcaps);
37b01d53
SP		 822}
823
ce8b602c 824void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
359b7064
MZ		 825 const char *info)
826{
75283501
SP		 827 for (; caps->matches; caps++) {
828 if (!caps->matches(caps))
359b7064
MZ		 829 continue;
830
75283501
SP		 831 if (!cpus_have_cap(caps->capability) && caps->desc)
832 pr_info("%s %s\n", info, caps->desc);
833 cpus_set_cap(caps->capability);
359b7064 834 }
ce8b602c
SP		 835}
836
837/*
dbb4e152
SP		 838 * Run through the enabled capabilities and enable() it on all active
839 * CPUs
ce8b602c 840 */
a7c61a34
JZ		 841static void __init
842enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
ce8b602c 843{
75283501
SP		 844 for (; caps->matches; caps++)
845 if (caps->enable && cpus_have_cap(caps->capability))
846 on_each_cpu(caps->enable, NULL, true);
dbb4e152
SP		 847}
848
dbb4e152
SP		 849/*
850 * Flag to indicate if we have computed the system wide
851 * capabilities based on the boot time active CPUs. This
852 * will be used to determine if a new booting CPU should
853 * go through the verification process to make sure that it
854 * supports the system capabilities, without using a hotplug
855 * notifier.
856 */
857static bool sys_caps_initialised;
858
859static inline void set_sys_caps_initialised(void)
860{
861 sys_caps_initialised = true;
862}
863
da8d02d1
SP		 864/*
865 * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated.
866 */
867static u64 __raw_read_system_reg(u32 sys_id)
868{
869 switch (sys_id) {
1cc6ed90
MR		 870 case SYS_ID_PFR0_EL1: return read_cpuid(ID_PFR0_EL1);
871 case SYS_ID_PFR1_EL1: return read_cpuid(ID_PFR1_EL1);
872 case SYS_ID_DFR0_EL1: return read_cpuid(ID_DFR0_EL1);
873 case SYS_ID_MMFR0_EL1: return read_cpuid(ID_MMFR0_EL1);
874 case SYS_ID_MMFR1_EL1: return read_cpuid(ID_MMFR1_EL1);
875 case SYS_ID_MMFR2_EL1: return read_cpuid(ID_MMFR2_EL1);
876 case SYS_ID_MMFR3_EL1: return read_cpuid(ID_MMFR3_EL1);
877 case SYS_ID_ISAR0_EL1: return read_cpuid(ID_ISAR0_EL1);
878 case SYS_ID_ISAR1_EL1: return read_cpuid(ID_ISAR1_EL1);
879 case SYS_ID_ISAR2_EL1: return read_cpuid(ID_ISAR2_EL1);
880 case SYS_ID_ISAR3_EL1: return read_cpuid(ID_ISAR3_EL1);
881 case SYS_ID_ISAR4_EL1: return read_cpuid(ID_ISAR4_EL1);
882 case SYS_ID_ISAR5_EL1: return read_cpuid(ID_ISAR4_EL1);
883 case SYS_MVFR0_EL1: return read_cpuid(MVFR0_EL1);
884 case SYS_MVFR1_EL1: return read_cpuid(MVFR1_EL1);
885 case SYS_MVFR2_EL1: return read_cpuid(MVFR2_EL1);
886
887 case SYS_ID_AA64PFR0_EL1: return read_cpuid(ID_AA64PFR0_EL1);
888 case SYS_ID_AA64PFR1_EL1: return read_cpuid(ID_AA64PFR0_EL1);
889 case SYS_ID_AA64DFR0_EL1: return read_cpuid(ID_AA64DFR0_EL1);
890 case SYS_ID_AA64DFR1_EL1: return read_cpuid(ID_AA64DFR0_EL1);
891 case SYS_ID_AA64MMFR0_EL1: return read_cpuid(ID_AA64MMFR0_EL1);
892 case SYS_ID_AA64MMFR1_EL1: return read_cpuid(ID_AA64MMFR1_EL1);
893 case SYS_ID_AA64MMFR2_EL1: return read_cpuid(ID_AA64MMFR2_EL1);
894 case SYS_ID_AA64ISAR0_EL1: return read_cpuid(ID_AA64ISAR0_EL1);
895 case SYS_ID_AA64ISAR1_EL1: return read_cpuid(ID_AA64ISAR1_EL1);
896
897 case SYS_CNTFRQ_EL0: return read_cpuid(CNTFRQ_EL0);
898 case SYS_CTR_EL0: return read_cpuid(CTR_EL0);
899 case SYS_DCZID_EL0: return read_cpuid(DCZID_EL0);
da8d02d1
SP		 900 default:
901 BUG();
902 return 0;
903 }
904}
905
dbb4e152 906/*
13f417f3
SP		 907 * Check for CPU features that are used in early boot
908 * based on the Boot CPU value.
dbb4e152 909 */
13f417f3 910static void check_early_cpu_features(void)
dbb4e152 911{
ac1ad20f 912 verify_cpu_run_el();
13f417f3 913 verify_cpu_asid_bits();
dbb4e152 914}
1c076303 915
75283501
SP		 916static void
917verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
918{
919
920 for (; caps->matches; caps++) {
921 if (!cpus_have_elf_hwcap(caps))
922 continue;
923 if (!feature_matches(__raw_read_system_reg(caps->sys_reg), caps)) {
924 pr_crit("CPU%d: missing HWCAP: %s\n",
925 smp_processor_id(), caps->desc);
926 cpu_die_early();
927 }
928 }
929}
930
931static void
932verify_local_cpu_features(const struct arm64_cpu_capabilities *caps)
933{
934 for (; caps->matches; caps++) {
935 if (!cpus_have_cap(caps->capability) || !caps->sys_reg)
936 continue;
937 /*
938 * If the new CPU misses an advertised feature, we cannot proceed
939 * further, park the cpu.
940 */
941 if (!feature_matches(__raw_read_system_reg(caps->sys_reg), caps)) {
942 pr_crit("CPU%d: missing feature: %s\n",
943 smp_processor_id(), caps->desc);
944 cpu_die_early();
945 }
946 if (caps->enable)
947 caps->enable(NULL);
948 }
949}
950
dbb4e152
SP		 951/*
952 * Run through the enabled system capabilities and enable() it on this CPU.
953 * The capabilities were decided based on the available CPUs at the boot time.
954 * Any new CPU should match the system wide status of the capability. If the
955 * new CPU doesn't have a capability which the system now has enabled, we
956 * cannot do anything to fix it up and could cause unexpected failures. So
957 * we park the CPU.
958 */
959void verify_local_cpu_capabilities(void)
960{
dbb4e152 961
13f417f3
SP		 962 check_early_cpu_features();
963
dbb4e152
SP		 964 /*
965 * If we haven't computed the system capabilities, there is nothing
966 * to verify.
967 */
968 if (!sys_caps_initialised)
969 return;
970
75283501
SP		 971 verify_local_cpu_features(arm64_features);
972 verify_local_elf_hwcaps(arm64_elf_hwcaps);
973 verify_local_elf_hwcaps(compat_elf_hwcaps);
359b7064
MZ		 974}
975
a7c61a34 976static void __init setup_feature_capabilities(void)
359b7064 977{
ce8b602c
SP		 978 update_cpu_capabilities(arm64_features, "detected feature:");
979 enable_cpu_capabilities(arm64_features);
359b7064
MZ		 980}
981
9cdf8ec4 982void __init setup_cpu_features(void)
359b7064 983{
9cdf8ec4
SP		 984 u32 cwg;
985 int cls;
986
dbb4e152
SP		 987 /* Set the CPU feature capabilies */
988 setup_feature_capabilities();
75283501
SP		 989 setup_elf_hwcaps(arm64_elf_hwcaps);
990 setup_elf_hwcaps(compat_elf_hwcaps);
dbb4e152
SP		 991
992 /* Advertise that we have computed the system capabilities */
993 set_sys_caps_initialised();
994
9cdf8ec4
SP		 995 /*
996 * Check for sane CTR_EL0.CWG value.
997 */
998 cwg = cache_type_cwg();
999 cls = cache_line_size();
1000 if (!cwg)
1001 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
1002 cls);
1003 if (L1_CACHE_BYTES < cls)
1004 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
1005 L1_CACHE_BYTES, cls);
359b7064 1006}
70544196
JM		 1007
1008static bool __maybe_unused
1009cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry)
1010{
1011 return (cpus_have_cap(ARM64_HAS_PAN) && !cpus_have_cap(ARM64_HAS_UAO));
1012}
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