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Merge branch 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-jammy-kernel.git] / arch / arm64 / kernel / cpufeature.c
CommitLineData
359b7064
MZ		 1/*
2 * Contains CPU feature definitions
3 *
4 * Copyright (C) 2015 ARM Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
9cdf8ec4 19#define pr_fmt(fmt) "CPU features: " fmt
359b7064 20
3c739b57 21#include <linux/bsearch.h>
2a6dcb2b 22#include <linux/cpumask.h>
5ffdfaed 23#include <linux/crash_dump.h>
3c739b57 24#include <linux/sort.h>
2a6dcb2b 25#include <linux/stop_machine.h>
359b7064 26#include <linux/types.h>
2077be67 27#include <linux/mm.h>
a111b7c0 28#include <linux/cpu.h>
359b7064
MZ		 29#include <asm/cpu.h>
30#include <asm/cpufeature.h>
dbb4e152 31#include <asm/cpu_ops.h>
2e0f2478 32#include <asm/fpsimd.h>
13f417f3 33#include <asm/mmu_context.h>
338d4f49 34#include <asm/processor.h>
cdcf817b 35#include <asm/sysreg.h>
77c97b4e 36#include <asm/traps.h>
d88701be 37#include <asm/virt.h>
359b7064 38
aec0bff7
AM		 39/* Kernel representation of AT_HWCAP and AT_HWCAP2 */
40static unsigned long elf_hwcap __read_mostly;
9cdf8ec4
SP		 41
42#ifdef CONFIG_COMPAT
43#define COMPAT_ELF_HWCAP_DEFAULT \
44 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
45 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
46 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
47 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
48 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
49 COMPAT_HWCAP_LPAE)
50unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
51unsigned int compat_elf_hwcap2 __read_mostly;
52#endif
53
54DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
4b65a5db 55EXPORT_SYMBOL(cpu_hwcaps);
82a3a21b 56static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
9cdf8ec4 57
0ceb0d56
DT		 58/* Need also bit for ARM64_CB_PATCH */
59DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
60
8f1eec57
DM		 61/*
62 * Flag to indicate if we have computed the system wide
63 * capabilities based on the boot time active CPUs. This
64 * will be used to determine if a new booting CPU should
65 * go through the verification process to make sure that it
66 * supports the system capabilities, without using a hotplug
67 * notifier.
68 */
69static bool sys_caps_initialised;
70
71static inline void set_sys_caps_initialised(void)
72{
73 sys_caps_initialised = true;
74}
75
8effeaaf
MR		 76static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
77{
78 /* file-wide pr_fmt adds "CPU features: " prefix */
79 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
80 return 0;
81}
82
83static struct notifier_block cpu_hwcaps_notifier = {
84 .notifier_call = dump_cpu_hwcaps
85};
86
87static int __init register_cpu_hwcaps_dumper(void)
88{
89 atomic_notifier_chain_register(&panic_notifier_list,
90 &cpu_hwcaps_notifier);
91 return 0;
92}
93__initcall(register_cpu_hwcaps_dumper);
94
efd9e03f
CM		 95DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
96EXPORT_SYMBOL(cpu_hwcap_keys);
97
fe4fbdbc 98#define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
3c739b57 99 { \
4f0a606b 100 .sign = SIGNED, \
fe4fbdbc 101 .visible = VISIBLE, \
3c739b57
SP		 102 .strict = STRICT, \
103 .type = TYPE, \
104 .shift = SHIFT, \
105 .width = WIDTH, \
106 .safe_val = SAFE_VAL, \
107 }
108
0710cfdb 109/* Define a feature with unsigned values */
fe4fbdbc
SP		 110#define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
111 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
4f0a606b 112
0710cfdb 113/* Define a feature with a signed value */
fe4fbdbc
SP		 114#define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
115 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
0710cfdb 116
3c739b57
SP		 117#define ARM64_FTR_END \
118 { \
119 .width = 0, \
120 }
121
70544196
JM		 122/* meta feature for alternatives */
123static bool __maybe_unused
92406f0c
SP		 124cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
125
5ffdfaed 126static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
70544196 127
4aa8a472
SP		 128/*
129 * NOTE: Any changes to the visibility of features should be kept in
130 * sync with the documentation of the CPU feature register ABI.
131 */
5e49d73c 132static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
7206dc93 133 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
3b3b6810 134 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
5bdecb79
SP		 135 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
136 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
137 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
138 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
139 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
fe4fbdbc
SP		 140 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
141 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
142 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
143 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
144 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
3c739b57
SP		 145 ARM64_FTR_END,
146};
147
c8c3798d 148static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
bd4fb6d2 149 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
6984eb47
MR		 150 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
151 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
152 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
153 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
5bdecb79
SP		 154 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
155 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
156 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
6984eb47
MR		 157 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
158 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0),
159 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
160 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0),
5bdecb79 161 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
c8c3798d
SP		 162 ARM64_FTR_END,
163};
164
5e49d73c 165static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
179a56f6 166 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
0f15adbb 167 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
7206dc93 168 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
3fab3999
DM		 169 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
170 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
64c02720 171 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
5bdecb79 172 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
fe4fbdbc
SP		 173 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
174 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
3c739b57 175 /* Linux doesn't care about the EL3 */
5bdecb79
SP		 176 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
177 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
178 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
179 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
3c739b57
SP		 180 ARM64_FTR_END,
181};
182
d71be2b6
WD		 183static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
184 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
185 ARM64_FTR_END,
186};
187
06a916fe
DM		 188static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
189 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
190 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
191 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
192 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
193 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
194 ARM64_FTR_END,
195};
196
5e49d73c 197static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
5bdecb79
SP		 198 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
199 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
200 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
201 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
3c739b57 202 /* Linux shouldn't care about secure memory */
5bdecb79
SP		 203 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
204 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
205 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
3c739b57
SP		 206 /*
207 * Differing PARange is fine as long as all peripherals and memory are mapped
208 * within the minimum PARange of all CPUs
209 */
fe4fbdbc 210 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
3c739b57
SP		 211 ARM64_FTR_END,
212};
213
5e49d73c 214static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
fe4fbdbc 215 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
5bdecb79
SP		 216 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
217 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
218 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
219 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
220 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
3c739b57
SP		 221 ARM64_FTR_END,
222};
223
5e49d73c 224static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
e48d53a9 225 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
7206dc93 226 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
5bdecb79
SP		 227 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
228 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
229 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
230 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
231 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
406e3087
JM		 232 ARM64_FTR_END,
233};
234
5e49d73c 235static const struct arm64_ftr_bits ftr_ctr[] = {
6ae4b6e0
SD		 236 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
237 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
238 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
239 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_CWG_SHIFT, 4, 0),
240 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_ERG_SHIFT, 4, 0),
241 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
3c739b57
SP		 242 /*
243 * Linux can handle differing I-cache policies. Userspace JITs will
ee7bc638 244 * make use of *minLine.
155433cb 245 * If we have differing I-cache policies, report it as the weakest - VIPT.
3c739b57 246 */
155433cb 247 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */
4c4a39dd 248 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
3c739b57
SP		 249 ARM64_FTR_END,
250};
251
675b0563
AB		 252struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
253 .name = "SYS_CTR_EL0",
254 .ftr_bits = ftr_ctr
255};
256
5e49d73c 257static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
5bdecb79
SP		 258 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf), /* InnerShr */
259 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), /* FCSE */
fe4fbdbc 260 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
5bdecb79
SP		 261 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), /* TCM */
262 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* ShareLvl */
263 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf), /* OuterShr */
264 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* PMSA */
265 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* VMSA */
3c739b57
SP		 266 ARM64_FTR_END,
267};
268
5e49d73c 269static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
fe4fbdbc
SP		 270 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
271 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
272 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
273 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
274 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
b20d1ba3
WD		 275 /*
276 * We can instantiate multiple PMU instances with different levels
277 * of support.
fe4fbdbc
SP		 278 */
279 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
280 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
281 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
3c739b57
SP		 282 ARM64_FTR_END,
283};
284
5e49d73c 285static const struct arm64_ftr_bits ftr_mvfr2[] = {
5bdecb79
SP		 286 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* FPMisc */
287 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* SIMDMisc */
3c739b57
SP		 288 ARM64_FTR_END,
289};
290
5e49d73c 291static const struct arm64_ftr_bits ftr_dczid[] = {
fe4fbdbc
SP		 292 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
293 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
3c739b57
SP		 294 ARM64_FTR_END,
295};
296
297
5e49d73c 298static const struct arm64_ftr_bits ftr_id_isar5[] = {
5bdecb79
SP		 299 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
300 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
302 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
303 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
304 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
3c739b57
SP		 305 ARM64_FTR_END,
306};
307
5e49d73c 308static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
5bdecb79 309 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* ac2 */
3c739b57
SP		 310 ARM64_FTR_END,
311};
312
5e49d73c 313static const struct arm64_ftr_bits ftr_id_pfr0[] = {
5bdecb79
SP		 314 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* State3 */
315 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), /* State2 */
316 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* State1 */
317 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* State0 */
3c739b57
SP		 318 ARM64_FTR_END,
319};
320
5e49d73c 321static const struct arm64_ftr_bits ftr_id_dfr0[] = {
fe4fbdbc
SP		 322 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
323 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */
324 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
325 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
326 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
327 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
328 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
329 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
e5343503
SP		 330 ARM64_FTR_END,
331};
332
2e0f2478
DM		 333static const struct arm64_ftr_bits ftr_zcr[] = {
334 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
335 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */
336 ARM64_FTR_END,
337};
338
3c739b57
SP		 339/*
340 * Common ftr bits for a 32bit register with all hidden, strict
341 * attributes, with 4bit feature fields and a default safe value of
342 * 0. Covers the following 32bit registers:
343 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
344 */
5e49d73c 345static const struct arm64_ftr_bits ftr_generic_32bits[] = {
fe4fbdbc
SP		 346 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
347 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
348 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
349 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
350 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
351 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
352 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
353 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
3c739b57
SP		 354 ARM64_FTR_END,
355};
356
eab43e88
SP		 357/* Table for a single 32bit feature value */
358static const struct arm64_ftr_bits ftr_single32[] = {
fe4fbdbc 359 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
3c739b57
SP		 360 ARM64_FTR_END,
361};
362
eab43e88 363static const struct arm64_ftr_bits ftr_raz[] = {
3c739b57
SP		 364 ARM64_FTR_END,
365};
366
6f2b7eef
AB		 367#define ARM64_FTR_REG(id, table) { \
368 .sys_id = id, \
369 .reg = &(struct arm64_ftr_reg){ \
3c739b57
SP		 370 .name = #id, \
371 .ftr_bits = &((table)[0]), \
6f2b7eef 372 }}
3c739b57 373
6f2b7eef
AB		 374static const struct __ftr_reg_entry {
375 u32 sys_id;
376 struct arm64_ftr_reg *reg;
377} arm64_ftr_regs[] = {
3c739b57
SP		 378
379 /* Op1 = 0, CRn = 0, CRm = 1 */
380 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
381 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
e5343503 382 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
3c739b57
SP		 383 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
384 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
385 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
386 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
387
388 /* Op1 = 0, CRn = 0, CRm = 2 */
389 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
390 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
391 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
392 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
393 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
394 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
395 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
396
397 /* Op1 = 0, CRn = 0, CRm = 3 */
398 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
399 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
400 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
401
402 /* Op1 = 0, CRn = 0, CRm = 4 */
403 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
d71be2b6 404 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
06a916fe 405 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
3c739b57
SP		 406
407 /* Op1 = 0, CRn = 0, CRm = 5 */
408 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
eab43e88 409 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
3c739b57
SP		 410
411 /* Op1 = 0, CRn = 0, CRm = 6 */
412 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
c8c3798d 413 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
3c739b57
SP		 414
415 /* Op1 = 0, CRn = 0, CRm = 7 */
416 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
417 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
406e3087 418 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
3c739b57 419
2e0f2478
DM		 420 /* Op1 = 0, CRn = 1, CRm = 2 */
421 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
422
3c739b57 423 /* Op1 = 3, CRn = 0, CRm = 0 */
675b0563 424 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
3c739b57
SP		 425 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
426
427 /* Op1 = 3, CRn = 14, CRm = 0 */
eab43e88 428 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
3c739b57
SP		 429};
430
431static int search_cmp_ftr_reg(const void *id, const void *regp)
432{
6f2b7eef 433 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
3c739b57
SP		 434}
435
436/*
437 * get_arm64_ftr_reg - Lookup a feature register entry using its
438 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
439 * ascending order of sys_id , we use binary search to find a matching
440 * entry.
441 *
442 * returns - Upon success, matching ftr_reg entry for id.
443 * - NULL on failure. It is upto the caller to decide
444 * the impact of a failure.
445 */
446static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
447{
6f2b7eef
AB		 448 const struct __ftr_reg_entry *ret;
449
450 ret = bsearch((const void *)(unsigned long)sys_id,
3c739b57
SP		 451 arm64_ftr_regs,
452 ARRAY_SIZE(arm64_ftr_regs),
453 sizeof(arm64_ftr_regs[0]),
454 search_cmp_ftr_reg);
6f2b7eef
AB		 455 if (ret)
456 return ret->reg;
457 return NULL;
3c739b57
SP		 458}
459
5e49d73c
AB		 460static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
461 s64 ftr_val)
3c739b57
SP		 462{
463 u64 mask = arm64_ftr_mask(ftrp);
464
465 reg &= ~mask;
466 reg |= (ftr_val << ftrp->shift) & mask;
467 return reg;
468}
469
5e49d73c
AB		 470static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
471 s64 cur)
3c739b57
SP		 472{
473 s64 ret = 0;
474
475 switch (ftrp->type) {
476 case FTR_EXACT:
477 ret = ftrp->safe_val;
478 break;
479 case FTR_LOWER_SAFE:
480 ret = new < cur ? new : cur;
481 break;
482 case FTR_HIGHER_SAFE:
483 ret = new > cur ? new : cur;
484 break;
485 default:
486 BUG();
487 }
488
489 return ret;
490}
491
3c739b57
SP		 492static void __init sort_ftr_regs(void)
493{
6f2b7eef
AB		 494 int i;
495
496 /* Check that the array is sorted so that we can do the binary search */
497 for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
498 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
3c739b57
SP		 499}
500
501/*
502 * Initialise the CPU feature register from Boot CPU values.
503 * Also initiliases the strict_mask for the register.
b389d799
MR		 504 * Any bits that are not covered by an arm64_ftr_bits entry are considered
505 * RES0 for the system-wide value, and must strictly match.
3c739b57
SP		 506 */
507static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
508{
509 u64 val = 0;
510 u64 strict_mask = ~0x0ULL;
fe4fbdbc 511 u64 user_mask = 0;
b389d799
MR		 512 u64 valid_mask = 0;
513
5e49d73c 514 const struct arm64_ftr_bits *ftrp;
3c739b57
SP		 515 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
516
517 BUG_ON(!reg);
518
519 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
b389d799 520 u64 ftr_mask = arm64_ftr_mask(ftrp);
3c739b57
SP		 521 s64 ftr_new = arm64_ftr_value(ftrp, new);
522
523 val = arm64_ftr_set_value(ftrp, val, ftr_new);
b389d799
MR		 524
525 valid_mask |= ftr_mask;
3c739b57 526 if (!ftrp->strict)
b389d799 527 strict_mask &= ~ftr_mask;
fe4fbdbc
SP		 528 if (ftrp->visible)
529 user_mask |= ftr_mask;
530 else
531 reg->user_val = arm64_ftr_set_value(ftrp,
532 reg->user_val,
533 ftrp->safe_val);
3c739b57 534 }
b389d799
MR		 535
536 val &= valid_mask;
537
3c739b57
SP		 538 reg->sys_val = val;
539 reg->strict_mask = strict_mask;
fe4fbdbc 540 reg->user_mask = user_mask;
3c739b57
SP		 541}
542
1e89baed 543extern const struct arm64_cpu_capabilities arm64_errata[];
82a3a21b
SP		 544static const struct arm64_cpu_capabilities arm64_features[];
545
546static void __init
547init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
548{
549 for (; caps->matches; caps++) {
550 if (WARN(caps->capability >= ARM64_NCAPS,
551 "Invalid capability %d\n", caps->capability))
552 continue;
553 if (WARN(cpu_hwcaps_ptrs[caps->capability],
554 "Duplicate entry for capability %d\n",
555 caps->capability))
556 continue;
557 cpu_hwcaps_ptrs[caps->capability] = caps;
558 }
559}
560
561static void __init init_cpu_hwcaps_indirect_list(void)
562{
563 init_cpu_hwcaps_indirect_list_from_array(arm64_features);
564 init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
565}
566
fd9d63da 567static void __init setup_boot_cpu_capabilities(void);
1e89baed 568
3c739b57
SP		 569void __init init_cpu_features(struct cpuinfo_arm64 *info)
570{
571 /* Before we start using the tables, make sure it is sorted */
572 sort_ftr_regs();
573
574 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
575 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
576 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
577 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
578 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
579 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
580 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
581 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
582 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
406e3087 583 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
3c739b57
SP		 584 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
585 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
2e0f2478 586 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
a6dc3cd7
SP		 587
588 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
589 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
590 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
591 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
592 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
593 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
594 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
595 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
596 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
597 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
598 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
599 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
600 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
601 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
602 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
603 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
604 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
605 }
606
2e0f2478
DM		 607 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
608 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
609 sve_init_vq_map();
610 }
5e91107b 611
82a3a21b
SP		 612 /*
613 * Initialize the indirect array of CPU hwcaps capabilities pointers
614 * before we handle the boot CPU below.
615 */
616 init_cpu_hwcaps_indirect_list();
617
5e91107b 618 /*
fd9d63da
SP		 619 * Detect and enable early CPU capabilities based on the boot CPU,
620 * after we have initialised the CPU feature infrastructure.
5e91107b 621 */
fd9d63da 622 setup_boot_cpu_capabilities();
3c739b57
SP		 623}
624
3086d391 625static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
3c739b57 626{
5e49d73c 627 const struct arm64_ftr_bits *ftrp;
3c739b57
SP		 628
629 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
630 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
631 s64 ftr_new = arm64_ftr_value(ftrp, new);
632
633 if (ftr_cur == ftr_new)
634 continue;
635 /* Find a safe value */
636 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
637 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
638 }
639
640}
641
3086d391 642static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
cdcf817b 643{
3086d391
SP		 644 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
645
646 BUG_ON(!regp);
647 update_cpu_ftr_reg(regp, val);
648 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
649 return 0;
650 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
651 regp->name, boot, cpu, val);
652 return 1;
653}
654
655/*
656 * Update system wide CPU feature registers with the values from a
657 * non-boot CPU. Also performs SANITY checks to make sure that there
658 * aren't any insane variations from that of the boot CPU.
659 */
660void update_cpu_features(int cpu,
661 struct cpuinfo_arm64 *info,
662 struct cpuinfo_arm64 *boot)
663{
664 int taint = 0;
665
666 /*
667 * The kernel can handle differing I-cache policies, but otherwise
668 * caches should look identical. Userspace JITs will make use of
669 * *minLine.
670 */
671 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
672 info->reg_ctr, boot->reg_ctr);
673
674 /*
675 * Userspace may perform DC ZVA instructions. Mismatched block sizes
676 * could result in too much or too little memory being zeroed if a
677 * process is preempted and migrated between CPUs.
678 */
679 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
680 info->reg_dczid, boot->reg_dczid);
681
682 /* If different, timekeeping will be broken (especially with KVM) */
683 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
684 info->reg_cntfrq, boot->reg_cntfrq);
685
686 /*
687 * The kernel uses self-hosted debug features and expects CPUs to
688 * support identical debug features. We presently need CTX_CMPs, WRPs,
689 * and BRPs to be identical.
690 * ID_AA64DFR1 is currently RES0.
691 */
692 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
693 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
694 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
695 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
696 /*
697 * Even in big.LITTLE, processors should be identical instruction-set
698 * wise.
699 */
700 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
701 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
702 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
703 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
704
705 /*
706 * Differing PARange support is fine as long as all peripherals and
707 * memory are mapped within the minimum PARange of all CPUs.
708 * Linux should not care about secure memory.
709 */
710 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
711 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
712 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
713 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
406e3087
JM		 714 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
715 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
3086d391
SP		 716
717 /*
718 * EL3 is not our concern.
3086d391
SP		 719 */
720 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
721 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
722 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
723 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
724
2e0f2478
DM		 725 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
726 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
727
3086d391 728 /*
a6dc3cd7
SP		 729 * If we have AArch32, we care about 32-bit features for compat.
730 * If the system doesn't support AArch32, don't update them.
3086d391 731 */
46823dd1 732 if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
a6dc3cd7
SP		 733 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
734
735 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
3086d391 736 info->reg_id_dfr0, boot->reg_id_dfr0);
a6dc3cd7 737 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
3086d391 738 info->reg_id_isar0, boot->reg_id_isar0);
a6dc3cd7 739 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
3086d391 740 info->reg_id_isar1, boot->reg_id_isar1);
a6dc3cd7 741 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
3086d391 742 info->reg_id_isar2, boot->reg_id_isar2);
a6dc3cd7 743 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
3086d391 744 info->reg_id_isar3, boot->reg_id_isar3);
a6dc3cd7 745 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
3086d391 746 info->reg_id_isar4, boot->reg_id_isar4);
a6dc3cd7 747 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
3086d391
SP		 748 info->reg_id_isar5, boot->reg_id_isar5);
749
a6dc3cd7
SP		 750 /*
751 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
752 * ACTLR formats could differ across CPUs and therefore would have to
753 * be trapped for virtualization anyway.
754 */
755 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
3086d391 756 info->reg_id_mmfr0, boot->reg_id_mmfr0);
a6dc3cd7 757 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
3086d391 758 info->reg_id_mmfr1, boot->reg_id_mmfr1);
a6dc3cd7 759 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
3086d391 760 info->reg_id_mmfr2, boot->reg_id_mmfr2);
a6dc3cd7 761 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
3086d391 762 info->reg_id_mmfr3, boot->reg_id_mmfr3);
a6dc3cd7 763 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
3086d391 764 info->reg_id_pfr0, boot->reg_id_pfr0);
a6dc3cd7 765 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
3086d391 766 info->reg_id_pfr1, boot->reg_id_pfr1);
a6dc3cd7 767 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
3086d391 768 info->reg_mvfr0, boot->reg_mvfr0);
a6dc3cd7 769 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
3086d391 770 info->reg_mvfr1, boot->reg_mvfr1);
a6dc3cd7 771 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
3086d391 772 info->reg_mvfr2, boot->reg_mvfr2);
a6dc3cd7 773 }
3086d391 774
2e0f2478
DM		 775 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
776 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
777 info->reg_zcr, boot->reg_zcr);
778
779 /* Probe vector lengths, unless we already gave up on SVE */
780 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
781 !sys_caps_initialised)
782 sve_update_vq_map();
783 }
784
3086d391
SP		 785 /*
786 * Mismatched CPU features are a recipe for disaster. Don't even
787 * pretend to support them.
788 */
8dd0ee65
WD		 789 if (taint) {
790 pr_warn_once("Unsupported CPU feature variation detected.\n");
791 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
792 }
cdcf817b
SP		 793}
794
46823dd1 795u64 read_sanitised_ftr_reg(u32 id)
b3f15378
SP		 796{
797 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
798
799 /* We shouldn't get a request for an unsupported register */
800 BUG_ON(!regp);
801 return regp->sys_val;
802}
359b7064 803
965861d6
MR		 804#define read_sysreg_case(r) \
805 case r: return read_sysreg_s(r)
806
92406f0c 807/*
46823dd1 808 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
92406f0c
SP		 809 * Read the system register on the current CPU
810 */
46823dd1 811static u64 __read_sysreg_by_encoding(u32 sys_id)
92406f0c
SP		 812{
813 switch (sys_id) {
965861d6
MR		 814 read_sysreg_case(SYS_ID_PFR0_EL1);
815 read_sysreg_case(SYS_ID_PFR1_EL1);
816 read_sysreg_case(SYS_ID_DFR0_EL1);
817 read_sysreg_case(SYS_ID_MMFR0_EL1);
818 read_sysreg_case(SYS_ID_MMFR1_EL1);
819 read_sysreg_case(SYS_ID_MMFR2_EL1);
820 read_sysreg_case(SYS_ID_MMFR3_EL1);
821 read_sysreg_case(SYS_ID_ISAR0_EL1);
822 read_sysreg_case(SYS_ID_ISAR1_EL1);
823 read_sysreg_case(SYS_ID_ISAR2_EL1);
824 read_sysreg_case(SYS_ID_ISAR3_EL1);
825 read_sysreg_case(SYS_ID_ISAR4_EL1);
826 read_sysreg_case(SYS_ID_ISAR5_EL1);
827 read_sysreg_case(SYS_MVFR0_EL1);
828 read_sysreg_case(SYS_MVFR1_EL1);
829 read_sysreg_case(SYS_MVFR2_EL1);
830
831 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
832 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
78ed70bf 833 read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
965861d6
MR		 834 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
835 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
836 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
837 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
838 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
839 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
840 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
841
842 read_sysreg_case(SYS_CNTFRQ_EL0);
843 read_sysreg_case(SYS_CTR_EL0);
844 read_sysreg_case(SYS_DCZID_EL0);
845
92406f0c
SP		 846 default:
847 BUG();
848 return 0;
849 }
850}
851
963fcd40
MZ		 852#include <linux/irqchip/arm-gic-v3.h>
853
18ffa046
JM		 854static bool
855feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
856{
28c5dcb2 857 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
18ffa046
JM		 858
859 return val >= entry->min_field_value;
860}
861
da8d02d1 862static bool
92406f0c 863has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
da8d02d1
SP		 864{
865 u64 val;
94a9e04a 866
92406f0c
SP		 867 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
868 if (scope == SCOPE_SYSTEM)
46823dd1 869 val = read_sanitised_ftr_reg(entry->sys_reg);
92406f0c 870 else
46823dd1 871 val = __read_sysreg_by_encoding(entry->sys_reg);
92406f0c 872
da8d02d1
SP		 873 return feature_matches(val, entry);
874}
338d4f49 875
92406f0c 876static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
963fcd40
MZ		 877{
878 bool has_sre;
879
92406f0c 880 if (!has_cpuid_feature(entry, scope))
963fcd40
MZ		 881 return false;
882
883 has_sre = gic_enable_sre();
884 if (!has_sre)
885 pr_warn_once("%s present but disabled by higher exception level\n",
886 entry->desc);
887
888 return has_sre;
889}
890
92406f0c 891static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
d5370f75
WD		 892{
893 u32 midr = read_cpuid_id();
d5370f75
WD		 894
895 /* Cavium ThunderX pass 1.x and 2.x */
fa5ce3d1
RR		 896 return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX,
897 MIDR_CPU_VAR_REV(0, 0),
898 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
d5370f75
WD		 899}
900
82e0191a
SP		 901static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
902{
46823dd1 903 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
82e0191a
SP		 904
905 return cpuid_feature_extract_signed_field(pfr0,
906 ID_AA64PFR0_FP_SHIFT) < 0;
907}
908
6ae4b6e0 909static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
8ab66cbe 910 int scope)
6ae4b6e0 911{
8ab66cbe
SP		 912 u64 ctr;
913
914 if (scope == SCOPE_SYSTEM)
915 ctr = arm64_ftr_reg_ctrel0.sys_val;
916 else
1602df02 917 ctr = read_cpuid_effective_cachetype();
8ab66cbe
SP		 918
919 return ctr & BIT(CTR_IDC_SHIFT);
6ae4b6e0
SD		 920}
921
1602df02
SP		 922static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
923{
924 /*
925 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
926 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
927 * to the CTR_EL0 on this CPU and emulate it with the real/safe
928 * value.
929 */
930 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
931 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
932}
933
6ae4b6e0 934static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
8ab66cbe 935 int scope)
6ae4b6e0 936{
8ab66cbe
SP		 937 u64 ctr;
938
939 if (scope == SCOPE_SYSTEM)
940 ctr = arm64_ftr_reg_ctrel0.sys_val;
941 else
942 ctr = read_cpuid_cachetype();
943
944 return ctr & BIT(CTR_DIC_SHIFT);
6ae4b6e0
SD		 945}
946
5ffdfaed
VM		 947static bool __maybe_unused
948has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
949{
950 /*
951 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
952 * may share TLB entries with a CPU stuck in the crashed
953 * kernel.
954 */
955 if (is_kdump_kernel())
956 return false;
957
958 return has_cpuid_feature(entry, scope);
959}
960
1b3ccf4b 961static bool __meltdown_safe = true;
ea1e3de8
WD		 962static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
963
964static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
d3aec8a2 965 int scope)
ea1e3de8 966{
be5b2998
SP		 967 /* List of CPUs that are not vulnerable and don't need KPTI */
968 static const struct midr_range kpti_safe_list[] = {
969 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
970 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
2a355ec2
WD		 971 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
972 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
973 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
974 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
975 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
976 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
0ecc471a 977 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
71c751f2 978 { /* sentinel */ }
be5b2998 979 };
a111b7c0 980 char const *str = "kpti command line option";
1b3ccf4b
JL		 981 bool meltdown_safe;
982
983 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
984
985 /* Defer to CPU feature registers */
986 if (has_cpuid_feature(entry, scope))
987 meltdown_safe = true;
988
989 if (!meltdown_safe)
990 __meltdown_safe = false;
179a56f6 991
6dc52b15
MZ		 992 /*
993 * For reasons that aren't entirely clear, enabling KPTI on Cavium
994 * ThunderX leads to apparent I-cache corruption of kernel text, which
995 * ends as well as you might imagine. Don't even try.
996 */
997 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
998 str = "ARM64_WORKAROUND_CAVIUM_27456";
999 __kpti_forced = -1;
1000 }
1001
1b3ccf4b
JL		 1002 /* Useful for KASLR robustness */
1003 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && kaslr_offset() > 0) {
1004 if (!__kpti_forced) {
1005 str = "KASLR";
1006 __kpti_forced = 1;
1007 }
1008 }
1009
a111b7c0
JP		 1010 if (cpu_mitigations_off() && !__kpti_forced) {
1011 str = "mitigations=off";
1012 __kpti_forced = -1;
1013 }
1014
1b3ccf4b
JL		 1015 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1016 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1017 return false;
1018 }
1019
6dc52b15 1020 /* Forced? */
ea1e3de8 1021 if (__kpti_forced) {
6dc52b15
MZ		 1022 pr_info_once("kernel page table isolation forced %s by %s\n",
1023 __kpti_forced > 0 ? "ON" : "OFF", str);
ea1e3de8
WD		 1024 return __kpti_forced > 0;
1025 }
1026
1b3ccf4b 1027 return !meltdown_safe;
ea1e3de8
WD		 1028}
1029
1b3ccf4b 1030#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
c0cda3b8
DM		 1031static void
1032kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
f992b4df
WD		 1033{
1034 typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1035 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1036 kpti_remap_fn *remap_fn;
1037
1038 static bool kpti_applied = false;
1039 int cpu = smp_processor_id();
1040
b89d82ef
WD		 1041 /*
1042 * We don't need to rewrite the page-tables if either we've done
1043 * it already or we have KASLR enabled and therefore have not
1044 * created any global mappings at all.
1045 */
1046 if (kpti_applied || kaslr_offset() > 0)
c0cda3b8 1047 return;
f992b4df
WD		 1048
1049 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
1050
1051 cpu_install_idmap();
1052 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1053 cpu_uninstall_idmap();
1054
1055 if (!cpu)
1056 kpti_applied = true;
1057
c0cda3b8 1058 return;
f992b4df 1059}
1b3ccf4b
JL		 1060#else
1061static void
1062kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1063{
1064}
1065#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
f992b4df 1066
ea1e3de8
WD		 1067static int __init parse_kpti(char *str)
1068{
1069 bool enabled;
1070 int ret = strtobool(str, &enabled);
1071
1072 if (ret)
1073 return ret;
1074
1075 __kpti_forced = enabled ? 1 : -1;
1076 return 0;
1077}
b5b7dd64 1078early_param("kpti", parse_kpti);
ea1e3de8 1079
05abb595
SP		 1080#ifdef CONFIG_ARM64_HW_AFDBM
1081static inline void __cpu_enable_hw_dbm(void)
1082{
1083 u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1084
1085 write_sysreg(tcr, tcr_el1);
1086 isb();
1087}
1088
ece1397c
SP		 1089static bool cpu_has_broken_dbm(void)
1090{
1091 /* List of CPUs which have broken DBM support. */
1092 static const struct midr_range cpus[] = {
1093#ifdef CONFIG_ARM64_ERRATUM_1024718
1094 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0
1095#endif
1096 {},
1097 };
1098
1099 return is_midr_in_range_list(read_cpuid_id(), cpus);
1100}
1101
05abb595
SP		 1102static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1103{
ece1397c
SP		 1104 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1105 !cpu_has_broken_dbm();
05abb595
SP		 1106}
1107
1108static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1109{
1110 if (cpu_can_use_dbm(cap))
1111 __cpu_enable_hw_dbm();
1112}
1113
1114static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1115 int __unused)
1116{
1117 static bool detected = false;
1118 /*
1119 * DBM is a non-conflicting feature. i.e, the kernel can safely
1120 * run a mix of CPUs with and without the feature. So, we
1121 * unconditionally enable the capability to allow any late CPU
1122 * to use the feature. We only enable the control bits on the
1123 * CPU, if it actually supports.
1124 *
1125 * We have to make sure we print the "feature" detection only
1126 * when at least one CPU actually uses it. So check if this CPU
1127 * can actually use it and print the message exactly once.
1128 *
1129 * This is safe as all CPUs (including secondary CPUs - due to the
1130 * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1131 * goes through the "matches" check exactly once. Also if a CPU
1132 * matches the criteria, it is guaranteed that the CPU will turn
1133 * the DBM on, as the capability is unconditionally enabled.
1134 */
1135 if (!detected && cpu_can_use_dbm(cap)) {
1136 detected = true;
1137 pr_info("detected: Hardware dirty bit management\n");
1138 }
1139
1140 return true;
1141}
1142
1143#endif
1144
12eb3691
WD		 1145#ifdef CONFIG_ARM64_VHE
1146static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1147{
1148 return is_kernel_in_hyp_mode();
1149}
1150
c0cda3b8 1151static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
6d99b689
JM		 1152{
1153 /*
1154 * Copy register values that aren't redirected by hardware.
1155 *
1156 * Before code patching, we only set tpidr_el1, all CPUs need to copy
1157 * this value to tpidr_el2 before we patch the code. Once we've done
1158 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1159 * do anything here.
1160 */
e9ab7a2e 1161 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
6d99b689 1162 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
6d99b689 1163}
12eb3691 1164#endif
6d99b689 1165
e48d53a9
MZ		 1166static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1167{
1168 u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1169
1170 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1171 WARN_ON(val & (7 << 27 | 7 << 21));
1172}
1173
8f04e8e6
WD		 1174#ifdef CONFIG_ARM64_SSBD
1175static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
1176{
1177 if (user_mode(regs))
1178 return 1;
1179
74e24828 1180 if (instr & BIT(PSTATE_Imm_shift))
8f04e8e6
WD		 1181 regs->pstate |= PSR_SSBS_BIT;
1182 else
1183 regs->pstate &= ~PSR_SSBS_BIT;
1184
1185 arm64_skip_faulting_instruction(regs, 4);
1186 return 0;
1187}
1188
1189static struct undef_hook ssbs_emulation_hook = {
74e24828
SP		 1190 .instr_mask = ~(1U << PSTATE_Imm_shift),
1191 .instr_val = 0xd500401f | PSTATE_SSBS,
8f04e8e6
WD		 1192 .fn = ssbs_emulation_handler,
1193};
1194
1195static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
1196{
1197 static bool undef_hook_registered = false;
1198 static DEFINE_SPINLOCK(hook_lock);
1199
1200 spin_lock(&hook_lock);
1201 if (!undef_hook_registered) {
1202 register_undef_hook(&ssbs_emulation_hook);
1203 undef_hook_registered = true;
1204 }
1205 spin_unlock(&hook_lock);
1206
1207 if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
1208 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
1209 arm64_set_ssbd_mitigation(false);
1210 } else {
1211 arm64_set_ssbd_mitigation(true);
1212 }
1213}
1214#endif /* CONFIG_ARM64_SSBD */
1215
b8925ee2
WD		 1216#ifdef CONFIG_ARM64_PAN
1217static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1218{
1219 /*
1220 * We modify PSTATE. This won't work from irq context as the PSTATE
1221 * is discarded once we return from the exception.
1222 */
1223 WARN_ON_ONCE(in_interrupt());
1224
1225 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1226 asm(SET_PSTATE_PAN(1));
1227}
1228#endif /* CONFIG_ARM64_PAN */
1229
1230#ifdef CONFIG_ARM64_RAS_EXTN
1231static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1232{
1233 /* Firmware may have left a deferred SError in this register. */
1234 write_sysreg_s(0, SYS_DISR_EL1);
1235}
1236#endif /* CONFIG_ARM64_RAS_EXTN */
1237
6984eb47 1238#ifdef CONFIG_ARM64_PTR_AUTH
75031975
MR		 1239static void cpu_enable_address_auth(struct arm64_cpu_capabilities const *cap)
1240{
1241 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ENIA | SCTLR_ELx_ENIB |
1242 SCTLR_ELx_ENDA | SCTLR_ELx_ENDB);
1243}
6984eb47
MR		 1244#endif /* CONFIG_ARM64_PTR_AUTH */
1245
b90d2b22 1246#ifdef CONFIG_ARM64_PSEUDO_NMI
bc3c03cc
JT		 1247static bool enable_pseudo_nmi;
1248
1249static int __init early_enable_pseudo_nmi(char *p)
1250{
1251 return strtobool(p, &enable_pseudo_nmi);
1252}
1253early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1254
b90d2b22
JT		 1255static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1256 int scope)
1257{
bc3c03cc 1258 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
b90d2b22
JT		 1259}
1260#endif
1261
359b7064 1262static const struct arm64_cpu_capabilities arm64_features[] = {
94a9e04a
MZ		 1263 {
1264 .desc = "GIC system register CPU interface",
1265 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
c9bfdf73 1266 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
963fcd40 1267 .matches = has_useable_gicv3_cpuif,
da8d02d1
SP		 1268 .sys_reg = SYS_ID_AA64PFR0_EL1,
1269 .field_pos = ID_AA64PFR0_GIC_SHIFT,
ff96f7bc 1270 .sign = FTR_UNSIGNED,
18ffa046 1271 .min_field_value = 1,
94a9e04a 1272 },
338d4f49
JM		 1273#ifdef CONFIG_ARM64_PAN
1274 {
1275 .desc = "Privileged Access Never",
1276 .capability = ARM64_HAS_PAN,
5b4747c5 1277 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
da8d02d1
SP		 1278 .matches = has_cpuid_feature,
1279 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1280 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
ff96f7bc 1281 .sign = FTR_UNSIGNED,
338d4f49 1282 .min_field_value = 1,
c0cda3b8 1283 .cpu_enable = cpu_enable_pan,
338d4f49
JM		 1284 },
1285#endif /* CONFIG_ARM64_PAN */
2e94da13
WD		 1286#if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
1287 {
1288 .desc = "LSE atomic instructions",
1289 .capability = ARM64_HAS_LSE_ATOMICS,
5b4747c5 1290 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
da8d02d1
SP		 1291 .matches = has_cpuid_feature,
1292 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1293 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
ff96f7bc 1294 .sign = FTR_UNSIGNED,
2e94da13
WD		 1295 .min_field_value = 2,
1296 },
1297#endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
d5370f75
WD		 1298 {
1299 .desc = "Software prefetching using PRFM",
1300 .capability = ARM64_HAS_NO_HW_PREFETCH,
5c137714 1301 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
d5370f75
WD		 1302 .matches = has_no_hw_prefetch,
1303 },
57f4959b
JM		 1304#ifdef CONFIG_ARM64_UAO
1305 {
1306 .desc = "User Access Override",
1307 .capability = ARM64_HAS_UAO,
5b4747c5 1308 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
57f4959b
JM		 1309 .matches = has_cpuid_feature,
1310 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1311 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1312 .min_field_value = 1,
c8b06e3f
JM		 1313 /*
1314 * We rely on stop_machine() calling uao_thread_switch() to set
1315 * UAO immediately after patching.
1316 */
57f4959b
JM		 1317 },
1318#endif /* CONFIG_ARM64_UAO */
70544196
JM		 1319#ifdef CONFIG_ARM64_PAN
1320 {
1321 .capability = ARM64_ALT_PAN_NOT_UAO,
5b4747c5 1322 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
70544196
JM		 1323 .matches = cpufeature_pan_not_uao,
1324 },
1325#endif /* CONFIG_ARM64_PAN */
830dcc9f 1326#ifdef CONFIG_ARM64_VHE
d88701be
MZ		 1327 {
1328 .desc = "Virtualization Host Extensions",
1329 .capability = ARM64_HAS_VIRT_HOST_EXTN,
830dcc9f 1330 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
d88701be 1331 .matches = runs_at_el2,
c0cda3b8 1332 .cpu_enable = cpu_copy_el2regs,
d88701be 1333 },
830dcc9f 1334#endif /* CONFIG_ARM64_VHE */
042446a3
SP		 1335 {
1336 .desc = "32-bit EL0 Support",
1337 .capability = ARM64_HAS_32BIT_EL0,
5b4747c5 1338 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
042446a3
SP		 1339 .matches = has_cpuid_feature,
1340 .sys_reg = SYS_ID_AA64PFR0_EL1,
1341 .sign = FTR_UNSIGNED,
1342 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1343 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1344 },
ea1e3de8 1345 {
179a56f6 1346 .desc = "Kernel page table isolation (KPTI)",
ea1e3de8 1347 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
d3aec8a2
SP		 1348 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1349 /*
1350 * The ID feature fields below are used to indicate that
1351 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1352 * more details.
1353 */
1354 .sys_reg = SYS_ID_AA64PFR0_EL1,
1355 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1356 .min_field_value = 1,
ea1e3de8 1357 .matches = unmap_kernel_at_el0,
c0cda3b8 1358 .cpu_enable = kpti_install_ng_mappings,
ea1e3de8 1359 },
82e0191a
SP		 1360 {
1361 /* FP/SIMD is not implemented */
1362 .capability = ARM64_HAS_NO_FPSIMD,
5b4747c5 1363 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
82e0191a
SP		 1364 .min_field_value = 0,
1365 .matches = has_no_fpsimd,
1366 },
d50e071f
RM		 1367#ifdef CONFIG_ARM64_PMEM
1368 {
1369 .desc = "Data cache clean to Point of Persistence",
1370 .capability = ARM64_HAS_DCPOP,
5b4747c5 1371 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
d50e071f
RM		 1372 .matches = has_cpuid_feature,
1373 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1374 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1375 .min_field_value = 1,
1376 },
b9585f53
AM		 1377 {
1378 .desc = "Data cache clean to Point of Deep Persistence",
1379 .capability = ARM64_HAS_DCPODP,
1380 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1381 .matches = has_cpuid_feature,
1382 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1383 .sign = FTR_UNSIGNED,
1384 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1385 .min_field_value = 2,
1386 },
d50e071f 1387#endif
43994d82
DM		 1388#ifdef CONFIG_ARM64_SVE
1389 {
1390 .desc = "Scalable Vector Extension",
5b4747c5 1391 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
43994d82 1392 .capability = ARM64_SVE,
43994d82
DM		 1393 .sys_reg = SYS_ID_AA64PFR0_EL1,
1394 .sign = FTR_UNSIGNED,
1395 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1396 .min_field_value = ID_AA64PFR0_SVE,
1397 .matches = has_cpuid_feature,
c0cda3b8 1398 .cpu_enable = sve_kernel_enable,
43994d82
DM		 1399 },
1400#endif /* CONFIG_ARM64_SVE */
64c02720
XX		 1401#ifdef CONFIG_ARM64_RAS_EXTN
1402 {
1403 .desc = "RAS Extension Support",
1404 .capability = ARM64_HAS_RAS_EXTN,
5b4747c5 1405 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
64c02720
XX		 1406 .matches = has_cpuid_feature,
1407 .sys_reg = SYS_ID_AA64PFR0_EL1,
1408 .sign = FTR_UNSIGNED,
1409 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1410 .min_field_value = ID_AA64PFR0_RAS_V1,
c0cda3b8 1411 .cpu_enable = cpu_clear_disr,
64c02720
XX		 1412 },
1413#endif /* CONFIG_ARM64_RAS_EXTN */
6ae4b6e0
SD		 1414 {
1415 .desc = "Data cache clean to the PoU not required for I/D coherence",
1416 .capability = ARM64_HAS_CACHE_IDC,
5b4747c5 1417 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
6ae4b6e0 1418 .matches = has_cache_idc,
1602df02 1419 .cpu_enable = cpu_emulate_effective_ctr,
6ae4b6e0
SD		 1420 },
1421 {
1422 .desc = "Instruction cache invalidation not required for I/D coherence",
1423 .capability = ARM64_HAS_CACHE_DIC,
5b4747c5 1424 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
6ae4b6e0
SD		 1425 .matches = has_cache_dic,
1426 },
e48d53a9
MZ		 1427 {
1428 .desc = "Stage-2 Force Write-Back",
1429 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1430 .capability = ARM64_HAS_STAGE2_FWB,
1431 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1432 .sign = FTR_UNSIGNED,
1433 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
1434 .min_field_value = 1,
1435 .matches = has_cpuid_feature,
1436 .cpu_enable = cpu_has_fwb,
1437 },
05abb595
SP		 1438#ifdef CONFIG_ARM64_HW_AFDBM
1439 {
1440 /*
1441 * Since we turn this on always, we don't want the user to
1442 * think that the feature is available when it may not be.
1443 * So hide the description.
1444 *
1445 * .desc = "Hardware pagetable Dirty Bit Management",
1446 *
1447 */
1448 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1449 .capability = ARM64_HW_DBM,
1450 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1451 .sign = FTR_UNSIGNED,
1452 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
1453 .min_field_value = 2,
1454 .matches = has_hw_dbm,
1455 .cpu_enable = cpu_enable_hw_dbm,
1456 },
1457#endif
86d0dd34
AB		 1458 {
1459 .desc = "CRC32 instructions",
1460 .capability = ARM64_HAS_CRC32,
1461 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1462 .matches = has_cpuid_feature,
1463 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1464 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
1465 .min_field_value = 1,
1466 },
4f9f4964 1467#ifdef CONFIG_ARM64_SSBD
d71be2b6
WD		 1468 {
1469 .desc = "Speculative Store Bypassing Safe (SSBS)",
1470 .capability = ARM64_SSBS,
1471 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1472 .matches = has_cpuid_feature,
1473 .sys_reg = SYS_ID_AA64PFR1_EL1,
1474 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
1475 .sign = FTR_UNSIGNED,
1476 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
8f04e8e6 1477 .cpu_enable = cpu_enable_ssbs,
d71be2b6 1478 },
5ffdfaed
VM		 1479#endif
1480#ifdef CONFIG_ARM64_CNP
1481 {
1482 .desc = "Common not Private translations",
1483 .capability = ARM64_HAS_CNP,
1484 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1485 .matches = has_useable_cnp,
1486 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1487 .sign = FTR_UNSIGNED,
1488 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
1489 .min_field_value = 1,
1490 .cpu_enable = cpu_enable_cnp,
1491 },
8f04e8e6 1492#endif
bd4fb6d2
WD		 1493 {
1494 .desc = "Speculation barrier (SB)",
1495 .capability = ARM64_HAS_SB,
1496 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1497 .matches = has_cpuid_feature,
1498 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1499 .field_pos = ID_AA64ISAR1_SB_SHIFT,
1500 .sign = FTR_UNSIGNED,
1501 .min_field_value = 1,
1502 },
6984eb47
MR		 1503#ifdef CONFIG_ARM64_PTR_AUTH
1504 {
1505 .desc = "Address authentication (architected algorithm)",
1506 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
1507 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1508 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1509 .sign = FTR_UNSIGNED,
1510 .field_pos = ID_AA64ISAR1_APA_SHIFT,
1511 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
1512 .matches = has_cpuid_feature,
a56005d3 1513 .cpu_enable = cpu_enable_address_auth,
6984eb47
MR		 1514 },
1515 {
1516 .desc = "Address authentication (IMP DEF algorithm)",
1517 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
1518 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1519 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1520 .sign = FTR_UNSIGNED,
1521 .field_pos = ID_AA64ISAR1_API_SHIFT,
1522 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
1523 .matches = has_cpuid_feature,
75031975 1524 .cpu_enable = cpu_enable_address_auth,
6984eb47
MR		 1525 },
1526 {
1527 .desc = "Generic authentication (architected algorithm)",
1528 .capability = ARM64_HAS_GENERIC_AUTH_ARCH,
1529 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1530 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1531 .sign = FTR_UNSIGNED,
1532 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
1533 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
1534 .matches = has_cpuid_feature,
1535 },
1536 {
1537 .desc = "Generic authentication (IMP DEF algorithm)",
1538 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
1539 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1540 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1541 .sign = FTR_UNSIGNED,
1542 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
1543 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
1544 .matches = has_cpuid_feature,
1545 },
6984eb47 1546#endif /* CONFIG_ARM64_PTR_AUTH */
b90d2b22
JT		 1547#ifdef CONFIG_ARM64_PSEUDO_NMI
1548 {
1549 /*
1550 * Depends on having GICv3
1551 */
1552 .desc = "IRQ priority masking",
1553 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
1554 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1555 .matches = can_use_gic_priorities,
1556 .sys_reg = SYS_ID_AA64PFR0_EL1,
1557 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1558 .sign = FTR_UNSIGNED,
1559 .min_field_value = 1,
1560 },
1561#endif
359b7064
MZ		 1562 {},
1563};
1564
1e013d06
WD		 1565#define HWCAP_CPUID_MATCH(reg, field, s, min_value) \
1566 .matches = has_cpuid_feature, \
1567 .sys_reg = reg, \
1568 .field_pos = field, \
1569 .sign = s, \
1570 .min_field_value = min_value,
1571
1572#define __HWCAP_CAP(name, cap_type, cap) \
1573 .desc = name, \
1574 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
1575 .hwcap_type = cap_type, \
1576 .hwcap = cap, \
1577
1578#define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \
1579 { \
1580 __HWCAP_CAP(#cap, cap_type, cap) \
1581 HWCAP_CPUID_MATCH(reg, field, s, min_value) \
37b01d53
SP		 1582 }
1583
1e013d06
WD		 1584#define HWCAP_MULTI_CAP(list, cap_type, cap) \
1585 { \
1586 __HWCAP_CAP(#cap, cap_type, cap) \
1587 .matches = cpucap_multi_entry_cap_matches, \
1588 .match_list = list, \
1589 }
1590
1591#ifdef CONFIG_ARM64_PTR_AUTH
1592static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
1593 {
1594 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
1595 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
1596 },
1597 {
1598 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
1599 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
1600 },
1601 {},
1602};
1603
1604static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
1605 {
1606 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
1607 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
1608 },
1609 {
1610 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
1611 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
1612 },
1613 {},
1614};
1615#endif
1616
f3efb675 1617static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
aaba098f
AM		 1618 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
1619 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
1620 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
1621 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
1622 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
1623 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
1624 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
1625 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
1626 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
1627 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
1628 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
1629 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
1630 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
1631 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
1632 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
1633 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
1634 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
1635 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
1636 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
1637 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
671db581 1638 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
aaba098f
AM		 1639 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
1640 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
1641 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
1642 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
1643 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
1644 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
43994d82 1645#ifdef CONFIG_ARM64_SVE
aaba098f 1646 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
06a916fe
DM		 1647 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
1648 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
1649 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
1650 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
1651 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
1652 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
43994d82 1653#endif
aaba098f 1654 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
75031975 1655#ifdef CONFIG_ARM64_PTR_AUTH
aaba098f
AM		 1656 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
1657 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
75031975 1658#endif
75283501
SP		 1659 {},
1660};
1661
1662static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
37b01d53 1663#ifdef CONFIG_COMPAT
ff96f7bc
SP		 1664 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
1665 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
1666 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
1667 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
1668 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
37b01d53
SP		 1669#endif
1670 {},
1671};
1672
f3efb675 1673static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 1674{
1675 switch (cap->hwcap_type) {
1676 case CAP_HWCAP:
aaba098f 1677 cpu_set_feature(cap->hwcap);
37b01d53
SP		 1678 break;
1679#ifdef CONFIG_COMPAT
1680 case CAP_COMPAT_HWCAP:
1681 compat_elf_hwcap |= (u32)cap->hwcap;
1682 break;
1683 case CAP_COMPAT_HWCAP2:
1684 compat_elf_hwcap2 |= (u32)cap->hwcap;
1685 break;
1686#endif
1687 default:
1688 WARN_ON(1);
1689 break;
1690 }
1691}
1692
1693/* Check if we have a particular HWCAP enabled */
f3efb675 1694static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 1695{
1696 bool rc;
1697
1698 switch (cap->hwcap_type) {
1699 case CAP_HWCAP:
aaba098f 1700 rc = cpu_have_feature(cap->hwcap);
37b01d53
SP		 1701 break;
1702#ifdef CONFIG_COMPAT
1703 case CAP_COMPAT_HWCAP:
1704 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1705 break;
1706 case CAP_COMPAT_HWCAP2:
1707 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1708 break;
1709#endif
1710 default:
1711 WARN_ON(1);
1712 rc = false;
1713 }
1714
1715 return rc;
1716}
1717
75283501 1718static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
37b01d53 1719{
77c97b4e 1720 /* We support emulation of accesses to CPU ID feature registers */
aaba098f 1721 cpu_set_named_feature(CPUID);
75283501 1722 for (; hwcaps->matches; hwcaps++)
143ba05d 1723 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
75283501 1724 cap_set_elf_hwcap(hwcaps);
37b01d53
SP		 1725}
1726
606f8e7b 1727static void update_cpu_capabilities(u16 scope_mask)
67948af4 1728{
606f8e7b 1729 int i;
67948af4
SP		 1730 const struct arm64_cpu_capabilities *caps;
1731
cce360b5 1732 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
606f8e7b
SP		 1733 for (i = 0; i < ARM64_NCAPS; i++) {
1734 caps = cpu_hwcaps_ptrs[i];
1735 if (!caps || !(caps->type & scope_mask) ||
1736 cpus_have_cap(caps->capability) ||
cce360b5 1737 !caps->matches(caps, cpucap_default_scope(caps)))
359b7064
MZ		 1738 continue;
1739
606f8e7b
SP		 1740 if (caps->desc)
1741 pr_info("detected: %s\n", caps->desc);
75283501 1742 cpus_set_cap(caps->capability);
0ceb0d56
DT		 1743
1744 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
1745 set_bit(caps->capability, boot_capabilities);
359b7064 1746 }
ce8b602c
SP		 1747}
1748
0b587c84
SP		 1749/*
1750 * Enable all the available capabilities on this CPU. The capabilities
1751 * with BOOT_CPU scope are handled separately and hence skipped here.
1752 */
1753static int cpu_enable_non_boot_scope_capabilities(void *__unused)
ed478b3f 1754{
0b587c84
SP		 1755 int i;
1756 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
ed478b3f 1757
0b587c84
SP		 1758 for_each_available_cap(i) {
1759 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
1760
1761 if (WARN_ON(!cap))
1762 continue;
c0cda3b8 1763
0b587c84
SP		 1764 if (!(cap->type & non_boot_scope))
1765 continue;
1766
1767 if (cap->cpu_enable)
1768 cap->cpu_enable(cap);
1769 }
c0cda3b8
DM		 1770 return 0;
1771}
1772
ce8b602c 1773/*
dbb4e152
SP		 1774 * Run through the enabled capabilities and enable() it on all active
1775 * CPUs
ce8b602c 1776 */
0b587c84 1777static void __init enable_cpu_capabilities(u16 scope_mask)
ce8b602c 1778{
0b587c84
SP		 1779 int i;
1780 const struct arm64_cpu_capabilities *caps;
1781 bool boot_scope;
1782
cce360b5 1783 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
0b587c84 1784 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
63a1e1c9 1785
0b587c84
SP		 1786 for (i = 0; i < ARM64_NCAPS; i++) {
1787 unsigned int num;
1788
1789 caps = cpu_hwcaps_ptrs[i];
1790 if (!caps || !(caps->type & scope_mask))
1791 continue;
1792 num = caps->capability;
1793 if (!cpus_have_cap(num))
63a1e1c9
MR		 1794 continue;
1795
1796 /* Ensure cpus_have_const_cap(num) works */
1797 static_branch_enable(&cpu_hwcap_keys[num]);
1798
0b587c84 1799 if (boot_scope && caps->cpu_enable)
2a6dcb2b 1800 /*
fd9d63da
SP		 1801 * Capabilities with SCOPE_BOOT_CPU scope are finalised
1802 * before any secondary CPU boots. Thus, each secondary
1803 * will enable the capability as appropriate via
1804 * check_local_cpu_capabilities(). The only exception is
1805 * the boot CPU, for which the capability must be
1806 * enabled here. This approach avoids costly
1807 * stop_machine() calls for this case.
2a6dcb2b 1808 */
0b587c84 1809 caps->cpu_enable(caps);
63a1e1c9 1810 }
dbb4e152 1811
0b587c84
SP		 1812 /*
1813 * For all non-boot scope capabilities, use stop_machine()
1814 * as it schedules the work allowing us to modify PSTATE,
1815 * instead of on_each_cpu() which uses an IPI, giving us a
1816 * PSTATE that disappears when we return.
1817 */
1818 if (!boot_scope)
1819 stop_machine(cpu_enable_non_boot_scope_capabilities,
1820 NULL, cpu_online_mask);
ed478b3f
SP		 1821}
1822
eaac4d83
SP		 1823/*
1824 * Run through the list of capabilities to check for conflicts.
1825 * If the system has already detected a capability, take necessary
1826 * action on this CPU.
1827 *
1828 * Returns "false" on conflicts.
1829 */
606f8e7b 1830static bool verify_local_cpu_caps(u16 scope_mask)
eaac4d83 1831{
606f8e7b 1832 int i;
eaac4d83 1833 bool cpu_has_cap, system_has_cap;
606f8e7b 1834 const struct arm64_cpu_capabilities *caps;
eaac4d83 1835
cce360b5
SP		 1836 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1837
606f8e7b
SP		 1838 for (i = 0; i < ARM64_NCAPS; i++) {
1839 caps = cpu_hwcaps_ptrs[i];
1840 if (!caps || !(caps->type & scope_mask))
cce360b5
SP		 1841 continue;
1842
ba7d9233 1843 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
eaac4d83
SP		 1844 system_has_cap = cpus_have_cap(caps->capability);
1845
1846 if (system_has_cap) {
1847 /*
1848 * Check if the new CPU misses an advertised feature,
1849 * which is not safe to miss.
1850 */
1851 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
1852 break;
1853 /*
1854 * We have to issue cpu_enable() irrespective of
1855 * whether the CPU has it or not, as it is enabeld
1856 * system wide. It is upto the call back to take
1857 * appropriate action on this CPU.
1858 */
1859 if (caps->cpu_enable)
1860 caps->cpu_enable(caps);
1861 } else {
1862 /*
1863 * Check if the CPU has this capability if it isn't
1864 * safe to have when the system doesn't.
1865 */
1866 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
1867 break;
1868 }
1869 }
1870
606f8e7b 1871 if (i < ARM64_NCAPS) {
eaac4d83
SP		 1872 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
1873 smp_processor_id(), caps->capability,
1874 caps->desc, system_has_cap, cpu_has_cap);
1875 return false;
1876 }
1877
1878 return true;
1879}
1880
dbb4e152 1881/*
13f417f3
SP		 1882 * Check for CPU features that are used in early boot
1883 * based on the Boot CPU value.
dbb4e152 1884 */
13f417f3 1885static void check_early_cpu_features(void)
dbb4e152 1886{
13f417f3 1887 verify_cpu_asid_bits();
fd9d63da
SP		 1888 /*
1889 * Early features are used by the kernel already. If there
1890 * is a conflict, we cannot proceed further.
1891 */
1892 if (!verify_local_cpu_caps(SCOPE_BOOT_CPU))
1893 cpu_panic_kernel();
dbb4e152 1894}
1c076303 1895
75283501
SP		 1896static void
1897verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1898{
1899
92406f0c
SP		 1900 for (; caps->matches; caps++)
1901 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
75283501
SP		 1902 pr_crit("CPU%d: missing HWCAP: %s\n",
1903 smp_processor_id(), caps->desc);
1904 cpu_die_early();
1905 }
75283501
SP		 1906}
1907
2e0f2478
DM		 1908static void verify_sve_features(void)
1909{
1910 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
1911 u64 zcr = read_zcr_features();
1912
1913 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
1914 unsigned int len = zcr & ZCR_ELx_LEN_MASK;
1915
1916 if (len < safe_len || sve_verify_vq_map()) {
d06b76be 1917 pr_crit("CPU%d: SVE: vector length support mismatch\n",
2e0f2478
DM		 1918 smp_processor_id());
1919 cpu_die_early();
1920 }
1921
1922 /* Add checks on other ZCR bits here if necessary */
1923}
1924
1e89baed 1925
dbb4e152
SP		 1926/*
1927 * Run through the enabled system capabilities and enable() it on this CPU.
1928 * The capabilities were decided based on the available CPUs at the boot time.
1929 * Any new CPU should match the system wide status of the capability. If the
1930 * new CPU doesn't have a capability which the system now has enabled, we
1931 * cannot do anything to fix it up and could cause unexpected failures. So
1932 * we park the CPU.
1933 */
c47a1900 1934static void verify_local_cpu_capabilities(void)
dbb4e152 1935{
fd9d63da
SP		 1936 /*
1937 * The capabilities with SCOPE_BOOT_CPU are checked from
1938 * check_early_cpu_features(), as they need to be verified
1939 * on all secondary CPUs.
1940 */
1941 if (!verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU))
600b9c91 1942 cpu_die_early();
ed478b3f 1943
c47a1900 1944 verify_local_elf_hwcaps(arm64_elf_hwcaps);
2e0f2478 1945
c47a1900
SP		 1946 if (system_supports_32bit_el0())
1947 verify_local_elf_hwcaps(compat_elf_hwcaps);
2e0f2478
DM		 1948
1949 if (system_supports_sve())
1950 verify_sve_features();
c47a1900 1951}
dbb4e152 1952
c47a1900
SP		 1953void check_local_cpu_capabilities(void)
1954{
1955 /*
1956 * All secondary CPUs should conform to the early CPU features
1957 * in use by the kernel based on boot CPU.
1958 */
13f417f3
SP		 1959 check_early_cpu_features();
1960
dbb4e152 1961 /*
c47a1900 1962 * If we haven't finalised the system capabilities, this CPU gets
fbd890b9 1963 * a chance to update the errata work arounds and local features.
c47a1900
SP		 1964 * Otherwise, this CPU should verify that it has all the system
1965 * advertised capabilities.
dbb4e152 1966 */
ed478b3f
SP		 1967 if (!sys_caps_initialised)
1968 update_cpu_capabilities(SCOPE_LOCAL_CPU);
1969 else
c47a1900 1970 verify_local_cpu_capabilities();
359b7064
MZ		 1971}
1972
fd9d63da
SP		 1973static void __init setup_boot_cpu_capabilities(void)
1974{
1975 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
1976 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
1977 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
1978 enable_cpu_capabilities(SCOPE_BOOT_CPU);
1979}
1980
63a1e1c9
MR		 1981DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
1982EXPORT_SYMBOL(arm64_const_caps_ready);
1983
1984static void __init mark_const_caps_ready(void)
1985{
1986 static_branch_enable(&arm64_const_caps_ready);
1987}
1988
f7bfc14a 1989bool this_cpu_has_cap(unsigned int n)
8f413758 1990{
f7bfc14a
SP		 1991 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
1992 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
1993
1994 if (cap)
1995 return cap->matches(cap, SCOPE_LOCAL_CPU);
1996 }
1997
1998 return false;
8f413758
MZ		 1999}
2000
aec0bff7
AM		 2001void cpu_set_feature(unsigned int num)
2002{
2003 WARN_ON(num >= MAX_CPU_FEATURES);
2004 elf_hwcap |= BIT(num);
2005}
2006EXPORT_SYMBOL_GPL(cpu_set_feature);
2007
2008bool cpu_have_feature(unsigned int num)
2009{
2010 WARN_ON(num >= MAX_CPU_FEATURES);
2011 return elf_hwcap & BIT(num);
2012}
2013EXPORT_SYMBOL_GPL(cpu_have_feature);
2014
2015unsigned long cpu_get_elf_hwcap(void)
2016{
2017 /*
2018 * We currently only populate the first 32 bits of AT_HWCAP. Please
2019 * note that for userspace compatibility we guarantee that bits 62
2020 * and 63 will always be returned as 0.
2021 */
2022 return lower_32_bits(elf_hwcap);
2023}
2024
2025unsigned long cpu_get_elf_hwcap2(void)
2026{
2027 return upper_32_bits(elf_hwcap);
2028}
2029
ed478b3f
SP		 2030static void __init setup_system_capabilities(void)
2031{
2032 /*
2033 * We have finalised the system-wide safe feature
2034 * registers, finalise the capabilities that depend
fd9d63da
SP		 2035 * on it. Also enable all the available capabilities,
2036 * that are not enabled already.
ed478b3f
SP		 2037 */
2038 update_cpu_capabilities(SCOPE_SYSTEM);
fd9d63da 2039 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
ed478b3f
SP		 2040}
2041
9cdf8ec4 2042void __init setup_cpu_features(void)
359b7064 2043{
9cdf8ec4 2044 u32 cwg;
9cdf8ec4 2045
ed478b3f 2046 setup_system_capabilities();
63a1e1c9 2047 mark_const_caps_ready();
75283501 2048 setup_elf_hwcaps(arm64_elf_hwcaps);
643d703d
SP		 2049
2050 if (system_supports_32bit_el0())
2051 setup_elf_hwcaps(compat_elf_hwcaps);
dbb4e152 2052
2e6f549f
KC		 2053 if (system_uses_ttbr0_pan())
2054 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
2055
2e0f2478 2056 sve_setup();
94b07c1f 2057 minsigstksz_setup();
2e0f2478 2058
dbb4e152
SP		 2059 /* Advertise that we have computed the system capabilities */
2060 set_sys_caps_initialised();
2061
9cdf8ec4
SP		 2062 /*
2063 * Check for sane CTR_EL0.CWG value.
2064 */
2065 cwg = cache_type_cwg();
9cdf8ec4 2066 if (!cwg)
ebc7e21e
CM		 2067 pr_warn("No Cache Writeback Granule information, assuming %d\n",
2068 ARCH_DMA_MINALIGN);
359b7064 2069}
70544196
JM		 2070
2071static bool __maybe_unused
92406f0c 2072cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
70544196 2073{
a4023f68 2074 return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
70544196 2075}
77c97b4e 2076
5ffdfaed
VM		 2077static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
2078{
2079 cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
2080}
2081
77c97b4e
SP		 2082/*
2083 * We emulate only the following system register space.
2084 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
2085 * See Table C5-6 System instruction encodings for System register accesses,
2086 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
2087 */
2088static inline bool __attribute_const__ is_emulated(u32 id)
2089{
2090 return (sys_reg_Op0(id) == 0x3 &&
2091 sys_reg_CRn(id) == 0x0 &&
2092 sys_reg_Op1(id) == 0x0 &&
2093 (sys_reg_CRm(id) == 0 ||
2094 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
2095}
2096
2097/*
2098 * With CRm == 0, reg should be one of :
2099 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
2100 */
2101static inline int emulate_id_reg(u32 id, u64 *valp)
2102{
2103 switch (id) {
2104 case SYS_MIDR_EL1:
2105 *valp = read_cpuid_id();
2106 break;
2107 case SYS_MPIDR_EL1:
2108 *valp = SYS_MPIDR_SAFE_VAL;
2109 break;
2110 case SYS_REVIDR_EL1:
2111 /* IMPLEMENTATION DEFINED values are emulated with 0 */
2112 *valp = 0;
2113 break;
2114 default:
2115 return -EINVAL;
2116 }
2117
2118 return 0;
2119}
2120
2121static int emulate_sys_reg(u32 id, u64 *valp)
2122{
2123 struct arm64_ftr_reg *regp;
2124
2125 if (!is_emulated(id))
2126 return -EINVAL;
2127
2128 if (sys_reg_CRm(id) == 0)
2129 return emulate_id_reg(id, valp);
2130
2131 regp = get_arm64_ftr_reg(id);
2132 if (regp)
2133 *valp = arm64_ftr_reg_user_value(regp);
2134 else
2135 /*
2136 * The untracked registers are either IMPLEMENTATION DEFINED
2137 * (e.g, ID_AFR0_EL1) or reserved RAZ.
2138 */
2139 *valp = 0;
2140 return 0;
2141}
2142
520ad988 2143int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
77c97b4e
SP		 2144{
2145 int rc;
77c97b4e
SP		 2146 u64 val;
2147
77c97b4e
SP		 2148 rc = emulate_sys_reg(sys_reg, &val);
2149 if (!rc) {
520ad988 2150 pt_regs_write_reg(regs, rt, val);
6436beee 2151 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
77c97b4e 2152 }
77c97b4e
SP		 2153 return rc;
2154}
2155
520ad988
AK		 2156static int emulate_mrs(struct pt_regs *regs, u32 insn)
2157{
2158 u32 sys_reg, rt;
2159
2160 /*
2161 * sys_reg values are defined as used in mrs/msr instruction.
2162 * shift the imm value to get the encoding.
2163 */
2164 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
2165 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
2166 return do_emulate_mrs(regs, sys_reg, rt);
2167}
2168
77c97b4e
SP		 2169static struct undef_hook mrs_hook = {
2170 .instr_mask = 0xfff00000,
2171 .instr_val = 0xd5300000,
d64567f6 2172 .pstate_mask = PSR_AA32_MODE_MASK,
77c97b4e
SP		 2173 .pstate_val = PSR_MODE_EL0t,
2174 .fn = emulate_mrs,
2175};
2176
2177static int __init enable_mrs_emulation(void)
2178{
2179 register_undef_hook(&mrs_hook);
2180 return 0;
2181}
2182
c0d8832e 2183core_initcall(enable_mrs_emulation);
1b3ccf4b
JL		 2184
2185ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
2186 char *buf)
2187{
2188 if (__meltdown_safe)
2189 return sprintf(buf, "Not affected\n");
2190
2191 if (arm64_kernel_unmapped_at_el0())
2192 return sprintf(buf, "Mitigation: PTI\n");
2193
2194 return sprintf(buf, "Vulnerable\n");
2195}
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