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478fcb2c WD |
1 | /* |
2 | * ARMv8 single-step debug support and mdscr context switching. | |
3 | * | |
4 | * Copyright (C) 2012 ARM Limited | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
18 | * Author: Will Deacon <will.deacon@arm.com> | |
19 | */ | |
20 | ||
21 | #include <linux/cpu.h> | |
22 | #include <linux/debugfs.h> | |
23 | #include <linux/hardirq.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/ptrace.h> | |
26 | #include <linux/stat.h> | |
1442b6ed | 27 | #include <linux/uaccess.h> |
478fcb2c WD |
28 | |
29 | #include <asm/debug-monitors.h> | |
478fcb2c WD |
30 | #include <asm/cputype.h> |
31 | #include <asm/system_misc.h> | |
32 | ||
33 | /* Low-level stepping controls. */ | |
34 | #define DBG_MDSCR_SS (1 << 0) | |
35 | #define DBG_SPSR_SS (1 << 21) | |
36 | ||
37 | /* MDSCR_EL1 enabling bits */ | |
38 | #define DBG_MDSCR_KDE (1 << 13) | |
39 | #define DBG_MDSCR_MDE (1 << 15) | |
40 | #define DBG_MDSCR_MASK ~(DBG_MDSCR_KDE | DBG_MDSCR_MDE) | |
41 | ||
42 | /* Determine debug architecture. */ | |
43 | u8 debug_monitors_arch(void) | |
44 | { | |
45 | return read_cpuid(ID_AA64DFR0_EL1) & 0xf; | |
46 | } | |
47 | ||
48 | /* | |
49 | * MDSCR access routines. | |
50 | */ | |
51 | static void mdscr_write(u32 mdscr) | |
52 | { | |
53 | unsigned long flags; | |
54 | local_dbg_save(flags); | |
55 | asm volatile("msr mdscr_el1, %0" :: "r" (mdscr)); | |
56 | local_dbg_restore(flags); | |
57 | } | |
58 | ||
59 | static u32 mdscr_read(void) | |
60 | { | |
61 | u32 mdscr; | |
62 | asm volatile("mrs %0, mdscr_el1" : "=r" (mdscr)); | |
63 | return mdscr; | |
64 | } | |
65 | ||
66 | /* | |
67 | * Allow root to disable self-hosted debug from userspace. | |
68 | * This is useful if you want to connect an external JTAG debugger. | |
69 | */ | |
70 | static u32 debug_enabled = 1; | |
71 | ||
72 | static int create_debug_debugfs_entry(void) | |
73 | { | |
74 | debugfs_create_bool("debug_enabled", 0644, NULL, &debug_enabled); | |
75 | return 0; | |
76 | } | |
77 | fs_initcall(create_debug_debugfs_entry); | |
78 | ||
79 | static int __init early_debug_disable(char *buf) | |
80 | { | |
81 | debug_enabled = 0; | |
82 | return 0; | |
83 | } | |
84 | ||
85 | early_param("nodebugmon", early_debug_disable); | |
86 | ||
87 | /* | |
88 | * Keep track of debug users on each core. | |
89 | * The ref counts are per-cpu so we use a local_t type. | |
90 | */ | |
1436c1aa CL |
91 | static DEFINE_PER_CPU(int, mde_ref_count); |
92 | static DEFINE_PER_CPU(int, kde_ref_count); | |
478fcb2c WD |
93 | |
94 | void enable_debug_monitors(enum debug_el el) | |
95 | { | |
96 | u32 mdscr, enable = 0; | |
97 | ||
98 | WARN_ON(preemptible()); | |
99 | ||
1436c1aa | 100 | if (this_cpu_inc_return(mde_ref_count) == 1) |
478fcb2c WD |
101 | enable = DBG_MDSCR_MDE; |
102 | ||
103 | if (el == DBG_ACTIVE_EL1 && | |
1436c1aa | 104 | this_cpu_inc_return(kde_ref_count) == 1) |
478fcb2c WD |
105 | enable |= DBG_MDSCR_KDE; |
106 | ||
107 | if (enable && debug_enabled) { | |
108 | mdscr = mdscr_read(); | |
109 | mdscr |= enable; | |
110 | mdscr_write(mdscr); | |
111 | } | |
112 | } | |
113 | ||
114 | void disable_debug_monitors(enum debug_el el) | |
115 | { | |
116 | u32 mdscr, disable = 0; | |
117 | ||
118 | WARN_ON(preemptible()); | |
119 | ||
1436c1aa | 120 | if (this_cpu_dec_return(mde_ref_count) == 0) |
478fcb2c WD |
121 | disable = ~DBG_MDSCR_MDE; |
122 | ||
123 | if (el == DBG_ACTIVE_EL1 && | |
1436c1aa | 124 | this_cpu_dec_return(kde_ref_count) == 0) |
478fcb2c WD |
125 | disable &= ~DBG_MDSCR_KDE; |
126 | ||
127 | if (disable) { | |
128 | mdscr = mdscr_read(); | |
129 | mdscr &= disable; | |
130 | mdscr_write(mdscr); | |
131 | } | |
132 | } | |
133 | ||
134 | /* | |
135 | * OS lock clearing. | |
136 | */ | |
137 | static void clear_os_lock(void *unused) | |
138 | { | |
478fcb2c | 139 | asm volatile("msr oslar_el1, %0" : : "r" (0)); |
478fcb2c WD |
140 | } |
141 | ||
b8c6453a | 142 | static int os_lock_notify(struct notifier_block *self, |
478fcb2c WD |
143 | unsigned long action, void *data) |
144 | { | |
145 | int cpu = (unsigned long)data; | |
146 | if (action == CPU_ONLINE) | |
147 | smp_call_function_single(cpu, clear_os_lock, NULL, 1); | |
148 | return NOTIFY_OK; | |
149 | } | |
150 | ||
b8c6453a | 151 | static struct notifier_block os_lock_nb = { |
478fcb2c WD |
152 | .notifier_call = os_lock_notify, |
153 | }; | |
154 | ||
b8c6453a | 155 | static int debug_monitors_init(void) |
478fcb2c | 156 | { |
4b0b68af SB |
157 | cpu_notifier_register_begin(); |
158 | ||
478fcb2c | 159 | /* Clear the OS lock. */ |
d8ed442a VK |
160 | on_each_cpu(clear_os_lock, NULL, 1); |
161 | isb(); | |
162 | local_dbg_enable(); | |
478fcb2c WD |
163 | |
164 | /* Register hotplug handler. */ | |
4b0b68af SB |
165 | __register_cpu_notifier(&os_lock_nb); |
166 | ||
167 | cpu_notifier_register_done(); | |
478fcb2c WD |
168 | return 0; |
169 | } | |
170 | postcore_initcall(debug_monitors_init); | |
171 | ||
172 | /* | |
173 | * Single step API and exception handling. | |
174 | */ | |
175 | static void set_regs_spsr_ss(struct pt_regs *regs) | |
176 | { | |
177 | unsigned long spsr; | |
178 | ||
179 | spsr = regs->pstate; | |
180 | spsr &= ~DBG_SPSR_SS; | |
181 | spsr |= DBG_SPSR_SS; | |
182 | regs->pstate = spsr; | |
183 | } | |
184 | ||
185 | static void clear_regs_spsr_ss(struct pt_regs *regs) | |
186 | { | |
187 | unsigned long spsr; | |
188 | ||
189 | spsr = regs->pstate; | |
190 | spsr &= ~DBG_SPSR_SS; | |
191 | regs->pstate = spsr; | |
192 | } | |
193 | ||
ee6214ce SP |
194 | /* EL1 Single Step Handler hooks */ |
195 | static LIST_HEAD(step_hook); | |
242c04bc | 196 | static DEFINE_RWLOCK(step_hook_lock); |
ee6214ce SP |
197 | |
198 | void register_step_hook(struct step_hook *hook) | |
199 | { | |
200 | write_lock(&step_hook_lock); | |
201 | list_add(&hook->node, &step_hook); | |
202 | write_unlock(&step_hook_lock); | |
203 | } | |
204 | ||
205 | void unregister_step_hook(struct step_hook *hook) | |
206 | { | |
207 | write_lock(&step_hook_lock); | |
208 | list_del(&hook->node); | |
209 | write_unlock(&step_hook_lock); | |
210 | } | |
211 | ||
212 | /* | |
213 | * Call registered single step handers | |
214 | * There is no Syndrome info to check for determining the handler. | |
215 | * So we call all the registered handlers, until the right handler is | |
216 | * found which returns zero. | |
217 | */ | |
218 | static int call_step_hook(struct pt_regs *regs, unsigned int esr) | |
219 | { | |
220 | struct step_hook *hook; | |
221 | int retval = DBG_HOOK_ERROR; | |
222 | ||
223 | read_lock(&step_hook_lock); | |
224 | ||
225 | list_for_each_entry(hook, &step_hook, node) { | |
226 | retval = hook->fn(regs, esr); | |
227 | if (retval == DBG_HOOK_HANDLED) | |
228 | break; | |
229 | } | |
230 | ||
231 | read_unlock(&step_hook_lock); | |
232 | ||
233 | return retval; | |
234 | } | |
235 | ||
478fcb2c WD |
236 | static int single_step_handler(unsigned long addr, unsigned int esr, |
237 | struct pt_regs *regs) | |
238 | { | |
239 | siginfo_t info; | |
240 | ||
241 | /* | |
242 | * If we are stepping a pending breakpoint, call the hw_breakpoint | |
243 | * handler first. | |
244 | */ | |
245 | if (!reinstall_suspended_bps(regs)) | |
246 | return 0; | |
247 | ||
248 | if (user_mode(regs)) { | |
249 | info.si_signo = SIGTRAP; | |
250 | info.si_errno = 0; | |
251 | info.si_code = TRAP_HWBKPT; | |
252 | info.si_addr = (void __user *)instruction_pointer(regs); | |
253 | force_sig_info(SIGTRAP, &info, current); | |
254 | ||
255 | /* | |
256 | * ptrace will disable single step unless explicitly | |
257 | * asked to re-enable it. For other clients, it makes | |
258 | * sense to leave it enabled (i.e. rewind the controls | |
259 | * to the active-not-pending state). | |
260 | */ | |
261 | user_rewind_single_step(current); | |
262 | } else { | |
ee6214ce SP |
263 | if (call_step_hook(regs, esr) == DBG_HOOK_HANDLED) |
264 | return 0; | |
265 | ||
478fcb2c WD |
266 | pr_warning("Unexpected kernel single-step exception at EL1\n"); |
267 | /* | |
268 | * Re-enable stepping since we know that we will be | |
269 | * returning to regs. | |
270 | */ | |
271 | set_regs_spsr_ss(regs); | |
272 | } | |
273 | ||
274 | return 0; | |
275 | } | |
276 | ||
ee6214ce SP |
277 | /* |
278 | * Breakpoint handler is re-entrant as another breakpoint can | |
279 | * hit within breakpoint handler, especically in kprobes. | |
280 | * Use reader/writer locks instead of plain spinlock. | |
281 | */ | |
282 | static LIST_HEAD(break_hook); | |
242c04bc | 283 | static DEFINE_RWLOCK(break_hook_lock); |
ee6214ce SP |
284 | |
285 | void register_break_hook(struct break_hook *hook) | |
286 | { | |
287 | write_lock(&break_hook_lock); | |
288 | list_add(&hook->node, &break_hook); | |
289 | write_unlock(&break_hook_lock); | |
290 | } | |
291 | ||
292 | void unregister_break_hook(struct break_hook *hook) | |
293 | { | |
294 | write_lock(&break_hook_lock); | |
295 | list_del(&hook->node); | |
296 | write_unlock(&break_hook_lock); | |
297 | } | |
298 | ||
299 | static int call_break_hook(struct pt_regs *regs, unsigned int esr) | |
300 | { | |
301 | struct break_hook *hook; | |
302 | int (*fn)(struct pt_regs *regs, unsigned int esr) = NULL; | |
303 | ||
304 | read_lock(&break_hook_lock); | |
305 | list_for_each_entry(hook, &break_hook, node) | |
306 | if ((esr & hook->esr_mask) == hook->esr_val) | |
307 | fn = hook->fn; | |
308 | read_unlock(&break_hook_lock); | |
309 | ||
310 | return fn ? fn(regs, esr) : DBG_HOOK_ERROR; | |
311 | } | |
312 | ||
1442b6ed WD |
313 | static int brk_handler(unsigned long addr, unsigned int esr, |
314 | struct pt_regs *regs) | |
315 | { | |
316 | siginfo_t info; | |
317 | ||
ee6214ce SP |
318 | if (call_break_hook(regs, esr) == DBG_HOOK_HANDLED) |
319 | return 0; | |
320 | ||
1442b6ed WD |
321 | if (!user_mode(regs)) |
322 | return -EFAULT; | |
323 | ||
324 | info = (siginfo_t) { | |
325 | .si_signo = SIGTRAP, | |
326 | .si_errno = 0, | |
327 | .si_code = TRAP_BRKPT, | |
328 | .si_addr = (void __user *)instruction_pointer(regs), | |
329 | }; | |
330 | ||
331 | force_sig_info(SIGTRAP, &info, current); | |
332 | return 0; | |
333 | } | |
334 | ||
335 | int aarch32_break_handler(struct pt_regs *regs) | |
336 | { | |
337 | siginfo_t info; | |
2dacab73 ML |
338 | u32 arm_instr; |
339 | u16 thumb_instr; | |
1442b6ed WD |
340 | bool bp = false; |
341 | void __user *pc = (void __user *)instruction_pointer(regs); | |
342 | ||
343 | if (!compat_user_mode(regs)) | |
344 | return -EFAULT; | |
345 | ||
346 | if (compat_thumb_mode(regs)) { | |
347 | /* get 16-bit Thumb instruction */ | |
2dacab73 ML |
348 | get_user(thumb_instr, (u16 __user *)pc); |
349 | thumb_instr = le16_to_cpu(thumb_instr); | |
350 | if (thumb_instr == AARCH32_BREAK_THUMB2_LO) { | |
1442b6ed | 351 | /* get second half of 32-bit Thumb-2 instruction */ |
2dacab73 ML |
352 | get_user(thumb_instr, (u16 __user *)(pc + 2)); |
353 | thumb_instr = le16_to_cpu(thumb_instr); | |
354 | bp = thumb_instr == AARCH32_BREAK_THUMB2_HI; | |
1442b6ed | 355 | } else { |
2dacab73 | 356 | bp = thumb_instr == AARCH32_BREAK_THUMB; |
1442b6ed WD |
357 | } |
358 | } else { | |
359 | /* 32-bit ARM instruction */ | |
2dacab73 ML |
360 | get_user(arm_instr, (u32 __user *)pc); |
361 | arm_instr = le32_to_cpu(arm_instr); | |
362 | bp = (arm_instr & ~0xf0000000) == AARCH32_BREAK_ARM; | |
1442b6ed WD |
363 | } |
364 | ||
365 | if (!bp) | |
366 | return -EFAULT; | |
367 | ||
368 | info = (siginfo_t) { | |
369 | .si_signo = SIGTRAP, | |
370 | .si_errno = 0, | |
371 | .si_code = TRAP_BRKPT, | |
372 | .si_addr = pc, | |
373 | }; | |
374 | ||
375 | force_sig_info(SIGTRAP, &info, current); | |
376 | return 0; | |
377 | } | |
378 | ||
379 | static int __init debug_traps_init(void) | |
478fcb2c WD |
380 | { |
381 | hook_debug_fault_code(DBG_ESR_EVT_HWSS, single_step_handler, SIGTRAP, | |
382 | TRAP_HWBKPT, "single-step handler"); | |
1442b6ed WD |
383 | hook_debug_fault_code(DBG_ESR_EVT_BRK, brk_handler, SIGTRAP, |
384 | TRAP_BRKPT, "ptrace BRK handler"); | |
478fcb2c WD |
385 | return 0; |
386 | } | |
1442b6ed | 387 | arch_initcall(debug_traps_init); |
478fcb2c WD |
388 | |
389 | /* Re-enable single step for syscall restarting. */ | |
390 | void user_rewind_single_step(struct task_struct *task) | |
391 | { | |
392 | /* | |
393 | * If single step is active for this thread, then set SPSR.SS | |
394 | * to 1 to avoid returning to the active-pending state. | |
395 | */ | |
396 | if (test_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP)) | |
397 | set_regs_spsr_ss(task_pt_regs(task)); | |
398 | } | |
399 | ||
400 | void user_fastforward_single_step(struct task_struct *task) | |
401 | { | |
402 | if (test_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP)) | |
403 | clear_regs_spsr_ss(task_pt_regs(task)); | |
404 | } | |
405 | ||
406 | /* Kernel API */ | |
407 | void kernel_enable_single_step(struct pt_regs *regs) | |
408 | { | |
409 | WARN_ON(!irqs_disabled()); | |
410 | set_regs_spsr_ss(regs); | |
411 | mdscr_write(mdscr_read() | DBG_MDSCR_SS); | |
412 | enable_debug_monitors(DBG_ACTIVE_EL1); | |
413 | } | |
414 | ||
415 | void kernel_disable_single_step(void) | |
416 | { | |
417 | WARN_ON(!irqs_disabled()); | |
418 | mdscr_write(mdscr_read() & ~DBG_MDSCR_SS); | |
419 | disable_debug_monitors(DBG_ACTIVE_EL1); | |
420 | } | |
421 | ||
422 | int kernel_active_single_step(void) | |
423 | { | |
424 | WARN_ON(!irqs_disabled()); | |
425 | return mdscr_read() & DBG_MDSCR_SS; | |
426 | } | |
427 | ||
428 | /* ptrace API */ | |
429 | void user_enable_single_step(struct task_struct *task) | |
430 | { | |
431 | set_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP); | |
432 | set_regs_spsr_ss(task_pt_regs(task)); | |
433 | } | |
434 | ||
435 | void user_disable_single_step(struct task_struct *task) | |
436 | { | |
437 | clear_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP); | |
438 | } |