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478fcb2c WD |
1 | /* |
2 | * ARMv8 single-step debug support and mdscr context switching. | |
3 | * | |
4 | * Copyright (C) 2012 ARM Limited | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
18 | * Author: Will Deacon <will.deacon@arm.com> | |
19 | */ | |
20 | ||
21 | #include <linux/cpu.h> | |
22 | #include <linux/debugfs.h> | |
23 | #include <linux/hardirq.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/ptrace.h> | |
26 | #include <linux/stat.h> | |
1442b6ed | 27 | #include <linux/uaccess.h> |
478fcb2c WD |
28 | |
29 | #include <asm/debug-monitors.h> | |
478fcb2c WD |
30 | #include <asm/cputype.h> |
31 | #include <asm/system_misc.h> | |
32 | ||
478fcb2c WD |
33 | /* Determine debug architecture. */ |
34 | u8 debug_monitors_arch(void) | |
35 | { | |
36 | return read_cpuid(ID_AA64DFR0_EL1) & 0xf; | |
37 | } | |
38 | ||
39 | /* | |
40 | * MDSCR access routines. | |
41 | */ | |
42 | static void mdscr_write(u32 mdscr) | |
43 | { | |
44 | unsigned long flags; | |
45 | local_dbg_save(flags); | |
46 | asm volatile("msr mdscr_el1, %0" :: "r" (mdscr)); | |
47 | local_dbg_restore(flags); | |
48 | } | |
49 | ||
50 | static u32 mdscr_read(void) | |
51 | { | |
52 | u32 mdscr; | |
53 | asm volatile("mrs %0, mdscr_el1" : "=r" (mdscr)); | |
54 | return mdscr; | |
55 | } | |
56 | ||
57 | /* | |
58 | * Allow root to disable self-hosted debug from userspace. | |
59 | * This is useful if you want to connect an external JTAG debugger. | |
60 | */ | |
61 | static u32 debug_enabled = 1; | |
62 | ||
63 | static int create_debug_debugfs_entry(void) | |
64 | { | |
65 | debugfs_create_bool("debug_enabled", 0644, NULL, &debug_enabled); | |
66 | return 0; | |
67 | } | |
68 | fs_initcall(create_debug_debugfs_entry); | |
69 | ||
70 | static int __init early_debug_disable(char *buf) | |
71 | { | |
72 | debug_enabled = 0; | |
73 | return 0; | |
74 | } | |
75 | ||
76 | early_param("nodebugmon", early_debug_disable); | |
77 | ||
78 | /* | |
79 | * Keep track of debug users on each core. | |
80 | * The ref counts are per-cpu so we use a local_t type. | |
81 | */ | |
1436c1aa CL |
82 | static DEFINE_PER_CPU(int, mde_ref_count); |
83 | static DEFINE_PER_CPU(int, kde_ref_count); | |
478fcb2c | 84 | |
6f883d10 | 85 | void enable_debug_monitors(enum dbg_active_el el) |
478fcb2c WD |
86 | { |
87 | u32 mdscr, enable = 0; | |
88 | ||
89 | WARN_ON(preemptible()); | |
90 | ||
1436c1aa | 91 | if (this_cpu_inc_return(mde_ref_count) == 1) |
478fcb2c WD |
92 | enable = DBG_MDSCR_MDE; |
93 | ||
94 | if (el == DBG_ACTIVE_EL1 && | |
1436c1aa | 95 | this_cpu_inc_return(kde_ref_count) == 1) |
478fcb2c WD |
96 | enable |= DBG_MDSCR_KDE; |
97 | ||
98 | if (enable && debug_enabled) { | |
99 | mdscr = mdscr_read(); | |
100 | mdscr |= enable; | |
101 | mdscr_write(mdscr); | |
102 | } | |
103 | } | |
104 | ||
6f883d10 | 105 | void disable_debug_monitors(enum dbg_active_el el) |
478fcb2c WD |
106 | { |
107 | u32 mdscr, disable = 0; | |
108 | ||
109 | WARN_ON(preemptible()); | |
110 | ||
1436c1aa | 111 | if (this_cpu_dec_return(mde_ref_count) == 0) |
478fcb2c WD |
112 | disable = ~DBG_MDSCR_MDE; |
113 | ||
114 | if (el == DBG_ACTIVE_EL1 && | |
1436c1aa | 115 | this_cpu_dec_return(kde_ref_count) == 0) |
478fcb2c WD |
116 | disable &= ~DBG_MDSCR_KDE; |
117 | ||
118 | if (disable) { | |
119 | mdscr = mdscr_read(); | |
120 | mdscr &= disable; | |
121 | mdscr_write(mdscr); | |
122 | } | |
123 | } | |
124 | ||
125 | /* | |
126 | * OS lock clearing. | |
127 | */ | |
128 | static void clear_os_lock(void *unused) | |
129 | { | |
478fcb2c | 130 | asm volatile("msr oslar_el1, %0" : : "r" (0)); |
478fcb2c WD |
131 | } |
132 | ||
b8c6453a | 133 | static int os_lock_notify(struct notifier_block *self, |
478fcb2c WD |
134 | unsigned long action, void *data) |
135 | { | |
136 | int cpu = (unsigned long)data; | |
e56d82a1 | 137 | if ((action & ~CPU_TASKS_FROZEN) == CPU_ONLINE) |
478fcb2c WD |
138 | smp_call_function_single(cpu, clear_os_lock, NULL, 1); |
139 | return NOTIFY_OK; | |
140 | } | |
141 | ||
b8c6453a | 142 | static struct notifier_block os_lock_nb = { |
478fcb2c WD |
143 | .notifier_call = os_lock_notify, |
144 | }; | |
145 | ||
b8c6453a | 146 | static int debug_monitors_init(void) |
478fcb2c | 147 | { |
4b0b68af SB |
148 | cpu_notifier_register_begin(); |
149 | ||
478fcb2c | 150 | /* Clear the OS lock. */ |
d8ed442a VK |
151 | on_each_cpu(clear_os_lock, NULL, 1); |
152 | isb(); | |
153 | local_dbg_enable(); | |
478fcb2c WD |
154 | |
155 | /* Register hotplug handler. */ | |
4b0b68af SB |
156 | __register_cpu_notifier(&os_lock_nb); |
157 | ||
158 | cpu_notifier_register_done(); | |
478fcb2c WD |
159 | return 0; |
160 | } | |
161 | postcore_initcall(debug_monitors_init); | |
162 | ||
163 | /* | |
164 | * Single step API and exception handling. | |
165 | */ | |
166 | static void set_regs_spsr_ss(struct pt_regs *regs) | |
167 | { | |
168 | unsigned long spsr; | |
169 | ||
170 | spsr = regs->pstate; | |
171 | spsr &= ~DBG_SPSR_SS; | |
172 | spsr |= DBG_SPSR_SS; | |
173 | regs->pstate = spsr; | |
174 | } | |
175 | ||
176 | static void clear_regs_spsr_ss(struct pt_regs *regs) | |
177 | { | |
178 | unsigned long spsr; | |
179 | ||
180 | spsr = regs->pstate; | |
181 | spsr &= ~DBG_SPSR_SS; | |
182 | regs->pstate = spsr; | |
183 | } | |
184 | ||
ee6214ce SP |
185 | /* EL1 Single Step Handler hooks */ |
186 | static LIST_HEAD(step_hook); | |
242c04bc | 187 | static DEFINE_RWLOCK(step_hook_lock); |
ee6214ce SP |
188 | |
189 | void register_step_hook(struct step_hook *hook) | |
190 | { | |
191 | write_lock(&step_hook_lock); | |
192 | list_add(&hook->node, &step_hook); | |
193 | write_unlock(&step_hook_lock); | |
194 | } | |
195 | ||
196 | void unregister_step_hook(struct step_hook *hook) | |
197 | { | |
198 | write_lock(&step_hook_lock); | |
199 | list_del(&hook->node); | |
200 | write_unlock(&step_hook_lock); | |
201 | } | |
202 | ||
203 | /* | |
95485fdc | 204 | * Call registered single step handlers |
ee6214ce SP |
205 | * There is no Syndrome info to check for determining the handler. |
206 | * So we call all the registered handlers, until the right handler is | |
207 | * found which returns zero. | |
208 | */ | |
209 | static int call_step_hook(struct pt_regs *regs, unsigned int esr) | |
210 | { | |
211 | struct step_hook *hook; | |
212 | int retval = DBG_HOOK_ERROR; | |
213 | ||
214 | read_lock(&step_hook_lock); | |
215 | ||
216 | list_for_each_entry(hook, &step_hook, node) { | |
217 | retval = hook->fn(regs, esr); | |
218 | if (retval == DBG_HOOK_HANDLED) | |
219 | break; | |
220 | } | |
221 | ||
222 | read_unlock(&step_hook_lock); | |
223 | ||
224 | return retval; | |
225 | } | |
226 | ||
478fcb2c WD |
227 | static int single_step_handler(unsigned long addr, unsigned int esr, |
228 | struct pt_regs *regs) | |
229 | { | |
230 | siginfo_t info; | |
231 | ||
232 | /* | |
233 | * If we are stepping a pending breakpoint, call the hw_breakpoint | |
234 | * handler first. | |
235 | */ | |
236 | if (!reinstall_suspended_bps(regs)) | |
237 | return 0; | |
238 | ||
239 | if (user_mode(regs)) { | |
240 | info.si_signo = SIGTRAP; | |
241 | info.si_errno = 0; | |
242 | info.si_code = TRAP_HWBKPT; | |
243 | info.si_addr = (void __user *)instruction_pointer(regs); | |
244 | force_sig_info(SIGTRAP, &info, current); | |
245 | ||
246 | /* | |
247 | * ptrace will disable single step unless explicitly | |
248 | * asked to re-enable it. For other clients, it makes | |
249 | * sense to leave it enabled (i.e. rewind the controls | |
250 | * to the active-not-pending state). | |
251 | */ | |
252 | user_rewind_single_step(current); | |
253 | } else { | |
ee6214ce SP |
254 | if (call_step_hook(regs, esr) == DBG_HOOK_HANDLED) |
255 | return 0; | |
256 | ||
478fcb2c WD |
257 | pr_warning("Unexpected kernel single-step exception at EL1\n"); |
258 | /* | |
259 | * Re-enable stepping since we know that we will be | |
260 | * returning to regs. | |
261 | */ | |
262 | set_regs_spsr_ss(regs); | |
263 | } | |
264 | ||
265 | return 0; | |
266 | } | |
267 | ||
ee6214ce SP |
268 | /* |
269 | * Breakpoint handler is re-entrant as another breakpoint can | |
270 | * hit within breakpoint handler, especically in kprobes. | |
271 | * Use reader/writer locks instead of plain spinlock. | |
272 | */ | |
273 | static LIST_HEAD(break_hook); | |
242c04bc | 274 | static DEFINE_RWLOCK(break_hook_lock); |
ee6214ce SP |
275 | |
276 | void register_break_hook(struct break_hook *hook) | |
277 | { | |
278 | write_lock(&break_hook_lock); | |
279 | list_add(&hook->node, &break_hook); | |
280 | write_unlock(&break_hook_lock); | |
281 | } | |
282 | ||
283 | void unregister_break_hook(struct break_hook *hook) | |
284 | { | |
285 | write_lock(&break_hook_lock); | |
286 | list_del(&hook->node); | |
287 | write_unlock(&break_hook_lock); | |
288 | } | |
289 | ||
290 | static int call_break_hook(struct pt_regs *regs, unsigned int esr) | |
291 | { | |
292 | struct break_hook *hook; | |
293 | int (*fn)(struct pt_regs *regs, unsigned int esr) = NULL; | |
294 | ||
295 | read_lock(&break_hook_lock); | |
296 | list_for_each_entry(hook, &break_hook, node) | |
297 | if ((esr & hook->esr_mask) == hook->esr_val) | |
298 | fn = hook->fn; | |
299 | read_unlock(&break_hook_lock); | |
300 | ||
301 | return fn ? fn(regs, esr) : DBG_HOOK_ERROR; | |
302 | } | |
303 | ||
1442b6ed WD |
304 | static int brk_handler(unsigned long addr, unsigned int esr, |
305 | struct pt_regs *regs) | |
306 | { | |
307 | siginfo_t info; | |
308 | ||
c878e0cf WD |
309 | if (user_mode(regs)) { |
310 | info = (siginfo_t) { | |
311 | .si_signo = SIGTRAP, | |
312 | .si_errno = 0, | |
313 | .si_code = TRAP_BRKPT, | |
314 | .si_addr = (void __user *)instruction_pointer(regs), | |
315 | }; | |
ee6214ce | 316 | |
c878e0cf WD |
317 | force_sig_info(SIGTRAP, &info, current); |
318 | } else if (call_break_hook(regs, esr) != DBG_HOOK_HANDLED) { | |
319 | pr_warning("Unexpected kernel BRK exception at EL1\n"); | |
1442b6ed | 320 | return -EFAULT; |
c878e0cf | 321 | } |
1442b6ed | 322 | |
1442b6ed WD |
323 | return 0; |
324 | } | |
325 | ||
326 | int aarch32_break_handler(struct pt_regs *regs) | |
327 | { | |
328 | siginfo_t info; | |
2dacab73 ML |
329 | u32 arm_instr; |
330 | u16 thumb_instr; | |
1442b6ed WD |
331 | bool bp = false; |
332 | void __user *pc = (void __user *)instruction_pointer(regs); | |
333 | ||
334 | if (!compat_user_mode(regs)) | |
335 | return -EFAULT; | |
336 | ||
337 | if (compat_thumb_mode(regs)) { | |
338 | /* get 16-bit Thumb instruction */ | |
2dacab73 ML |
339 | get_user(thumb_instr, (u16 __user *)pc); |
340 | thumb_instr = le16_to_cpu(thumb_instr); | |
341 | if (thumb_instr == AARCH32_BREAK_THUMB2_LO) { | |
1442b6ed | 342 | /* get second half of 32-bit Thumb-2 instruction */ |
2dacab73 ML |
343 | get_user(thumb_instr, (u16 __user *)(pc + 2)); |
344 | thumb_instr = le16_to_cpu(thumb_instr); | |
345 | bp = thumb_instr == AARCH32_BREAK_THUMB2_HI; | |
1442b6ed | 346 | } else { |
2dacab73 | 347 | bp = thumb_instr == AARCH32_BREAK_THUMB; |
1442b6ed WD |
348 | } |
349 | } else { | |
350 | /* 32-bit ARM instruction */ | |
2dacab73 ML |
351 | get_user(arm_instr, (u32 __user *)pc); |
352 | arm_instr = le32_to_cpu(arm_instr); | |
353 | bp = (arm_instr & ~0xf0000000) == AARCH32_BREAK_ARM; | |
1442b6ed WD |
354 | } |
355 | ||
356 | if (!bp) | |
357 | return -EFAULT; | |
358 | ||
359 | info = (siginfo_t) { | |
360 | .si_signo = SIGTRAP, | |
361 | .si_errno = 0, | |
362 | .si_code = TRAP_BRKPT, | |
363 | .si_addr = pc, | |
364 | }; | |
365 | ||
366 | force_sig_info(SIGTRAP, &info, current); | |
367 | return 0; | |
368 | } | |
369 | ||
370 | static int __init debug_traps_init(void) | |
478fcb2c WD |
371 | { |
372 | hook_debug_fault_code(DBG_ESR_EVT_HWSS, single_step_handler, SIGTRAP, | |
373 | TRAP_HWBKPT, "single-step handler"); | |
1442b6ed WD |
374 | hook_debug_fault_code(DBG_ESR_EVT_BRK, brk_handler, SIGTRAP, |
375 | TRAP_BRKPT, "ptrace BRK handler"); | |
478fcb2c WD |
376 | return 0; |
377 | } | |
1442b6ed | 378 | arch_initcall(debug_traps_init); |
478fcb2c WD |
379 | |
380 | /* Re-enable single step for syscall restarting. */ | |
381 | void user_rewind_single_step(struct task_struct *task) | |
382 | { | |
383 | /* | |
384 | * If single step is active for this thread, then set SPSR.SS | |
385 | * to 1 to avoid returning to the active-pending state. | |
386 | */ | |
387 | if (test_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP)) | |
388 | set_regs_spsr_ss(task_pt_regs(task)); | |
389 | } | |
390 | ||
391 | void user_fastforward_single_step(struct task_struct *task) | |
392 | { | |
393 | if (test_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP)) | |
394 | clear_regs_spsr_ss(task_pt_regs(task)); | |
395 | } | |
396 | ||
397 | /* Kernel API */ | |
398 | void kernel_enable_single_step(struct pt_regs *regs) | |
399 | { | |
400 | WARN_ON(!irqs_disabled()); | |
401 | set_regs_spsr_ss(regs); | |
402 | mdscr_write(mdscr_read() | DBG_MDSCR_SS); | |
403 | enable_debug_monitors(DBG_ACTIVE_EL1); | |
404 | } | |
405 | ||
406 | void kernel_disable_single_step(void) | |
407 | { | |
408 | WARN_ON(!irqs_disabled()); | |
409 | mdscr_write(mdscr_read() & ~DBG_MDSCR_SS); | |
410 | disable_debug_monitors(DBG_ACTIVE_EL1); | |
411 | } | |
412 | ||
413 | int kernel_active_single_step(void) | |
414 | { | |
415 | WARN_ON(!irqs_disabled()); | |
416 | return mdscr_read() & DBG_MDSCR_SS; | |
417 | } | |
418 | ||
419 | /* ptrace API */ | |
420 | void user_enable_single_step(struct task_struct *task) | |
421 | { | |
422 | set_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP); | |
423 | set_regs_spsr_ss(task_pt_regs(task)); | |
424 | } | |
425 | ||
426 | void user_disable_single_step(struct task_struct *task) | |
427 | { | |
428 | clear_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP); | |
429 | } |