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478fcb2c WD |
1 | /* |
2 | * ARMv8 single-step debug support and mdscr context switching. | |
3 | * | |
4 | * Copyright (C) 2012 ARM Limited | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
18 | * Author: Will Deacon <will.deacon@arm.com> | |
19 | */ | |
20 | ||
21 | #include <linux/cpu.h> | |
22 | #include <linux/debugfs.h> | |
23 | #include <linux/hardirq.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/ptrace.h> | |
26 | #include <linux/stat.h> | |
1442b6ed | 27 | #include <linux/uaccess.h> |
478fcb2c | 28 | |
3085bb01 | 29 | #include <asm/cpufeature.h> |
478fcb2c | 30 | #include <asm/cputype.h> |
3085bb01 | 31 | #include <asm/debug-monitors.h> |
478fcb2c WD |
32 | #include <asm/system_misc.h> |
33 | ||
478fcb2c WD |
34 | /* Determine debug architecture. */ |
35 | u8 debug_monitors_arch(void) | |
36 | { | |
3085bb01 SP |
37 | return cpuid_feature_extract_field(read_system_reg(SYS_ID_AA64DFR0_EL1), |
38 | ID_AA64DFR0_DEBUGVER_SHIFT); | |
478fcb2c WD |
39 | } |
40 | ||
41 | /* | |
42 | * MDSCR access routines. | |
43 | */ | |
44 | static void mdscr_write(u32 mdscr) | |
45 | { | |
46 | unsigned long flags; | |
47 | local_dbg_save(flags); | |
48 | asm volatile("msr mdscr_el1, %0" :: "r" (mdscr)); | |
49 | local_dbg_restore(flags); | |
50 | } | |
51 | ||
52 | static u32 mdscr_read(void) | |
53 | { | |
54 | u32 mdscr; | |
55 | asm volatile("mrs %0, mdscr_el1" : "=r" (mdscr)); | |
56 | return mdscr; | |
57 | } | |
58 | ||
59 | /* | |
60 | * Allow root to disable self-hosted debug from userspace. | |
61 | * This is useful if you want to connect an external JTAG debugger. | |
62 | */ | |
621a5f7a | 63 | static bool debug_enabled = true; |
478fcb2c WD |
64 | |
65 | static int create_debug_debugfs_entry(void) | |
66 | { | |
67 | debugfs_create_bool("debug_enabled", 0644, NULL, &debug_enabled); | |
68 | return 0; | |
69 | } | |
70 | fs_initcall(create_debug_debugfs_entry); | |
71 | ||
72 | static int __init early_debug_disable(char *buf) | |
73 | { | |
621a5f7a | 74 | debug_enabled = false; |
478fcb2c WD |
75 | return 0; |
76 | } | |
77 | ||
78 | early_param("nodebugmon", early_debug_disable); | |
79 | ||
80 | /* | |
81 | * Keep track of debug users on each core. | |
82 | * The ref counts are per-cpu so we use a local_t type. | |
83 | */ | |
1436c1aa CL |
84 | static DEFINE_PER_CPU(int, mde_ref_count); |
85 | static DEFINE_PER_CPU(int, kde_ref_count); | |
478fcb2c | 86 | |
6f883d10 | 87 | void enable_debug_monitors(enum dbg_active_el el) |
478fcb2c WD |
88 | { |
89 | u32 mdscr, enable = 0; | |
90 | ||
91 | WARN_ON(preemptible()); | |
92 | ||
1436c1aa | 93 | if (this_cpu_inc_return(mde_ref_count) == 1) |
478fcb2c WD |
94 | enable = DBG_MDSCR_MDE; |
95 | ||
96 | if (el == DBG_ACTIVE_EL1 && | |
1436c1aa | 97 | this_cpu_inc_return(kde_ref_count) == 1) |
478fcb2c WD |
98 | enable |= DBG_MDSCR_KDE; |
99 | ||
100 | if (enable && debug_enabled) { | |
101 | mdscr = mdscr_read(); | |
102 | mdscr |= enable; | |
103 | mdscr_write(mdscr); | |
104 | } | |
105 | } | |
106 | ||
6f883d10 | 107 | void disable_debug_monitors(enum dbg_active_el el) |
478fcb2c WD |
108 | { |
109 | u32 mdscr, disable = 0; | |
110 | ||
111 | WARN_ON(preemptible()); | |
112 | ||
1436c1aa | 113 | if (this_cpu_dec_return(mde_ref_count) == 0) |
478fcb2c WD |
114 | disable = ~DBG_MDSCR_MDE; |
115 | ||
116 | if (el == DBG_ACTIVE_EL1 && | |
1436c1aa | 117 | this_cpu_dec_return(kde_ref_count) == 0) |
478fcb2c WD |
118 | disable &= ~DBG_MDSCR_KDE; |
119 | ||
120 | if (disable) { | |
121 | mdscr = mdscr_read(); | |
122 | mdscr &= disable; | |
123 | mdscr_write(mdscr); | |
124 | } | |
125 | } | |
126 | ||
127 | /* | |
128 | * OS lock clearing. | |
129 | */ | |
130 | static void clear_os_lock(void *unused) | |
131 | { | |
478fcb2c | 132 | asm volatile("msr oslar_el1, %0" : : "r" (0)); |
478fcb2c WD |
133 | } |
134 | ||
b8c6453a | 135 | static int os_lock_notify(struct notifier_block *self, |
478fcb2c WD |
136 | unsigned long action, void *data) |
137 | { | |
138 | int cpu = (unsigned long)data; | |
e56d82a1 | 139 | if ((action & ~CPU_TASKS_FROZEN) == CPU_ONLINE) |
478fcb2c WD |
140 | smp_call_function_single(cpu, clear_os_lock, NULL, 1); |
141 | return NOTIFY_OK; | |
142 | } | |
143 | ||
b8c6453a | 144 | static struct notifier_block os_lock_nb = { |
478fcb2c WD |
145 | .notifier_call = os_lock_notify, |
146 | }; | |
147 | ||
b8c6453a | 148 | static int debug_monitors_init(void) |
478fcb2c | 149 | { |
4b0b68af SB |
150 | cpu_notifier_register_begin(); |
151 | ||
478fcb2c | 152 | /* Clear the OS lock. */ |
d8ed442a VK |
153 | on_each_cpu(clear_os_lock, NULL, 1); |
154 | isb(); | |
155 | local_dbg_enable(); | |
478fcb2c WD |
156 | |
157 | /* Register hotplug handler. */ | |
4b0b68af SB |
158 | __register_cpu_notifier(&os_lock_nb); |
159 | ||
160 | cpu_notifier_register_done(); | |
478fcb2c WD |
161 | return 0; |
162 | } | |
163 | postcore_initcall(debug_monitors_init); | |
164 | ||
165 | /* | |
166 | * Single step API and exception handling. | |
167 | */ | |
168 | static void set_regs_spsr_ss(struct pt_regs *regs) | |
169 | { | |
170 | unsigned long spsr; | |
171 | ||
172 | spsr = regs->pstate; | |
173 | spsr &= ~DBG_SPSR_SS; | |
174 | spsr |= DBG_SPSR_SS; | |
175 | regs->pstate = spsr; | |
176 | } | |
177 | ||
178 | static void clear_regs_spsr_ss(struct pt_regs *regs) | |
179 | { | |
180 | unsigned long spsr; | |
181 | ||
182 | spsr = regs->pstate; | |
183 | spsr &= ~DBG_SPSR_SS; | |
184 | regs->pstate = spsr; | |
185 | } | |
186 | ||
ee6214ce SP |
187 | /* EL1 Single Step Handler hooks */ |
188 | static LIST_HEAD(step_hook); | |
cf0a2543 | 189 | static DEFINE_SPINLOCK(step_hook_lock); |
ee6214ce SP |
190 | |
191 | void register_step_hook(struct step_hook *hook) | |
192 | { | |
cf0a2543 YS |
193 | spin_lock(&step_hook_lock); |
194 | list_add_rcu(&hook->node, &step_hook); | |
195 | spin_unlock(&step_hook_lock); | |
ee6214ce SP |
196 | } |
197 | ||
198 | void unregister_step_hook(struct step_hook *hook) | |
199 | { | |
cf0a2543 YS |
200 | spin_lock(&step_hook_lock); |
201 | list_del_rcu(&hook->node); | |
202 | spin_unlock(&step_hook_lock); | |
203 | synchronize_rcu(); | |
ee6214ce SP |
204 | } |
205 | ||
206 | /* | |
95485fdc | 207 | * Call registered single step handlers |
ee6214ce SP |
208 | * There is no Syndrome info to check for determining the handler. |
209 | * So we call all the registered handlers, until the right handler is | |
210 | * found which returns zero. | |
211 | */ | |
212 | static int call_step_hook(struct pt_regs *regs, unsigned int esr) | |
213 | { | |
214 | struct step_hook *hook; | |
215 | int retval = DBG_HOOK_ERROR; | |
216 | ||
cf0a2543 | 217 | rcu_read_lock(); |
ee6214ce | 218 | |
cf0a2543 | 219 | list_for_each_entry_rcu(hook, &step_hook, node) { |
ee6214ce SP |
220 | retval = hook->fn(regs, esr); |
221 | if (retval == DBG_HOOK_HANDLED) | |
222 | break; | |
223 | } | |
224 | ||
cf0a2543 | 225 | rcu_read_unlock(); |
ee6214ce SP |
226 | |
227 | return retval; | |
228 | } | |
229 | ||
478fcb2c WD |
230 | static int single_step_handler(unsigned long addr, unsigned int esr, |
231 | struct pt_regs *regs) | |
232 | { | |
233 | siginfo_t info; | |
234 | ||
235 | /* | |
236 | * If we are stepping a pending breakpoint, call the hw_breakpoint | |
237 | * handler first. | |
238 | */ | |
239 | if (!reinstall_suspended_bps(regs)) | |
240 | return 0; | |
241 | ||
242 | if (user_mode(regs)) { | |
243 | info.si_signo = SIGTRAP; | |
244 | info.si_errno = 0; | |
245 | info.si_code = TRAP_HWBKPT; | |
246 | info.si_addr = (void __user *)instruction_pointer(regs); | |
247 | force_sig_info(SIGTRAP, &info, current); | |
248 | ||
249 | /* | |
250 | * ptrace will disable single step unless explicitly | |
251 | * asked to re-enable it. For other clients, it makes | |
252 | * sense to leave it enabled (i.e. rewind the controls | |
253 | * to the active-not-pending state). | |
254 | */ | |
255 | user_rewind_single_step(current); | |
256 | } else { | |
ee6214ce SP |
257 | if (call_step_hook(regs, esr) == DBG_HOOK_HANDLED) |
258 | return 0; | |
259 | ||
478fcb2c WD |
260 | pr_warning("Unexpected kernel single-step exception at EL1\n"); |
261 | /* | |
262 | * Re-enable stepping since we know that we will be | |
263 | * returning to regs. | |
264 | */ | |
265 | set_regs_spsr_ss(regs); | |
266 | } | |
267 | ||
268 | return 0; | |
269 | } | |
270 | ||
ee6214ce SP |
271 | /* |
272 | * Breakpoint handler is re-entrant as another breakpoint can | |
273 | * hit within breakpoint handler, especically in kprobes. | |
274 | * Use reader/writer locks instead of plain spinlock. | |
275 | */ | |
276 | static LIST_HEAD(break_hook); | |
62c6c61a | 277 | static DEFINE_SPINLOCK(break_hook_lock); |
ee6214ce SP |
278 | |
279 | void register_break_hook(struct break_hook *hook) | |
280 | { | |
62c6c61a YS |
281 | spin_lock(&break_hook_lock); |
282 | list_add_rcu(&hook->node, &break_hook); | |
283 | spin_unlock(&break_hook_lock); | |
ee6214ce SP |
284 | } |
285 | ||
286 | void unregister_break_hook(struct break_hook *hook) | |
287 | { | |
62c6c61a YS |
288 | spin_lock(&break_hook_lock); |
289 | list_del_rcu(&hook->node); | |
290 | spin_unlock(&break_hook_lock); | |
291 | synchronize_rcu(); | |
ee6214ce SP |
292 | } |
293 | ||
294 | static int call_break_hook(struct pt_regs *regs, unsigned int esr) | |
295 | { | |
296 | struct break_hook *hook; | |
297 | int (*fn)(struct pt_regs *regs, unsigned int esr) = NULL; | |
298 | ||
62c6c61a YS |
299 | rcu_read_lock(); |
300 | list_for_each_entry_rcu(hook, &break_hook, node) | |
ee6214ce SP |
301 | if ((esr & hook->esr_mask) == hook->esr_val) |
302 | fn = hook->fn; | |
62c6c61a | 303 | rcu_read_unlock(); |
ee6214ce SP |
304 | |
305 | return fn ? fn(regs, esr) : DBG_HOOK_ERROR; | |
306 | } | |
307 | ||
1442b6ed WD |
308 | static int brk_handler(unsigned long addr, unsigned int esr, |
309 | struct pt_regs *regs) | |
310 | { | |
311 | siginfo_t info; | |
312 | ||
c878e0cf WD |
313 | if (user_mode(regs)) { |
314 | info = (siginfo_t) { | |
315 | .si_signo = SIGTRAP, | |
316 | .si_errno = 0, | |
317 | .si_code = TRAP_BRKPT, | |
318 | .si_addr = (void __user *)instruction_pointer(regs), | |
319 | }; | |
ee6214ce | 320 | |
c878e0cf WD |
321 | force_sig_info(SIGTRAP, &info, current); |
322 | } else if (call_break_hook(regs, esr) != DBG_HOOK_HANDLED) { | |
323 | pr_warning("Unexpected kernel BRK exception at EL1\n"); | |
1442b6ed | 324 | return -EFAULT; |
c878e0cf | 325 | } |
1442b6ed | 326 | |
1442b6ed WD |
327 | return 0; |
328 | } | |
329 | ||
330 | int aarch32_break_handler(struct pt_regs *regs) | |
331 | { | |
332 | siginfo_t info; | |
2dacab73 ML |
333 | u32 arm_instr; |
334 | u16 thumb_instr; | |
1442b6ed WD |
335 | bool bp = false; |
336 | void __user *pc = (void __user *)instruction_pointer(regs); | |
337 | ||
338 | if (!compat_user_mode(regs)) | |
339 | return -EFAULT; | |
340 | ||
341 | if (compat_thumb_mode(regs)) { | |
342 | /* get 16-bit Thumb instruction */ | |
2dacab73 ML |
343 | get_user(thumb_instr, (u16 __user *)pc); |
344 | thumb_instr = le16_to_cpu(thumb_instr); | |
345 | if (thumb_instr == AARCH32_BREAK_THUMB2_LO) { | |
1442b6ed | 346 | /* get second half of 32-bit Thumb-2 instruction */ |
2dacab73 ML |
347 | get_user(thumb_instr, (u16 __user *)(pc + 2)); |
348 | thumb_instr = le16_to_cpu(thumb_instr); | |
349 | bp = thumb_instr == AARCH32_BREAK_THUMB2_HI; | |
1442b6ed | 350 | } else { |
2dacab73 | 351 | bp = thumb_instr == AARCH32_BREAK_THUMB; |
1442b6ed WD |
352 | } |
353 | } else { | |
354 | /* 32-bit ARM instruction */ | |
2dacab73 ML |
355 | get_user(arm_instr, (u32 __user *)pc); |
356 | arm_instr = le32_to_cpu(arm_instr); | |
357 | bp = (arm_instr & ~0xf0000000) == AARCH32_BREAK_ARM; | |
1442b6ed WD |
358 | } |
359 | ||
360 | if (!bp) | |
361 | return -EFAULT; | |
362 | ||
363 | info = (siginfo_t) { | |
364 | .si_signo = SIGTRAP, | |
365 | .si_errno = 0, | |
366 | .si_code = TRAP_BRKPT, | |
367 | .si_addr = pc, | |
368 | }; | |
369 | ||
370 | force_sig_info(SIGTRAP, &info, current); | |
371 | return 0; | |
372 | } | |
373 | ||
374 | static int __init debug_traps_init(void) | |
478fcb2c WD |
375 | { |
376 | hook_debug_fault_code(DBG_ESR_EVT_HWSS, single_step_handler, SIGTRAP, | |
377 | TRAP_HWBKPT, "single-step handler"); | |
1442b6ed WD |
378 | hook_debug_fault_code(DBG_ESR_EVT_BRK, brk_handler, SIGTRAP, |
379 | TRAP_BRKPT, "ptrace BRK handler"); | |
478fcb2c WD |
380 | return 0; |
381 | } | |
1442b6ed | 382 | arch_initcall(debug_traps_init); |
478fcb2c WD |
383 | |
384 | /* Re-enable single step for syscall restarting. */ | |
385 | void user_rewind_single_step(struct task_struct *task) | |
386 | { | |
387 | /* | |
388 | * If single step is active for this thread, then set SPSR.SS | |
389 | * to 1 to avoid returning to the active-pending state. | |
390 | */ | |
391 | if (test_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP)) | |
392 | set_regs_spsr_ss(task_pt_regs(task)); | |
393 | } | |
394 | ||
395 | void user_fastforward_single_step(struct task_struct *task) | |
396 | { | |
397 | if (test_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP)) | |
398 | clear_regs_spsr_ss(task_pt_regs(task)); | |
399 | } | |
400 | ||
401 | /* Kernel API */ | |
402 | void kernel_enable_single_step(struct pt_regs *regs) | |
403 | { | |
404 | WARN_ON(!irqs_disabled()); | |
405 | set_regs_spsr_ss(regs); | |
406 | mdscr_write(mdscr_read() | DBG_MDSCR_SS); | |
407 | enable_debug_monitors(DBG_ACTIVE_EL1); | |
408 | } | |
409 | ||
410 | void kernel_disable_single_step(void) | |
411 | { | |
412 | WARN_ON(!irqs_disabled()); | |
413 | mdscr_write(mdscr_read() & ~DBG_MDSCR_SS); | |
414 | disable_debug_monitors(DBG_ACTIVE_EL1); | |
415 | } | |
416 | ||
417 | int kernel_active_single_step(void) | |
418 | { | |
419 | WARN_ON(!irqs_disabled()); | |
420 | return mdscr_read() & DBG_MDSCR_SS; | |
421 | } | |
422 | ||
423 | /* ptrace API */ | |
424 | void user_enable_single_step(struct task_struct *task) | |
425 | { | |
426 | set_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP); | |
427 | set_regs_spsr_ss(task_pt_regs(task)); | |
428 | } | |
429 | ||
430 | void user_disable_single_step(struct task_struct *task) | |
431 | { | |
432 | clear_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP); | |
433 | } |