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60ffc30d CM |
1 | /* |
2 | * Low-level exception handling code | |
3 | * | |
4 | * Copyright (C) 2012 ARM Ltd. | |
5 | * Authors: Catalin Marinas <catalin.marinas@arm.com> | |
6 | * Will Deacon <will.deacon@arm.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include <linux/init.h> | |
22 | #include <linux/linkage.h> | |
23 | ||
8d883b23 | 24 | #include <asm/alternative.h> |
60ffc30d CM |
25 | #include <asm/assembler.h> |
26 | #include <asm/asm-offsets.h> | |
905e8c5d | 27 | #include <asm/cpufeature.h> |
60ffc30d | 28 | #include <asm/errno.h> |
5c1ce6f7 | 29 | #include <asm/esr.h> |
8e23dacd | 30 | #include <asm/irq.h> |
e19a6ee2 | 31 | #include <asm/memory.h> |
39bc88e5 | 32 | #include <asm/ptrace.h> |
60ffc30d | 33 | #include <asm/thread_info.h> |
b4b8664d | 34 | #include <asm/asm-uaccess.h> |
60ffc30d CM |
35 | #include <asm/unistd.h> |
36 | ||
6c81fe79 LB |
37 | /* |
38 | * Context tracking subsystem. Used to instrument transitions | |
39 | * between user and kernel mode. | |
40 | */ | |
41 | .macro ct_user_exit, syscall = 0 | |
42 | #ifdef CONFIG_CONTEXT_TRACKING | |
43 | bl context_tracking_user_exit | |
44 | .if \syscall == 1 | |
45 | /* | |
46 | * Save/restore needed during syscalls. Restore syscall arguments from | |
47 | * the values already saved on stack during kernel_entry. | |
48 | */ | |
49 | ldp x0, x1, [sp] | |
50 | ldp x2, x3, [sp, #S_X2] | |
51 | ldp x4, x5, [sp, #S_X4] | |
52 | ldp x6, x7, [sp, #S_X6] | |
53 | .endif | |
54 | #endif | |
55 | .endm | |
56 | ||
57 | .macro ct_user_enter | |
58 | #ifdef CONFIG_CONTEXT_TRACKING | |
59 | bl context_tracking_user_enter | |
60 | #endif | |
61 | .endm | |
62 | ||
60ffc30d CM |
63 | /* |
64 | * Bad Abort numbers | |
65 | *----------------- | |
66 | */ | |
67 | #define BAD_SYNC 0 | |
68 | #define BAD_IRQ 1 | |
69 | #define BAD_FIQ 2 | |
70 | #define BAD_ERROR 3 | |
71 | ||
b11e5759 MR |
72 | .macro kernel_ventry label |
73 | .align 7 | |
63648dd2 | 74 | sub sp, sp, #S_FRAME_SIZE |
b11e5759 MR |
75 | b \label |
76 | .endm | |
77 | ||
78 | .macro kernel_entry, el, regsize = 64 | |
60ffc30d CM |
79 | .if \regsize == 32 |
80 | mov w0, w0 // zero upper 32 bits of x0 | |
81 | .endif | |
63648dd2 WD |
82 | stp x0, x1, [sp, #16 * 0] |
83 | stp x2, x3, [sp, #16 * 1] | |
84 | stp x4, x5, [sp, #16 * 2] | |
85 | stp x6, x7, [sp, #16 * 3] | |
86 | stp x8, x9, [sp, #16 * 4] | |
87 | stp x10, x11, [sp, #16 * 5] | |
88 | stp x12, x13, [sp, #16 * 6] | |
89 | stp x14, x15, [sp, #16 * 7] | |
90 | stp x16, x17, [sp, #16 * 8] | |
91 | stp x18, x19, [sp, #16 * 9] | |
92 | stp x20, x21, [sp, #16 * 10] | |
93 | stp x22, x23, [sp, #16 * 11] | |
94 | stp x24, x25, [sp, #16 * 12] | |
95 | stp x26, x27, [sp, #16 * 13] | |
96 | stp x28, x29, [sp, #16 * 14] | |
97 | ||
60ffc30d CM |
98 | .if \el == 0 |
99 | mrs x21, sp_el0 | |
c02433dd MR |
100 | ldr_this_cpu tsk, __entry_task, x20 // Ensure MDSCR_EL1.SS is clear, |
101 | ldr x19, [tsk, #TSK_TI_FLAGS] // since we can unmask debug | |
2a283070 | 102 | disable_step_tsk x19, x20 // exceptions when scheduling. |
49003a8d JM |
103 | |
104 | mov x29, xzr // fp pointed to user-space | |
60ffc30d CM |
105 | .else |
106 | add x21, sp, #S_FRAME_SIZE | |
e19a6ee2 JM |
107 | get_thread_info tsk |
108 | /* Save the task's original addr_limit and set USER_DS (TASK_SIZE_64) */ | |
c02433dd | 109 | ldr x20, [tsk, #TSK_TI_ADDR_LIMIT] |
e19a6ee2 JM |
110 | str x20, [sp, #S_ORIG_ADDR_LIMIT] |
111 | mov x20, #TASK_SIZE_64 | |
c02433dd | 112 | str x20, [tsk, #TSK_TI_ADDR_LIMIT] |
563cada0 | 113 | /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */ |
e19a6ee2 | 114 | .endif /* \el == 0 */ |
60ffc30d CM |
115 | mrs x22, elr_el1 |
116 | mrs x23, spsr_el1 | |
117 | stp lr, x21, [sp, #S_LR] | |
39bc88e5 | 118 | |
73267498 AB |
119 | /* |
120 | * In order to be able to dump the contents of struct pt_regs at the | |
121 | * time the exception was taken (in case we attempt to walk the call | |
122 | * stack later), chain it together with the stack frames. | |
123 | */ | |
124 | .if \el == 0 | |
125 | stp xzr, xzr, [sp, #S_STACKFRAME] | |
126 | .else | |
127 | stp x29, x22, [sp, #S_STACKFRAME] | |
128 | .endif | |
129 | add x29, sp, #S_STACKFRAME | |
130 | ||
39bc88e5 CM |
131 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN |
132 | /* | |
133 | * Set the TTBR0 PAN bit in SPSR. When the exception is taken from | |
134 | * EL0, there is no need to check the state of TTBR0_EL1 since | |
135 | * accesses are always enabled. | |
136 | * Note that the meaning of this bit differs from the ARMv8.1 PAN | |
137 | * feature as all TTBR0_EL1 accesses are disabled, not just those to | |
138 | * user mappings. | |
139 | */ | |
140 | alternative_if ARM64_HAS_PAN | |
141 | b 1f // skip TTBR0 PAN | |
142 | alternative_else_nop_endif | |
143 | ||
144 | .if \el != 0 | |
145 | mrs x21, ttbr0_el1 | |
146 | tst x21, #0xffff << 48 // Check for the reserved ASID | |
147 | orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR | |
148 | b.eq 1f // TTBR0 access already disabled | |
149 | and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR | |
150 | .endif | |
151 | ||
152 | __uaccess_ttbr0_disable x21 | |
153 | 1: | |
154 | #endif | |
155 | ||
60ffc30d CM |
156 | stp x22, x23, [sp, #S_PC] |
157 | ||
158 | /* | |
159 | * Set syscallno to -1 by default (overridden later if real syscall). | |
160 | */ | |
161 | .if \el == 0 | |
162 | mvn x21, xzr | |
163 | str x21, [sp, #S_SYSCALLNO] | |
164 | .endif | |
165 | ||
6cdf9c7c JL |
166 | /* |
167 | * Set sp_el0 to current thread_info. | |
168 | */ | |
169 | .if \el == 0 | |
170 | msr sp_el0, tsk | |
171 | .endif | |
172 | ||
60ffc30d CM |
173 | /* |
174 | * Registers that may be useful after this macro is invoked: | |
175 | * | |
176 | * x21 - aborted SP | |
177 | * x22 - aborted PC | |
178 | * x23 - aborted PSTATE | |
179 | */ | |
180 | .endm | |
181 | ||
412fcb6c | 182 | .macro kernel_exit, el |
e19a6ee2 JM |
183 | .if \el != 0 |
184 | /* Restore the task's original addr_limit. */ | |
185 | ldr x20, [sp, #S_ORIG_ADDR_LIMIT] | |
c02433dd | 186 | str x20, [tsk, #TSK_TI_ADDR_LIMIT] |
e19a6ee2 JM |
187 | |
188 | /* No need to restore UAO, it will be restored from SPSR_EL1 */ | |
189 | .endif | |
190 | ||
60ffc30d CM |
191 | ldp x21, x22, [sp, #S_PC] // load ELR, SPSR |
192 | .if \el == 0 | |
6c81fe79 | 193 | ct_user_enter |
39bc88e5 CM |
194 | .endif |
195 | ||
196 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN | |
197 | /* | |
198 | * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR | |
199 | * PAN bit checking. | |
200 | */ | |
201 | alternative_if ARM64_HAS_PAN | |
202 | b 2f // skip TTBR0 PAN | |
203 | alternative_else_nop_endif | |
204 | ||
205 | .if \el != 0 | |
206 | tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set | |
207 | .endif | |
208 | ||
209 | __uaccess_ttbr0_enable x0 | |
210 | ||
211 | .if \el == 0 | |
212 | /* | |
213 | * Enable errata workarounds only if returning to user. The only | |
214 | * workaround currently required for TTBR0_EL1 changes are for the | |
215 | * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache | |
216 | * corruption). | |
217 | */ | |
218 | post_ttbr0_update_workaround | |
219 | .endif | |
220 | 1: | |
221 | .if \el != 0 | |
222 | and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit | |
223 | .endif | |
224 | 2: | |
225 | #endif | |
226 | ||
227 | .if \el == 0 | |
60ffc30d | 228 | ldr x23, [sp, #S_SP] // load return stack pointer |
63648dd2 | 229 | msr sp_el0, x23 |
905e8c5d | 230 | #ifdef CONFIG_ARM64_ERRATUM_845719 |
6ba3b554 | 231 | alternative_if ARM64_WORKAROUND_845719 |
e28cabf1 DT |
232 | tbz x22, #4, 1f |
233 | #ifdef CONFIG_PID_IN_CONTEXTIDR | |
234 | mrs x29, contextidr_el1 | |
235 | msr contextidr_el1, x29 | |
905e8c5d | 236 | #else |
e28cabf1 | 237 | msr contextidr_el1, xzr |
905e8c5d | 238 | #endif |
e28cabf1 | 239 | 1: |
6ba3b554 | 240 | alternative_else_nop_endif |
905e8c5d | 241 | #endif |
60ffc30d | 242 | .endif |
39bc88e5 | 243 | |
63648dd2 WD |
244 | msr elr_el1, x21 // set up the return data |
245 | msr spsr_el1, x22 | |
63648dd2 | 246 | ldp x0, x1, [sp, #16 * 0] |
63648dd2 WD |
247 | ldp x2, x3, [sp, #16 * 1] |
248 | ldp x4, x5, [sp, #16 * 2] | |
249 | ldp x6, x7, [sp, #16 * 3] | |
250 | ldp x8, x9, [sp, #16 * 4] | |
251 | ldp x10, x11, [sp, #16 * 5] | |
252 | ldp x12, x13, [sp, #16 * 6] | |
253 | ldp x14, x15, [sp, #16 * 7] | |
254 | ldp x16, x17, [sp, #16 * 8] | |
255 | ldp x18, x19, [sp, #16 * 9] | |
256 | ldp x20, x21, [sp, #16 * 10] | |
257 | ldp x22, x23, [sp, #16 * 11] | |
258 | ldp x24, x25, [sp, #16 * 12] | |
259 | ldp x26, x27, [sp, #16 * 13] | |
260 | ldp x28, x29, [sp, #16 * 14] | |
261 | ldr lr, [sp, #S_LR] | |
262 | add sp, sp, #S_FRAME_SIZE // restore sp | |
60ffc30d CM |
263 | eret // return to kernel |
264 | .endm | |
265 | ||
971c67ce | 266 | .macro irq_stack_entry |
8e23dacd JM |
267 | mov x19, sp // preserve the original sp |
268 | ||
8e23dacd | 269 | /* |
c02433dd MR |
270 | * Compare sp with the base of the task stack. |
271 | * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack, | |
272 | * and should switch to the irq stack. | |
8e23dacd | 273 | */ |
c02433dd MR |
274 | ldr x25, [tsk, TSK_STACK] |
275 | eor x25, x25, x19 | |
276 | and x25, x25, #~(THREAD_SIZE - 1) | |
277 | cbnz x25, 9998f | |
8e23dacd | 278 | |
f60fe78f | 279 | ldr_this_cpu x25, irq_stack_ptr, x26 |
34be98f4 | 280 | mov x26, #IRQ_STACK_SIZE |
8e23dacd | 281 | add x26, x25, x26 |
d224a69e JM |
282 | |
283 | /* switch to the irq stack */ | |
8e23dacd | 284 | mov sp, x26 |
8e23dacd JM |
285 | 9998: |
286 | .endm | |
287 | ||
288 | /* | |
289 | * x19 should be preserved between irq_stack_entry and | |
290 | * irq_stack_exit. | |
291 | */ | |
292 | .macro irq_stack_exit | |
293 | mov sp, x19 | |
294 | .endm | |
295 | ||
60ffc30d CM |
296 | /* |
297 | * These are the registers used in the syscall handler, and allow us to | |
298 | * have in theory up to 7 arguments to a function - x0 to x6. | |
299 | * | |
300 | * x7 is reserved for the system call number in 32-bit mode. | |
301 | */ | |
302 | sc_nr .req x25 // number of system calls | |
303 | scno .req x26 // syscall number | |
304 | stbl .req x27 // syscall table pointer | |
305 | tsk .req x28 // current thread_info | |
306 | ||
307 | /* | |
308 | * Interrupt handling. | |
309 | */ | |
310 | .macro irq_handler | |
8e23dacd | 311 | ldr_l x1, handle_arch_irq |
60ffc30d | 312 | mov x0, sp |
971c67ce | 313 | irq_stack_entry |
60ffc30d | 314 | blr x1 |
8e23dacd | 315 | irq_stack_exit |
60ffc30d CM |
316 | .endm |
317 | ||
318 | .text | |
319 | ||
320 | /* | |
321 | * Exception vectors. | |
322 | */ | |
888b3c87 | 323 | .pushsection ".entry.text", "ax" |
60ffc30d CM |
324 | |
325 | .align 11 | |
326 | ENTRY(vectors) | |
b11e5759 MR |
327 | kernel_ventry el1_sync_invalid // Synchronous EL1t |
328 | kernel_ventry el1_irq_invalid // IRQ EL1t | |
329 | kernel_ventry el1_fiq_invalid // FIQ EL1t | |
330 | kernel_ventry el1_error_invalid // Error EL1t | |
60ffc30d | 331 | |
b11e5759 MR |
332 | kernel_ventry el1_sync // Synchronous EL1h |
333 | kernel_ventry el1_irq // IRQ EL1h | |
334 | kernel_ventry el1_fiq_invalid // FIQ EL1h | |
335 | kernel_ventry el1_error_invalid // Error EL1h | |
60ffc30d | 336 | |
b11e5759 MR |
337 | kernel_ventry el0_sync // Synchronous 64-bit EL0 |
338 | kernel_ventry el0_irq // IRQ 64-bit EL0 | |
339 | kernel_ventry el0_fiq_invalid // FIQ 64-bit EL0 | |
340 | kernel_ventry el0_error_invalid // Error 64-bit EL0 | |
60ffc30d CM |
341 | |
342 | #ifdef CONFIG_COMPAT | |
b11e5759 MR |
343 | kernel_ventry el0_sync_compat // Synchronous 32-bit EL0 |
344 | kernel_ventry el0_irq_compat // IRQ 32-bit EL0 | |
345 | kernel_ventry el0_fiq_invalid_compat // FIQ 32-bit EL0 | |
346 | kernel_ventry el0_error_invalid_compat // Error 32-bit EL0 | |
60ffc30d | 347 | #else |
b11e5759 MR |
348 | kernel_ventry el0_sync_invalid // Synchronous 32-bit EL0 |
349 | kernel_ventry el0_irq_invalid // IRQ 32-bit EL0 | |
350 | kernel_ventry el0_fiq_invalid // FIQ 32-bit EL0 | |
351 | kernel_ventry el0_error_invalid // Error 32-bit EL0 | |
60ffc30d CM |
352 | #endif |
353 | END(vectors) | |
354 | ||
355 | /* | |
356 | * Invalid mode handlers | |
357 | */ | |
358 | .macro inv_entry, el, reason, regsize = 64 | |
b660950c | 359 | kernel_entry \el, \regsize |
60ffc30d CM |
360 | mov x0, sp |
361 | mov x1, #\reason | |
362 | mrs x2, esr_el1 | |
2d0e751a MR |
363 | bl bad_mode |
364 | ASM_BUG() | |
60ffc30d CM |
365 | .endm |
366 | ||
367 | el0_sync_invalid: | |
368 | inv_entry 0, BAD_SYNC | |
369 | ENDPROC(el0_sync_invalid) | |
370 | ||
371 | el0_irq_invalid: | |
372 | inv_entry 0, BAD_IRQ | |
373 | ENDPROC(el0_irq_invalid) | |
374 | ||
375 | el0_fiq_invalid: | |
376 | inv_entry 0, BAD_FIQ | |
377 | ENDPROC(el0_fiq_invalid) | |
378 | ||
379 | el0_error_invalid: | |
380 | inv_entry 0, BAD_ERROR | |
381 | ENDPROC(el0_error_invalid) | |
382 | ||
383 | #ifdef CONFIG_COMPAT | |
384 | el0_fiq_invalid_compat: | |
385 | inv_entry 0, BAD_FIQ, 32 | |
386 | ENDPROC(el0_fiq_invalid_compat) | |
387 | ||
388 | el0_error_invalid_compat: | |
389 | inv_entry 0, BAD_ERROR, 32 | |
390 | ENDPROC(el0_error_invalid_compat) | |
391 | #endif | |
392 | ||
393 | el1_sync_invalid: | |
394 | inv_entry 1, BAD_SYNC | |
395 | ENDPROC(el1_sync_invalid) | |
396 | ||
397 | el1_irq_invalid: | |
398 | inv_entry 1, BAD_IRQ | |
399 | ENDPROC(el1_irq_invalid) | |
400 | ||
401 | el1_fiq_invalid: | |
402 | inv_entry 1, BAD_FIQ | |
403 | ENDPROC(el1_fiq_invalid) | |
404 | ||
405 | el1_error_invalid: | |
406 | inv_entry 1, BAD_ERROR | |
407 | ENDPROC(el1_error_invalid) | |
408 | ||
409 | /* | |
410 | * EL1 mode handlers. | |
411 | */ | |
412 | .align 6 | |
413 | el1_sync: | |
414 | kernel_entry 1 | |
415 | mrs x1, esr_el1 // read the syndrome register | |
aed40e01 MR |
416 | lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class |
417 | cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1 | |
60ffc30d | 418 | b.eq el1_da |
9adeb8e7 LA |
419 | cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1 |
420 | b.eq el1_ia | |
aed40e01 | 421 | cmp x24, #ESR_ELx_EC_SYS64 // configurable trap |
60ffc30d | 422 | b.eq el1_undef |
aed40e01 | 423 | cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception |
60ffc30d | 424 | b.eq el1_sp_pc |
aed40e01 | 425 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
60ffc30d | 426 | b.eq el1_sp_pc |
aed40e01 | 427 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1 |
60ffc30d | 428 | b.eq el1_undef |
aed40e01 | 429 | cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1 |
60ffc30d CM |
430 | b.ge el1_dbg |
431 | b el1_inv | |
9adeb8e7 LA |
432 | |
433 | el1_ia: | |
434 | /* | |
435 | * Fall through to the Data abort case | |
436 | */ | |
60ffc30d CM |
437 | el1_da: |
438 | /* | |
439 | * Data abort handling | |
440 | */ | |
276e9327 | 441 | mrs x3, far_el1 |
2a283070 | 442 | enable_dbg |
60ffc30d CM |
443 | // re-enable interrupts if they were enabled in the aborted context |
444 | tbnz x23, #7, 1f // PSR_I_BIT | |
445 | enable_irq | |
446 | 1: | |
276e9327 | 447 | clear_address_tag x0, x3 |
60ffc30d CM |
448 | mov x2, sp // struct pt_regs |
449 | bl do_mem_abort | |
450 | ||
451 | // disable interrupts before pulling preserved data off the stack | |
452 | disable_irq | |
453 | kernel_exit 1 | |
454 | el1_sp_pc: | |
455 | /* | |
456 | * Stack or PC alignment exception handling | |
457 | */ | |
458 | mrs x0, far_el1 | |
2a283070 | 459 | enable_dbg |
60ffc30d | 460 | mov x2, sp |
2d0e751a MR |
461 | bl do_sp_pc_abort |
462 | ASM_BUG() | |
60ffc30d CM |
463 | el1_undef: |
464 | /* | |
465 | * Undefined instruction | |
466 | */ | |
2a283070 | 467 | enable_dbg |
60ffc30d | 468 | mov x0, sp |
2d0e751a MR |
469 | bl do_undefinstr |
470 | ASM_BUG() | |
60ffc30d CM |
471 | el1_dbg: |
472 | /* | |
473 | * Debug exception handling | |
474 | */ | |
aed40e01 | 475 | cmp x24, #ESR_ELx_EC_BRK64 // if BRK64 |
ee6214ce | 476 | cinc x24, x24, eq // set bit '0' |
60ffc30d CM |
477 | tbz x24, #0, el1_inv // EL1 only |
478 | mrs x0, far_el1 | |
479 | mov x2, sp // struct pt_regs | |
480 | bl do_debug_exception | |
60ffc30d CM |
481 | kernel_exit 1 |
482 | el1_inv: | |
483 | // TODO: add support for undefined instructions in kernel mode | |
2a283070 | 484 | enable_dbg |
60ffc30d | 485 | mov x0, sp |
1b42804d | 486 | mov x2, x1 |
60ffc30d | 487 | mov x1, #BAD_SYNC |
2d0e751a MR |
488 | bl bad_mode |
489 | ASM_BUG() | |
60ffc30d CM |
490 | ENDPROC(el1_sync) |
491 | ||
492 | .align 6 | |
493 | el1_irq: | |
494 | kernel_entry 1 | |
2a283070 | 495 | enable_dbg |
60ffc30d CM |
496 | #ifdef CONFIG_TRACE_IRQFLAGS |
497 | bl trace_hardirqs_off | |
498 | #endif | |
64681787 | 499 | |
60ffc30d | 500 | irq_handler |
64681787 | 501 | |
60ffc30d | 502 | #ifdef CONFIG_PREEMPT |
c02433dd | 503 | ldr w24, [tsk, #TSK_TI_PREEMPT] // get preempt count |
717321fc | 504 | cbnz w24, 1f // preempt count != 0 |
c02433dd | 505 | ldr x0, [tsk, #TSK_TI_FLAGS] // get flags |
60ffc30d CM |
506 | tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling? |
507 | bl el1_preempt | |
508 | 1: | |
509 | #endif | |
510 | #ifdef CONFIG_TRACE_IRQFLAGS | |
511 | bl trace_hardirqs_on | |
512 | #endif | |
513 | kernel_exit 1 | |
514 | ENDPROC(el1_irq) | |
515 | ||
516 | #ifdef CONFIG_PREEMPT | |
517 | el1_preempt: | |
518 | mov x24, lr | |
2a283070 | 519 | 1: bl preempt_schedule_irq // irq en/disable is done inside |
c02433dd | 520 | ldr x0, [tsk, #TSK_TI_FLAGS] // get new tasks TI_FLAGS |
60ffc30d CM |
521 | tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling? |
522 | ret x24 | |
523 | #endif | |
524 | ||
525 | /* | |
526 | * EL0 mode handlers. | |
527 | */ | |
528 | .align 6 | |
529 | el0_sync: | |
530 | kernel_entry 0 | |
531 | mrs x25, esr_el1 // read the syndrome register | |
aed40e01 MR |
532 | lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class |
533 | cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state | |
60ffc30d | 534 | b.eq el0_svc |
aed40e01 | 535 | cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0 |
60ffc30d | 536 | b.eq el0_da |
aed40e01 | 537 | cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0 |
60ffc30d | 538 | b.eq el0_ia |
aed40e01 | 539 | cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access |
60ffc30d | 540 | b.eq el0_fpsimd_acc |
aed40e01 | 541 | cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception |
60ffc30d | 542 | b.eq el0_fpsimd_exc |
aed40e01 | 543 | cmp x24, #ESR_ELx_EC_SYS64 // configurable trap |
7dd01aef | 544 | b.eq el0_sys |
aed40e01 | 545 | cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception |
60ffc30d | 546 | b.eq el0_sp_pc |
aed40e01 | 547 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
60ffc30d | 548 | b.eq el0_sp_pc |
aed40e01 | 549 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0 |
60ffc30d | 550 | b.eq el0_undef |
aed40e01 | 551 | cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0 |
60ffc30d CM |
552 | b.ge el0_dbg |
553 | b el0_inv | |
554 | ||
555 | #ifdef CONFIG_COMPAT | |
556 | .align 6 | |
557 | el0_sync_compat: | |
558 | kernel_entry 0, 32 | |
559 | mrs x25, esr_el1 // read the syndrome register | |
aed40e01 MR |
560 | lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class |
561 | cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state | |
60ffc30d | 562 | b.eq el0_svc_compat |
aed40e01 | 563 | cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0 |
60ffc30d | 564 | b.eq el0_da |
aed40e01 | 565 | cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0 |
60ffc30d | 566 | b.eq el0_ia |
aed40e01 | 567 | cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access |
60ffc30d | 568 | b.eq el0_fpsimd_acc |
aed40e01 | 569 | cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception |
60ffc30d | 570 | b.eq el0_fpsimd_exc |
77f3228f MS |
571 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
572 | b.eq el0_sp_pc | |
aed40e01 | 573 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0 |
60ffc30d | 574 | b.eq el0_undef |
aed40e01 | 575 | cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap |
381cc2b9 | 576 | b.eq el0_undef |
aed40e01 | 577 | cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap |
381cc2b9 | 578 | b.eq el0_undef |
aed40e01 | 579 | cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap |
381cc2b9 | 580 | b.eq el0_undef |
aed40e01 | 581 | cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap |
381cc2b9 | 582 | b.eq el0_undef |
aed40e01 | 583 | cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap |
381cc2b9 | 584 | b.eq el0_undef |
aed40e01 | 585 | cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0 |
60ffc30d CM |
586 | b.ge el0_dbg |
587 | b el0_inv | |
588 | el0_svc_compat: | |
589 | /* | |
590 | * AArch32 syscall handling | |
591 | */ | |
0156411b | 592 | adrp stbl, compat_sys_call_table // load compat syscall table pointer |
60ffc30d CM |
593 | uxtw scno, w7 // syscall number in w7 (r7) |
594 | mov sc_nr, #__NR_compat_syscalls | |
595 | b el0_svc_naked | |
596 | ||
597 | .align 6 | |
598 | el0_irq_compat: | |
599 | kernel_entry 0, 32 | |
600 | b el0_irq_naked | |
601 | #endif | |
602 | ||
603 | el0_da: | |
604 | /* | |
605 | * Data abort handling | |
606 | */ | |
6ab6463a | 607 | mrs x26, far_el1 |
60ffc30d | 608 | // enable interrupts before calling the main handler |
2a283070 | 609 | enable_dbg_and_irq |
6c81fe79 | 610 | ct_user_exit |
276e9327 | 611 | clear_address_tag x0, x26 |
60ffc30d CM |
612 | mov x1, x25 |
613 | mov x2, sp | |
d54e81f9 WD |
614 | bl do_mem_abort |
615 | b ret_to_user | |
60ffc30d CM |
616 | el0_ia: |
617 | /* | |
618 | * Instruction abort handling | |
619 | */ | |
6ab6463a | 620 | mrs x26, far_el1 |
60ffc30d | 621 | // enable interrupts before calling the main handler |
2a283070 | 622 | enable_dbg_and_irq |
6c81fe79 | 623 | ct_user_exit |
6ab6463a | 624 | mov x0, x26 |
541ec870 | 625 | mov x1, x25 |
60ffc30d | 626 | mov x2, sp |
d54e81f9 WD |
627 | bl do_mem_abort |
628 | b ret_to_user | |
60ffc30d CM |
629 | el0_fpsimd_acc: |
630 | /* | |
631 | * Floating Point or Advanced SIMD access | |
632 | */ | |
2a283070 | 633 | enable_dbg |
6c81fe79 | 634 | ct_user_exit |
60ffc30d CM |
635 | mov x0, x25 |
636 | mov x1, sp | |
d54e81f9 WD |
637 | bl do_fpsimd_acc |
638 | b ret_to_user | |
60ffc30d CM |
639 | el0_fpsimd_exc: |
640 | /* | |
641 | * Floating Point or Advanced SIMD exception | |
642 | */ | |
2a283070 | 643 | enable_dbg |
6c81fe79 | 644 | ct_user_exit |
60ffc30d CM |
645 | mov x0, x25 |
646 | mov x1, sp | |
d54e81f9 WD |
647 | bl do_fpsimd_exc |
648 | b ret_to_user | |
60ffc30d CM |
649 | el0_sp_pc: |
650 | /* | |
651 | * Stack or PC alignment exception handling | |
652 | */ | |
6ab6463a | 653 | mrs x26, far_el1 |
60ffc30d | 654 | // enable interrupts before calling the main handler |
2a283070 | 655 | enable_dbg_and_irq |
46b0567c | 656 | ct_user_exit |
6ab6463a | 657 | mov x0, x26 |
60ffc30d CM |
658 | mov x1, x25 |
659 | mov x2, sp | |
d54e81f9 WD |
660 | bl do_sp_pc_abort |
661 | b ret_to_user | |
60ffc30d CM |
662 | el0_undef: |
663 | /* | |
664 | * Undefined instruction | |
665 | */ | |
2600e130 | 666 | // enable interrupts before calling the main handler |
2a283070 | 667 | enable_dbg_and_irq |
6c81fe79 | 668 | ct_user_exit |
2a283070 | 669 | mov x0, sp |
d54e81f9 WD |
670 | bl do_undefinstr |
671 | b ret_to_user | |
7dd01aef AP |
672 | el0_sys: |
673 | /* | |
674 | * System instructions, for trapped cache maintenance instructions | |
675 | */ | |
676 | enable_dbg_and_irq | |
677 | ct_user_exit | |
678 | mov x0, x25 | |
679 | mov x1, sp | |
680 | bl do_sysinstr | |
681 | b ret_to_user | |
60ffc30d CM |
682 | el0_dbg: |
683 | /* | |
684 | * Debug exception handling | |
685 | */ | |
686 | tbnz x24, #0, el0_inv // EL0 only | |
687 | mrs x0, far_el1 | |
60ffc30d CM |
688 | mov x1, x25 |
689 | mov x2, sp | |
2a283070 WD |
690 | bl do_debug_exception |
691 | enable_dbg | |
6c81fe79 | 692 | ct_user_exit |
2a283070 | 693 | b ret_to_user |
60ffc30d | 694 | el0_inv: |
2a283070 | 695 | enable_dbg |
6c81fe79 | 696 | ct_user_exit |
60ffc30d CM |
697 | mov x0, sp |
698 | mov x1, #BAD_SYNC | |
1b42804d | 699 | mov x2, x25 |
7d9e8f71 | 700 | bl bad_el0_sync |
d54e81f9 | 701 | b ret_to_user |
60ffc30d CM |
702 | ENDPROC(el0_sync) |
703 | ||
704 | .align 6 | |
705 | el0_irq: | |
706 | kernel_entry 0 | |
707 | el0_irq_naked: | |
60ffc30d CM |
708 | enable_dbg |
709 | #ifdef CONFIG_TRACE_IRQFLAGS | |
710 | bl trace_hardirqs_off | |
711 | #endif | |
64681787 | 712 | |
6c81fe79 | 713 | ct_user_exit |
60ffc30d | 714 | irq_handler |
64681787 | 715 | |
60ffc30d CM |
716 | #ifdef CONFIG_TRACE_IRQFLAGS |
717 | bl trace_hardirqs_on | |
718 | #endif | |
719 | b ret_to_user | |
720 | ENDPROC(el0_irq) | |
721 | ||
60ffc30d CM |
722 | /* |
723 | * This is the fast syscall return path. We do as little as possible here, | |
724 | * and this includes saving x0 back into the kernel stack. | |
725 | */ | |
726 | ret_fast_syscall: | |
727 | disable_irq // disable interrupts | |
412fcb6c | 728 | str x0, [sp, #S_X0] // returned x0 |
c02433dd | 729 | ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for syscall tracing |
04d7e098 JS |
730 | and x2, x1, #_TIF_SYSCALL_WORK |
731 | cbnz x2, ret_fast_syscall_trace | |
60ffc30d | 732 | and x2, x1, #_TIF_WORK_MASK |
412fcb6c | 733 | cbnz x2, work_pending |
2a283070 | 734 | enable_step_tsk x1, x2 |
412fcb6c | 735 | kernel_exit 0 |
04d7e098 JS |
736 | ret_fast_syscall_trace: |
737 | enable_irq // enable interrupts | |
412fcb6c | 738 | b __sys_trace_return_skipped // we already saved x0 |
60ffc30d CM |
739 | |
740 | /* | |
741 | * Ok, we need to do extra processing, enter the slow path. | |
742 | */ | |
60ffc30d | 743 | work_pending: |
60ffc30d | 744 | mov x0, sp // 'regs' |
60ffc30d | 745 | bl do_notify_resume |
db3899a6 | 746 | #ifdef CONFIG_TRACE_IRQFLAGS |
421dd6fa | 747 | bl trace_hardirqs_on // enabled while in userspace |
db3899a6 | 748 | #endif |
c02433dd | 749 | ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for single-step |
421dd6fa | 750 | b finish_ret_to_user |
60ffc30d CM |
751 | /* |
752 | * "slow" syscall return path. | |
753 | */ | |
59dc67b0 | 754 | ret_to_user: |
60ffc30d | 755 | disable_irq // disable interrupts |
c02433dd | 756 | ldr x1, [tsk, #TSK_TI_FLAGS] |
60ffc30d CM |
757 | and x2, x1, #_TIF_WORK_MASK |
758 | cbnz x2, work_pending | |
421dd6fa | 759 | finish_ret_to_user: |
2a283070 | 760 | enable_step_tsk x1, x2 |
412fcb6c | 761 | kernel_exit 0 |
60ffc30d CM |
762 | ENDPROC(ret_to_user) |
763 | ||
60ffc30d CM |
764 | /* |
765 | * SVC handler. | |
766 | */ | |
767 | .align 6 | |
768 | el0_svc: | |
769 | adrp stbl, sys_call_table // load syscall table pointer | |
770 | uxtw scno, w8 // syscall number in w8 | |
771 | mov sc_nr, #__NR_syscalls | |
772 | el0_svc_naked: // compat entry point | |
773 | stp x0, scno, [sp, #S_ORIG_X0] // save the original x0 and syscall number | |
2a283070 | 774 | enable_dbg_and_irq |
6c81fe79 | 775 | ct_user_exit 1 |
60ffc30d | 776 | |
c02433dd | 777 | ldr x16, [tsk, #TSK_TI_FLAGS] // check for syscall hooks |
449f81a4 AT |
778 | tst x16, #_TIF_SYSCALL_WORK |
779 | b.ne __sys_trace | |
60ffc30d CM |
780 | cmp scno, sc_nr // check upper syscall limit |
781 | b.hs ni_sys | |
782 | ldr x16, [stbl, scno, lsl #3] // address in the syscall table | |
d54e81f9 WD |
783 | blr x16 // call sys_* routine |
784 | b ret_fast_syscall | |
60ffc30d CM |
785 | ni_sys: |
786 | mov x0, sp | |
d54e81f9 WD |
787 | bl do_ni_syscall |
788 | b ret_fast_syscall | |
60ffc30d CM |
789 | ENDPROC(el0_svc) |
790 | ||
791 | /* | |
792 | * This is the really slow path. We're going to be doing context | |
793 | * switches, and waiting for our parent to respond. | |
794 | */ | |
795 | __sys_trace: | |
1014c81d AT |
796 | mov w0, #-1 // set default errno for |
797 | cmp scno, x0 // user-issued syscall(-1) | |
798 | b.ne 1f | |
799 | mov x0, #-ENOSYS | |
800 | str x0, [sp, #S_X0] | |
801 | 1: mov x0, sp | |
3157858f | 802 | bl syscall_trace_enter |
1014c81d AT |
803 | cmp w0, #-1 // skip the syscall? |
804 | b.eq __sys_trace_return_skipped | |
60ffc30d CM |
805 | uxtw scno, w0 // syscall number (possibly new) |
806 | mov x1, sp // pointer to regs | |
807 | cmp scno, sc_nr // check upper syscall limit | |
d54e81f9 | 808 | b.hs __ni_sys_trace |
60ffc30d CM |
809 | ldp x0, x1, [sp] // restore the syscall args |
810 | ldp x2, x3, [sp, #S_X2] | |
811 | ldp x4, x5, [sp, #S_X4] | |
812 | ldp x6, x7, [sp, #S_X6] | |
813 | ldr x16, [stbl, scno, lsl #3] // address in the syscall table | |
d54e81f9 | 814 | blr x16 // call sys_* routine |
60ffc30d CM |
815 | |
816 | __sys_trace_return: | |
1014c81d AT |
817 | str x0, [sp, #S_X0] // save returned x0 |
818 | __sys_trace_return_skipped: | |
3157858f AT |
819 | mov x0, sp |
820 | bl syscall_trace_exit | |
60ffc30d CM |
821 | b ret_to_user |
822 | ||
d54e81f9 WD |
823 | __ni_sys_trace: |
824 | mov x0, sp | |
825 | bl do_ni_syscall | |
826 | b __sys_trace_return | |
827 | ||
888b3c87 PA |
828 | .popsection // .entry.text |
829 | ||
60ffc30d CM |
830 | /* |
831 | * Special system call wrappers. | |
832 | */ | |
60ffc30d CM |
833 | ENTRY(sys_rt_sigreturn_wrapper) |
834 | mov x0, sp | |
835 | b sys_rt_sigreturn | |
836 | ENDPROC(sys_rt_sigreturn_wrapper) | |
ed84b4e9 MR |
837 | |
838 | /* | |
839 | * Register switch for AArch64. The callee-saved registers need to be saved | |
840 | * and restored. On entry: | |
841 | * x0 = previous task_struct (must be preserved across the switch) | |
842 | * x1 = next task_struct | |
843 | * Previous and next are guaranteed not to be the same. | |
844 | * | |
845 | */ | |
846 | ENTRY(cpu_switch_to) | |
847 | mov x10, #THREAD_CPU_CONTEXT | |
848 | add x8, x0, x10 | |
849 | mov x9, sp | |
850 | stp x19, x20, [x8], #16 // store callee-saved registers | |
851 | stp x21, x22, [x8], #16 | |
852 | stp x23, x24, [x8], #16 | |
853 | stp x25, x26, [x8], #16 | |
854 | stp x27, x28, [x8], #16 | |
855 | stp x29, x9, [x8], #16 | |
856 | str lr, [x8] | |
857 | add x8, x1, x10 | |
858 | ldp x19, x20, [x8], #16 // restore callee-saved registers | |
859 | ldp x21, x22, [x8], #16 | |
860 | ldp x23, x24, [x8], #16 | |
861 | ldp x25, x26, [x8], #16 | |
862 | ldp x27, x28, [x8], #16 | |
863 | ldp x29, x9, [x8], #16 | |
864 | ldr lr, [x8] | |
865 | mov sp, x9 | |
866 | msr sp_el0, x1 | |
867 | ret | |
868 | ENDPROC(cpu_switch_to) | |
869 | NOKPROBE(cpu_switch_to) | |
870 | ||
871 | /* | |
872 | * This is how we return from a fork. | |
873 | */ | |
874 | ENTRY(ret_from_fork) | |
875 | bl schedule_tail | |
876 | cbz x19, 1f // not a kernel thread | |
877 | mov x0, x20 | |
878 | blr x19 | |
879 | 1: get_thread_info tsk | |
880 | b ret_to_user | |
881 | ENDPROC(ret_from_fork) | |
882 | NOKPROBE(ret_from_fork) |