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60ffc30d CM |
1 | /* |
2 | * Low-level exception handling code | |
3 | * | |
4 | * Copyright (C) 2012 ARM Ltd. | |
5 | * Authors: Catalin Marinas <catalin.marinas@arm.com> | |
6 | * Will Deacon <will.deacon@arm.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include <linux/init.h> | |
22 | #include <linux/linkage.h> | |
23 | ||
8d883b23 | 24 | #include <asm/alternative.h> |
60ffc30d CM |
25 | #include <asm/assembler.h> |
26 | #include <asm/asm-offsets.h> | |
905e8c5d | 27 | #include <asm/cpufeature.h> |
60ffc30d | 28 | #include <asm/errno.h> |
5c1ce6f7 | 29 | #include <asm/esr.h> |
8e23dacd | 30 | #include <asm/irq.h> |
e19a6ee2 | 31 | #include <asm/memory.h> |
60ffc30d CM |
32 | #include <asm/thread_info.h> |
33 | #include <asm/unistd.h> | |
34 | ||
6c81fe79 LB |
35 | /* |
36 | * Context tracking subsystem. Used to instrument transitions | |
37 | * between user and kernel mode. | |
38 | */ | |
39 | .macro ct_user_exit, syscall = 0 | |
40 | #ifdef CONFIG_CONTEXT_TRACKING | |
41 | bl context_tracking_user_exit | |
42 | .if \syscall == 1 | |
43 | /* | |
44 | * Save/restore needed during syscalls. Restore syscall arguments from | |
45 | * the values already saved on stack during kernel_entry. | |
46 | */ | |
47 | ldp x0, x1, [sp] | |
48 | ldp x2, x3, [sp, #S_X2] | |
49 | ldp x4, x5, [sp, #S_X4] | |
50 | ldp x6, x7, [sp, #S_X6] | |
51 | .endif | |
52 | #endif | |
53 | .endm | |
54 | ||
55 | .macro ct_user_enter | |
56 | #ifdef CONFIG_CONTEXT_TRACKING | |
57 | bl context_tracking_user_enter | |
58 | #endif | |
59 | .endm | |
60 | ||
60ffc30d CM |
61 | /* |
62 | * Bad Abort numbers | |
63 | *----------------- | |
64 | */ | |
65 | #define BAD_SYNC 0 | |
66 | #define BAD_IRQ 1 | |
67 | #define BAD_FIQ 2 | |
68 | #define BAD_ERROR 3 | |
69 | ||
70 | .macro kernel_entry, el, regsize = 64 | |
63648dd2 | 71 | sub sp, sp, #S_FRAME_SIZE |
60ffc30d CM |
72 | .if \regsize == 32 |
73 | mov w0, w0 // zero upper 32 bits of x0 | |
74 | .endif | |
63648dd2 WD |
75 | stp x0, x1, [sp, #16 * 0] |
76 | stp x2, x3, [sp, #16 * 1] | |
77 | stp x4, x5, [sp, #16 * 2] | |
78 | stp x6, x7, [sp, #16 * 3] | |
79 | stp x8, x9, [sp, #16 * 4] | |
80 | stp x10, x11, [sp, #16 * 5] | |
81 | stp x12, x13, [sp, #16 * 6] | |
82 | stp x14, x15, [sp, #16 * 7] | |
83 | stp x16, x17, [sp, #16 * 8] | |
84 | stp x18, x19, [sp, #16 * 9] | |
85 | stp x20, x21, [sp, #16 * 10] | |
86 | stp x22, x23, [sp, #16 * 11] | |
87 | stp x24, x25, [sp, #16 * 12] | |
88 | stp x26, x27, [sp, #16 * 13] | |
89 | stp x28, x29, [sp, #16 * 14] | |
90 | ||
60ffc30d CM |
91 | .if \el == 0 |
92 | mrs x21, sp_el0 | |
c02433dd MR |
93 | ldr_this_cpu tsk, __entry_task, x20 // Ensure MDSCR_EL1.SS is clear, |
94 | ldr x19, [tsk, #TSK_TI_FLAGS] // since we can unmask debug | |
2a283070 | 95 | disable_step_tsk x19, x20 // exceptions when scheduling. |
49003a8d JM |
96 | |
97 | mov x29, xzr // fp pointed to user-space | |
60ffc30d CM |
98 | .else |
99 | add x21, sp, #S_FRAME_SIZE | |
e19a6ee2 JM |
100 | get_thread_info tsk |
101 | /* Save the task's original addr_limit and set USER_DS (TASK_SIZE_64) */ | |
c02433dd | 102 | ldr x20, [tsk, #TSK_TI_ADDR_LIMIT] |
e19a6ee2 JM |
103 | str x20, [sp, #S_ORIG_ADDR_LIMIT] |
104 | mov x20, #TASK_SIZE_64 | |
c02433dd | 105 | str x20, [tsk, #TSK_TI_ADDR_LIMIT] |
563cada0 | 106 | /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */ |
e19a6ee2 | 107 | .endif /* \el == 0 */ |
60ffc30d CM |
108 | mrs x22, elr_el1 |
109 | mrs x23, spsr_el1 | |
110 | stp lr, x21, [sp, #S_LR] | |
111 | stp x22, x23, [sp, #S_PC] | |
112 | ||
113 | /* | |
114 | * Set syscallno to -1 by default (overridden later if real syscall). | |
115 | */ | |
116 | .if \el == 0 | |
117 | mvn x21, xzr | |
118 | str x21, [sp, #S_SYSCALLNO] | |
119 | .endif | |
120 | ||
6cdf9c7c JL |
121 | /* |
122 | * Set sp_el0 to current thread_info. | |
123 | */ | |
124 | .if \el == 0 | |
125 | msr sp_el0, tsk | |
126 | .endif | |
127 | ||
60ffc30d CM |
128 | /* |
129 | * Registers that may be useful after this macro is invoked: | |
130 | * | |
131 | * x21 - aborted SP | |
132 | * x22 - aborted PC | |
133 | * x23 - aborted PSTATE | |
134 | */ | |
135 | .endm | |
136 | ||
412fcb6c | 137 | .macro kernel_exit, el |
e19a6ee2 JM |
138 | .if \el != 0 |
139 | /* Restore the task's original addr_limit. */ | |
140 | ldr x20, [sp, #S_ORIG_ADDR_LIMIT] | |
c02433dd | 141 | str x20, [tsk, #TSK_TI_ADDR_LIMIT] |
e19a6ee2 JM |
142 | |
143 | /* No need to restore UAO, it will be restored from SPSR_EL1 */ | |
144 | .endif | |
145 | ||
60ffc30d CM |
146 | ldp x21, x22, [sp, #S_PC] // load ELR, SPSR |
147 | .if \el == 0 | |
6c81fe79 | 148 | ct_user_enter |
60ffc30d | 149 | ldr x23, [sp, #S_SP] // load return stack pointer |
63648dd2 | 150 | msr sp_el0, x23 |
905e8c5d | 151 | #ifdef CONFIG_ARM64_ERRATUM_845719 |
6ba3b554 | 152 | alternative_if ARM64_WORKAROUND_845719 |
e28cabf1 DT |
153 | tbz x22, #4, 1f |
154 | #ifdef CONFIG_PID_IN_CONTEXTIDR | |
155 | mrs x29, contextidr_el1 | |
156 | msr contextidr_el1, x29 | |
905e8c5d | 157 | #else |
e28cabf1 | 158 | msr contextidr_el1, xzr |
905e8c5d | 159 | #endif |
e28cabf1 | 160 | 1: |
6ba3b554 | 161 | alternative_else_nop_endif |
905e8c5d | 162 | #endif |
60ffc30d | 163 | .endif |
63648dd2 WD |
164 | msr elr_el1, x21 // set up the return data |
165 | msr spsr_el1, x22 | |
63648dd2 | 166 | ldp x0, x1, [sp, #16 * 0] |
63648dd2 WD |
167 | ldp x2, x3, [sp, #16 * 1] |
168 | ldp x4, x5, [sp, #16 * 2] | |
169 | ldp x6, x7, [sp, #16 * 3] | |
170 | ldp x8, x9, [sp, #16 * 4] | |
171 | ldp x10, x11, [sp, #16 * 5] | |
172 | ldp x12, x13, [sp, #16 * 6] | |
173 | ldp x14, x15, [sp, #16 * 7] | |
174 | ldp x16, x17, [sp, #16 * 8] | |
175 | ldp x18, x19, [sp, #16 * 9] | |
176 | ldp x20, x21, [sp, #16 * 10] | |
177 | ldp x22, x23, [sp, #16 * 11] | |
178 | ldp x24, x25, [sp, #16 * 12] | |
179 | ldp x26, x27, [sp, #16 * 13] | |
180 | ldp x28, x29, [sp, #16 * 14] | |
181 | ldr lr, [sp, #S_LR] | |
182 | add sp, sp, #S_FRAME_SIZE // restore sp | |
60ffc30d CM |
183 | eret // return to kernel |
184 | .endm | |
185 | ||
971c67ce | 186 | .macro irq_stack_entry |
8e23dacd JM |
187 | mov x19, sp // preserve the original sp |
188 | ||
8e23dacd | 189 | /* |
c02433dd MR |
190 | * Compare sp with the base of the task stack. |
191 | * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack, | |
192 | * and should switch to the irq stack. | |
8e23dacd | 193 | */ |
c02433dd MR |
194 | ldr x25, [tsk, TSK_STACK] |
195 | eor x25, x25, x19 | |
196 | and x25, x25, #~(THREAD_SIZE - 1) | |
197 | cbnz x25, 9998f | |
8e23dacd | 198 | |
1b7e2296 | 199 | adr_this_cpu x25, irq_stack, x26 |
8e23dacd JM |
200 | mov x26, #IRQ_STACK_START_SP |
201 | add x26, x25, x26 | |
d224a69e JM |
202 | |
203 | /* switch to the irq stack */ | |
8e23dacd JM |
204 | mov sp, x26 |
205 | ||
971c67ce JM |
206 | /* |
207 | * Add a dummy stack frame, this non-standard format is fixed up | |
208 | * by unwind_frame() | |
209 | */ | |
210 | stp x29, x19, [sp, #-16]! | |
8e23dacd | 211 | mov x29, sp |
8e23dacd JM |
212 | |
213 | 9998: | |
214 | .endm | |
215 | ||
216 | /* | |
217 | * x19 should be preserved between irq_stack_entry and | |
218 | * irq_stack_exit. | |
219 | */ | |
220 | .macro irq_stack_exit | |
221 | mov sp, x19 | |
222 | .endm | |
223 | ||
60ffc30d CM |
224 | /* |
225 | * These are the registers used in the syscall handler, and allow us to | |
226 | * have in theory up to 7 arguments to a function - x0 to x6. | |
227 | * | |
228 | * x7 is reserved for the system call number in 32-bit mode. | |
229 | */ | |
230 | sc_nr .req x25 // number of system calls | |
231 | scno .req x26 // syscall number | |
232 | stbl .req x27 // syscall table pointer | |
233 | tsk .req x28 // current thread_info | |
234 | ||
235 | /* | |
236 | * Interrupt handling. | |
237 | */ | |
238 | .macro irq_handler | |
8e23dacd | 239 | ldr_l x1, handle_arch_irq |
60ffc30d | 240 | mov x0, sp |
971c67ce | 241 | irq_stack_entry |
60ffc30d | 242 | blr x1 |
8e23dacd | 243 | irq_stack_exit |
60ffc30d CM |
244 | .endm |
245 | ||
246 | .text | |
247 | ||
248 | /* | |
249 | * Exception vectors. | |
250 | */ | |
888b3c87 | 251 | .pushsection ".entry.text", "ax" |
60ffc30d CM |
252 | |
253 | .align 11 | |
254 | ENTRY(vectors) | |
255 | ventry el1_sync_invalid // Synchronous EL1t | |
256 | ventry el1_irq_invalid // IRQ EL1t | |
257 | ventry el1_fiq_invalid // FIQ EL1t | |
258 | ventry el1_error_invalid // Error EL1t | |
259 | ||
260 | ventry el1_sync // Synchronous EL1h | |
261 | ventry el1_irq // IRQ EL1h | |
262 | ventry el1_fiq_invalid // FIQ EL1h | |
263 | ventry el1_error_invalid // Error EL1h | |
264 | ||
265 | ventry el0_sync // Synchronous 64-bit EL0 | |
266 | ventry el0_irq // IRQ 64-bit EL0 | |
267 | ventry el0_fiq_invalid // FIQ 64-bit EL0 | |
268 | ventry el0_error_invalid // Error 64-bit EL0 | |
269 | ||
270 | #ifdef CONFIG_COMPAT | |
271 | ventry el0_sync_compat // Synchronous 32-bit EL0 | |
272 | ventry el0_irq_compat // IRQ 32-bit EL0 | |
273 | ventry el0_fiq_invalid_compat // FIQ 32-bit EL0 | |
274 | ventry el0_error_invalid_compat // Error 32-bit EL0 | |
275 | #else | |
276 | ventry el0_sync_invalid // Synchronous 32-bit EL0 | |
277 | ventry el0_irq_invalid // IRQ 32-bit EL0 | |
278 | ventry el0_fiq_invalid // FIQ 32-bit EL0 | |
279 | ventry el0_error_invalid // Error 32-bit EL0 | |
280 | #endif | |
281 | END(vectors) | |
282 | ||
283 | /* | |
284 | * Invalid mode handlers | |
285 | */ | |
286 | .macro inv_entry, el, reason, regsize = 64 | |
b660950c | 287 | kernel_entry \el, \regsize |
60ffc30d CM |
288 | mov x0, sp |
289 | mov x1, #\reason | |
290 | mrs x2, esr_el1 | |
291 | b bad_mode | |
292 | .endm | |
293 | ||
294 | el0_sync_invalid: | |
295 | inv_entry 0, BAD_SYNC | |
296 | ENDPROC(el0_sync_invalid) | |
297 | ||
298 | el0_irq_invalid: | |
299 | inv_entry 0, BAD_IRQ | |
300 | ENDPROC(el0_irq_invalid) | |
301 | ||
302 | el0_fiq_invalid: | |
303 | inv_entry 0, BAD_FIQ | |
304 | ENDPROC(el0_fiq_invalid) | |
305 | ||
306 | el0_error_invalid: | |
307 | inv_entry 0, BAD_ERROR | |
308 | ENDPROC(el0_error_invalid) | |
309 | ||
310 | #ifdef CONFIG_COMPAT | |
311 | el0_fiq_invalid_compat: | |
312 | inv_entry 0, BAD_FIQ, 32 | |
313 | ENDPROC(el0_fiq_invalid_compat) | |
314 | ||
315 | el0_error_invalid_compat: | |
316 | inv_entry 0, BAD_ERROR, 32 | |
317 | ENDPROC(el0_error_invalid_compat) | |
318 | #endif | |
319 | ||
320 | el1_sync_invalid: | |
321 | inv_entry 1, BAD_SYNC | |
322 | ENDPROC(el1_sync_invalid) | |
323 | ||
324 | el1_irq_invalid: | |
325 | inv_entry 1, BAD_IRQ | |
326 | ENDPROC(el1_irq_invalid) | |
327 | ||
328 | el1_fiq_invalid: | |
329 | inv_entry 1, BAD_FIQ | |
330 | ENDPROC(el1_fiq_invalid) | |
331 | ||
332 | el1_error_invalid: | |
333 | inv_entry 1, BAD_ERROR | |
334 | ENDPROC(el1_error_invalid) | |
335 | ||
336 | /* | |
337 | * EL1 mode handlers. | |
338 | */ | |
339 | .align 6 | |
340 | el1_sync: | |
341 | kernel_entry 1 | |
342 | mrs x1, esr_el1 // read the syndrome register | |
aed40e01 MR |
343 | lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class |
344 | cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1 | |
60ffc30d | 345 | b.eq el1_da |
9adeb8e7 LA |
346 | cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1 |
347 | b.eq el1_ia | |
aed40e01 | 348 | cmp x24, #ESR_ELx_EC_SYS64 // configurable trap |
60ffc30d | 349 | b.eq el1_undef |
aed40e01 | 350 | cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception |
60ffc30d | 351 | b.eq el1_sp_pc |
aed40e01 | 352 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
60ffc30d | 353 | b.eq el1_sp_pc |
aed40e01 | 354 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1 |
60ffc30d | 355 | b.eq el1_undef |
aed40e01 | 356 | cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1 |
60ffc30d CM |
357 | b.ge el1_dbg |
358 | b el1_inv | |
9adeb8e7 LA |
359 | |
360 | el1_ia: | |
361 | /* | |
362 | * Fall through to the Data abort case | |
363 | */ | |
60ffc30d CM |
364 | el1_da: |
365 | /* | |
366 | * Data abort handling | |
367 | */ | |
368 | mrs x0, far_el1 | |
2a283070 | 369 | enable_dbg |
60ffc30d CM |
370 | // re-enable interrupts if they were enabled in the aborted context |
371 | tbnz x23, #7, 1f // PSR_I_BIT | |
372 | enable_irq | |
373 | 1: | |
374 | mov x2, sp // struct pt_regs | |
375 | bl do_mem_abort | |
376 | ||
377 | // disable interrupts before pulling preserved data off the stack | |
378 | disable_irq | |
379 | kernel_exit 1 | |
380 | el1_sp_pc: | |
381 | /* | |
382 | * Stack or PC alignment exception handling | |
383 | */ | |
384 | mrs x0, far_el1 | |
2a283070 | 385 | enable_dbg |
60ffc30d CM |
386 | mov x2, sp |
387 | b do_sp_pc_abort | |
388 | el1_undef: | |
389 | /* | |
390 | * Undefined instruction | |
391 | */ | |
2a283070 | 392 | enable_dbg |
60ffc30d CM |
393 | mov x0, sp |
394 | b do_undefinstr | |
395 | el1_dbg: | |
396 | /* | |
397 | * Debug exception handling | |
398 | */ | |
aed40e01 | 399 | cmp x24, #ESR_ELx_EC_BRK64 // if BRK64 |
ee6214ce | 400 | cinc x24, x24, eq // set bit '0' |
60ffc30d CM |
401 | tbz x24, #0, el1_inv // EL1 only |
402 | mrs x0, far_el1 | |
403 | mov x2, sp // struct pt_regs | |
404 | bl do_debug_exception | |
60ffc30d CM |
405 | kernel_exit 1 |
406 | el1_inv: | |
407 | // TODO: add support for undefined instructions in kernel mode | |
2a283070 | 408 | enable_dbg |
60ffc30d | 409 | mov x0, sp |
1b42804d | 410 | mov x2, x1 |
60ffc30d | 411 | mov x1, #BAD_SYNC |
60ffc30d CM |
412 | b bad_mode |
413 | ENDPROC(el1_sync) | |
414 | ||
415 | .align 6 | |
416 | el1_irq: | |
417 | kernel_entry 1 | |
2a283070 | 418 | enable_dbg |
60ffc30d CM |
419 | #ifdef CONFIG_TRACE_IRQFLAGS |
420 | bl trace_hardirqs_off | |
421 | #endif | |
64681787 | 422 | |
60ffc30d | 423 | irq_handler |
64681787 | 424 | |
60ffc30d | 425 | #ifdef CONFIG_PREEMPT |
c02433dd | 426 | ldr w24, [tsk, #TSK_TI_PREEMPT] // get preempt count |
717321fc | 427 | cbnz w24, 1f // preempt count != 0 |
c02433dd | 428 | ldr x0, [tsk, #TSK_TI_FLAGS] // get flags |
60ffc30d CM |
429 | tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling? |
430 | bl el1_preempt | |
431 | 1: | |
432 | #endif | |
433 | #ifdef CONFIG_TRACE_IRQFLAGS | |
434 | bl trace_hardirqs_on | |
435 | #endif | |
436 | kernel_exit 1 | |
437 | ENDPROC(el1_irq) | |
438 | ||
439 | #ifdef CONFIG_PREEMPT | |
440 | el1_preempt: | |
441 | mov x24, lr | |
2a283070 | 442 | 1: bl preempt_schedule_irq // irq en/disable is done inside |
c02433dd | 443 | ldr x0, [tsk, #TSK_TI_FLAGS] // get new tasks TI_FLAGS |
60ffc30d CM |
444 | tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling? |
445 | ret x24 | |
446 | #endif | |
447 | ||
448 | /* | |
449 | * EL0 mode handlers. | |
450 | */ | |
451 | .align 6 | |
452 | el0_sync: | |
453 | kernel_entry 0 | |
454 | mrs x25, esr_el1 // read the syndrome register | |
aed40e01 MR |
455 | lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class |
456 | cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state | |
60ffc30d | 457 | b.eq el0_svc |
aed40e01 | 458 | cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0 |
60ffc30d | 459 | b.eq el0_da |
aed40e01 | 460 | cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0 |
60ffc30d | 461 | b.eq el0_ia |
aed40e01 | 462 | cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access |
60ffc30d | 463 | b.eq el0_fpsimd_acc |
aed40e01 | 464 | cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception |
60ffc30d | 465 | b.eq el0_fpsimd_exc |
aed40e01 | 466 | cmp x24, #ESR_ELx_EC_SYS64 // configurable trap |
7dd01aef | 467 | b.eq el0_sys |
aed40e01 | 468 | cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception |
60ffc30d | 469 | b.eq el0_sp_pc |
aed40e01 | 470 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
60ffc30d | 471 | b.eq el0_sp_pc |
aed40e01 | 472 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0 |
60ffc30d | 473 | b.eq el0_undef |
aed40e01 | 474 | cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0 |
60ffc30d CM |
475 | b.ge el0_dbg |
476 | b el0_inv | |
477 | ||
478 | #ifdef CONFIG_COMPAT | |
479 | .align 6 | |
480 | el0_sync_compat: | |
481 | kernel_entry 0, 32 | |
482 | mrs x25, esr_el1 // read the syndrome register | |
aed40e01 MR |
483 | lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class |
484 | cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state | |
60ffc30d | 485 | b.eq el0_svc_compat |
aed40e01 | 486 | cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0 |
60ffc30d | 487 | b.eq el0_da |
aed40e01 | 488 | cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0 |
60ffc30d | 489 | b.eq el0_ia |
aed40e01 | 490 | cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access |
60ffc30d | 491 | b.eq el0_fpsimd_acc |
aed40e01 | 492 | cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception |
60ffc30d | 493 | b.eq el0_fpsimd_exc |
77f3228f MS |
494 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
495 | b.eq el0_sp_pc | |
aed40e01 | 496 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0 |
60ffc30d | 497 | b.eq el0_undef |
aed40e01 | 498 | cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap |
381cc2b9 | 499 | b.eq el0_undef |
aed40e01 | 500 | cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap |
381cc2b9 | 501 | b.eq el0_undef |
aed40e01 | 502 | cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap |
381cc2b9 | 503 | b.eq el0_undef |
aed40e01 | 504 | cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap |
381cc2b9 | 505 | b.eq el0_undef |
aed40e01 | 506 | cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap |
381cc2b9 | 507 | b.eq el0_undef |
aed40e01 | 508 | cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0 |
60ffc30d CM |
509 | b.ge el0_dbg |
510 | b el0_inv | |
511 | el0_svc_compat: | |
512 | /* | |
513 | * AArch32 syscall handling | |
514 | */ | |
0156411b | 515 | adrp stbl, compat_sys_call_table // load compat syscall table pointer |
60ffc30d CM |
516 | uxtw scno, w7 // syscall number in w7 (r7) |
517 | mov sc_nr, #__NR_compat_syscalls | |
518 | b el0_svc_naked | |
519 | ||
520 | .align 6 | |
521 | el0_irq_compat: | |
522 | kernel_entry 0, 32 | |
523 | b el0_irq_naked | |
524 | #endif | |
525 | ||
526 | el0_da: | |
527 | /* | |
528 | * Data abort handling | |
529 | */ | |
6ab6463a | 530 | mrs x26, far_el1 |
60ffc30d | 531 | // enable interrupts before calling the main handler |
2a283070 | 532 | enable_dbg_and_irq |
6c81fe79 | 533 | ct_user_exit |
6ab6463a | 534 | bic x0, x26, #(0xff << 56) |
60ffc30d CM |
535 | mov x1, x25 |
536 | mov x2, sp | |
d54e81f9 WD |
537 | bl do_mem_abort |
538 | b ret_to_user | |
60ffc30d CM |
539 | el0_ia: |
540 | /* | |
541 | * Instruction abort handling | |
542 | */ | |
6ab6463a | 543 | mrs x26, far_el1 |
60ffc30d | 544 | // enable interrupts before calling the main handler |
2a283070 | 545 | enable_dbg_and_irq |
6c81fe79 | 546 | ct_user_exit |
6ab6463a | 547 | mov x0, x26 |
541ec870 | 548 | mov x1, x25 |
60ffc30d | 549 | mov x2, sp |
d54e81f9 WD |
550 | bl do_mem_abort |
551 | b ret_to_user | |
60ffc30d CM |
552 | el0_fpsimd_acc: |
553 | /* | |
554 | * Floating Point or Advanced SIMD access | |
555 | */ | |
2a283070 | 556 | enable_dbg |
6c81fe79 | 557 | ct_user_exit |
60ffc30d CM |
558 | mov x0, x25 |
559 | mov x1, sp | |
d54e81f9 WD |
560 | bl do_fpsimd_acc |
561 | b ret_to_user | |
60ffc30d CM |
562 | el0_fpsimd_exc: |
563 | /* | |
564 | * Floating Point or Advanced SIMD exception | |
565 | */ | |
2a283070 | 566 | enable_dbg |
6c81fe79 | 567 | ct_user_exit |
60ffc30d CM |
568 | mov x0, x25 |
569 | mov x1, sp | |
d54e81f9 WD |
570 | bl do_fpsimd_exc |
571 | b ret_to_user | |
60ffc30d CM |
572 | el0_sp_pc: |
573 | /* | |
574 | * Stack or PC alignment exception handling | |
575 | */ | |
6ab6463a | 576 | mrs x26, far_el1 |
60ffc30d | 577 | // enable interrupts before calling the main handler |
2a283070 | 578 | enable_dbg_and_irq |
46b0567c | 579 | ct_user_exit |
6ab6463a | 580 | mov x0, x26 |
60ffc30d CM |
581 | mov x1, x25 |
582 | mov x2, sp | |
d54e81f9 WD |
583 | bl do_sp_pc_abort |
584 | b ret_to_user | |
60ffc30d CM |
585 | el0_undef: |
586 | /* | |
587 | * Undefined instruction | |
588 | */ | |
2600e130 | 589 | // enable interrupts before calling the main handler |
2a283070 | 590 | enable_dbg_and_irq |
6c81fe79 | 591 | ct_user_exit |
2a283070 | 592 | mov x0, sp |
d54e81f9 WD |
593 | bl do_undefinstr |
594 | b ret_to_user | |
7dd01aef AP |
595 | el0_sys: |
596 | /* | |
597 | * System instructions, for trapped cache maintenance instructions | |
598 | */ | |
599 | enable_dbg_and_irq | |
600 | ct_user_exit | |
601 | mov x0, x25 | |
602 | mov x1, sp | |
603 | bl do_sysinstr | |
604 | b ret_to_user | |
60ffc30d CM |
605 | el0_dbg: |
606 | /* | |
607 | * Debug exception handling | |
608 | */ | |
609 | tbnz x24, #0, el0_inv // EL0 only | |
610 | mrs x0, far_el1 | |
60ffc30d CM |
611 | mov x1, x25 |
612 | mov x2, sp | |
2a283070 WD |
613 | bl do_debug_exception |
614 | enable_dbg | |
6c81fe79 | 615 | ct_user_exit |
2a283070 | 616 | b ret_to_user |
60ffc30d | 617 | el0_inv: |
2a283070 | 618 | enable_dbg |
6c81fe79 | 619 | ct_user_exit |
60ffc30d CM |
620 | mov x0, sp |
621 | mov x1, #BAD_SYNC | |
1b42804d | 622 | mov x2, x25 |
d54e81f9 WD |
623 | bl bad_mode |
624 | b ret_to_user | |
60ffc30d CM |
625 | ENDPROC(el0_sync) |
626 | ||
627 | .align 6 | |
628 | el0_irq: | |
629 | kernel_entry 0 | |
630 | el0_irq_naked: | |
60ffc30d CM |
631 | enable_dbg |
632 | #ifdef CONFIG_TRACE_IRQFLAGS | |
633 | bl trace_hardirqs_off | |
634 | #endif | |
64681787 | 635 | |
6c81fe79 | 636 | ct_user_exit |
60ffc30d | 637 | irq_handler |
64681787 | 638 | |
60ffc30d CM |
639 | #ifdef CONFIG_TRACE_IRQFLAGS |
640 | bl trace_hardirqs_on | |
641 | #endif | |
642 | b ret_to_user | |
643 | ENDPROC(el0_irq) | |
644 | ||
60ffc30d CM |
645 | /* |
646 | * Register switch for AArch64. The callee-saved registers need to be saved | |
647 | * and restored. On entry: | |
648 | * x0 = previous task_struct (must be preserved across the switch) | |
649 | * x1 = next task_struct | |
650 | * Previous and next are guaranteed not to be the same. | |
651 | * | |
652 | */ | |
653 | ENTRY(cpu_switch_to) | |
c0d3fce5 WD |
654 | mov x10, #THREAD_CPU_CONTEXT |
655 | add x8, x0, x10 | |
60ffc30d CM |
656 | mov x9, sp |
657 | stp x19, x20, [x8], #16 // store callee-saved registers | |
658 | stp x21, x22, [x8], #16 | |
659 | stp x23, x24, [x8], #16 | |
660 | stp x25, x26, [x8], #16 | |
661 | stp x27, x28, [x8], #16 | |
662 | stp x29, x9, [x8], #16 | |
663 | str lr, [x8] | |
c0d3fce5 | 664 | add x8, x1, x10 |
60ffc30d CM |
665 | ldp x19, x20, [x8], #16 // restore callee-saved registers |
666 | ldp x21, x22, [x8], #16 | |
667 | ldp x23, x24, [x8], #16 | |
668 | ldp x25, x26, [x8], #16 | |
669 | ldp x27, x28, [x8], #16 | |
670 | ldp x29, x9, [x8], #16 | |
671 | ldr lr, [x8] | |
672 | mov sp, x9 | |
c02433dd | 673 | msr sp_el0, x1 |
60ffc30d CM |
674 | ret |
675 | ENDPROC(cpu_switch_to) | |
676 | ||
677 | /* | |
678 | * This is the fast syscall return path. We do as little as possible here, | |
679 | * and this includes saving x0 back into the kernel stack. | |
680 | */ | |
681 | ret_fast_syscall: | |
682 | disable_irq // disable interrupts | |
412fcb6c | 683 | str x0, [sp, #S_X0] // returned x0 |
c02433dd | 684 | ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for syscall tracing |
04d7e098 JS |
685 | and x2, x1, #_TIF_SYSCALL_WORK |
686 | cbnz x2, ret_fast_syscall_trace | |
60ffc30d | 687 | and x2, x1, #_TIF_WORK_MASK |
412fcb6c | 688 | cbnz x2, work_pending |
2a283070 | 689 | enable_step_tsk x1, x2 |
412fcb6c | 690 | kernel_exit 0 |
04d7e098 JS |
691 | ret_fast_syscall_trace: |
692 | enable_irq // enable interrupts | |
412fcb6c | 693 | b __sys_trace_return_skipped // we already saved x0 |
60ffc30d CM |
694 | |
695 | /* | |
696 | * Ok, we need to do extra processing, enter the slow path. | |
697 | */ | |
60ffc30d | 698 | work_pending: |
60ffc30d | 699 | mov x0, sp // 'regs' |
60ffc30d | 700 | bl do_notify_resume |
db3899a6 | 701 | #ifdef CONFIG_TRACE_IRQFLAGS |
421dd6fa | 702 | bl trace_hardirqs_on // enabled while in userspace |
db3899a6 | 703 | #endif |
c02433dd | 704 | ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for single-step |
421dd6fa | 705 | b finish_ret_to_user |
60ffc30d CM |
706 | /* |
707 | * "slow" syscall return path. | |
708 | */ | |
59dc67b0 | 709 | ret_to_user: |
60ffc30d | 710 | disable_irq // disable interrupts |
c02433dd | 711 | ldr x1, [tsk, #TSK_TI_FLAGS] |
60ffc30d CM |
712 | and x2, x1, #_TIF_WORK_MASK |
713 | cbnz x2, work_pending | |
421dd6fa | 714 | finish_ret_to_user: |
2a283070 | 715 | enable_step_tsk x1, x2 |
412fcb6c | 716 | kernel_exit 0 |
60ffc30d CM |
717 | ENDPROC(ret_to_user) |
718 | ||
719 | /* | |
720 | * This is how we return from a fork. | |
721 | */ | |
722 | ENTRY(ret_from_fork) | |
723 | bl schedule_tail | |
c34501d2 CM |
724 | cbz x19, 1f // not a kernel thread |
725 | mov x0, x20 | |
726 | blr x19 | |
727 | 1: get_thread_info tsk | |
60ffc30d CM |
728 | b ret_to_user |
729 | ENDPROC(ret_from_fork) | |
730 | ||
731 | /* | |
732 | * SVC handler. | |
733 | */ | |
734 | .align 6 | |
735 | el0_svc: | |
736 | adrp stbl, sys_call_table // load syscall table pointer | |
737 | uxtw scno, w8 // syscall number in w8 | |
738 | mov sc_nr, #__NR_syscalls | |
739 | el0_svc_naked: // compat entry point | |
740 | stp x0, scno, [sp, #S_ORIG_X0] // save the original x0 and syscall number | |
2a283070 | 741 | enable_dbg_and_irq |
6c81fe79 | 742 | ct_user_exit 1 |
60ffc30d | 743 | |
c02433dd | 744 | ldr x16, [tsk, #TSK_TI_FLAGS] // check for syscall hooks |
449f81a4 AT |
745 | tst x16, #_TIF_SYSCALL_WORK |
746 | b.ne __sys_trace | |
60ffc30d CM |
747 | cmp scno, sc_nr // check upper syscall limit |
748 | b.hs ni_sys | |
749 | ldr x16, [stbl, scno, lsl #3] // address in the syscall table | |
d54e81f9 WD |
750 | blr x16 // call sys_* routine |
751 | b ret_fast_syscall | |
60ffc30d CM |
752 | ni_sys: |
753 | mov x0, sp | |
d54e81f9 WD |
754 | bl do_ni_syscall |
755 | b ret_fast_syscall | |
60ffc30d CM |
756 | ENDPROC(el0_svc) |
757 | ||
758 | /* | |
759 | * This is the really slow path. We're going to be doing context | |
760 | * switches, and waiting for our parent to respond. | |
761 | */ | |
762 | __sys_trace: | |
1014c81d AT |
763 | mov w0, #-1 // set default errno for |
764 | cmp scno, x0 // user-issued syscall(-1) | |
765 | b.ne 1f | |
766 | mov x0, #-ENOSYS | |
767 | str x0, [sp, #S_X0] | |
768 | 1: mov x0, sp | |
3157858f | 769 | bl syscall_trace_enter |
1014c81d AT |
770 | cmp w0, #-1 // skip the syscall? |
771 | b.eq __sys_trace_return_skipped | |
60ffc30d CM |
772 | uxtw scno, w0 // syscall number (possibly new) |
773 | mov x1, sp // pointer to regs | |
774 | cmp scno, sc_nr // check upper syscall limit | |
d54e81f9 | 775 | b.hs __ni_sys_trace |
60ffc30d CM |
776 | ldp x0, x1, [sp] // restore the syscall args |
777 | ldp x2, x3, [sp, #S_X2] | |
778 | ldp x4, x5, [sp, #S_X4] | |
779 | ldp x6, x7, [sp, #S_X6] | |
780 | ldr x16, [stbl, scno, lsl #3] // address in the syscall table | |
d54e81f9 | 781 | blr x16 // call sys_* routine |
60ffc30d CM |
782 | |
783 | __sys_trace_return: | |
1014c81d AT |
784 | str x0, [sp, #S_X0] // save returned x0 |
785 | __sys_trace_return_skipped: | |
3157858f AT |
786 | mov x0, sp |
787 | bl syscall_trace_exit | |
60ffc30d CM |
788 | b ret_to_user |
789 | ||
d54e81f9 WD |
790 | __ni_sys_trace: |
791 | mov x0, sp | |
792 | bl do_ni_syscall | |
793 | b __sys_trace_return | |
794 | ||
888b3c87 PA |
795 | .popsection // .entry.text |
796 | ||
60ffc30d CM |
797 | /* |
798 | * Special system call wrappers. | |
799 | */ | |
60ffc30d CM |
800 | ENTRY(sys_rt_sigreturn_wrapper) |
801 | mov x0, sp | |
802 | b sys_rt_sigreturn | |
803 | ENDPROC(sys_rt_sigreturn_wrapper) |