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60ffc30d CM |
1 | /* |
2 | * Low-level exception handling code | |
3 | * | |
4 | * Copyright (C) 2012 ARM Ltd. | |
5 | * Authors: Catalin Marinas <catalin.marinas@arm.com> | |
6 | * Will Deacon <will.deacon@arm.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include <linux/init.h> | |
22 | #include <linux/linkage.h> | |
23 | ||
8d883b23 | 24 | #include <asm/alternative.h> |
60ffc30d CM |
25 | #include <asm/assembler.h> |
26 | #include <asm/asm-offsets.h> | |
905e8c5d | 27 | #include <asm/cpufeature.h> |
60ffc30d | 28 | #include <asm/errno.h> |
5c1ce6f7 | 29 | #include <asm/esr.h> |
8e23dacd | 30 | #include <asm/irq.h> |
d57a98a9 WD |
31 | #include <asm/memory.h> |
32 | #include <asm/mmu.h> | |
eef94a3d | 33 | #include <asm/processor.h> |
39bc88e5 | 34 | #include <asm/ptrace.h> |
60ffc30d | 35 | #include <asm/thread_info.h> |
b4b8664d | 36 | #include <asm/asm-uaccess.h> |
60ffc30d CM |
37 | #include <asm/unistd.h> |
38 | ||
6c81fe79 LB |
39 | /* |
40 | * Context tracking subsystem. Used to instrument transitions | |
41 | * between user and kernel mode. | |
42 | */ | |
43 | .macro ct_user_exit, syscall = 0 | |
44 | #ifdef CONFIG_CONTEXT_TRACKING | |
45 | bl context_tracking_user_exit | |
46 | .if \syscall == 1 | |
47 | /* | |
48 | * Save/restore needed during syscalls. Restore syscall arguments from | |
49 | * the values already saved on stack during kernel_entry. | |
50 | */ | |
51 | ldp x0, x1, [sp] | |
52 | ldp x2, x3, [sp, #S_X2] | |
53 | ldp x4, x5, [sp, #S_X4] | |
54 | ldp x6, x7, [sp, #S_X6] | |
55 | .endif | |
56 | #endif | |
57 | .endm | |
58 | ||
59 | .macro ct_user_enter | |
60 | #ifdef CONFIG_CONTEXT_TRACKING | |
61 | bl context_tracking_user_enter | |
62 | #endif | |
63 | .endm | |
64 | ||
60ffc30d CM |
65 | /* |
66 | * Bad Abort numbers | |
67 | *----------------- | |
68 | */ | |
69 | #define BAD_SYNC 0 | |
70 | #define BAD_IRQ 1 | |
71 | #define BAD_FIQ 2 | |
72 | #define BAD_ERROR 3 | |
73 | ||
ca58e0a9 | 74 | .macro kernel_ventry, el, label, regsize = 64 |
b11e5759 | 75 | .align 7 |
63648dd2 | 76 | sub sp, sp, #S_FRAME_SIZE |
872d8327 MR |
77 | #ifdef CONFIG_VMAP_STACK |
78 | /* | |
79 | * Test whether the SP has overflowed, without corrupting a GPR. | |
80 | * Task and IRQ stacks are aligned to (1 << THREAD_SHIFT). | |
81 | */ | |
82 | add sp, sp, x0 // sp' = sp + x0 | |
83 | sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp | |
84 | tbnz x0, #THREAD_SHIFT, 0f | |
85 | sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0 | |
86 | sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp | |
ca58e0a9 | 87 | b el\()\el\()_\label |
872d8327 MR |
88 | |
89 | 0: | |
90 | /* | |
91 | * Either we've just detected an overflow, or we've taken an exception | |
92 | * while on the overflow stack. Either way, we won't return to | |
93 | * userspace, and can clobber EL0 registers to free up GPRs. | |
94 | */ | |
95 | ||
96 | /* Stash the original SP (minus S_FRAME_SIZE) in tpidr_el0. */ | |
97 | msr tpidr_el0, x0 | |
98 | ||
99 | /* Recover the original x0 value and stash it in tpidrro_el0 */ | |
100 | sub x0, sp, x0 | |
101 | msr tpidrro_el0, x0 | |
102 | ||
103 | /* Switch to the overflow stack */ | |
104 | adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0 | |
105 | ||
106 | /* | |
107 | * Check whether we were already on the overflow stack. This may happen | |
108 | * after panic() re-enables interrupts. | |
109 | */ | |
110 | mrs x0, tpidr_el0 // sp of interrupted context | |
111 | sub x0, sp, x0 // delta with top of overflow stack | |
112 | tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range? | |
113 | b.ne __bad_stack // no? -> bad stack pointer | |
114 | ||
115 | /* We were already on the overflow stack. Restore sp/x0 and carry on. */ | |
116 | sub sp, sp, x0 | |
117 | mrs x0, tpidrro_el0 | |
118 | #endif | |
ca58e0a9 | 119 | b el\()\el\()_\label |
b11e5759 MR |
120 | .endm |
121 | ||
122 | .macro kernel_entry, el, regsize = 64 | |
60ffc30d CM |
123 | .if \regsize == 32 |
124 | mov w0, w0 // zero upper 32 bits of x0 | |
125 | .endif | |
63648dd2 WD |
126 | stp x0, x1, [sp, #16 * 0] |
127 | stp x2, x3, [sp, #16 * 1] | |
128 | stp x4, x5, [sp, #16 * 2] | |
129 | stp x6, x7, [sp, #16 * 3] | |
130 | stp x8, x9, [sp, #16 * 4] | |
131 | stp x10, x11, [sp, #16 * 5] | |
132 | stp x12, x13, [sp, #16 * 6] | |
133 | stp x14, x15, [sp, #16 * 7] | |
134 | stp x16, x17, [sp, #16 * 8] | |
135 | stp x18, x19, [sp, #16 * 9] | |
136 | stp x20, x21, [sp, #16 * 10] | |
137 | stp x22, x23, [sp, #16 * 11] | |
138 | stp x24, x25, [sp, #16 * 12] | |
139 | stp x26, x27, [sp, #16 * 13] | |
140 | stp x28, x29, [sp, #16 * 14] | |
141 | ||
60ffc30d CM |
142 | .if \el == 0 |
143 | mrs x21, sp_el0 | |
c02433dd MR |
144 | ldr_this_cpu tsk, __entry_task, x20 // Ensure MDSCR_EL1.SS is clear, |
145 | ldr x19, [tsk, #TSK_TI_FLAGS] // since we can unmask debug | |
2a283070 | 146 | disable_step_tsk x19, x20 // exceptions when scheduling. |
49003a8d JM |
147 | |
148 | mov x29, xzr // fp pointed to user-space | |
60ffc30d CM |
149 | .else |
150 | add x21, sp, #S_FRAME_SIZE | |
e19a6ee2 JM |
151 | get_thread_info tsk |
152 | /* Save the task's original addr_limit and set USER_DS (TASK_SIZE_64) */ | |
c02433dd | 153 | ldr x20, [tsk, #TSK_TI_ADDR_LIMIT] |
e19a6ee2 JM |
154 | str x20, [sp, #S_ORIG_ADDR_LIMIT] |
155 | mov x20, #TASK_SIZE_64 | |
c02433dd | 156 | str x20, [tsk, #TSK_TI_ADDR_LIMIT] |
563cada0 | 157 | /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */ |
e19a6ee2 | 158 | .endif /* \el == 0 */ |
60ffc30d CM |
159 | mrs x22, elr_el1 |
160 | mrs x23, spsr_el1 | |
161 | stp lr, x21, [sp, #S_LR] | |
39bc88e5 | 162 | |
73267498 AB |
163 | /* |
164 | * In order to be able to dump the contents of struct pt_regs at the | |
165 | * time the exception was taken (in case we attempt to walk the call | |
166 | * stack later), chain it together with the stack frames. | |
167 | */ | |
168 | .if \el == 0 | |
169 | stp xzr, xzr, [sp, #S_STACKFRAME] | |
170 | .else | |
171 | stp x29, x22, [sp, #S_STACKFRAME] | |
172 | .endif | |
173 | add x29, sp, #S_STACKFRAME | |
174 | ||
39bc88e5 CM |
175 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN |
176 | /* | |
177 | * Set the TTBR0 PAN bit in SPSR. When the exception is taken from | |
178 | * EL0, there is no need to check the state of TTBR0_EL1 since | |
179 | * accesses are always enabled. | |
180 | * Note that the meaning of this bit differs from the ARMv8.1 PAN | |
181 | * feature as all TTBR0_EL1 accesses are disabled, not just those to | |
182 | * user mappings. | |
183 | */ | |
184 | alternative_if ARM64_HAS_PAN | |
185 | b 1f // skip TTBR0 PAN | |
186 | alternative_else_nop_endif | |
187 | ||
188 | .if \el != 0 | |
7a7e2f4d | 189 | mrs x21, ttbr1_el1 |
39bc88e5 CM |
190 | tst x21, #0xffff << 48 // Check for the reserved ASID |
191 | orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR | |
192 | b.eq 1f // TTBR0 access already disabled | |
193 | and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR | |
194 | .endif | |
195 | ||
196 | __uaccess_ttbr0_disable x21 | |
197 | 1: | |
198 | #endif | |
199 | ||
60ffc30d CM |
200 | stp x22, x23, [sp, #S_PC] |
201 | ||
17c28958 | 202 | /* Not in a syscall by default (el0_svc overwrites for real syscall) */ |
60ffc30d | 203 | .if \el == 0 |
17c28958 | 204 | mov w21, #NO_SYSCALL |
35d0e6fb | 205 | str w21, [sp, #S_SYSCALLNO] |
60ffc30d CM |
206 | .endif |
207 | ||
6cdf9c7c JL |
208 | /* |
209 | * Set sp_el0 to current thread_info. | |
210 | */ | |
211 | .if \el == 0 | |
212 | msr sp_el0, tsk | |
213 | .endif | |
214 | ||
60ffc30d CM |
215 | /* |
216 | * Registers that may be useful after this macro is invoked: | |
217 | * | |
218 | * x21 - aborted SP | |
219 | * x22 - aborted PC | |
220 | * x23 - aborted PSTATE | |
221 | */ | |
222 | .endm | |
223 | ||
412fcb6c | 224 | .macro kernel_exit, el |
e19a6ee2 | 225 | .if \el != 0 |
8d66772e JM |
226 | disable_daif |
227 | ||
e19a6ee2 JM |
228 | /* Restore the task's original addr_limit. */ |
229 | ldr x20, [sp, #S_ORIG_ADDR_LIMIT] | |
c02433dd | 230 | str x20, [tsk, #TSK_TI_ADDR_LIMIT] |
e19a6ee2 JM |
231 | |
232 | /* No need to restore UAO, it will be restored from SPSR_EL1 */ | |
233 | .endif | |
234 | ||
60ffc30d CM |
235 | ldp x21, x22, [sp, #S_PC] // load ELR, SPSR |
236 | .if \el == 0 | |
6c81fe79 | 237 | ct_user_enter |
39bc88e5 CM |
238 | .endif |
239 | ||
240 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN | |
241 | /* | |
242 | * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR | |
243 | * PAN bit checking. | |
244 | */ | |
245 | alternative_if ARM64_HAS_PAN | |
246 | b 2f // skip TTBR0 PAN | |
247 | alternative_else_nop_endif | |
248 | ||
249 | .if \el != 0 | |
250 | tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set | |
251 | .endif | |
252 | ||
7a7e2f4d | 253 | __uaccess_ttbr0_enable x0, x1 |
39bc88e5 CM |
254 | |
255 | .if \el == 0 | |
256 | /* | |
257 | * Enable errata workarounds only if returning to user. The only | |
258 | * workaround currently required for TTBR0_EL1 changes are for the | |
259 | * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache | |
260 | * corruption). | |
261 | */ | |
7a2f1a8a | 262 | post_ttbr_update_workaround |
39bc88e5 CM |
263 | .endif |
264 | 1: | |
265 | .if \el != 0 | |
266 | and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit | |
267 | .endif | |
268 | 2: | |
269 | #endif | |
270 | ||
271 | .if \el == 0 | |
60ffc30d | 272 | ldr x23, [sp, #S_SP] // load return stack pointer |
63648dd2 | 273 | msr sp_el0, x23 |
905e8c5d | 274 | #ifdef CONFIG_ARM64_ERRATUM_845719 |
6ba3b554 | 275 | alternative_if ARM64_WORKAROUND_845719 |
e28cabf1 DT |
276 | tbz x22, #4, 1f |
277 | #ifdef CONFIG_PID_IN_CONTEXTIDR | |
278 | mrs x29, contextidr_el1 | |
279 | msr contextidr_el1, x29 | |
905e8c5d | 280 | #else |
e28cabf1 | 281 | msr contextidr_el1, xzr |
905e8c5d | 282 | #endif |
e28cabf1 | 283 | 1: |
6ba3b554 | 284 | alternative_else_nop_endif |
905e8c5d | 285 | #endif |
60ffc30d | 286 | .endif |
39bc88e5 | 287 | |
63648dd2 WD |
288 | msr elr_el1, x21 // set up the return data |
289 | msr spsr_el1, x22 | |
63648dd2 | 290 | ldp x0, x1, [sp, #16 * 0] |
63648dd2 WD |
291 | ldp x2, x3, [sp, #16 * 1] |
292 | ldp x4, x5, [sp, #16 * 2] | |
293 | ldp x6, x7, [sp, #16 * 3] | |
294 | ldp x8, x9, [sp, #16 * 4] | |
295 | ldp x10, x11, [sp, #16 * 5] | |
296 | ldp x12, x13, [sp, #16 * 6] | |
297 | ldp x14, x15, [sp, #16 * 7] | |
298 | ldp x16, x17, [sp, #16 * 8] | |
299 | ldp x18, x19, [sp, #16 * 9] | |
300 | ldp x20, x21, [sp, #16 * 10] | |
301 | ldp x22, x23, [sp, #16 * 11] | |
302 | ldp x24, x25, [sp, #16 * 12] | |
303 | ldp x26, x27, [sp, #16 * 13] | |
304 | ldp x28, x29, [sp, #16 * 14] | |
305 | ldr lr, [sp, #S_LR] | |
306 | add sp, sp, #S_FRAME_SIZE // restore sp | |
60ffc30d CM |
307 | eret // return to kernel |
308 | .endm | |
309 | ||
971c67ce | 310 | .macro irq_stack_entry |
8e23dacd JM |
311 | mov x19, sp // preserve the original sp |
312 | ||
8e23dacd | 313 | /* |
c02433dd MR |
314 | * Compare sp with the base of the task stack. |
315 | * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack, | |
316 | * and should switch to the irq stack. | |
8e23dacd | 317 | */ |
c02433dd MR |
318 | ldr x25, [tsk, TSK_STACK] |
319 | eor x25, x25, x19 | |
320 | and x25, x25, #~(THREAD_SIZE - 1) | |
321 | cbnz x25, 9998f | |
8e23dacd | 322 | |
f60fe78f | 323 | ldr_this_cpu x25, irq_stack_ptr, x26 |
34be98f4 | 324 | mov x26, #IRQ_STACK_SIZE |
8e23dacd | 325 | add x26, x25, x26 |
d224a69e JM |
326 | |
327 | /* switch to the irq stack */ | |
8e23dacd | 328 | mov sp, x26 |
8e23dacd JM |
329 | 9998: |
330 | .endm | |
331 | ||
332 | /* | |
333 | * x19 should be preserved between irq_stack_entry and | |
334 | * irq_stack_exit. | |
335 | */ | |
336 | .macro irq_stack_exit | |
337 | mov sp, x19 | |
338 | .endm | |
339 | ||
60ffc30d CM |
340 | /* |
341 | * These are the registers used in the syscall handler, and allow us to | |
342 | * have in theory up to 7 arguments to a function - x0 to x6. | |
343 | * | |
344 | * x7 is reserved for the system call number in 32-bit mode. | |
345 | */ | |
35d0e6fb DM |
346 | wsc_nr .req w25 // number of system calls |
347 | wscno .req w26 // syscall number | |
348 | xscno .req x26 // syscall number (zero-extended) | |
60ffc30d CM |
349 | stbl .req x27 // syscall table pointer |
350 | tsk .req x28 // current thread_info | |
351 | ||
352 | /* | |
353 | * Interrupt handling. | |
354 | */ | |
355 | .macro irq_handler | |
8e23dacd | 356 | ldr_l x1, handle_arch_irq |
60ffc30d | 357 | mov x0, sp |
971c67ce | 358 | irq_stack_entry |
60ffc30d | 359 | blr x1 |
8e23dacd | 360 | irq_stack_exit |
60ffc30d CM |
361 | .endm |
362 | ||
363 | .text | |
364 | ||
365 | /* | |
366 | * Exception vectors. | |
367 | */ | |
888b3c87 | 368 | .pushsection ".entry.text", "ax" |
60ffc30d CM |
369 | |
370 | .align 11 | |
371 | ENTRY(vectors) | |
ca58e0a9 WD |
372 | kernel_ventry 1, sync_invalid // Synchronous EL1t |
373 | kernel_ventry 1, irq_invalid // IRQ EL1t | |
374 | kernel_ventry 1, fiq_invalid // FIQ EL1t | |
375 | kernel_ventry 1, error_invalid // Error EL1t | |
60ffc30d | 376 | |
ca58e0a9 WD |
377 | kernel_ventry 1, sync // Synchronous EL1h |
378 | kernel_ventry 1, irq // IRQ EL1h | |
379 | kernel_ventry 1, fiq_invalid // FIQ EL1h | |
380 | kernel_ventry 1, error // Error EL1h | |
60ffc30d | 381 | |
ca58e0a9 WD |
382 | kernel_ventry 0, sync // Synchronous 64-bit EL0 |
383 | kernel_ventry 0, irq // IRQ 64-bit EL0 | |
384 | kernel_ventry 0, fiq_invalid // FIQ 64-bit EL0 | |
385 | kernel_ventry 0, error // Error 64-bit EL0 | |
60ffc30d CM |
386 | |
387 | #ifdef CONFIG_COMPAT | |
ca58e0a9 WD |
388 | kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0 |
389 | kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0 | |
390 | kernel_ventry 0, fiq_invalid_compat, 32 // FIQ 32-bit EL0 | |
391 | kernel_ventry 0, error_compat, 32 // Error 32-bit EL0 | |
60ffc30d | 392 | #else |
ca58e0a9 WD |
393 | kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0 |
394 | kernel_ventry 0, irq_invalid, 32 // IRQ 32-bit EL0 | |
395 | kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0 | |
396 | kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0 | |
60ffc30d CM |
397 | #endif |
398 | END(vectors) | |
399 | ||
872d8327 MR |
400 | #ifdef CONFIG_VMAP_STACK |
401 | /* | |
402 | * We detected an overflow in kernel_ventry, which switched to the | |
403 | * overflow stack. Stash the exception regs, and head to our overflow | |
404 | * handler. | |
405 | */ | |
406 | __bad_stack: | |
407 | /* Restore the original x0 value */ | |
408 | mrs x0, tpidrro_el0 | |
409 | ||
410 | /* | |
411 | * Store the original GPRs to the new stack. The orginal SP (minus | |
412 | * S_FRAME_SIZE) was stashed in tpidr_el0 by kernel_ventry. | |
413 | */ | |
414 | sub sp, sp, #S_FRAME_SIZE | |
415 | kernel_entry 1 | |
416 | mrs x0, tpidr_el0 | |
417 | add x0, x0, #S_FRAME_SIZE | |
418 | str x0, [sp, #S_SP] | |
419 | ||
420 | /* Stash the regs for handle_bad_stack */ | |
421 | mov x0, sp | |
422 | ||
423 | /* Time to die */ | |
424 | bl handle_bad_stack | |
425 | ASM_BUG() | |
426 | #endif /* CONFIG_VMAP_STACK */ | |
427 | ||
60ffc30d CM |
428 | /* |
429 | * Invalid mode handlers | |
430 | */ | |
431 | .macro inv_entry, el, reason, regsize = 64 | |
b660950c | 432 | kernel_entry \el, \regsize |
60ffc30d CM |
433 | mov x0, sp |
434 | mov x1, #\reason | |
435 | mrs x2, esr_el1 | |
2d0e751a MR |
436 | bl bad_mode |
437 | ASM_BUG() | |
60ffc30d CM |
438 | .endm |
439 | ||
440 | el0_sync_invalid: | |
441 | inv_entry 0, BAD_SYNC | |
442 | ENDPROC(el0_sync_invalid) | |
443 | ||
444 | el0_irq_invalid: | |
445 | inv_entry 0, BAD_IRQ | |
446 | ENDPROC(el0_irq_invalid) | |
447 | ||
448 | el0_fiq_invalid: | |
449 | inv_entry 0, BAD_FIQ | |
450 | ENDPROC(el0_fiq_invalid) | |
451 | ||
452 | el0_error_invalid: | |
453 | inv_entry 0, BAD_ERROR | |
454 | ENDPROC(el0_error_invalid) | |
455 | ||
456 | #ifdef CONFIG_COMPAT | |
457 | el0_fiq_invalid_compat: | |
458 | inv_entry 0, BAD_FIQ, 32 | |
459 | ENDPROC(el0_fiq_invalid_compat) | |
60ffc30d CM |
460 | #endif |
461 | ||
462 | el1_sync_invalid: | |
463 | inv_entry 1, BAD_SYNC | |
464 | ENDPROC(el1_sync_invalid) | |
465 | ||
466 | el1_irq_invalid: | |
467 | inv_entry 1, BAD_IRQ | |
468 | ENDPROC(el1_irq_invalid) | |
469 | ||
470 | el1_fiq_invalid: | |
471 | inv_entry 1, BAD_FIQ | |
472 | ENDPROC(el1_fiq_invalid) | |
473 | ||
474 | el1_error_invalid: | |
475 | inv_entry 1, BAD_ERROR | |
476 | ENDPROC(el1_error_invalid) | |
477 | ||
478 | /* | |
479 | * EL1 mode handlers. | |
480 | */ | |
481 | .align 6 | |
482 | el1_sync: | |
483 | kernel_entry 1 | |
484 | mrs x1, esr_el1 // read the syndrome register | |
aed40e01 MR |
485 | lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class |
486 | cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1 | |
60ffc30d | 487 | b.eq el1_da |
9adeb8e7 LA |
488 | cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1 |
489 | b.eq el1_ia | |
aed40e01 | 490 | cmp x24, #ESR_ELx_EC_SYS64 // configurable trap |
60ffc30d | 491 | b.eq el1_undef |
aed40e01 | 492 | cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception |
60ffc30d | 493 | b.eq el1_sp_pc |
aed40e01 | 494 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
60ffc30d | 495 | b.eq el1_sp_pc |
aed40e01 | 496 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1 |
60ffc30d | 497 | b.eq el1_undef |
aed40e01 | 498 | cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1 |
60ffc30d CM |
499 | b.ge el1_dbg |
500 | b el1_inv | |
9adeb8e7 LA |
501 | |
502 | el1_ia: | |
503 | /* | |
504 | * Fall through to the Data abort case | |
505 | */ | |
60ffc30d CM |
506 | el1_da: |
507 | /* | |
508 | * Data abort handling | |
509 | */ | |
276e9327 | 510 | mrs x3, far_el1 |
b55a5a1b | 511 | inherit_daif pstate=x23, tmp=x2 |
276e9327 | 512 | clear_address_tag x0, x3 |
60ffc30d CM |
513 | mov x2, sp // struct pt_regs |
514 | bl do_mem_abort | |
515 | ||
60ffc30d CM |
516 | kernel_exit 1 |
517 | el1_sp_pc: | |
518 | /* | |
519 | * Stack or PC alignment exception handling | |
520 | */ | |
521 | mrs x0, far_el1 | |
b55a5a1b | 522 | inherit_daif pstate=x23, tmp=x2 |
60ffc30d | 523 | mov x2, sp |
2d0e751a MR |
524 | bl do_sp_pc_abort |
525 | ASM_BUG() | |
60ffc30d CM |
526 | el1_undef: |
527 | /* | |
528 | * Undefined instruction | |
529 | */ | |
b55a5a1b | 530 | inherit_daif pstate=x23, tmp=x2 |
60ffc30d | 531 | mov x0, sp |
2d0e751a MR |
532 | bl do_undefinstr |
533 | ASM_BUG() | |
60ffc30d CM |
534 | el1_dbg: |
535 | /* | |
536 | * Debug exception handling | |
537 | */ | |
aed40e01 | 538 | cmp x24, #ESR_ELx_EC_BRK64 // if BRK64 |
ee6214ce | 539 | cinc x24, x24, eq // set bit '0' |
60ffc30d CM |
540 | tbz x24, #0, el1_inv // EL1 only |
541 | mrs x0, far_el1 | |
542 | mov x2, sp // struct pt_regs | |
543 | bl do_debug_exception | |
60ffc30d CM |
544 | kernel_exit 1 |
545 | el1_inv: | |
546 | // TODO: add support for undefined instructions in kernel mode | |
b55a5a1b | 547 | inherit_daif pstate=x23, tmp=x2 |
60ffc30d | 548 | mov x0, sp |
1b42804d | 549 | mov x2, x1 |
60ffc30d | 550 | mov x1, #BAD_SYNC |
2d0e751a MR |
551 | bl bad_mode |
552 | ASM_BUG() | |
60ffc30d CM |
553 | ENDPROC(el1_sync) |
554 | ||
555 | .align 6 | |
556 | el1_irq: | |
557 | kernel_entry 1 | |
b282e1ce | 558 | enable_da_f |
60ffc30d CM |
559 | #ifdef CONFIG_TRACE_IRQFLAGS |
560 | bl trace_hardirqs_off | |
561 | #endif | |
64681787 | 562 | |
60ffc30d | 563 | irq_handler |
64681787 | 564 | |
60ffc30d | 565 | #ifdef CONFIG_PREEMPT |
c02433dd | 566 | ldr w24, [tsk, #TSK_TI_PREEMPT] // get preempt count |
717321fc | 567 | cbnz w24, 1f // preempt count != 0 |
c02433dd | 568 | ldr x0, [tsk, #TSK_TI_FLAGS] // get flags |
60ffc30d CM |
569 | tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling? |
570 | bl el1_preempt | |
571 | 1: | |
572 | #endif | |
573 | #ifdef CONFIG_TRACE_IRQFLAGS | |
574 | bl trace_hardirqs_on | |
575 | #endif | |
576 | kernel_exit 1 | |
577 | ENDPROC(el1_irq) | |
578 | ||
579 | #ifdef CONFIG_PREEMPT | |
580 | el1_preempt: | |
581 | mov x24, lr | |
2a283070 | 582 | 1: bl preempt_schedule_irq // irq en/disable is done inside |
c02433dd | 583 | ldr x0, [tsk, #TSK_TI_FLAGS] // get new tasks TI_FLAGS |
60ffc30d CM |
584 | tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling? |
585 | ret x24 | |
586 | #endif | |
587 | ||
588 | /* | |
589 | * EL0 mode handlers. | |
590 | */ | |
591 | .align 6 | |
592 | el0_sync: | |
593 | kernel_entry 0 | |
594 | mrs x25, esr_el1 // read the syndrome register | |
aed40e01 MR |
595 | lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class |
596 | cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state | |
60ffc30d | 597 | b.eq el0_svc |
aed40e01 | 598 | cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0 |
60ffc30d | 599 | b.eq el0_da |
aed40e01 | 600 | cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0 |
60ffc30d | 601 | b.eq el0_ia |
aed40e01 | 602 | cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access |
60ffc30d | 603 | b.eq el0_fpsimd_acc |
bc0ee476 DM |
604 | cmp x24, #ESR_ELx_EC_SVE // SVE access |
605 | b.eq el0_sve_acc | |
aed40e01 | 606 | cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception |
60ffc30d | 607 | b.eq el0_fpsimd_exc |
aed40e01 | 608 | cmp x24, #ESR_ELx_EC_SYS64 // configurable trap |
7dd01aef | 609 | b.eq el0_sys |
aed40e01 | 610 | cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception |
60ffc30d | 611 | b.eq el0_sp_pc |
aed40e01 | 612 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
60ffc30d | 613 | b.eq el0_sp_pc |
aed40e01 | 614 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0 |
60ffc30d | 615 | b.eq el0_undef |
aed40e01 | 616 | cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0 |
60ffc30d CM |
617 | b.ge el0_dbg |
618 | b el0_inv | |
619 | ||
620 | #ifdef CONFIG_COMPAT | |
621 | .align 6 | |
622 | el0_sync_compat: | |
623 | kernel_entry 0, 32 | |
624 | mrs x25, esr_el1 // read the syndrome register | |
aed40e01 MR |
625 | lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class |
626 | cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state | |
60ffc30d | 627 | b.eq el0_svc_compat |
aed40e01 | 628 | cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0 |
60ffc30d | 629 | b.eq el0_da |
aed40e01 | 630 | cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0 |
60ffc30d | 631 | b.eq el0_ia |
aed40e01 | 632 | cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access |
60ffc30d | 633 | b.eq el0_fpsimd_acc |
aed40e01 | 634 | cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception |
60ffc30d | 635 | b.eq el0_fpsimd_exc |
77f3228f MS |
636 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
637 | b.eq el0_sp_pc | |
aed40e01 | 638 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0 |
60ffc30d | 639 | b.eq el0_undef |
aed40e01 | 640 | cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap |
381cc2b9 | 641 | b.eq el0_undef |
aed40e01 | 642 | cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap |
381cc2b9 | 643 | b.eq el0_undef |
aed40e01 | 644 | cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap |
381cc2b9 | 645 | b.eq el0_undef |
aed40e01 | 646 | cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap |
381cc2b9 | 647 | b.eq el0_undef |
aed40e01 | 648 | cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap |
381cc2b9 | 649 | b.eq el0_undef |
aed40e01 | 650 | cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0 |
60ffc30d CM |
651 | b.ge el0_dbg |
652 | b el0_inv | |
653 | el0_svc_compat: | |
654 | /* | |
655 | * AArch32 syscall handling | |
656 | */ | |
bc0ee476 | 657 | ldr x16, [tsk, #TSK_TI_FLAGS] // load thread flags |
0156411b | 658 | adrp stbl, compat_sys_call_table // load compat syscall table pointer |
35d0e6fb DM |
659 | mov wscno, w7 // syscall number in w7 (r7) |
660 | mov wsc_nr, #__NR_compat_syscalls | |
60ffc30d CM |
661 | b el0_svc_naked |
662 | ||
663 | .align 6 | |
664 | el0_irq_compat: | |
665 | kernel_entry 0, 32 | |
666 | b el0_irq_naked | |
a92d4d14 XX |
667 | |
668 | el0_error_compat: | |
669 | kernel_entry 0, 32 | |
670 | b el0_error_naked | |
60ffc30d CM |
671 | #endif |
672 | ||
673 | el0_da: | |
674 | /* | |
675 | * Data abort handling | |
676 | */ | |
6ab6463a | 677 | mrs x26, far_el1 |
746647c7 | 678 | enable_daif |
6c81fe79 | 679 | ct_user_exit |
276e9327 | 680 | clear_address_tag x0, x26 |
60ffc30d CM |
681 | mov x1, x25 |
682 | mov x2, sp | |
d54e81f9 WD |
683 | bl do_mem_abort |
684 | b ret_to_user | |
60ffc30d CM |
685 | el0_ia: |
686 | /* | |
687 | * Instruction abort handling | |
688 | */ | |
6ab6463a | 689 | mrs x26, far_el1 |
746647c7 | 690 | enable_daif |
6c81fe79 | 691 | ct_user_exit |
6ab6463a | 692 | mov x0, x26 |
541ec870 | 693 | mov x1, x25 |
60ffc30d | 694 | mov x2, sp |
d54e81f9 WD |
695 | bl do_mem_abort |
696 | b ret_to_user | |
60ffc30d CM |
697 | el0_fpsimd_acc: |
698 | /* | |
699 | * Floating Point or Advanced SIMD access | |
700 | */ | |
746647c7 | 701 | enable_daif |
6c81fe79 | 702 | ct_user_exit |
60ffc30d CM |
703 | mov x0, x25 |
704 | mov x1, sp | |
d54e81f9 WD |
705 | bl do_fpsimd_acc |
706 | b ret_to_user | |
bc0ee476 DM |
707 | el0_sve_acc: |
708 | /* | |
709 | * Scalable Vector Extension access | |
710 | */ | |
711 | enable_daif | |
712 | ct_user_exit | |
713 | mov x0, x25 | |
714 | mov x1, sp | |
715 | bl do_sve_acc | |
716 | b ret_to_user | |
60ffc30d CM |
717 | el0_fpsimd_exc: |
718 | /* | |
bc0ee476 | 719 | * Floating Point, Advanced SIMD or SVE exception |
60ffc30d | 720 | */ |
746647c7 | 721 | enable_daif |
6c81fe79 | 722 | ct_user_exit |
60ffc30d CM |
723 | mov x0, x25 |
724 | mov x1, sp | |
d54e81f9 WD |
725 | bl do_fpsimd_exc |
726 | b ret_to_user | |
60ffc30d CM |
727 | el0_sp_pc: |
728 | /* | |
729 | * Stack or PC alignment exception handling | |
730 | */ | |
6ab6463a | 731 | mrs x26, far_el1 |
746647c7 | 732 | enable_daif |
46b0567c | 733 | ct_user_exit |
6ab6463a | 734 | mov x0, x26 |
60ffc30d CM |
735 | mov x1, x25 |
736 | mov x2, sp | |
d54e81f9 WD |
737 | bl do_sp_pc_abort |
738 | b ret_to_user | |
60ffc30d CM |
739 | el0_undef: |
740 | /* | |
741 | * Undefined instruction | |
742 | */ | |
746647c7 | 743 | enable_daif |
6c81fe79 | 744 | ct_user_exit |
2a283070 | 745 | mov x0, sp |
d54e81f9 WD |
746 | bl do_undefinstr |
747 | b ret_to_user | |
7dd01aef AP |
748 | el0_sys: |
749 | /* | |
750 | * System instructions, for trapped cache maintenance instructions | |
751 | */ | |
746647c7 | 752 | enable_daif |
7dd01aef AP |
753 | ct_user_exit |
754 | mov x0, x25 | |
755 | mov x1, sp | |
756 | bl do_sysinstr | |
757 | b ret_to_user | |
60ffc30d CM |
758 | el0_dbg: |
759 | /* | |
760 | * Debug exception handling | |
761 | */ | |
762 | tbnz x24, #0, el0_inv // EL0 only | |
763 | mrs x0, far_el1 | |
60ffc30d CM |
764 | mov x1, x25 |
765 | mov x2, sp | |
2a283070 | 766 | bl do_debug_exception |
746647c7 | 767 | enable_daif |
6c81fe79 | 768 | ct_user_exit |
2a283070 | 769 | b ret_to_user |
60ffc30d | 770 | el0_inv: |
746647c7 | 771 | enable_daif |
6c81fe79 | 772 | ct_user_exit |
60ffc30d CM |
773 | mov x0, sp |
774 | mov x1, #BAD_SYNC | |
1b42804d | 775 | mov x2, x25 |
7d9e8f71 | 776 | bl bad_el0_sync |
d54e81f9 | 777 | b ret_to_user |
60ffc30d CM |
778 | ENDPROC(el0_sync) |
779 | ||
780 | .align 6 | |
781 | el0_irq: | |
782 | kernel_entry 0 | |
783 | el0_irq_naked: | |
b282e1ce | 784 | enable_da_f |
60ffc30d CM |
785 | #ifdef CONFIG_TRACE_IRQFLAGS |
786 | bl trace_hardirqs_off | |
787 | #endif | |
64681787 | 788 | |
6c81fe79 | 789 | ct_user_exit |
60ffc30d | 790 | irq_handler |
64681787 | 791 | |
60ffc30d CM |
792 | #ifdef CONFIG_TRACE_IRQFLAGS |
793 | bl trace_hardirqs_on | |
794 | #endif | |
795 | b ret_to_user | |
796 | ENDPROC(el0_irq) | |
797 | ||
a92d4d14 XX |
798 | el1_error: |
799 | kernel_entry 1 | |
800 | mrs x1, esr_el1 | |
801 | enable_dbg | |
802 | mov x0, sp | |
803 | bl do_serror | |
804 | kernel_exit 1 | |
805 | ENDPROC(el1_error) | |
806 | ||
807 | el0_error: | |
808 | kernel_entry 0 | |
809 | el0_error_naked: | |
810 | mrs x1, esr_el1 | |
811 | enable_dbg | |
812 | mov x0, sp | |
813 | bl do_serror | |
814 | enable_daif | |
815 | ct_user_exit | |
816 | b ret_to_user | |
817 | ENDPROC(el0_error) | |
818 | ||
819 | ||
60ffc30d CM |
820 | /* |
821 | * This is the fast syscall return path. We do as little as possible here, | |
822 | * and this includes saving x0 back into the kernel stack. | |
823 | */ | |
824 | ret_fast_syscall: | |
8d66772e | 825 | disable_daif |
412fcb6c | 826 | str x0, [sp, #S_X0] // returned x0 |
c02433dd | 827 | ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for syscall tracing |
04d7e098 JS |
828 | and x2, x1, #_TIF_SYSCALL_WORK |
829 | cbnz x2, ret_fast_syscall_trace | |
60ffc30d | 830 | and x2, x1, #_TIF_WORK_MASK |
412fcb6c | 831 | cbnz x2, work_pending |
2a283070 | 832 | enable_step_tsk x1, x2 |
412fcb6c | 833 | kernel_exit 0 |
04d7e098 | 834 | ret_fast_syscall_trace: |
8d66772e | 835 | enable_daif |
412fcb6c | 836 | b __sys_trace_return_skipped // we already saved x0 |
60ffc30d CM |
837 | |
838 | /* | |
839 | * Ok, we need to do extra processing, enter the slow path. | |
840 | */ | |
60ffc30d | 841 | work_pending: |
60ffc30d | 842 | mov x0, sp // 'regs' |
60ffc30d | 843 | bl do_notify_resume |
db3899a6 | 844 | #ifdef CONFIG_TRACE_IRQFLAGS |
421dd6fa | 845 | bl trace_hardirqs_on // enabled while in userspace |
db3899a6 | 846 | #endif |
c02433dd | 847 | ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for single-step |
421dd6fa | 848 | b finish_ret_to_user |
60ffc30d CM |
849 | /* |
850 | * "slow" syscall return path. | |
851 | */ | |
59dc67b0 | 852 | ret_to_user: |
8d66772e | 853 | disable_daif |
c02433dd | 854 | ldr x1, [tsk, #TSK_TI_FLAGS] |
60ffc30d CM |
855 | and x2, x1, #_TIF_WORK_MASK |
856 | cbnz x2, work_pending | |
421dd6fa | 857 | finish_ret_to_user: |
2a283070 | 858 | enable_step_tsk x1, x2 |
412fcb6c | 859 | kernel_exit 0 |
60ffc30d CM |
860 | ENDPROC(ret_to_user) |
861 | ||
60ffc30d CM |
862 | /* |
863 | * SVC handler. | |
864 | */ | |
865 | .align 6 | |
866 | el0_svc: | |
bc0ee476 | 867 | ldr x16, [tsk, #TSK_TI_FLAGS] // load thread flags |
60ffc30d | 868 | adrp stbl, sys_call_table // load syscall table pointer |
35d0e6fb DM |
869 | mov wscno, w8 // syscall number in w8 |
870 | mov wsc_nr, #__NR_syscalls | |
bc0ee476 | 871 | |
43994d82 DM |
872 | #ifdef CONFIG_ARM64_SVE |
873 | alternative_if_not ARM64_SVE | |
bc0ee476 | 874 | b el0_svc_naked |
43994d82 | 875 | alternative_else_nop_endif |
bc0ee476 DM |
876 | tbz x16, #TIF_SVE, el0_svc_naked // Skip unless TIF_SVE set: |
877 | bic x16, x16, #_TIF_SVE // discard SVE state | |
878 | str x16, [tsk, #TSK_TI_FLAGS] | |
879 | ||
880 | /* | |
881 | * task_fpsimd_load() won't be called to update CPACR_EL1 in | |
882 | * ret_to_user unless TIF_FOREIGN_FPSTATE is still set, which only | |
883 | * happens if a context switch or kernel_neon_begin() or context | |
884 | * modification (sigreturn, ptrace) intervenes. | |
885 | * So, ensure that CPACR_EL1 is already correct for the fast-path case: | |
886 | */ | |
887 | mrs x9, cpacr_el1 | |
888 | bic x9, x9, #CPACR_EL1_ZEN_EL0EN // disable SVE for el0 | |
889 | msr cpacr_el1, x9 // synchronised by eret to el0 | |
43994d82 | 890 | #endif |
bc0ee476 | 891 | |
60ffc30d | 892 | el0_svc_naked: // compat entry point |
35d0e6fb | 893 | stp x0, xscno, [sp, #S_ORIG_X0] // save the original x0 and syscall number |
746647c7 | 894 | enable_daif |
6c81fe79 | 895 | ct_user_exit 1 |
60ffc30d | 896 | |
bc0ee476 | 897 | tst x16, #_TIF_SYSCALL_WORK // check for syscall hooks |
449f81a4 | 898 | b.ne __sys_trace |
35d0e6fb | 899 | cmp wscno, wsc_nr // check upper syscall limit |
60ffc30d | 900 | b.hs ni_sys |
35d0e6fb | 901 | ldr x16, [stbl, xscno, lsl #3] // address in the syscall table |
d54e81f9 WD |
902 | blr x16 // call sys_* routine |
903 | b ret_fast_syscall | |
60ffc30d CM |
904 | ni_sys: |
905 | mov x0, sp | |
d54e81f9 WD |
906 | bl do_ni_syscall |
907 | b ret_fast_syscall | |
60ffc30d CM |
908 | ENDPROC(el0_svc) |
909 | ||
910 | /* | |
911 | * This is the really slow path. We're going to be doing context | |
912 | * switches, and waiting for our parent to respond. | |
913 | */ | |
914 | __sys_trace: | |
17c28958 | 915 | cmp wscno, #NO_SYSCALL // user-issued syscall(-1)? |
1014c81d | 916 | b.ne 1f |
35d0e6fb | 917 | mov x0, #-ENOSYS // set default errno if so |
1014c81d AT |
918 | str x0, [sp, #S_X0] |
919 | 1: mov x0, sp | |
3157858f | 920 | bl syscall_trace_enter |
17c28958 | 921 | cmp w0, #NO_SYSCALL // skip the syscall? |
1014c81d | 922 | b.eq __sys_trace_return_skipped |
35d0e6fb | 923 | mov wscno, w0 // syscall number (possibly new) |
60ffc30d | 924 | mov x1, sp // pointer to regs |
35d0e6fb | 925 | cmp wscno, wsc_nr // check upper syscall limit |
d54e81f9 | 926 | b.hs __ni_sys_trace |
60ffc30d CM |
927 | ldp x0, x1, [sp] // restore the syscall args |
928 | ldp x2, x3, [sp, #S_X2] | |
929 | ldp x4, x5, [sp, #S_X4] | |
930 | ldp x6, x7, [sp, #S_X6] | |
35d0e6fb | 931 | ldr x16, [stbl, xscno, lsl #3] // address in the syscall table |
d54e81f9 | 932 | blr x16 // call sys_* routine |
60ffc30d CM |
933 | |
934 | __sys_trace_return: | |
1014c81d AT |
935 | str x0, [sp, #S_X0] // save returned x0 |
936 | __sys_trace_return_skipped: | |
3157858f AT |
937 | mov x0, sp |
938 | bl syscall_trace_exit | |
60ffc30d CM |
939 | b ret_to_user |
940 | ||
d54e81f9 WD |
941 | __ni_sys_trace: |
942 | mov x0, sp | |
943 | bl do_ni_syscall | |
944 | b __sys_trace_return | |
945 | ||
888b3c87 PA |
946 | .popsection // .entry.text |
947 | ||
d57a98a9 WD |
948 | #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 |
949 | /* | |
950 | * Exception vectors trampoline. | |
951 | */ | |
952 | .pushsection ".entry.tramp.text", "ax" | |
953 | ||
954 | .macro tramp_map_kernel, tmp | |
955 | mrs \tmp, ttbr1_el1 | |
956 | sub \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE) | |
957 | bic \tmp, \tmp, #USER_ASID_FLAG | |
958 | msr ttbr1_el1, \tmp | |
959 | .endm | |
960 | ||
961 | .macro tramp_unmap_kernel, tmp | |
962 | mrs \tmp, ttbr1_el1 | |
963 | add \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE) | |
964 | orr \tmp, \tmp, #USER_ASID_FLAG | |
965 | msr ttbr1_el1, \tmp | |
966 | /* | |
967 | * We avoid running the post_ttbr_update_workaround here because the | |
968 | * user and kernel ASIDs don't have conflicting mappings, so any | |
969 | * "blessing" as described in: | |
970 | * | |
971 | * http://lkml.kernel.org/r/56BB848A.6060603@caviumnetworks.com | |
972 | * | |
973 | * will not hurt correctness. Whilst this may partially defeat the | |
974 | * point of using split ASIDs in the first place, it avoids | |
975 | * the hit of invalidating the entire I-cache on every return to | |
976 | * userspace. | |
977 | */ | |
978 | .endm | |
979 | ||
980 | .macro tramp_ventry, regsize = 64 | |
981 | .align 7 | |
982 | 1: | |
983 | .if \regsize == 64 | |
984 | msr tpidrro_el0, x30 // Restored in kernel_ventry | |
985 | .endif | |
986 | tramp_map_kernel x30 | |
987 | ldr x30, =vectors | |
988 | prfm plil1strm, [x30, #(1b - tramp_vectors)] | |
989 | msr vbar_el1, x30 | |
990 | add x30, x30, #(1b - tramp_vectors) | |
991 | isb | |
992 | br x30 | |
993 | .endm | |
994 | ||
995 | .macro tramp_exit, regsize = 64 | |
996 | adr x30, tramp_vectors | |
997 | msr vbar_el1, x30 | |
998 | tramp_unmap_kernel x30 | |
999 | .if \regsize == 64 | |
1000 | mrs x30, far_el1 | |
1001 | .endif | |
1002 | eret | |
1003 | .endm | |
1004 | ||
1005 | .align 11 | |
1006 | ENTRY(tramp_vectors) | |
1007 | .space 0x400 | |
1008 | ||
1009 | tramp_ventry | |
1010 | tramp_ventry | |
1011 | tramp_ventry | |
1012 | tramp_ventry | |
1013 | ||
1014 | tramp_ventry 32 | |
1015 | tramp_ventry 32 | |
1016 | tramp_ventry 32 | |
1017 | tramp_ventry 32 | |
1018 | END(tramp_vectors) | |
1019 | ||
1020 | ENTRY(tramp_exit_native) | |
1021 | tramp_exit | |
1022 | END(tramp_exit_native) | |
1023 | ||
1024 | ENTRY(tramp_exit_compat) | |
1025 | tramp_exit 32 | |
1026 | END(tramp_exit_compat) | |
1027 | ||
1028 | .ltorg | |
1029 | .popsection // .entry.tramp.text | |
1030 | #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ | |
1031 | ||
60ffc30d CM |
1032 | /* |
1033 | * Special system call wrappers. | |
1034 | */ | |
60ffc30d CM |
1035 | ENTRY(sys_rt_sigreturn_wrapper) |
1036 | mov x0, sp | |
1037 | b sys_rt_sigreturn | |
1038 | ENDPROC(sys_rt_sigreturn_wrapper) | |
ed84b4e9 MR |
1039 | |
1040 | /* | |
1041 | * Register switch for AArch64. The callee-saved registers need to be saved | |
1042 | * and restored. On entry: | |
1043 | * x0 = previous task_struct (must be preserved across the switch) | |
1044 | * x1 = next task_struct | |
1045 | * Previous and next are guaranteed not to be the same. | |
1046 | * | |
1047 | */ | |
1048 | ENTRY(cpu_switch_to) | |
1049 | mov x10, #THREAD_CPU_CONTEXT | |
1050 | add x8, x0, x10 | |
1051 | mov x9, sp | |
1052 | stp x19, x20, [x8], #16 // store callee-saved registers | |
1053 | stp x21, x22, [x8], #16 | |
1054 | stp x23, x24, [x8], #16 | |
1055 | stp x25, x26, [x8], #16 | |
1056 | stp x27, x28, [x8], #16 | |
1057 | stp x29, x9, [x8], #16 | |
1058 | str lr, [x8] | |
1059 | add x8, x1, x10 | |
1060 | ldp x19, x20, [x8], #16 // restore callee-saved registers | |
1061 | ldp x21, x22, [x8], #16 | |
1062 | ldp x23, x24, [x8], #16 | |
1063 | ldp x25, x26, [x8], #16 | |
1064 | ldp x27, x28, [x8], #16 | |
1065 | ldp x29, x9, [x8], #16 | |
1066 | ldr lr, [x8] | |
1067 | mov sp, x9 | |
1068 | msr sp_el0, x1 | |
1069 | ret | |
1070 | ENDPROC(cpu_switch_to) | |
1071 | NOKPROBE(cpu_switch_to) | |
1072 | ||
1073 | /* | |
1074 | * This is how we return from a fork. | |
1075 | */ | |
1076 | ENTRY(ret_from_fork) | |
1077 | bl schedule_tail | |
1078 | cbz x19, 1f // not a kernel thread | |
1079 | mov x0, x20 | |
1080 | blr x19 | |
1081 | 1: get_thread_info tsk | |
1082 | b ret_to_user | |
1083 | ENDPROC(ret_from_fork) | |
1084 | NOKPROBE(ret_from_fork) |