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60ffc30d CM |
1 | /* |
2 | * Low-level exception handling code | |
3 | * | |
4 | * Copyright (C) 2012 ARM Ltd. | |
5 | * Authors: Catalin Marinas <catalin.marinas@arm.com> | |
6 | * Will Deacon <will.deacon@arm.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include <linux/init.h> | |
22 | #include <linux/linkage.h> | |
23 | ||
8d883b23 | 24 | #include <asm/alternative.h> |
60ffc30d CM |
25 | #include <asm/assembler.h> |
26 | #include <asm/asm-offsets.h> | |
905e8c5d | 27 | #include <asm/cpufeature.h> |
60ffc30d | 28 | #include <asm/errno.h> |
5c1ce6f7 | 29 | #include <asm/esr.h> |
60ffc30d CM |
30 | #include <asm/thread_info.h> |
31 | #include <asm/unistd.h> | |
32 | ||
6c81fe79 LB |
33 | /* |
34 | * Context tracking subsystem. Used to instrument transitions | |
35 | * between user and kernel mode. | |
36 | */ | |
37 | .macro ct_user_exit, syscall = 0 | |
38 | #ifdef CONFIG_CONTEXT_TRACKING | |
39 | bl context_tracking_user_exit | |
40 | .if \syscall == 1 | |
41 | /* | |
42 | * Save/restore needed during syscalls. Restore syscall arguments from | |
43 | * the values already saved on stack during kernel_entry. | |
44 | */ | |
45 | ldp x0, x1, [sp] | |
46 | ldp x2, x3, [sp, #S_X2] | |
47 | ldp x4, x5, [sp, #S_X4] | |
48 | ldp x6, x7, [sp, #S_X6] | |
49 | .endif | |
50 | #endif | |
51 | .endm | |
52 | ||
53 | .macro ct_user_enter | |
54 | #ifdef CONFIG_CONTEXT_TRACKING | |
55 | bl context_tracking_user_enter | |
56 | #endif | |
57 | .endm | |
58 | ||
60ffc30d CM |
59 | /* |
60 | * Bad Abort numbers | |
61 | *----------------- | |
62 | */ | |
63 | #define BAD_SYNC 0 | |
64 | #define BAD_IRQ 1 | |
65 | #define BAD_FIQ 2 | |
66 | #define BAD_ERROR 3 | |
67 | ||
68 | .macro kernel_entry, el, regsize = 64 | |
63648dd2 | 69 | sub sp, sp, #S_FRAME_SIZE |
60ffc30d CM |
70 | .if \regsize == 32 |
71 | mov w0, w0 // zero upper 32 bits of x0 | |
72 | .endif | |
63648dd2 WD |
73 | stp x0, x1, [sp, #16 * 0] |
74 | stp x2, x3, [sp, #16 * 1] | |
75 | stp x4, x5, [sp, #16 * 2] | |
76 | stp x6, x7, [sp, #16 * 3] | |
77 | stp x8, x9, [sp, #16 * 4] | |
78 | stp x10, x11, [sp, #16 * 5] | |
79 | stp x12, x13, [sp, #16 * 6] | |
80 | stp x14, x15, [sp, #16 * 7] | |
81 | stp x16, x17, [sp, #16 * 8] | |
82 | stp x18, x19, [sp, #16 * 9] | |
83 | stp x20, x21, [sp, #16 * 10] | |
84 | stp x22, x23, [sp, #16 * 11] | |
85 | stp x24, x25, [sp, #16 * 12] | |
86 | stp x26, x27, [sp, #16 * 13] | |
87 | stp x28, x29, [sp, #16 * 14] | |
88 | ||
60ffc30d CM |
89 | .if \el == 0 |
90 | mrs x21, sp_el0 | |
2a283070 WD |
91 | get_thread_info tsk // Ensure MDSCR_EL1.SS is clear, |
92 | ldr x19, [tsk, #TI_FLAGS] // since we can unmask debug | |
93 | disable_step_tsk x19, x20 // exceptions when scheduling. | |
60ffc30d CM |
94 | .else |
95 | add x21, sp, #S_FRAME_SIZE | |
96 | .endif | |
97 | mrs x22, elr_el1 | |
98 | mrs x23, spsr_el1 | |
99 | stp lr, x21, [sp, #S_LR] | |
100 | stp x22, x23, [sp, #S_PC] | |
101 | ||
102 | /* | |
103 | * Set syscallno to -1 by default (overridden later if real syscall). | |
104 | */ | |
105 | .if \el == 0 | |
106 | mvn x21, xzr | |
107 | str x21, [sp, #S_SYSCALLNO] | |
108 | .endif | |
109 | ||
110 | /* | |
111 | * Registers that may be useful after this macro is invoked: | |
112 | * | |
113 | * x21 - aborted SP | |
114 | * x22 - aborted PC | |
115 | * x23 - aborted PSTATE | |
116 | */ | |
117 | .endm | |
118 | ||
119 | .macro kernel_exit, el, ret = 0 | |
120 | ldp x21, x22, [sp, #S_PC] // load ELR, SPSR | |
121 | .if \el == 0 | |
6c81fe79 | 122 | ct_user_enter |
60ffc30d | 123 | ldr x23, [sp, #S_SP] // load return stack pointer |
63648dd2 | 124 | msr sp_el0, x23 |
905e8c5d | 125 | #ifdef CONFIG_ARM64_ERRATUM_845719 |
e28cabf1 DT |
126 | alternative_if_not ARM64_WORKAROUND_845719 |
127 | nop | |
128 | nop | |
905e8c5d | 129 | #ifdef CONFIG_PID_IN_CONTEXTIDR |
e28cabf1 DT |
130 | nop |
131 | #endif | |
132 | alternative_else | |
133 | tbz x22, #4, 1f | |
134 | #ifdef CONFIG_PID_IN_CONTEXTIDR | |
135 | mrs x29, contextidr_el1 | |
136 | msr contextidr_el1, x29 | |
905e8c5d | 137 | #else |
e28cabf1 | 138 | msr contextidr_el1, xzr |
905e8c5d | 139 | #endif |
e28cabf1 DT |
140 | 1: |
141 | alternative_endif | |
905e8c5d | 142 | #endif |
60ffc30d | 143 | .endif |
63648dd2 WD |
144 | msr elr_el1, x21 // set up the return data |
145 | msr spsr_el1, x22 | |
60ffc30d CM |
146 | .if \ret |
147 | ldr x1, [sp, #S_X1] // preserve x0 (syscall return) | |
60ffc30d | 148 | .else |
63648dd2 | 149 | ldp x0, x1, [sp, #16 * 0] |
60ffc30d | 150 | .endif |
63648dd2 WD |
151 | ldp x2, x3, [sp, #16 * 1] |
152 | ldp x4, x5, [sp, #16 * 2] | |
153 | ldp x6, x7, [sp, #16 * 3] | |
154 | ldp x8, x9, [sp, #16 * 4] | |
155 | ldp x10, x11, [sp, #16 * 5] | |
156 | ldp x12, x13, [sp, #16 * 6] | |
157 | ldp x14, x15, [sp, #16 * 7] | |
158 | ldp x16, x17, [sp, #16 * 8] | |
159 | ldp x18, x19, [sp, #16 * 9] | |
160 | ldp x20, x21, [sp, #16 * 10] | |
161 | ldp x22, x23, [sp, #16 * 11] | |
162 | ldp x24, x25, [sp, #16 * 12] | |
163 | ldp x26, x27, [sp, #16 * 13] | |
164 | ldp x28, x29, [sp, #16 * 14] | |
165 | ldr lr, [sp, #S_LR] | |
166 | add sp, sp, #S_FRAME_SIZE // restore sp | |
60ffc30d CM |
167 | eret // return to kernel |
168 | .endm | |
169 | ||
170 | .macro get_thread_info, rd | |
171 | mov \rd, sp | |
845ad05e | 172 | and \rd, \rd, #~(THREAD_SIZE - 1) // top of stack |
60ffc30d CM |
173 | .endm |
174 | ||
175 | /* | |
176 | * These are the registers used in the syscall handler, and allow us to | |
177 | * have in theory up to 7 arguments to a function - x0 to x6. | |
178 | * | |
179 | * x7 is reserved for the system call number in 32-bit mode. | |
180 | */ | |
181 | sc_nr .req x25 // number of system calls | |
182 | scno .req x26 // syscall number | |
183 | stbl .req x27 // syscall table pointer | |
184 | tsk .req x28 // current thread_info | |
185 | ||
186 | /* | |
187 | * Interrupt handling. | |
188 | */ | |
189 | .macro irq_handler | |
fcff5886 LA |
190 | adrp x1, handle_arch_irq |
191 | ldr x1, [x1, #:lo12:handle_arch_irq] | |
60ffc30d CM |
192 | mov x0, sp |
193 | blr x1 | |
194 | .endm | |
195 | ||
196 | .text | |
197 | ||
198 | /* | |
199 | * Exception vectors. | |
200 | */ | |
60ffc30d CM |
201 | |
202 | .align 11 | |
203 | ENTRY(vectors) | |
204 | ventry el1_sync_invalid // Synchronous EL1t | |
205 | ventry el1_irq_invalid // IRQ EL1t | |
206 | ventry el1_fiq_invalid // FIQ EL1t | |
207 | ventry el1_error_invalid // Error EL1t | |
208 | ||
209 | ventry el1_sync // Synchronous EL1h | |
210 | ventry el1_irq // IRQ EL1h | |
211 | ventry el1_fiq_invalid // FIQ EL1h | |
212 | ventry el1_error_invalid // Error EL1h | |
213 | ||
214 | ventry el0_sync // Synchronous 64-bit EL0 | |
215 | ventry el0_irq // IRQ 64-bit EL0 | |
216 | ventry el0_fiq_invalid // FIQ 64-bit EL0 | |
217 | ventry el0_error_invalid // Error 64-bit EL0 | |
218 | ||
219 | #ifdef CONFIG_COMPAT | |
220 | ventry el0_sync_compat // Synchronous 32-bit EL0 | |
221 | ventry el0_irq_compat // IRQ 32-bit EL0 | |
222 | ventry el0_fiq_invalid_compat // FIQ 32-bit EL0 | |
223 | ventry el0_error_invalid_compat // Error 32-bit EL0 | |
224 | #else | |
225 | ventry el0_sync_invalid // Synchronous 32-bit EL0 | |
226 | ventry el0_irq_invalid // IRQ 32-bit EL0 | |
227 | ventry el0_fiq_invalid // FIQ 32-bit EL0 | |
228 | ventry el0_error_invalid // Error 32-bit EL0 | |
229 | #endif | |
230 | END(vectors) | |
231 | ||
232 | /* | |
233 | * Invalid mode handlers | |
234 | */ | |
235 | .macro inv_entry, el, reason, regsize = 64 | |
236 | kernel_entry el, \regsize | |
237 | mov x0, sp | |
238 | mov x1, #\reason | |
239 | mrs x2, esr_el1 | |
240 | b bad_mode | |
241 | .endm | |
242 | ||
243 | el0_sync_invalid: | |
244 | inv_entry 0, BAD_SYNC | |
245 | ENDPROC(el0_sync_invalid) | |
246 | ||
247 | el0_irq_invalid: | |
248 | inv_entry 0, BAD_IRQ | |
249 | ENDPROC(el0_irq_invalid) | |
250 | ||
251 | el0_fiq_invalid: | |
252 | inv_entry 0, BAD_FIQ | |
253 | ENDPROC(el0_fiq_invalid) | |
254 | ||
255 | el0_error_invalid: | |
256 | inv_entry 0, BAD_ERROR | |
257 | ENDPROC(el0_error_invalid) | |
258 | ||
259 | #ifdef CONFIG_COMPAT | |
260 | el0_fiq_invalid_compat: | |
261 | inv_entry 0, BAD_FIQ, 32 | |
262 | ENDPROC(el0_fiq_invalid_compat) | |
263 | ||
264 | el0_error_invalid_compat: | |
265 | inv_entry 0, BAD_ERROR, 32 | |
266 | ENDPROC(el0_error_invalid_compat) | |
267 | #endif | |
268 | ||
269 | el1_sync_invalid: | |
270 | inv_entry 1, BAD_SYNC | |
271 | ENDPROC(el1_sync_invalid) | |
272 | ||
273 | el1_irq_invalid: | |
274 | inv_entry 1, BAD_IRQ | |
275 | ENDPROC(el1_irq_invalid) | |
276 | ||
277 | el1_fiq_invalid: | |
278 | inv_entry 1, BAD_FIQ | |
279 | ENDPROC(el1_fiq_invalid) | |
280 | ||
281 | el1_error_invalid: | |
282 | inv_entry 1, BAD_ERROR | |
283 | ENDPROC(el1_error_invalid) | |
284 | ||
285 | /* | |
286 | * EL1 mode handlers. | |
287 | */ | |
288 | .align 6 | |
289 | el1_sync: | |
290 | kernel_entry 1 | |
291 | mrs x1, esr_el1 // read the syndrome register | |
aed40e01 MR |
292 | lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class |
293 | cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1 | |
60ffc30d | 294 | b.eq el1_da |
aed40e01 | 295 | cmp x24, #ESR_ELx_EC_SYS64 // configurable trap |
60ffc30d | 296 | b.eq el1_undef |
aed40e01 | 297 | cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception |
60ffc30d | 298 | b.eq el1_sp_pc |
aed40e01 | 299 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
60ffc30d | 300 | b.eq el1_sp_pc |
aed40e01 | 301 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1 |
60ffc30d | 302 | b.eq el1_undef |
aed40e01 | 303 | cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1 |
60ffc30d CM |
304 | b.ge el1_dbg |
305 | b el1_inv | |
306 | el1_da: | |
307 | /* | |
308 | * Data abort handling | |
309 | */ | |
310 | mrs x0, far_el1 | |
2a283070 | 311 | enable_dbg |
60ffc30d CM |
312 | // re-enable interrupts if they were enabled in the aborted context |
313 | tbnz x23, #7, 1f // PSR_I_BIT | |
314 | enable_irq | |
315 | 1: | |
316 | mov x2, sp // struct pt_regs | |
317 | bl do_mem_abort | |
318 | ||
319 | // disable interrupts before pulling preserved data off the stack | |
320 | disable_irq | |
321 | kernel_exit 1 | |
322 | el1_sp_pc: | |
323 | /* | |
324 | * Stack or PC alignment exception handling | |
325 | */ | |
326 | mrs x0, far_el1 | |
2a283070 | 327 | enable_dbg |
60ffc30d CM |
328 | mov x2, sp |
329 | b do_sp_pc_abort | |
330 | el1_undef: | |
331 | /* | |
332 | * Undefined instruction | |
333 | */ | |
2a283070 | 334 | enable_dbg |
60ffc30d CM |
335 | mov x0, sp |
336 | b do_undefinstr | |
337 | el1_dbg: | |
338 | /* | |
339 | * Debug exception handling | |
340 | */ | |
aed40e01 | 341 | cmp x24, #ESR_ELx_EC_BRK64 // if BRK64 |
ee6214ce | 342 | cinc x24, x24, eq // set bit '0' |
60ffc30d CM |
343 | tbz x24, #0, el1_inv // EL1 only |
344 | mrs x0, far_el1 | |
345 | mov x2, sp // struct pt_regs | |
346 | bl do_debug_exception | |
60ffc30d CM |
347 | kernel_exit 1 |
348 | el1_inv: | |
349 | // TODO: add support for undefined instructions in kernel mode | |
2a283070 | 350 | enable_dbg |
60ffc30d | 351 | mov x0, sp |
1b42804d | 352 | mov x2, x1 |
60ffc30d | 353 | mov x1, #BAD_SYNC |
60ffc30d CM |
354 | b bad_mode |
355 | ENDPROC(el1_sync) | |
356 | ||
357 | .align 6 | |
358 | el1_irq: | |
359 | kernel_entry 1 | |
2a283070 | 360 | enable_dbg |
60ffc30d CM |
361 | #ifdef CONFIG_TRACE_IRQFLAGS |
362 | bl trace_hardirqs_off | |
363 | #endif | |
64681787 | 364 | |
60ffc30d | 365 | irq_handler |
64681787 | 366 | |
60ffc30d | 367 | #ifdef CONFIG_PREEMPT |
64681787 | 368 | get_thread_info tsk |
883c0573 | 369 | ldr w24, [tsk, #TI_PREEMPT] // get preempt count |
717321fc | 370 | cbnz w24, 1f // preempt count != 0 |
60ffc30d CM |
371 | ldr x0, [tsk, #TI_FLAGS] // get flags |
372 | tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling? | |
373 | bl el1_preempt | |
374 | 1: | |
375 | #endif | |
376 | #ifdef CONFIG_TRACE_IRQFLAGS | |
377 | bl trace_hardirqs_on | |
378 | #endif | |
379 | kernel_exit 1 | |
380 | ENDPROC(el1_irq) | |
381 | ||
382 | #ifdef CONFIG_PREEMPT | |
383 | el1_preempt: | |
384 | mov x24, lr | |
2a283070 | 385 | 1: bl preempt_schedule_irq // irq en/disable is done inside |
60ffc30d CM |
386 | ldr x0, [tsk, #TI_FLAGS] // get new tasks TI_FLAGS |
387 | tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling? | |
388 | ret x24 | |
389 | #endif | |
390 | ||
391 | /* | |
392 | * EL0 mode handlers. | |
393 | */ | |
394 | .align 6 | |
395 | el0_sync: | |
396 | kernel_entry 0 | |
397 | mrs x25, esr_el1 // read the syndrome register | |
aed40e01 MR |
398 | lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class |
399 | cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state | |
60ffc30d | 400 | b.eq el0_svc |
aed40e01 | 401 | cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0 |
60ffc30d | 402 | b.eq el0_da |
aed40e01 | 403 | cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0 |
60ffc30d | 404 | b.eq el0_ia |
aed40e01 | 405 | cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access |
60ffc30d | 406 | b.eq el0_fpsimd_acc |
aed40e01 | 407 | cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception |
60ffc30d | 408 | b.eq el0_fpsimd_exc |
aed40e01 | 409 | cmp x24, #ESR_ELx_EC_SYS64 // configurable trap |
60ffc30d | 410 | b.eq el0_undef |
aed40e01 | 411 | cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception |
60ffc30d | 412 | b.eq el0_sp_pc |
aed40e01 | 413 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
60ffc30d | 414 | b.eq el0_sp_pc |
aed40e01 | 415 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0 |
60ffc30d | 416 | b.eq el0_undef |
aed40e01 | 417 | cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0 |
60ffc30d CM |
418 | b.ge el0_dbg |
419 | b el0_inv | |
420 | ||
421 | #ifdef CONFIG_COMPAT | |
422 | .align 6 | |
423 | el0_sync_compat: | |
424 | kernel_entry 0, 32 | |
425 | mrs x25, esr_el1 // read the syndrome register | |
aed40e01 MR |
426 | lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class |
427 | cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state | |
60ffc30d | 428 | b.eq el0_svc_compat |
aed40e01 | 429 | cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0 |
60ffc30d | 430 | b.eq el0_da |
aed40e01 | 431 | cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0 |
60ffc30d | 432 | b.eq el0_ia |
aed40e01 | 433 | cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access |
60ffc30d | 434 | b.eq el0_fpsimd_acc |
aed40e01 | 435 | cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception |
60ffc30d | 436 | b.eq el0_fpsimd_exc |
aed40e01 | 437 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0 |
60ffc30d | 438 | b.eq el0_undef |
aed40e01 | 439 | cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap |
381cc2b9 | 440 | b.eq el0_undef |
aed40e01 | 441 | cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap |
381cc2b9 | 442 | b.eq el0_undef |
aed40e01 | 443 | cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap |
381cc2b9 | 444 | b.eq el0_undef |
aed40e01 | 445 | cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap |
381cc2b9 | 446 | b.eq el0_undef |
aed40e01 | 447 | cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap |
381cc2b9 | 448 | b.eq el0_undef |
aed40e01 | 449 | cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0 |
60ffc30d CM |
450 | b.ge el0_dbg |
451 | b el0_inv | |
452 | el0_svc_compat: | |
453 | /* | |
454 | * AArch32 syscall handling | |
455 | */ | |
0156411b | 456 | adrp stbl, compat_sys_call_table // load compat syscall table pointer |
60ffc30d CM |
457 | uxtw scno, w7 // syscall number in w7 (r7) |
458 | mov sc_nr, #__NR_compat_syscalls | |
459 | b el0_svc_naked | |
460 | ||
461 | .align 6 | |
462 | el0_irq_compat: | |
463 | kernel_entry 0, 32 | |
464 | b el0_irq_naked | |
465 | #endif | |
466 | ||
467 | el0_da: | |
468 | /* | |
469 | * Data abort handling | |
470 | */ | |
6ab6463a | 471 | mrs x26, far_el1 |
60ffc30d | 472 | // enable interrupts before calling the main handler |
2a283070 | 473 | enable_dbg_and_irq |
6c81fe79 | 474 | ct_user_exit |
6ab6463a | 475 | bic x0, x26, #(0xff << 56) |
60ffc30d CM |
476 | mov x1, x25 |
477 | mov x2, sp | |
d54e81f9 WD |
478 | bl do_mem_abort |
479 | b ret_to_user | |
60ffc30d CM |
480 | el0_ia: |
481 | /* | |
482 | * Instruction abort handling | |
483 | */ | |
6ab6463a | 484 | mrs x26, far_el1 |
60ffc30d | 485 | // enable interrupts before calling the main handler |
2a283070 | 486 | enable_dbg_and_irq |
6c81fe79 | 487 | ct_user_exit |
6ab6463a | 488 | mov x0, x26 |
60ffc30d CM |
489 | orr x1, x25, #1 << 24 // use reserved ISS bit for instruction aborts |
490 | mov x2, sp | |
d54e81f9 WD |
491 | bl do_mem_abort |
492 | b ret_to_user | |
60ffc30d CM |
493 | el0_fpsimd_acc: |
494 | /* | |
495 | * Floating Point or Advanced SIMD access | |
496 | */ | |
2a283070 | 497 | enable_dbg |
6c81fe79 | 498 | ct_user_exit |
60ffc30d CM |
499 | mov x0, x25 |
500 | mov x1, sp | |
d54e81f9 WD |
501 | bl do_fpsimd_acc |
502 | b ret_to_user | |
60ffc30d CM |
503 | el0_fpsimd_exc: |
504 | /* | |
505 | * Floating Point or Advanced SIMD exception | |
506 | */ | |
2a283070 | 507 | enable_dbg |
6c81fe79 | 508 | ct_user_exit |
60ffc30d CM |
509 | mov x0, x25 |
510 | mov x1, sp | |
d54e81f9 WD |
511 | bl do_fpsimd_exc |
512 | b ret_to_user | |
60ffc30d CM |
513 | el0_sp_pc: |
514 | /* | |
515 | * Stack or PC alignment exception handling | |
516 | */ | |
6ab6463a | 517 | mrs x26, far_el1 |
60ffc30d | 518 | // enable interrupts before calling the main handler |
2a283070 | 519 | enable_dbg_and_irq |
46b0567c | 520 | ct_user_exit |
6ab6463a | 521 | mov x0, x26 |
60ffc30d CM |
522 | mov x1, x25 |
523 | mov x2, sp | |
d54e81f9 WD |
524 | bl do_sp_pc_abort |
525 | b ret_to_user | |
60ffc30d CM |
526 | el0_undef: |
527 | /* | |
528 | * Undefined instruction | |
529 | */ | |
2600e130 | 530 | // enable interrupts before calling the main handler |
2a283070 | 531 | enable_dbg_and_irq |
6c81fe79 | 532 | ct_user_exit |
2a283070 | 533 | mov x0, sp |
d54e81f9 WD |
534 | bl do_undefinstr |
535 | b ret_to_user | |
60ffc30d CM |
536 | el0_dbg: |
537 | /* | |
538 | * Debug exception handling | |
539 | */ | |
540 | tbnz x24, #0, el0_inv // EL0 only | |
541 | mrs x0, far_el1 | |
60ffc30d CM |
542 | mov x1, x25 |
543 | mov x2, sp | |
2a283070 WD |
544 | bl do_debug_exception |
545 | enable_dbg | |
6c81fe79 | 546 | ct_user_exit |
2a283070 | 547 | b ret_to_user |
60ffc30d | 548 | el0_inv: |
2a283070 | 549 | enable_dbg |
6c81fe79 | 550 | ct_user_exit |
60ffc30d CM |
551 | mov x0, sp |
552 | mov x1, #BAD_SYNC | |
1b42804d | 553 | mov x2, x25 |
d54e81f9 WD |
554 | bl bad_mode |
555 | b ret_to_user | |
60ffc30d CM |
556 | ENDPROC(el0_sync) |
557 | ||
558 | .align 6 | |
559 | el0_irq: | |
560 | kernel_entry 0 | |
561 | el0_irq_naked: | |
60ffc30d CM |
562 | enable_dbg |
563 | #ifdef CONFIG_TRACE_IRQFLAGS | |
564 | bl trace_hardirqs_off | |
565 | #endif | |
64681787 | 566 | |
6c81fe79 | 567 | ct_user_exit |
60ffc30d | 568 | irq_handler |
64681787 | 569 | |
60ffc30d CM |
570 | #ifdef CONFIG_TRACE_IRQFLAGS |
571 | bl trace_hardirqs_on | |
572 | #endif | |
573 | b ret_to_user | |
574 | ENDPROC(el0_irq) | |
575 | ||
60ffc30d CM |
576 | /* |
577 | * Register switch for AArch64. The callee-saved registers need to be saved | |
578 | * and restored. On entry: | |
579 | * x0 = previous task_struct (must be preserved across the switch) | |
580 | * x1 = next task_struct | |
581 | * Previous and next are guaranteed not to be the same. | |
582 | * | |
583 | */ | |
584 | ENTRY(cpu_switch_to) | |
c0d3fce5 WD |
585 | mov x10, #THREAD_CPU_CONTEXT |
586 | add x8, x0, x10 | |
60ffc30d CM |
587 | mov x9, sp |
588 | stp x19, x20, [x8], #16 // store callee-saved registers | |
589 | stp x21, x22, [x8], #16 | |
590 | stp x23, x24, [x8], #16 | |
591 | stp x25, x26, [x8], #16 | |
592 | stp x27, x28, [x8], #16 | |
593 | stp x29, x9, [x8], #16 | |
594 | str lr, [x8] | |
c0d3fce5 | 595 | add x8, x1, x10 |
60ffc30d CM |
596 | ldp x19, x20, [x8], #16 // restore callee-saved registers |
597 | ldp x21, x22, [x8], #16 | |
598 | ldp x23, x24, [x8], #16 | |
599 | ldp x25, x26, [x8], #16 | |
600 | ldp x27, x28, [x8], #16 | |
601 | ldp x29, x9, [x8], #16 | |
602 | ldr lr, [x8] | |
603 | mov sp, x9 | |
604 | ret | |
605 | ENDPROC(cpu_switch_to) | |
606 | ||
607 | /* | |
608 | * This is the fast syscall return path. We do as little as possible here, | |
609 | * and this includes saving x0 back into the kernel stack. | |
610 | */ | |
611 | ret_fast_syscall: | |
612 | disable_irq // disable interrupts | |
04d7e098 JS |
613 | ldr x1, [tsk, #TI_FLAGS] // re-check for syscall tracing |
614 | and x2, x1, #_TIF_SYSCALL_WORK | |
615 | cbnz x2, ret_fast_syscall_trace | |
60ffc30d CM |
616 | and x2, x1, #_TIF_WORK_MASK |
617 | cbnz x2, fast_work_pending | |
2a283070 | 618 | enable_step_tsk x1, x2 |
60ffc30d | 619 | kernel_exit 0, ret = 1 |
04d7e098 JS |
620 | ret_fast_syscall_trace: |
621 | enable_irq // enable interrupts | |
622 | b __sys_trace_return | |
60ffc30d CM |
623 | |
624 | /* | |
625 | * Ok, we need to do extra processing, enter the slow path. | |
626 | */ | |
627 | fast_work_pending: | |
628 | str x0, [sp, #S_X0] // returned x0 | |
629 | work_pending: | |
630 | tbnz x1, #TIF_NEED_RESCHED, work_resched | |
005f78cd | 631 | /* TIF_SIGPENDING, TIF_NOTIFY_RESUME or TIF_FOREIGN_FPSTATE case */ |
60ffc30d CM |
632 | ldr x2, [sp, #S_PSTATE] |
633 | mov x0, sp // 'regs' | |
634 | tst x2, #PSR_MODE_MASK // user mode regs? | |
635 | b.ne no_work_pending // returning to kernel | |
6916fd08 | 636 | enable_irq // enable interrupts for do_notify_resume() |
60ffc30d CM |
637 | bl do_notify_resume |
638 | b ret_to_user | |
639 | work_resched: | |
60ffc30d CM |
640 | bl schedule |
641 | ||
642 | /* | |
643 | * "slow" syscall return path. | |
644 | */ | |
59dc67b0 | 645 | ret_to_user: |
60ffc30d CM |
646 | disable_irq // disable interrupts |
647 | ldr x1, [tsk, #TI_FLAGS] | |
648 | and x2, x1, #_TIF_WORK_MASK | |
649 | cbnz x2, work_pending | |
2a283070 | 650 | enable_step_tsk x1, x2 |
60ffc30d CM |
651 | no_work_pending: |
652 | kernel_exit 0, ret = 0 | |
653 | ENDPROC(ret_to_user) | |
654 | ||
655 | /* | |
656 | * This is how we return from a fork. | |
657 | */ | |
658 | ENTRY(ret_from_fork) | |
659 | bl schedule_tail | |
c34501d2 CM |
660 | cbz x19, 1f // not a kernel thread |
661 | mov x0, x20 | |
662 | blr x19 | |
663 | 1: get_thread_info tsk | |
60ffc30d CM |
664 | b ret_to_user |
665 | ENDPROC(ret_from_fork) | |
666 | ||
667 | /* | |
668 | * SVC handler. | |
669 | */ | |
670 | .align 6 | |
671 | el0_svc: | |
672 | adrp stbl, sys_call_table // load syscall table pointer | |
673 | uxtw scno, w8 // syscall number in w8 | |
674 | mov sc_nr, #__NR_syscalls | |
675 | el0_svc_naked: // compat entry point | |
676 | stp x0, scno, [sp, #S_ORIG_X0] // save the original x0 and syscall number | |
2a283070 | 677 | enable_dbg_and_irq |
6c81fe79 | 678 | ct_user_exit 1 |
60ffc30d | 679 | |
449f81a4 AT |
680 | ldr x16, [tsk, #TI_FLAGS] // check for syscall hooks |
681 | tst x16, #_TIF_SYSCALL_WORK | |
682 | b.ne __sys_trace | |
60ffc30d CM |
683 | cmp scno, sc_nr // check upper syscall limit |
684 | b.hs ni_sys | |
685 | ldr x16, [stbl, scno, lsl #3] // address in the syscall table | |
d54e81f9 WD |
686 | blr x16 // call sys_* routine |
687 | b ret_fast_syscall | |
60ffc30d CM |
688 | ni_sys: |
689 | mov x0, sp | |
d54e81f9 WD |
690 | bl do_ni_syscall |
691 | b ret_fast_syscall | |
60ffc30d CM |
692 | ENDPROC(el0_svc) |
693 | ||
694 | /* | |
695 | * This is the really slow path. We're going to be doing context | |
696 | * switches, and waiting for our parent to respond. | |
697 | */ | |
698 | __sys_trace: | |
1014c81d AT |
699 | mov w0, #-1 // set default errno for |
700 | cmp scno, x0 // user-issued syscall(-1) | |
701 | b.ne 1f | |
702 | mov x0, #-ENOSYS | |
703 | str x0, [sp, #S_X0] | |
704 | 1: mov x0, sp | |
3157858f | 705 | bl syscall_trace_enter |
1014c81d AT |
706 | cmp w0, #-1 // skip the syscall? |
707 | b.eq __sys_trace_return_skipped | |
60ffc30d CM |
708 | uxtw scno, w0 // syscall number (possibly new) |
709 | mov x1, sp // pointer to regs | |
710 | cmp scno, sc_nr // check upper syscall limit | |
d54e81f9 | 711 | b.hs __ni_sys_trace |
60ffc30d CM |
712 | ldp x0, x1, [sp] // restore the syscall args |
713 | ldp x2, x3, [sp, #S_X2] | |
714 | ldp x4, x5, [sp, #S_X4] | |
715 | ldp x6, x7, [sp, #S_X6] | |
716 | ldr x16, [stbl, scno, lsl #3] // address in the syscall table | |
d54e81f9 | 717 | blr x16 // call sys_* routine |
60ffc30d CM |
718 | |
719 | __sys_trace_return: | |
1014c81d AT |
720 | str x0, [sp, #S_X0] // save returned x0 |
721 | __sys_trace_return_skipped: | |
3157858f AT |
722 | mov x0, sp |
723 | bl syscall_trace_exit | |
60ffc30d CM |
724 | b ret_to_user |
725 | ||
d54e81f9 WD |
726 | __ni_sys_trace: |
727 | mov x0, sp | |
728 | bl do_ni_syscall | |
729 | b __sys_trace_return | |
730 | ||
60ffc30d CM |
731 | /* |
732 | * Special system call wrappers. | |
733 | */ | |
60ffc30d CM |
734 | ENTRY(sys_rt_sigreturn_wrapper) |
735 | mov x0, sp | |
736 | b sys_rt_sigreturn | |
737 | ENDPROC(sys_rt_sigreturn_wrapper) |