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9703d9d7 CM |
1 | /* |
2 | * Low-level CPU initialisation | |
3 | * Based on arch/arm/kernel/head.S | |
4 | * | |
5 | * Copyright (C) 1994-2002 Russell King | |
6 | * Copyright (C) 2003-2012 ARM Ltd. | |
7 | * Authors: Catalin Marinas <catalin.marinas@arm.com> | |
8 | * Will Deacon <will.deacon@arm.com> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #include <linux/linkage.h> | |
24 | #include <linux/init.h> | |
021f6537 | 25 | #include <linux/irqchip/arm-gic-v3.h> |
9703d9d7 CM |
26 | |
27 | #include <asm/assembler.h> | |
28 | #include <asm/ptrace.h> | |
29 | #include <asm/asm-offsets.h> | |
c218bca7 | 30 | #include <asm/cache.h> |
0359b0e2 | 31 | #include <asm/cputype.h> |
9703d9d7 CM |
32 | #include <asm/memory.h> |
33 | #include <asm/thread_info.h> | |
34 | #include <asm/pgtable-hwdef.h> | |
35 | #include <asm/pgtable.h> | |
36 | #include <asm/page.h> | |
f35a9205 | 37 | #include <asm/virt.h> |
9703d9d7 | 38 | |
6f4d57fa | 39 | #define __PHYS_OFFSET (KERNEL_START - TEXT_OFFSET) |
9703d9d7 | 40 | |
4190312b AB |
41 | #if (TEXT_OFFSET & 0xfff) != 0 |
42 | #error TEXT_OFFSET must be at least 4KB aligned | |
43 | #elif (PAGE_OFFSET & 0x1fffff) != 0 | |
da57a369 | 44 | #error PAGE_OFFSET must be at least 2MB aligned |
4190312b | 45 | #elif TEXT_OFFSET > 0x1fffff |
da57a369 | 46 | #error TEXT_OFFSET must be less than 2MB |
9703d9d7 CM |
47 | #endif |
48 | ||
9703d9d7 CM |
49 | #ifdef CONFIG_ARM64_64K_PAGES |
50 | #define BLOCK_SHIFT PAGE_SHIFT | |
51 | #define BLOCK_SIZE PAGE_SIZE | |
383c2799 | 52 | #define TABLE_SHIFT PMD_SHIFT |
9703d9d7 CM |
53 | #else |
54 | #define BLOCK_SHIFT SECTION_SHIFT | |
55 | #define BLOCK_SIZE SECTION_SIZE | |
383c2799 | 56 | #define TABLE_SHIFT PUD_SHIFT |
9703d9d7 CM |
57 | #endif |
58 | ||
6f4d57fa | 59 | #define KERNEL_START _text |
9703d9d7 CM |
60 | #define KERNEL_END _end |
61 | ||
62 | /* | |
63 | * Initial memory map attributes. | |
64 | */ | |
9703d9d7 CM |
65 | #define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF | PTE_SHARED |
66 | #define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S | |
9703d9d7 CM |
67 | |
68 | #ifdef CONFIG_ARM64_64K_PAGES | |
69 | #define MM_MMUFLAGS PTE_ATTRINDX(MT_NORMAL) | PTE_FLAGS | |
9703d9d7 CM |
70 | #else |
71 | #define MM_MMUFLAGS PMD_ATTRINDX(MT_NORMAL) | PMD_FLAGS | |
9703d9d7 CM |
72 | #endif |
73 | ||
74 | /* | |
75 | * Kernel startup entry point. | |
76 | * --------------------------- | |
77 | * | |
78 | * The requirements are: | |
79 | * MMU = off, D-cache = off, I-cache = on or off, | |
80 | * x0 = physical address to the FDT blob. | |
81 | * | |
82 | * This code is mostly position independent so you call this at | |
83 | * __pa(PAGE_OFFSET + TEXT_OFFSET). | |
84 | * | |
85 | * Note that the callee-saved registers are used for storing variables | |
86 | * that are useful before the MMU is enabled. The allocations are described | |
87 | * in the entry routines. | |
88 | */ | |
89 | __HEAD | |
90 | ||
91 | /* | |
92 | * DO NOT MODIFY. Image header expected by Linux boot-loaders. | |
93 | */ | |
3c7f2550 MS |
94 | #ifdef CONFIG_EFI |
95 | efi_head: | |
96 | /* | |
97 | * This add instruction has no meaningful effect except that | |
98 | * its opcode forms the magic "MZ" signature required by UEFI. | |
99 | */ | |
100 | add x13, x18, #0x16 | |
101 | b stext | |
102 | #else | |
9703d9d7 CM |
103 | b stext // branch to kernel start, magic |
104 | .long 0 // reserved | |
3c7f2550 | 105 | #endif |
a2c1d73b MR |
106 | .quad _kernel_offset_le // Image load offset from start of RAM, little-endian |
107 | .quad _kernel_size_le // Effective size of kernel image, little-endian | |
108 | .quad _kernel_flags_le // Informative flags, little-endian | |
4370eec0 RF |
109 | .quad 0 // reserved |
110 | .quad 0 // reserved | |
111 | .quad 0 // reserved | |
112 | .byte 0x41 // Magic number, "ARM\x64" | |
113 | .byte 0x52 | |
114 | .byte 0x4d | |
115 | .byte 0x64 | |
3c7f2550 MS |
116 | #ifdef CONFIG_EFI |
117 | .long pe_header - efi_head // Offset to the PE header. | |
118 | #else | |
4370eec0 | 119 | .word 0 // reserved |
3c7f2550 MS |
120 | #endif |
121 | ||
122 | #ifdef CONFIG_EFI | |
95b39596 AB |
123 | .globl stext_offset |
124 | .set stext_offset, stext - efi_head | |
3c7f2550 MS |
125 | .align 3 |
126 | pe_header: | |
127 | .ascii "PE" | |
128 | .short 0 | |
129 | coff_header: | |
130 | .short 0xaa64 // AArch64 | |
131 | .short 2 // nr_sections | |
132 | .long 0 // TimeDateStamp | |
133 | .long 0 // PointerToSymbolTable | |
134 | .long 1 // NumberOfSymbols | |
135 | .short section_table - optional_header // SizeOfOptionalHeader | |
136 | .short 0x206 // Characteristics. | |
137 | // IMAGE_FILE_DEBUG_STRIPPED | | |
138 | // IMAGE_FILE_EXECUTABLE_IMAGE | | |
139 | // IMAGE_FILE_LINE_NUMS_STRIPPED | |
140 | optional_header: | |
141 | .short 0x20b // PE32+ format | |
142 | .byte 0x02 // MajorLinkerVersion | |
143 | .byte 0x14 // MinorLinkerVersion | |
c16173fa | 144 | .long _end - stext // SizeOfCode |
3c7f2550 MS |
145 | .long 0 // SizeOfInitializedData |
146 | .long 0 // SizeOfUninitializedData | |
147 | .long efi_stub_entry - efi_head // AddressOfEntryPoint | |
95b39596 | 148 | .long stext_offset // BaseOfCode |
3c7f2550 MS |
149 | |
150 | extra_header_fields: | |
151 | .quad 0 // ImageBase | |
ea6bc80d | 152 | .long 0x1000 // SectionAlignment |
a352ea3e | 153 | .long PECOFF_FILE_ALIGNMENT // FileAlignment |
3c7f2550 MS |
154 | .short 0 // MajorOperatingSystemVersion |
155 | .short 0 // MinorOperatingSystemVersion | |
156 | .short 0 // MajorImageVersion | |
157 | .short 0 // MinorImageVersion | |
158 | .short 0 // MajorSubsystemVersion | |
159 | .short 0 // MinorSubsystemVersion | |
160 | .long 0 // Win32VersionValue | |
161 | ||
c16173fa | 162 | .long _end - efi_head // SizeOfImage |
3c7f2550 MS |
163 | |
164 | // Everything before the kernel image is considered part of the header | |
95b39596 | 165 | .long stext_offset // SizeOfHeaders |
3c7f2550 MS |
166 | .long 0 // CheckSum |
167 | .short 0xa // Subsystem (EFI application) | |
168 | .short 0 // DllCharacteristics | |
169 | .quad 0 // SizeOfStackReserve | |
170 | .quad 0 // SizeOfStackCommit | |
171 | .quad 0 // SizeOfHeapReserve | |
172 | .quad 0 // SizeOfHeapCommit | |
173 | .long 0 // LoaderFlags | |
174 | .long 0x6 // NumberOfRvaAndSizes | |
175 | ||
176 | .quad 0 // ExportTable | |
177 | .quad 0 // ImportTable | |
178 | .quad 0 // ResourceTable | |
179 | .quad 0 // ExceptionTable | |
180 | .quad 0 // CertificationTable | |
181 | .quad 0 // BaseRelocationTable | |
182 | ||
183 | // Section table | |
184 | section_table: | |
185 | ||
186 | /* | |
187 | * The EFI application loader requires a relocation section | |
188 | * because EFI applications must be relocatable. This is a | |
189 | * dummy section as far as we are concerned. | |
190 | */ | |
191 | .ascii ".reloc" | |
192 | .byte 0 | |
193 | .byte 0 // end of 0 padding of section name | |
194 | .long 0 | |
195 | .long 0 | |
196 | .long 0 // SizeOfRawData | |
197 | .long 0 // PointerToRawData | |
198 | .long 0 // PointerToRelocations | |
199 | .long 0 // PointerToLineNumbers | |
200 | .short 0 // NumberOfRelocations | |
201 | .short 0 // NumberOfLineNumbers | |
202 | .long 0x42100040 // Characteristics (section flags) | |
203 | ||
204 | ||
205 | .ascii ".text" | |
206 | .byte 0 | |
207 | .byte 0 | |
208 | .byte 0 // end of 0 padding of section name | |
c16173fa | 209 | .long _end - stext // VirtualSize |
95b39596 | 210 | .long stext_offset // VirtualAddress |
3c7f2550 | 211 | .long _edata - stext // SizeOfRawData |
95b39596 | 212 | .long stext_offset // PointerToRawData |
3c7f2550 MS |
213 | |
214 | .long 0 // PointerToRelocations (0 for executables) | |
215 | .long 0 // PointerToLineNumbers (0 for executables) | |
216 | .short 0 // NumberOfRelocations (0 for executables) | |
217 | .short 0 // NumberOfLineNumbers (0 for executables) | |
218 | .long 0xe0500020 // Characteristics (section flags) | |
ea6bc80d AB |
219 | |
220 | /* | |
221 | * EFI will load stext onwards at the 4k section alignment | |
222 | * described in the PE/COFF header. To ensure that instruction | |
223 | * sequences using an adrp and a :lo12: immediate will function | |
224 | * correctly at this alignment, we must ensure that stext is | |
225 | * placed at a 4k boundary in the Image to begin with. | |
226 | */ | |
227 | .align 12 | |
3c7f2550 | 228 | #endif |
9703d9d7 CM |
229 | |
230 | ENTRY(stext) | |
da9c177d | 231 | bl preserve_boot_args |
828e9834 | 232 | bl el2_setup // Drop to EL1, w20=cpu_boot_mode |
6f4d57fa | 233 | adrp x24, __PHYS_OFFSET |
828e9834 | 234 | bl set_cpu_boot_mode_flag |
9703d9d7 CM |
235 | bl __create_page_tables // x25=TTBR0, x26=TTBR1 |
236 | /* | |
a591ede4 MZ |
237 | * The following calls CPU setup code, see arch/arm64/mm/proc.S for |
238 | * details. | |
9703d9d7 CM |
239 | * On return, the CPU will be ready for the MMU to be turned on and |
240 | * the TCR will have been set. | |
241 | */ | |
a871d354 | 242 | ldr x27, =__mmap_switched // address to jump to after |
9703d9d7 | 243 | // MMU has been enabled |
8b0a9575 | 244 | adr_l lr, __enable_mmu // return (PIC) address |
a591ede4 | 245 | b __cpu_setup // initialise processor |
9703d9d7 CM |
246 | ENDPROC(stext) |
247 | ||
da9c177d AB |
248 | /* |
249 | * Preserve the arguments passed by the bootloader in x0 .. x3 | |
250 | */ | |
251 | preserve_boot_args: | |
252 | mov x21, x0 // x21=FDT | |
253 | ||
254 | adr_l x0, boot_args // record the contents of | |
255 | stp x21, x1, [x0] // x0 .. x3 at kernel entry | |
256 | stp x2, x3, [x0, #16] | |
257 | ||
258 | dmb sy // needed before dc ivac with | |
259 | // MMU off | |
260 | ||
261 | add x1, x0, #0x20 // 4 x 8 bytes | |
262 | b __inval_cache_range // tail call | |
263 | ENDPROC(preserve_boot_args) | |
264 | ||
034edabe LA |
265 | /* |
266 | * Macro to create a table entry to the next page. | |
267 | * | |
268 | * tbl: page table address | |
269 | * virt: virtual address | |
270 | * shift: #imm page table shift | |
271 | * ptrs: #imm pointers per table page | |
272 | * | |
273 | * Preserves: virt | |
274 | * Corrupts: tmp1, tmp2 | |
275 | * Returns: tbl -> next level table page address | |
276 | */ | |
277 | .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2 | |
278 | lsr \tmp1, \virt, #\shift | |
279 | and \tmp1, \tmp1, #\ptrs - 1 // table index | |
280 | add \tmp2, \tbl, #PAGE_SIZE | |
281 | orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type | |
282 | str \tmp2, [\tbl, \tmp1, lsl #3] | |
283 | add \tbl, \tbl, #PAGE_SIZE // next level table page | |
284 | .endm | |
285 | ||
286 | /* | |
287 | * Macro to populate the PGD (and possibily PUD) for the corresponding | |
288 | * block entry in the next level (tbl) for the given virtual address. | |
289 | * | |
290 | * Preserves: tbl, next, virt | |
291 | * Corrupts: tmp1, tmp2 | |
292 | */ | |
293 | .macro create_pgd_entry, tbl, virt, tmp1, tmp2 | |
294 | create_table_entry \tbl, \virt, PGDIR_SHIFT, PTRS_PER_PGD, \tmp1, \tmp2 | |
295 | #if SWAPPER_PGTABLE_LEVELS == 3 | |
296 | create_table_entry \tbl, \virt, TABLE_SHIFT, PTRS_PER_PTE, \tmp1, \tmp2 | |
297 | #endif | |
298 | .endm | |
299 | ||
300 | /* | |
301 | * Macro to populate block entries in the page table for the start..end | |
302 | * virtual range (inclusive). | |
303 | * | |
304 | * Preserves: tbl, flags | |
305 | * Corrupts: phys, start, end, pstate | |
306 | */ | |
307 | .macro create_block_map, tbl, flags, phys, start, end | |
308 | lsr \phys, \phys, #BLOCK_SHIFT | |
309 | lsr \start, \start, #BLOCK_SHIFT | |
310 | and \start, \start, #PTRS_PER_PTE - 1 // table index | |
311 | orr \phys, \flags, \phys, lsl #BLOCK_SHIFT // table entry | |
312 | lsr \end, \end, #BLOCK_SHIFT | |
313 | and \end, \end, #PTRS_PER_PTE - 1 // table end index | |
314 | 9999: str \phys, [\tbl, \start, lsl #3] // store the entry | |
315 | add \start, \start, #1 // next entry | |
316 | add \phys, \phys, #BLOCK_SIZE // next block | |
317 | cmp \start, \end | |
318 | b.ls 9999b | |
319 | .endm | |
320 | ||
321 | /* | |
322 | * Setup the initial page tables. We only setup the barest amount which is | |
323 | * required to get the kernel running. The following sections are required: | |
324 | * - identity mapping to enable the MMU (low address, TTBR0) | |
325 | * - first few MB of the kernel linear mapping to jump to once the MMU has | |
61bd93ce | 326 | * been enabled |
034edabe LA |
327 | */ |
328 | __create_page_tables: | |
6f4d57fa AB |
329 | adrp x25, idmap_pg_dir |
330 | adrp x26, swapper_pg_dir | |
034edabe LA |
331 | mov x27, lr |
332 | ||
333 | /* | |
334 | * Invalidate the idmap and swapper page tables to avoid potential | |
335 | * dirty cache lines being evicted. | |
336 | */ | |
337 | mov x0, x25 | |
338 | add x1, x26, #SWAPPER_DIR_SIZE | |
339 | bl __inval_cache_range | |
340 | ||
341 | /* | |
342 | * Clear the idmap and swapper page tables. | |
343 | */ | |
344 | mov x0, x25 | |
345 | add x6, x26, #SWAPPER_DIR_SIZE | |
346 | 1: stp xzr, xzr, [x0], #16 | |
347 | stp xzr, xzr, [x0], #16 | |
348 | stp xzr, xzr, [x0], #16 | |
349 | stp xzr, xzr, [x0], #16 | |
350 | cmp x0, x6 | |
351 | b.lo 1b | |
352 | ||
353 | ldr x7, =MM_MMUFLAGS | |
354 | ||
355 | /* | |
356 | * Create the identity mapping. | |
357 | */ | |
358 | mov x0, x25 // idmap_pg_dir | |
5dfe9d7d | 359 | adrp x3, __idmap_text_start // __pa(__idmap_text_start) |
dd006da2 AB |
360 | |
361 | #ifndef CONFIG_ARM64_VA_BITS_48 | |
362 | #define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3) | |
363 | #define EXTRA_PTRS (1 << (48 - EXTRA_SHIFT)) | |
364 | ||
365 | /* | |
366 | * If VA_BITS < 48, it may be too small to allow for an ID mapping to be | |
367 | * created that covers system RAM if that is located sufficiently high | |
368 | * in the physical address space. So for the ID map, use an extended | |
369 | * virtual range in that case, by configuring an additional translation | |
370 | * level. | |
371 | * First, we have to verify our assumption that the current value of | |
372 | * VA_BITS was chosen such that all translation levels are fully | |
373 | * utilised, and that lowering T0SZ will always result in an additional | |
374 | * translation level to be configured. | |
375 | */ | |
376 | #if VA_BITS != EXTRA_SHIFT | |
377 | #error "Mismatch between VA_BITS and page size/number of translation levels" | |
378 | #endif | |
379 | ||
380 | /* | |
381 | * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the | |
5dfe9d7d | 382 | * entire ID map region can be mapped. As T0SZ == (64 - #bits used), |
dd006da2 | 383 | * this number conveniently equals the number of leading zeroes in |
5dfe9d7d | 384 | * the physical address of __idmap_text_end. |
dd006da2 | 385 | */ |
5dfe9d7d | 386 | adrp x5, __idmap_text_end |
dd006da2 AB |
387 | clz x5, x5 |
388 | cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough? | |
389 | b.ge 1f // .. then skip additional level | |
390 | ||
0c20856c MR |
391 | adr_l x6, idmap_t0sz |
392 | str x5, [x6] | |
393 | dmb sy | |
394 | dc ivac, x6 // Invalidate potentially stale cache line | |
dd006da2 AB |
395 | |
396 | create_table_entry x0, x3, EXTRA_SHIFT, EXTRA_PTRS, x5, x6 | |
397 | 1: | |
398 | #endif | |
399 | ||
034edabe | 400 | create_pgd_entry x0, x3, x5, x6 |
5dfe9d7d AB |
401 | mov x5, x3 // __pa(__idmap_text_start) |
402 | adr_l x6, __idmap_text_end // __pa(__idmap_text_end) | |
034edabe LA |
403 | create_block_map x0, x7, x3, x5, x6 |
404 | ||
405 | /* | |
406 | * Map the kernel image (starting with PHYS_OFFSET). | |
407 | */ | |
408 | mov x0, x26 // swapper_pg_dir | |
409 | mov x5, #PAGE_OFFSET | |
410 | create_pgd_entry x0, x5, x3, x6 | |
6f4d57fa | 411 | ldr x6, =KERNEL_END // __va(KERNEL_END) |
034edabe LA |
412 | mov x3, x24 // phys offset |
413 | create_block_map x0, x7, x3, x5, x6 | |
414 | ||
034edabe LA |
415 | /* |
416 | * Since the page tables have been populated with non-cacheable | |
417 | * accesses (MMU disabled), invalidate the idmap and swapper page | |
418 | * tables again to remove any speculatively loaded cache lines. | |
419 | */ | |
420 | mov x0, x25 | |
421 | add x1, x26, #SWAPPER_DIR_SIZE | |
91d57155 | 422 | dmb sy |
034edabe LA |
423 | bl __inval_cache_range |
424 | ||
425 | mov lr, x27 | |
426 | ret | |
427 | ENDPROC(__create_page_tables) | |
428 | .ltorg | |
429 | ||
034edabe | 430 | /* |
a871d354 | 431 | * The following fragment of code is executed with the MMU enabled. |
034edabe | 432 | */ |
a871d354 | 433 | .set initial_sp, init_thread_union + THREAD_START_SP |
034edabe | 434 | __mmap_switched: |
a871d354 AB |
435 | adr_l x6, __bss_start |
436 | adr_l x7, __bss_stop | |
034edabe | 437 | |
034edabe LA |
438 | 1: cmp x6, x7 |
439 | b.hs 2f | |
440 | str xzr, [x6], #8 // Clear BSS | |
441 | b 1b | |
442 | 2: | |
a871d354 AB |
443 | adr_l sp, initial_sp, x4 |
444 | str_l x21, __fdt_pointer, x5 // Save FDT pointer | |
445 | str_l x24, memstart_addr, x6 // Save PHYS_OFFSET | |
034edabe LA |
446 | mov x29, #0 |
447 | b start_kernel | |
448 | ENDPROC(__mmap_switched) | |
449 | ||
450 | /* | |
451 | * end early head section, begin head code that is also used for | |
452 | * hotplug and needs to have the same protections as the text region | |
453 | */ | |
454 | .section ".text","ax" | |
9703d9d7 CM |
455 | /* |
456 | * If we're fortunate enough to boot at EL2, ensure that the world is | |
457 | * sane before dropping to EL1. | |
828e9834 ML |
458 | * |
459 | * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x20 if | |
460 | * booted in EL1 or EL2 respectively. | |
9703d9d7 CM |
461 | */ |
462 | ENTRY(el2_setup) | |
463 | mrs x0, CurrentEL | |
974c8e45 | 464 | cmp x0, #CurrentEL_EL2 |
9cf71728 ML |
465 | b.ne 1f |
466 | mrs x0, sctlr_el2 | |
467 | CPU_BE( orr x0, x0, #(1 << 25) ) // Set the EE bit for EL2 | |
468 | CPU_LE( bic x0, x0, #(1 << 25) ) // Clear the EE bit for EL2 | |
469 | msr sctlr_el2, x0 | |
470 | b 2f | |
471 | 1: mrs x0, sctlr_el1 | |
472 | CPU_BE( orr x0, x0, #(3 << 24) ) // Set the EE and E0E bits for EL1 | |
473 | CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1 | |
474 | msr sctlr_el1, x0 | |
828e9834 | 475 | mov w20, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1 |
9cf71728 | 476 | isb |
9703d9d7 CM |
477 | ret |
478 | ||
479 | /* Hyp configuration. */ | |
9cf71728 | 480 | 2: mov x0, #(1 << 31) // 64-bit EL1 |
9703d9d7 CM |
481 | msr hcr_el2, x0 |
482 | ||
483 | /* Generic timers. */ | |
484 | mrs x0, cnthctl_el2 | |
485 | orr x0, x0, #3 // Enable EL1 physical timers | |
486 | msr cnthctl_el2, x0 | |
1f75ff0a | 487 | msr cntvoff_el2, xzr // Clear virtual offset |
9703d9d7 | 488 | |
021f6537 MZ |
489 | #ifdef CONFIG_ARM_GIC_V3 |
490 | /* GICv3 system register access */ | |
491 | mrs x0, id_aa64pfr0_el1 | |
492 | ubfx x0, x0, #24, #4 | |
493 | cmp x0, #1 | |
494 | b.ne 3f | |
495 | ||
72c58395 | 496 | mrs_s x0, ICC_SRE_EL2 |
021f6537 MZ |
497 | orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1 |
498 | orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1 | |
72c58395 | 499 | msr_s ICC_SRE_EL2, x0 |
021f6537 | 500 | isb // Make sure SRE is now set |
d271976d MZ |
501 | mrs_s x0, ICC_SRE_EL2 // Read SRE back, |
502 | tbz x0, #0, 3f // and check that it sticks | |
72c58395 | 503 | msr_s ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults |
021f6537 MZ |
504 | |
505 | 3: | |
506 | #endif | |
507 | ||
9703d9d7 CM |
508 | /* Populate ID registers. */ |
509 | mrs x0, midr_el1 | |
510 | mrs x1, mpidr_el1 | |
511 | msr vpidr_el2, x0 | |
512 | msr vmpidr_el2, x1 | |
513 | ||
514 | /* sctlr_el1 */ | |
515 | mov x0, #0x0800 // Set/clear RES{1,0} bits | |
9cf71728 ML |
516 | CPU_BE( movk x0, #0x33d0, lsl #16 ) // Set EE and E0E on BE systems |
517 | CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems | |
9703d9d7 CM |
518 | msr sctlr_el1, x0 |
519 | ||
520 | /* Coprocessor traps. */ | |
521 | mov x0, #0x33ff | |
522 | msr cptr_el2, x0 // Disable copro. traps to EL2 | |
523 | ||
524 | #ifdef CONFIG_COMPAT | |
525 | msr hstr_el2, xzr // Disable CP15 traps to EL2 | |
526 | #endif | |
527 | ||
d10bcd47 WD |
528 | /* EL2 debug */ |
529 | mrs x0, pmcr_el0 // Disable debug access traps | |
530 | ubfx x0, x0, #11, #5 // to EL2 and allow access to | |
531 | msr mdcr_el2, x0 // all PMU counters from EL1 | |
532 | ||
7dbfbe5b MZ |
533 | /* Stage-2 translation */ |
534 | msr vttbr_el2, xzr | |
535 | ||
712c6ff4 | 536 | /* Hypervisor stub */ |
ac2dec5f LA |
537 | adrp x0, __hyp_stub_vectors |
538 | add x0, x0, #:lo12:__hyp_stub_vectors | |
712c6ff4 MZ |
539 | msr vbar_el2, x0 |
540 | ||
9703d9d7 CM |
541 | /* spsr */ |
542 | mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\ | |
543 | PSR_MODE_EL1h) | |
544 | msr spsr_el2, x0 | |
545 | msr elr_el2, lr | |
828e9834 | 546 | mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 |
9703d9d7 CM |
547 | eret |
548 | ENDPROC(el2_setup) | |
549 | ||
828e9834 ML |
550 | /* |
551 | * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed | |
552 | * in x20. See arch/arm64/include/asm/virt.h for more info. | |
553 | */ | |
554 | ENTRY(set_cpu_boot_mode_flag) | |
6f4d57fa | 555 | adr_l x1, __boot_cpu_mode |
828e9834 ML |
556 | cmp w20, #BOOT_CPU_MODE_EL2 |
557 | b.ne 1f | |
558 | add x1, x1, #4 | |
d0488597 WD |
559 | 1: str w20, [x1] // This CPU has booted in EL1 |
560 | dmb sy | |
561 | dc ivac, x1 // Invalidate potentially stale cache line | |
828e9834 ML |
562 | ret |
563 | ENDPROC(set_cpu_boot_mode_flag) | |
564 | ||
f35a9205 MZ |
565 | /* |
566 | * We need to find out the CPU boot mode long after boot, so we need to | |
567 | * store it in a writable variable. | |
568 | * | |
569 | * This is not in .bss, because we set it sufficiently early that the boot-time | |
570 | * zeroing of .bss would clobber it. | |
571 | */ | |
c218bca7 | 572 | .pushsection .data..cacheline_aligned |
c218bca7 | 573 | .align L1_CACHE_SHIFT |
947bb758 | 574 | ENTRY(__boot_cpu_mode) |
f35a9205 | 575 | .long BOOT_CPU_MODE_EL2 |
424a3838 | 576 | .long BOOT_CPU_MODE_EL1 |
f35a9205 MZ |
577 | .popsection |
578 | ||
9703d9d7 CM |
579 | /* |
580 | * This provides a "holding pen" for platforms to hold all secondary | |
581 | * cores are held until we're ready for them to initialise. | |
582 | */ | |
583 | ENTRY(secondary_holding_pen) | |
828e9834 | 584 | bl el2_setup // Drop to EL1, w20=cpu_boot_mode |
828e9834 | 585 | bl set_cpu_boot_mode_flag |
9703d9d7 | 586 | mrs x0, mpidr_el1 |
0359b0e2 JM |
587 | ldr x1, =MPIDR_HWID_BITMASK |
588 | and x0, x0, x1 | |
b1c98297 | 589 | adr_l x3, secondary_holding_pen_release |
9703d9d7 CM |
590 | pen: ldr x4, [x3] |
591 | cmp x4, x0 | |
592 | b.eq secondary_startup | |
593 | wfe | |
594 | b pen | |
595 | ENDPROC(secondary_holding_pen) | |
652af899 MR |
596 | |
597 | /* | |
598 | * Secondary entry point that jumps straight into the kernel. Only to | |
599 | * be used where CPUs are brought online dynamically by the kernel. | |
600 | */ | |
601 | ENTRY(secondary_entry) | |
652af899 | 602 | bl el2_setup // Drop to EL1 |
85cc00ea | 603 | bl set_cpu_boot_mode_flag |
652af899 MR |
604 | b secondary_startup |
605 | ENDPROC(secondary_entry) | |
9703d9d7 CM |
606 | |
607 | ENTRY(secondary_startup) | |
608 | /* | |
609 | * Common entry point for secondary CPUs. | |
610 | */ | |
6f4d57fa AB |
611 | adrp x25, idmap_pg_dir |
612 | adrp x26, swapper_pg_dir | |
a591ede4 | 613 | bl __cpu_setup // initialise processor |
9703d9d7 CM |
614 | |
615 | ldr x21, =secondary_data | |
616 | ldr x27, =__secondary_switched // address to jump to after enabling the MMU | |
617 | b __enable_mmu | |
618 | ENDPROC(secondary_startup) | |
619 | ||
620 | ENTRY(__secondary_switched) | |
621 | ldr x0, [x21] // get secondary_data.stack | |
622 | mov sp, x0 | |
623 | mov x29, #0 | |
624 | b secondary_start_kernel | |
625 | ENDPROC(__secondary_switched) | |
9703d9d7 CM |
626 | |
627 | /* | |
8b0a9575 | 628 | * Enable the MMU. |
9703d9d7 | 629 | * |
8b0a9575 AB |
630 | * x0 = SCTLR_EL1 value for turning on the MMU. |
631 | * x27 = *virtual* address to jump to upon completion | |
632 | * | |
633 | * other registers depend on the function called upon completion | |
9703d9d7 | 634 | */ |
5dfe9d7d | 635 | .section ".idmap.text", "ax" |
9703d9d7 CM |
636 | __enable_mmu: |
637 | ldr x5, =vectors | |
638 | msr vbar_el1, x5 | |
639 | msr ttbr0_el1, x25 // load TTBR0 | |
640 | msr ttbr1_el1, x26 // load TTBR1 | |
641 | isb | |
9703d9d7 CM |
642 | msr sctlr_el1, x0 |
643 | isb | |
8ec41987 WD |
644 | /* |
645 | * Invalidate the local I-cache so that any instructions fetched | |
646 | * speculatively from the PoC are discarded, since they may have | |
647 | * been dynamically patched at the PoU. | |
648 | */ | |
649 | ic iallu | |
650 | dsb nsh | |
651 | isb | |
9703d9d7 | 652 | br x27 |
8b0a9575 | 653 | ENDPROC(__enable_mmu) |