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9703d9d7 CM |
1 | /* |
2 | * Low-level CPU initialisation | |
3 | * Based on arch/arm/kernel/head.S | |
4 | * | |
5 | * Copyright (C) 1994-2002 Russell King | |
6 | * Copyright (C) 2003-2012 ARM Ltd. | |
7 | * Authors: Catalin Marinas <catalin.marinas@arm.com> | |
8 | * Will Deacon <will.deacon@arm.com> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #include <linux/linkage.h> | |
24 | #include <linux/init.h> | |
021f6537 | 25 | #include <linux/irqchip/arm-gic-v3.h> |
9703d9d7 CM |
26 | |
27 | #include <asm/assembler.h> | |
28 | #include <asm/ptrace.h> | |
29 | #include <asm/asm-offsets.h> | |
c218bca7 | 30 | #include <asm/cache.h> |
0359b0e2 | 31 | #include <asm/cputype.h> |
9703d9d7 CM |
32 | #include <asm/memory.h> |
33 | #include <asm/thread_info.h> | |
34 | #include <asm/pgtable-hwdef.h> | |
35 | #include <asm/pgtable.h> | |
36 | #include <asm/page.h> | |
f35a9205 | 37 | #include <asm/virt.h> |
9703d9d7 | 38 | |
6f4d57fa | 39 | #define __PHYS_OFFSET (KERNEL_START - TEXT_OFFSET) |
9703d9d7 | 40 | |
4190312b AB |
41 | #if (TEXT_OFFSET & 0xfff) != 0 |
42 | #error TEXT_OFFSET must be at least 4KB aligned | |
43 | #elif (PAGE_OFFSET & 0x1fffff) != 0 | |
da57a369 | 44 | #error PAGE_OFFSET must be at least 2MB aligned |
4190312b | 45 | #elif TEXT_OFFSET > 0x1fffff |
da57a369 | 46 | #error TEXT_OFFSET must be less than 2MB |
9703d9d7 CM |
47 | #endif |
48 | ||
9703d9d7 CM |
49 | #ifdef CONFIG_ARM64_64K_PAGES |
50 | #define BLOCK_SHIFT PAGE_SHIFT | |
51 | #define BLOCK_SIZE PAGE_SIZE | |
383c2799 | 52 | #define TABLE_SHIFT PMD_SHIFT |
9703d9d7 CM |
53 | #else |
54 | #define BLOCK_SHIFT SECTION_SHIFT | |
55 | #define BLOCK_SIZE SECTION_SIZE | |
383c2799 | 56 | #define TABLE_SHIFT PUD_SHIFT |
9703d9d7 CM |
57 | #endif |
58 | ||
6f4d57fa | 59 | #define KERNEL_START _text |
9703d9d7 CM |
60 | #define KERNEL_END _end |
61 | ||
62 | /* | |
63 | * Initial memory map attributes. | |
64 | */ | |
65 | #ifndef CONFIG_SMP | |
66 | #define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF | |
67 | #define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF | |
68 | #else | |
69 | #define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF | PTE_SHARED | |
70 | #define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S | |
71 | #endif | |
72 | ||
73 | #ifdef CONFIG_ARM64_64K_PAGES | |
74 | #define MM_MMUFLAGS PTE_ATTRINDX(MT_NORMAL) | PTE_FLAGS | |
9703d9d7 CM |
75 | #else |
76 | #define MM_MMUFLAGS PMD_ATTRINDX(MT_NORMAL) | PMD_FLAGS | |
9703d9d7 CM |
77 | #endif |
78 | ||
79 | /* | |
80 | * Kernel startup entry point. | |
81 | * --------------------------- | |
82 | * | |
83 | * The requirements are: | |
84 | * MMU = off, D-cache = off, I-cache = on or off, | |
85 | * x0 = physical address to the FDT blob. | |
86 | * | |
87 | * This code is mostly position independent so you call this at | |
88 | * __pa(PAGE_OFFSET + TEXT_OFFSET). | |
89 | * | |
90 | * Note that the callee-saved registers are used for storing variables | |
91 | * that are useful before the MMU is enabled. The allocations are described | |
92 | * in the entry routines. | |
93 | */ | |
94 | __HEAD | |
95 | ||
96 | /* | |
97 | * DO NOT MODIFY. Image header expected by Linux boot-loaders. | |
98 | */ | |
3c7f2550 MS |
99 | #ifdef CONFIG_EFI |
100 | efi_head: | |
101 | /* | |
102 | * This add instruction has no meaningful effect except that | |
103 | * its opcode forms the magic "MZ" signature required by UEFI. | |
104 | */ | |
105 | add x13, x18, #0x16 | |
106 | b stext | |
107 | #else | |
9703d9d7 CM |
108 | b stext // branch to kernel start, magic |
109 | .long 0 // reserved | |
3c7f2550 | 110 | #endif |
a2c1d73b MR |
111 | .quad _kernel_offset_le // Image load offset from start of RAM, little-endian |
112 | .quad _kernel_size_le // Effective size of kernel image, little-endian | |
113 | .quad _kernel_flags_le // Informative flags, little-endian | |
4370eec0 RF |
114 | .quad 0 // reserved |
115 | .quad 0 // reserved | |
116 | .quad 0 // reserved | |
117 | .byte 0x41 // Magic number, "ARM\x64" | |
118 | .byte 0x52 | |
119 | .byte 0x4d | |
120 | .byte 0x64 | |
3c7f2550 MS |
121 | #ifdef CONFIG_EFI |
122 | .long pe_header - efi_head // Offset to the PE header. | |
123 | #else | |
4370eec0 | 124 | .word 0 // reserved |
3c7f2550 MS |
125 | #endif |
126 | ||
127 | #ifdef CONFIG_EFI | |
95b39596 AB |
128 | .globl stext_offset |
129 | .set stext_offset, stext - efi_head | |
3c7f2550 MS |
130 | .align 3 |
131 | pe_header: | |
132 | .ascii "PE" | |
133 | .short 0 | |
134 | coff_header: | |
135 | .short 0xaa64 // AArch64 | |
136 | .short 2 // nr_sections | |
137 | .long 0 // TimeDateStamp | |
138 | .long 0 // PointerToSymbolTable | |
139 | .long 1 // NumberOfSymbols | |
140 | .short section_table - optional_header // SizeOfOptionalHeader | |
141 | .short 0x206 // Characteristics. | |
142 | // IMAGE_FILE_DEBUG_STRIPPED | | |
143 | // IMAGE_FILE_EXECUTABLE_IMAGE | | |
144 | // IMAGE_FILE_LINE_NUMS_STRIPPED | |
145 | optional_header: | |
146 | .short 0x20b // PE32+ format | |
147 | .byte 0x02 // MajorLinkerVersion | |
148 | .byte 0x14 // MinorLinkerVersion | |
c16173fa | 149 | .long _end - stext // SizeOfCode |
3c7f2550 MS |
150 | .long 0 // SizeOfInitializedData |
151 | .long 0 // SizeOfUninitializedData | |
152 | .long efi_stub_entry - efi_head // AddressOfEntryPoint | |
95b39596 | 153 | .long stext_offset // BaseOfCode |
3c7f2550 MS |
154 | |
155 | extra_header_fields: | |
156 | .quad 0 // ImageBase | |
ea6bc80d | 157 | .long 0x1000 // SectionAlignment |
a352ea3e | 158 | .long PECOFF_FILE_ALIGNMENT // FileAlignment |
3c7f2550 MS |
159 | .short 0 // MajorOperatingSystemVersion |
160 | .short 0 // MinorOperatingSystemVersion | |
161 | .short 0 // MajorImageVersion | |
162 | .short 0 // MinorImageVersion | |
163 | .short 0 // MajorSubsystemVersion | |
164 | .short 0 // MinorSubsystemVersion | |
165 | .long 0 // Win32VersionValue | |
166 | ||
c16173fa | 167 | .long _end - efi_head // SizeOfImage |
3c7f2550 MS |
168 | |
169 | // Everything before the kernel image is considered part of the header | |
95b39596 | 170 | .long stext_offset // SizeOfHeaders |
3c7f2550 MS |
171 | .long 0 // CheckSum |
172 | .short 0xa // Subsystem (EFI application) | |
173 | .short 0 // DllCharacteristics | |
174 | .quad 0 // SizeOfStackReserve | |
175 | .quad 0 // SizeOfStackCommit | |
176 | .quad 0 // SizeOfHeapReserve | |
177 | .quad 0 // SizeOfHeapCommit | |
178 | .long 0 // LoaderFlags | |
179 | .long 0x6 // NumberOfRvaAndSizes | |
180 | ||
181 | .quad 0 // ExportTable | |
182 | .quad 0 // ImportTable | |
183 | .quad 0 // ResourceTable | |
184 | .quad 0 // ExceptionTable | |
185 | .quad 0 // CertificationTable | |
186 | .quad 0 // BaseRelocationTable | |
187 | ||
188 | // Section table | |
189 | section_table: | |
190 | ||
191 | /* | |
192 | * The EFI application loader requires a relocation section | |
193 | * because EFI applications must be relocatable. This is a | |
194 | * dummy section as far as we are concerned. | |
195 | */ | |
196 | .ascii ".reloc" | |
197 | .byte 0 | |
198 | .byte 0 // end of 0 padding of section name | |
199 | .long 0 | |
200 | .long 0 | |
201 | .long 0 // SizeOfRawData | |
202 | .long 0 // PointerToRawData | |
203 | .long 0 // PointerToRelocations | |
204 | .long 0 // PointerToLineNumbers | |
205 | .short 0 // NumberOfRelocations | |
206 | .short 0 // NumberOfLineNumbers | |
207 | .long 0x42100040 // Characteristics (section flags) | |
208 | ||
209 | ||
210 | .ascii ".text" | |
211 | .byte 0 | |
212 | .byte 0 | |
213 | .byte 0 // end of 0 padding of section name | |
c16173fa | 214 | .long _end - stext // VirtualSize |
95b39596 | 215 | .long stext_offset // VirtualAddress |
3c7f2550 | 216 | .long _edata - stext // SizeOfRawData |
95b39596 | 217 | .long stext_offset // PointerToRawData |
3c7f2550 MS |
218 | |
219 | .long 0 // PointerToRelocations (0 for executables) | |
220 | .long 0 // PointerToLineNumbers (0 for executables) | |
221 | .short 0 // NumberOfRelocations (0 for executables) | |
222 | .short 0 // NumberOfLineNumbers (0 for executables) | |
223 | .long 0xe0500020 // Characteristics (section flags) | |
ea6bc80d AB |
224 | |
225 | /* | |
226 | * EFI will load stext onwards at the 4k section alignment | |
227 | * described in the PE/COFF header. To ensure that instruction | |
228 | * sequences using an adrp and a :lo12: immediate will function | |
229 | * correctly at this alignment, we must ensure that stext is | |
230 | * placed at a 4k boundary in the Image to begin with. | |
231 | */ | |
232 | .align 12 | |
3c7f2550 | 233 | #endif |
9703d9d7 CM |
234 | |
235 | ENTRY(stext) | |
236 | mov x21, x0 // x21=FDT | |
828e9834 | 237 | bl el2_setup // Drop to EL1, w20=cpu_boot_mode |
6f4d57fa | 238 | adrp x24, __PHYS_OFFSET |
828e9834 | 239 | bl set_cpu_boot_mode_flag |
a591ede4 | 240 | |
9703d9d7 CM |
241 | bl __vet_fdt |
242 | bl __create_page_tables // x25=TTBR0, x26=TTBR1 | |
243 | /* | |
a591ede4 MZ |
244 | * The following calls CPU setup code, see arch/arm64/mm/proc.S for |
245 | * details. | |
9703d9d7 CM |
246 | * On return, the CPU will be ready for the MMU to be turned on and |
247 | * the TCR will have been set. | |
248 | */ | |
a871d354 | 249 | ldr x27, =__mmap_switched // address to jump to after |
9703d9d7 | 250 | // MMU has been enabled |
8b0a9575 | 251 | adr_l lr, __enable_mmu // return (PIC) address |
a591ede4 | 252 | b __cpu_setup // initialise processor |
9703d9d7 CM |
253 | ENDPROC(stext) |
254 | ||
034edabe LA |
255 | /* |
256 | * Determine validity of the x21 FDT pointer. | |
257 | * The dtb must be 8-byte aligned and live in the first 512M of memory. | |
258 | */ | |
259 | __vet_fdt: | |
260 | tst x21, #0x7 | |
261 | b.ne 1f | |
262 | cmp x21, x24 | |
263 | b.lt 1f | |
264 | mov x0, #(1 << 29) | |
265 | add x0, x0, x24 | |
266 | cmp x21, x0 | |
267 | b.ge 1f | |
268 | ret | |
269 | 1: | |
270 | mov x21, #0 | |
271 | ret | |
272 | ENDPROC(__vet_fdt) | |
273 | /* | |
274 | * Macro to create a table entry to the next page. | |
275 | * | |
276 | * tbl: page table address | |
277 | * virt: virtual address | |
278 | * shift: #imm page table shift | |
279 | * ptrs: #imm pointers per table page | |
280 | * | |
281 | * Preserves: virt | |
282 | * Corrupts: tmp1, tmp2 | |
283 | * Returns: tbl -> next level table page address | |
284 | */ | |
285 | .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2 | |
286 | lsr \tmp1, \virt, #\shift | |
287 | and \tmp1, \tmp1, #\ptrs - 1 // table index | |
288 | add \tmp2, \tbl, #PAGE_SIZE | |
289 | orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type | |
290 | str \tmp2, [\tbl, \tmp1, lsl #3] | |
291 | add \tbl, \tbl, #PAGE_SIZE // next level table page | |
292 | .endm | |
293 | ||
294 | /* | |
295 | * Macro to populate the PGD (and possibily PUD) for the corresponding | |
296 | * block entry in the next level (tbl) for the given virtual address. | |
297 | * | |
298 | * Preserves: tbl, next, virt | |
299 | * Corrupts: tmp1, tmp2 | |
300 | */ | |
301 | .macro create_pgd_entry, tbl, virt, tmp1, tmp2 | |
302 | create_table_entry \tbl, \virt, PGDIR_SHIFT, PTRS_PER_PGD, \tmp1, \tmp2 | |
303 | #if SWAPPER_PGTABLE_LEVELS == 3 | |
304 | create_table_entry \tbl, \virt, TABLE_SHIFT, PTRS_PER_PTE, \tmp1, \tmp2 | |
305 | #endif | |
306 | .endm | |
307 | ||
308 | /* | |
309 | * Macro to populate block entries in the page table for the start..end | |
310 | * virtual range (inclusive). | |
311 | * | |
312 | * Preserves: tbl, flags | |
313 | * Corrupts: phys, start, end, pstate | |
314 | */ | |
315 | .macro create_block_map, tbl, flags, phys, start, end | |
316 | lsr \phys, \phys, #BLOCK_SHIFT | |
317 | lsr \start, \start, #BLOCK_SHIFT | |
318 | and \start, \start, #PTRS_PER_PTE - 1 // table index | |
319 | orr \phys, \flags, \phys, lsl #BLOCK_SHIFT // table entry | |
320 | lsr \end, \end, #BLOCK_SHIFT | |
321 | and \end, \end, #PTRS_PER_PTE - 1 // table end index | |
322 | 9999: str \phys, [\tbl, \start, lsl #3] // store the entry | |
323 | add \start, \start, #1 // next entry | |
324 | add \phys, \phys, #BLOCK_SIZE // next block | |
325 | cmp \start, \end | |
326 | b.ls 9999b | |
327 | .endm | |
328 | ||
329 | /* | |
330 | * Setup the initial page tables. We only setup the barest amount which is | |
331 | * required to get the kernel running. The following sections are required: | |
332 | * - identity mapping to enable the MMU (low address, TTBR0) | |
333 | * - first few MB of the kernel linear mapping to jump to once the MMU has | |
334 | * been enabled, including the FDT blob (TTBR1) | |
335 | * - pgd entry for fixed mappings (TTBR1) | |
336 | */ | |
337 | __create_page_tables: | |
6f4d57fa AB |
338 | adrp x25, idmap_pg_dir |
339 | adrp x26, swapper_pg_dir | |
034edabe LA |
340 | mov x27, lr |
341 | ||
342 | /* | |
343 | * Invalidate the idmap and swapper page tables to avoid potential | |
344 | * dirty cache lines being evicted. | |
345 | */ | |
346 | mov x0, x25 | |
347 | add x1, x26, #SWAPPER_DIR_SIZE | |
348 | bl __inval_cache_range | |
349 | ||
350 | /* | |
351 | * Clear the idmap and swapper page tables. | |
352 | */ | |
353 | mov x0, x25 | |
354 | add x6, x26, #SWAPPER_DIR_SIZE | |
355 | 1: stp xzr, xzr, [x0], #16 | |
356 | stp xzr, xzr, [x0], #16 | |
357 | stp xzr, xzr, [x0], #16 | |
358 | stp xzr, xzr, [x0], #16 | |
359 | cmp x0, x6 | |
360 | b.lo 1b | |
361 | ||
362 | ldr x7, =MM_MMUFLAGS | |
363 | ||
364 | /* | |
365 | * Create the identity mapping. | |
366 | */ | |
367 | mov x0, x25 // idmap_pg_dir | |
6f4d57fa | 368 | adrp x3, KERNEL_START // __pa(KERNEL_START) |
034edabe | 369 | create_pgd_entry x0, x3, x5, x6 |
034edabe | 370 | mov x5, x3 // __pa(KERNEL_START) |
6f4d57fa | 371 | adr_l x6, KERNEL_END // __pa(KERNEL_END) |
034edabe LA |
372 | create_block_map x0, x7, x3, x5, x6 |
373 | ||
374 | /* | |
375 | * Map the kernel image (starting with PHYS_OFFSET). | |
376 | */ | |
377 | mov x0, x26 // swapper_pg_dir | |
378 | mov x5, #PAGE_OFFSET | |
379 | create_pgd_entry x0, x5, x3, x6 | |
6f4d57fa | 380 | ldr x6, =KERNEL_END // __va(KERNEL_END) |
034edabe LA |
381 | mov x3, x24 // phys offset |
382 | create_block_map x0, x7, x3, x5, x6 | |
383 | ||
384 | /* | |
385 | * Map the FDT blob (maximum 2MB; must be within 512MB of | |
386 | * PHYS_OFFSET). | |
387 | */ | |
388 | mov x3, x21 // FDT phys address | |
389 | and x3, x3, #~((1 << 21) - 1) // 2MB aligned | |
390 | mov x6, #PAGE_OFFSET | |
391 | sub x5, x3, x24 // subtract PHYS_OFFSET | |
392 | tst x5, #~((1 << 29) - 1) // within 512MB? | |
393 | csel x21, xzr, x21, ne // zero the FDT pointer | |
394 | b.ne 1f | |
395 | add x5, x5, x6 // __va(FDT blob) | |
396 | add x6, x5, #1 << 21 // 2MB for the FDT blob | |
397 | sub x6, x6, #1 // inclusive range | |
398 | create_block_map x0, x7, x3, x5, x6 | |
399 | 1: | |
400 | /* | |
401 | * Since the page tables have been populated with non-cacheable | |
402 | * accesses (MMU disabled), invalidate the idmap and swapper page | |
403 | * tables again to remove any speculatively loaded cache lines. | |
404 | */ | |
405 | mov x0, x25 | |
406 | add x1, x26, #SWAPPER_DIR_SIZE | |
407 | bl __inval_cache_range | |
408 | ||
409 | mov lr, x27 | |
410 | ret | |
411 | ENDPROC(__create_page_tables) | |
412 | .ltorg | |
413 | ||
034edabe | 414 | /* |
a871d354 | 415 | * The following fragment of code is executed with the MMU enabled. |
034edabe | 416 | */ |
a871d354 | 417 | .set initial_sp, init_thread_union + THREAD_START_SP |
034edabe | 418 | __mmap_switched: |
a871d354 AB |
419 | adr_l x6, __bss_start |
420 | adr_l x7, __bss_stop | |
034edabe | 421 | |
034edabe LA |
422 | 1: cmp x6, x7 |
423 | b.hs 2f | |
424 | str xzr, [x6], #8 // Clear BSS | |
425 | b 1b | |
426 | 2: | |
a871d354 AB |
427 | adr_l sp, initial_sp, x4 |
428 | str_l x21, __fdt_pointer, x5 // Save FDT pointer | |
429 | str_l x24, memstart_addr, x6 // Save PHYS_OFFSET | |
034edabe LA |
430 | mov x29, #0 |
431 | b start_kernel | |
432 | ENDPROC(__mmap_switched) | |
433 | ||
434 | /* | |
435 | * end early head section, begin head code that is also used for | |
436 | * hotplug and needs to have the same protections as the text region | |
437 | */ | |
438 | .section ".text","ax" | |
9703d9d7 CM |
439 | /* |
440 | * If we're fortunate enough to boot at EL2, ensure that the world is | |
441 | * sane before dropping to EL1. | |
828e9834 ML |
442 | * |
443 | * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x20 if | |
444 | * booted in EL1 or EL2 respectively. | |
9703d9d7 CM |
445 | */ |
446 | ENTRY(el2_setup) | |
447 | mrs x0, CurrentEL | |
974c8e45 | 448 | cmp x0, #CurrentEL_EL2 |
9cf71728 ML |
449 | b.ne 1f |
450 | mrs x0, sctlr_el2 | |
451 | CPU_BE( orr x0, x0, #(1 << 25) ) // Set the EE bit for EL2 | |
452 | CPU_LE( bic x0, x0, #(1 << 25) ) // Clear the EE bit for EL2 | |
453 | msr sctlr_el2, x0 | |
454 | b 2f | |
455 | 1: mrs x0, sctlr_el1 | |
456 | CPU_BE( orr x0, x0, #(3 << 24) ) // Set the EE and E0E bits for EL1 | |
457 | CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1 | |
458 | msr sctlr_el1, x0 | |
828e9834 | 459 | mov w20, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1 |
9cf71728 | 460 | isb |
9703d9d7 CM |
461 | ret |
462 | ||
463 | /* Hyp configuration. */ | |
9cf71728 | 464 | 2: mov x0, #(1 << 31) // 64-bit EL1 |
9703d9d7 CM |
465 | msr hcr_el2, x0 |
466 | ||
467 | /* Generic timers. */ | |
468 | mrs x0, cnthctl_el2 | |
469 | orr x0, x0, #3 // Enable EL1 physical timers | |
470 | msr cnthctl_el2, x0 | |
1f75ff0a | 471 | msr cntvoff_el2, xzr // Clear virtual offset |
9703d9d7 | 472 | |
021f6537 MZ |
473 | #ifdef CONFIG_ARM_GIC_V3 |
474 | /* GICv3 system register access */ | |
475 | mrs x0, id_aa64pfr0_el1 | |
476 | ubfx x0, x0, #24, #4 | |
477 | cmp x0, #1 | |
478 | b.ne 3f | |
479 | ||
72c58395 | 480 | mrs_s x0, ICC_SRE_EL2 |
021f6537 MZ |
481 | orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1 |
482 | orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1 | |
72c58395 | 483 | msr_s ICC_SRE_EL2, x0 |
021f6537 | 484 | isb // Make sure SRE is now set |
72c58395 | 485 | msr_s ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults |
021f6537 MZ |
486 | |
487 | 3: | |
488 | #endif | |
489 | ||
9703d9d7 CM |
490 | /* Populate ID registers. */ |
491 | mrs x0, midr_el1 | |
492 | mrs x1, mpidr_el1 | |
493 | msr vpidr_el2, x0 | |
494 | msr vmpidr_el2, x1 | |
495 | ||
496 | /* sctlr_el1 */ | |
497 | mov x0, #0x0800 // Set/clear RES{1,0} bits | |
9cf71728 ML |
498 | CPU_BE( movk x0, #0x33d0, lsl #16 ) // Set EE and E0E on BE systems |
499 | CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems | |
9703d9d7 CM |
500 | msr sctlr_el1, x0 |
501 | ||
502 | /* Coprocessor traps. */ | |
503 | mov x0, #0x33ff | |
504 | msr cptr_el2, x0 // Disable copro. traps to EL2 | |
505 | ||
506 | #ifdef CONFIG_COMPAT | |
507 | msr hstr_el2, xzr // Disable CP15 traps to EL2 | |
508 | #endif | |
509 | ||
7dbfbe5b MZ |
510 | /* Stage-2 translation */ |
511 | msr vttbr_el2, xzr | |
512 | ||
712c6ff4 | 513 | /* Hypervisor stub */ |
ac2dec5f LA |
514 | adrp x0, __hyp_stub_vectors |
515 | add x0, x0, #:lo12:__hyp_stub_vectors | |
712c6ff4 MZ |
516 | msr vbar_el2, x0 |
517 | ||
9703d9d7 CM |
518 | /* spsr */ |
519 | mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\ | |
520 | PSR_MODE_EL1h) | |
521 | msr spsr_el2, x0 | |
522 | msr elr_el2, lr | |
828e9834 | 523 | mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 |
9703d9d7 CM |
524 | eret |
525 | ENDPROC(el2_setup) | |
526 | ||
828e9834 ML |
527 | /* |
528 | * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed | |
529 | * in x20. See arch/arm64/include/asm/virt.h for more info. | |
530 | */ | |
531 | ENTRY(set_cpu_boot_mode_flag) | |
6f4d57fa | 532 | adr_l x1, __boot_cpu_mode |
828e9834 ML |
533 | cmp w20, #BOOT_CPU_MODE_EL2 |
534 | b.ne 1f | |
535 | add x1, x1, #4 | |
d0488597 WD |
536 | 1: str w20, [x1] // This CPU has booted in EL1 |
537 | dmb sy | |
538 | dc ivac, x1 // Invalidate potentially stale cache line | |
828e9834 ML |
539 | ret |
540 | ENDPROC(set_cpu_boot_mode_flag) | |
541 | ||
f35a9205 MZ |
542 | /* |
543 | * We need to find out the CPU boot mode long after boot, so we need to | |
544 | * store it in a writable variable. | |
545 | * | |
546 | * This is not in .bss, because we set it sufficiently early that the boot-time | |
547 | * zeroing of .bss would clobber it. | |
548 | */ | |
c218bca7 | 549 | .pushsection .data..cacheline_aligned |
c218bca7 | 550 | .align L1_CACHE_SHIFT |
947bb758 | 551 | ENTRY(__boot_cpu_mode) |
f35a9205 | 552 | .long BOOT_CPU_MODE_EL2 |
424a3838 | 553 | .long BOOT_CPU_MODE_EL1 |
f35a9205 MZ |
554 | .popsection |
555 | ||
9703d9d7 | 556 | #ifdef CONFIG_SMP |
9703d9d7 CM |
557 | /* |
558 | * This provides a "holding pen" for platforms to hold all secondary | |
559 | * cores are held until we're ready for them to initialise. | |
560 | */ | |
561 | ENTRY(secondary_holding_pen) | |
828e9834 | 562 | bl el2_setup // Drop to EL1, w20=cpu_boot_mode |
828e9834 | 563 | bl set_cpu_boot_mode_flag |
9703d9d7 | 564 | mrs x0, mpidr_el1 |
0359b0e2 JM |
565 | ldr x1, =MPIDR_HWID_BITMASK |
566 | and x0, x0, x1 | |
b1c98297 | 567 | adr_l x3, secondary_holding_pen_release |
9703d9d7 CM |
568 | pen: ldr x4, [x3] |
569 | cmp x4, x0 | |
570 | b.eq secondary_startup | |
571 | wfe | |
572 | b pen | |
573 | ENDPROC(secondary_holding_pen) | |
652af899 MR |
574 | |
575 | /* | |
576 | * Secondary entry point that jumps straight into the kernel. Only to | |
577 | * be used where CPUs are brought online dynamically by the kernel. | |
578 | */ | |
579 | ENTRY(secondary_entry) | |
652af899 | 580 | bl el2_setup // Drop to EL1 |
85cc00ea | 581 | bl set_cpu_boot_mode_flag |
652af899 MR |
582 | b secondary_startup |
583 | ENDPROC(secondary_entry) | |
9703d9d7 CM |
584 | |
585 | ENTRY(secondary_startup) | |
586 | /* | |
587 | * Common entry point for secondary CPUs. | |
588 | */ | |
6f4d57fa AB |
589 | adrp x25, idmap_pg_dir |
590 | adrp x26, swapper_pg_dir | |
a591ede4 | 591 | bl __cpu_setup // initialise processor |
9703d9d7 CM |
592 | |
593 | ldr x21, =secondary_data | |
594 | ldr x27, =__secondary_switched // address to jump to after enabling the MMU | |
595 | b __enable_mmu | |
596 | ENDPROC(secondary_startup) | |
597 | ||
598 | ENTRY(__secondary_switched) | |
599 | ldr x0, [x21] // get secondary_data.stack | |
600 | mov sp, x0 | |
601 | mov x29, #0 | |
602 | b secondary_start_kernel | |
603 | ENDPROC(__secondary_switched) | |
604 | #endif /* CONFIG_SMP */ | |
605 | ||
606 | /* | |
8b0a9575 | 607 | * Enable the MMU. |
9703d9d7 | 608 | * |
8b0a9575 AB |
609 | * x0 = SCTLR_EL1 value for turning on the MMU. |
610 | * x27 = *virtual* address to jump to upon completion | |
611 | * | |
612 | * other registers depend on the function called upon completion | |
9703d9d7 CM |
613 | */ |
614 | __enable_mmu: | |
615 | ldr x5, =vectors | |
616 | msr vbar_el1, x5 | |
617 | msr ttbr0_el1, x25 // load TTBR0 | |
618 | msr ttbr1_el1, x26 // load TTBR1 | |
619 | isb | |
9703d9d7 CM |
620 | msr sctlr_el1, x0 |
621 | isb | |
622 | br x27 | |
8b0a9575 | 623 | ENDPROC(__enable_mmu) |