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9703d9d7 CM |
1 | /* |
2 | * Low-level CPU initialisation | |
3 | * Based on arch/arm/kernel/head.S | |
4 | * | |
5 | * Copyright (C) 1994-2002 Russell King | |
6 | * Copyright (C) 2003-2012 ARM Ltd. | |
7 | * Authors: Catalin Marinas <catalin.marinas@arm.com> | |
8 | * Will Deacon <will.deacon@arm.com> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #include <linux/linkage.h> | |
24 | #include <linux/init.h> | |
021f6537 | 25 | #include <linux/irqchip/arm-gic-v3.h> |
9703d9d7 CM |
26 | |
27 | #include <asm/assembler.h> | |
08cdac61 | 28 | #include <asm/boot.h> |
9703d9d7 CM |
29 | #include <asm/ptrace.h> |
30 | #include <asm/asm-offsets.h> | |
c218bca7 | 31 | #include <asm/cache.h> |
0359b0e2 | 32 | #include <asm/cputype.h> |
1e48ef7f | 33 | #include <asm/elf.h> |
87d1587b | 34 | #include <asm/kernel-pgtable.h> |
1f364c8c | 35 | #include <asm/kvm_arm.h> |
9703d9d7 | 36 | #include <asm/memory.h> |
9703d9d7 CM |
37 | #include <asm/pgtable-hwdef.h> |
38 | #include <asm/pgtable.h> | |
39 | #include <asm/page.h> | |
bb905274 | 40 | #include <asm/smp.h> |
4bf8b96e SP |
41 | #include <asm/sysreg.h> |
42 | #include <asm/thread_info.h> | |
f35a9205 | 43 | #include <asm/virt.h> |
9703d9d7 | 44 | |
6f4d57fa | 45 | #define __PHYS_OFFSET (KERNEL_START - TEXT_OFFSET) |
9703d9d7 | 46 | |
4190312b AB |
47 | #if (TEXT_OFFSET & 0xfff) != 0 |
48 | #error TEXT_OFFSET must be at least 4KB aligned | |
49 | #elif (PAGE_OFFSET & 0x1fffff) != 0 | |
da57a369 | 50 | #error PAGE_OFFSET must be at least 2MB aligned |
4190312b | 51 | #elif TEXT_OFFSET > 0x1fffff |
da57a369 | 52 | #error TEXT_OFFSET must be less than 2MB |
9703d9d7 CM |
53 | #endif |
54 | ||
6f4d57fa | 55 | #define KERNEL_START _text |
9703d9d7 CM |
56 | #define KERNEL_END _end |
57 | ||
9703d9d7 CM |
58 | /* |
59 | * Kernel startup entry point. | |
60 | * --------------------------- | |
61 | * | |
62 | * The requirements are: | |
63 | * MMU = off, D-cache = off, I-cache = on or off, | |
64 | * x0 = physical address to the FDT blob. | |
65 | * | |
66 | * This code is mostly position independent so you call this at | |
67 | * __pa(PAGE_OFFSET + TEXT_OFFSET). | |
68 | * | |
69 | * Note that the callee-saved registers are used for storing variables | |
70 | * that are useful before the MMU is enabled. The allocations are described | |
71 | * in the entry routines. | |
72 | */ | |
73 | __HEAD | |
2bf31a4a | 74 | _head: |
9703d9d7 CM |
75 | /* |
76 | * DO NOT MODIFY. Image header expected by Linux boot-loaders. | |
77 | */ | |
3c7f2550 | 78 | #ifdef CONFIG_EFI |
3c7f2550 MS |
79 | /* |
80 | * This add instruction has no meaningful effect except that | |
81 | * its opcode forms the magic "MZ" signature required by UEFI. | |
82 | */ | |
83 | add x13, x18, #0x16 | |
84 | b stext | |
85 | #else | |
9703d9d7 CM |
86 | b stext // branch to kernel start, magic |
87 | .long 0 // reserved | |
3c7f2550 | 88 | #endif |
6ad1fe5d AB |
89 | le64sym _kernel_offset_le // Image load offset from start of RAM, little-endian |
90 | le64sym _kernel_size_le // Effective size of kernel image, little-endian | |
91 | le64sym _kernel_flags_le // Informative flags, little-endian | |
4370eec0 RF |
92 | .quad 0 // reserved |
93 | .quad 0 // reserved | |
94 | .quad 0 // reserved | |
95 | .byte 0x41 // Magic number, "ARM\x64" | |
96 | .byte 0x52 | |
97 | .byte 0x4d | |
98 | .byte 0x64 | |
3c7f2550 | 99 | #ifdef CONFIG_EFI |
2bf31a4a | 100 | .long pe_header - _head // Offset to the PE header. |
3c7f2550 | 101 | #else |
4370eec0 | 102 | .word 0 // reserved |
3c7f2550 MS |
103 | #endif |
104 | ||
105 | #ifdef CONFIG_EFI | |
106 | .align 3 | |
107 | pe_header: | |
108 | .ascii "PE" | |
109 | .short 0 | |
110 | coff_header: | |
111 | .short 0xaa64 // AArch64 | |
112 | .short 2 // nr_sections | |
113 | .long 0 // TimeDateStamp | |
114 | .long 0 // PointerToSymbolTable | |
115 | .long 1 // NumberOfSymbols | |
116 | .short section_table - optional_header // SizeOfOptionalHeader | |
117 | .short 0x206 // Characteristics. | |
118 | // IMAGE_FILE_DEBUG_STRIPPED | | |
119 | // IMAGE_FILE_EXECUTABLE_IMAGE | | |
120 | // IMAGE_FILE_LINE_NUMS_STRIPPED | |
121 | optional_header: | |
122 | .short 0x20b // PE32+ format | |
123 | .byte 0x02 // MajorLinkerVersion | |
124 | .byte 0x14 // MinorLinkerVersion | |
546c8c44 | 125 | .long _end - efi_header_end // SizeOfCode |
3c7f2550 MS |
126 | .long 0 // SizeOfInitializedData |
127 | .long 0 // SizeOfUninitializedData | |
2bf31a4a | 128 | .long __efistub_entry - _head // AddressOfEntryPoint |
546c8c44 | 129 | .long efi_header_end - _head // BaseOfCode |
3c7f2550 MS |
130 | |
131 | extra_header_fields: | |
132 | .quad 0 // ImageBase | |
ea6bc80d | 133 | .long 0x1000 // SectionAlignment |
a352ea3e | 134 | .long PECOFF_FILE_ALIGNMENT // FileAlignment |
3c7f2550 MS |
135 | .short 0 // MajorOperatingSystemVersion |
136 | .short 0 // MinorOperatingSystemVersion | |
137 | .short 0 // MajorImageVersion | |
138 | .short 0 // MinorImageVersion | |
139 | .short 0 // MajorSubsystemVersion | |
140 | .short 0 // MinorSubsystemVersion | |
141 | .long 0 // Win32VersionValue | |
142 | ||
2bf31a4a | 143 | .long _end - _head // SizeOfImage |
3c7f2550 MS |
144 | |
145 | // Everything before the kernel image is considered part of the header | |
546c8c44 | 146 | .long efi_header_end - _head // SizeOfHeaders |
3c7f2550 MS |
147 | .long 0 // CheckSum |
148 | .short 0xa // Subsystem (EFI application) | |
149 | .short 0 // DllCharacteristics | |
150 | .quad 0 // SizeOfStackReserve | |
151 | .quad 0 // SizeOfStackCommit | |
152 | .quad 0 // SizeOfHeapReserve | |
153 | .quad 0 // SizeOfHeapCommit | |
154 | .long 0 // LoaderFlags | |
155 | .long 0x6 // NumberOfRvaAndSizes | |
156 | ||
157 | .quad 0 // ExportTable | |
158 | .quad 0 // ImportTable | |
159 | .quad 0 // ResourceTable | |
160 | .quad 0 // ExceptionTable | |
161 | .quad 0 // CertificationTable | |
162 | .quad 0 // BaseRelocationTable | |
163 | ||
164 | // Section table | |
165 | section_table: | |
166 | ||
167 | /* | |
168 | * The EFI application loader requires a relocation section | |
169 | * because EFI applications must be relocatable. This is a | |
170 | * dummy section as far as we are concerned. | |
171 | */ | |
172 | .ascii ".reloc" | |
173 | .byte 0 | |
174 | .byte 0 // end of 0 padding of section name | |
175 | .long 0 | |
176 | .long 0 | |
177 | .long 0 // SizeOfRawData | |
178 | .long 0 // PointerToRawData | |
179 | .long 0 // PointerToRelocations | |
180 | .long 0 // PointerToLineNumbers | |
181 | .short 0 // NumberOfRelocations | |
182 | .short 0 // NumberOfLineNumbers | |
183 | .long 0x42100040 // Characteristics (section flags) | |
184 | ||
185 | ||
186 | .ascii ".text" | |
187 | .byte 0 | |
188 | .byte 0 | |
189 | .byte 0 // end of 0 padding of section name | |
546c8c44 AB |
190 | .long _end - efi_header_end // VirtualSize |
191 | .long efi_header_end - _head // VirtualAddress | |
192 | .long _edata - efi_header_end // SizeOfRawData | |
193 | .long efi_header_end - _head // PointerToRawData | |
3c7f2550 MS |
194 | |
195 | .long 0 // PointerToRelocations (0 for executables) | |
196 | .long 0 // PointerToLineNumbers (0 for executables) | |
197 | .short 0 // NumberOfRelocations (0 for executables) | |
198 | .short 0 // NumberOfLineNumbers (0 for executables) | |
199 | .long 0xe0500020 // Characteristics (section flags) | |
ea6bc80d AB |
200 | |
201 | /* | |
546c8c44 | 202 | * EFI will load .text onwards at the 4k section alignment |
ea6bc80d AB |
203 | * described in the PE/COFF header. To ensure that instruction |
204 | * sequences using an adrp and a :lo12: immediate will function | |
546c8c44 | 205 | * correctly at this alignment, we must ensure that .text is |
ea6bc80d AB |
206 | * placed at a 4k boundary in the Image to begin with. |
207 | */ | |
208 | .align 12 | |
546c8c44 | 209 | efi_header_end: |
3c7f2550 | 210 | #endif |
9703d9d7 | 211 | |
546c8c44 AB |
212 | __INIT |
213 | ||
9703d9d7 | 214 | ENTRY(stext) |
da9c177d | 215 | bl preserve_boot_args |
828e9834 | 216 | bl el2_setup // Drop to EL1, w20=cpu_boot_mode |
6f4d57fa | 217 | adrp x24, __PHYS_OFFSET |
08cdac61 | 218 | and x23, x24, MIN_KIMG_ALIGN - 1 // KASLR offset, defaults to 0 |
828e9834 | 219 | bl set_cpu_boot_mode_flag |
9703d9d7 CM |
220 | bl __create_page_tables // x25=TTBR0, x26=TTBR1 |
221 | /* | |
a591ede4 MZ |
222 | * The following calls CPU setup code, see arch/arm64/mm/proc.S for |
223 | * details. | |
9703d9d7 CM |
224 | * On return, the CPU will be ready for the MMU to be turned on and |
225 | * the TCR will have been set. | |
226 | */ | |
0cd3defe AB |
227 | bl __cpu_setup // initialise processor |
228 | adr_l x27, __primary_switch // address to jump to after | |
229 | // MMU has been enabled | |
230 | b __enable_mmu | |
9703d9d7 CM |
231 | ENDPROC(stext) |
232 | ||
da9c177d AB |
233 | /* |
234 | * Preserve the arguments passed by the bootloader in x0 .. x3 | |
235 | */ | |
236 | preserve_boot_args: | |
237 | mov x21, x0 // x21=FDT | |
238 | ||
239 | adr_l x0, boot_args // record the contents of | |
240 | stp x21, x1, [x0] // x0 .. x3 at kernel entry | |
241 | stp x2, x3, [x0, #16] | |
242 | ||
243 | dmb sy // needed before dc ivac with | |
244 | // MMU off | |
245 | ||
246 | add x1, x0, #0x20 // 4 x 8 bytes | |
247 | b __inval_cache_range // tail call | |
248 | ENDPROC(preserve_boot_args) | |
249 | ||
034edabe LA |
250 | /* |
251 | * Macro to create a table entry to the next page. | |
252 | * | |
253 | * tbl: page table address | |
254 | * virt: virtual address | |
255 | * shift: #imm page table shift | |
256 | * ptrs: #imm pointers per table page | |
257 | * | |
258 | * Preserves: virt | |
259 | * Corrupts: tmp1, tmp2 | |
260 | * Returns: tbl -> next level table page address | |
261 | */ | |
262 | .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2 | |
263 | lsr \tmp1, \virt, #\shift | |
264 | and \tmp1, \tmp1, #\ptrs - 1 // table index | |
265 | add \tmp2, \tbl, #PAGE_SIZE | |
266 | orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type | |
267 | str \tmp2, [\tbl, \tmp1, lsl #3] | |
268 | add \tbl, \tbl, #PAGE_SIZE // next level table page | |
269 | .endm | |
270 | ||
271 | /* | |
272 | * Macro to populate the PGD (and possibily PUD) for the corresponding | |
273 | * block entry in the next level (tbl) for the given virtual address. | |
274 | * | |
275 | * Preserves: tbl, next, virt | |
276 | * Corrupts: tmp1, tmp2 | |
277 | */ | |
278 | .macro create_pgd_entry, tbl, virt, tmp1, tmp2 | |
279 | create_table_entry \tbl, \virt, PGDIR_SHIFT, PTRS_PER_PGD, \tmp1, \tmp2 | |
6a3fd402 SP |
280 | #if SWAPPER_PGTABLE_LEVELS > 3 |
281 | create_table_entry \tbl, \virt, PUD_SHIFT, PTRS_PER_PUD, \tmp1, \tmp2 | |
282 | #endif | |
283 | #if SWAPPER_PGTABLE_LEVELS > 2 | |
87d1587b | 284 | create_table_entry \tbl, \virt, SWAPPER_TABLE_SHIFT, PTRS_PER_PTE, \tmp1, \tmp2 |
034edabe LA |
285 | #endif |
286 | .endm | |
287 | ||
288 | /* | |
289 | * Macro to populate block entries in the page table for the start..end | |
290 | * virtual range (inclusive). | |
291 | * | |
292 | * Preserves: tbl, flags | |
293 | * Corrupts: phys, start, end, pstate | |
294 | */ | |
295 | .macro create_block_map, tbl, flags, phys, start, end | |
87d1587b SP |
296 | lsr \phys, \phys, #SWAPPER_BLOCK_SHIFT |
297 | lsr \start, \start, #SWAPPER_BLOCK_SHIFT | |
034edabe | 298 | and \start, \start, #PTRS_PER_PTE - 1 // table index |
87d1587b SP |
299 | orr \phys, \flags, \phys, lsl #SWAPPER_BLOCK_SHIFT // table entry |
300 | lsr \end, \end, #SWAPPER_BLOCK_SHIFT | |
034edabe LA |
301 | and \end, \end, #PTRS_PER_PTE - 1 // table end index |
302 | 9999: str \phys, [\tbl, \start, lsl #3] // store the entry | |
303 | add \start, \start, #1 // next entry | |
87d1587b | 304 | add \phys, \phys, #SWAPPER_BLOCK_SIZE // next block |
034edabe LA |
305 | cmp \start, \end |
306 | b.ls 9999b | |
307 | .endm | |
308 | ||
309 | /* | |
310 | * Setup the initial page tables. We only setup the barest amount which is | |
311 | * required to get the kernel running. The following sections are required: | |
312 | * - identity mapping to enable the MMU (low address, TTBR0) | |
313 | * - first few MB of the kernel linear mapping to jump to once the MMU has | |
61bd93ce | 314 | * been enabled |
034edabe LA |
315 | */ |
316 | __create_page_tables: | |
6f4d57fa AB |
317 | adrp x25, idmap_pg_dir |
318 | adrp x26, swapper_pg_dir | |
f80fb3a3 | 319 | mov x28, lr |
034edabe LA |
320 | |
321 | /* | |
322 | * Invalidate the idmap and swapper page tables to avoid potential | |
323 | * dirty cache lines being evicted. | |
324 | */ | |
325 | mov x0, x25 | |
326 | add x1, x26, #SWAPPER_DIR_SIZE | |
327 | bl __inval_cache_range | |
328 | ||
329 | /* | |
330 | * Clear the idmap and swapper page tables. | |
331 | */ | |
332 | mov x0, x25 | |
333 | add x6, x26, #SWAPPER_DIR_SIZE | |
334 | 1: stp xzr, xzr, [x0], #16 | |
335 | stp xzr, xzr, [x0], #16 | |
336 | stp xzr, xzr, [x0], #16 | |
337 | stp xzr, xzr, [x0], #16 | |
338 | cmp x0, x6 | |
339 | b.lo 1b | |
340 | ||
b03cc885 | 341 | mov x7, SWAPPER_MM_MMUFLAGS |
034edabe LA |
342 | |
343 | /* | |
344 | * Create the identity mapping. | |
345 | */ | |
346 | mov x0, x25 // idmap_pg_dir | |
5dfe9d7d | 347 | adrp x3, __idmap_text_start // __pa(__idmap_text_start) |
dd006da2 AB |
348 | |
349 | #ifndef CONFIG_ARM64_VA_BITS_48 | |
350 | #define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3) | |
351 | #define EXTRA_PTRS (1 << (48 - EXTRA_SHIFT)) | |
352 | ||
353 | /* | |
354 | * If VA_BITS < 48, it may be too small to allow for an ID mapping to be | |
355 | * created that covers system RAM if that is located sufficiently high | |
356 | * in the physical address space. So for the ID map, use an extended | |
357 | * virtual range in that case, by configuring an additional translation | |
358 | * level. | |
359 | * First, we have to verify our assumption that the current value of | |
360 | * VA_BITS was chosen such that all translation levels are fully | |
361 | * utilised, and that lowering T0SZ will always result in an additional | |
362 | * translation level to be configured. | |
363 | */ | |
364 | #if VA_BITS != EXTRA_SHIFT | |
365 | #error "Mismatch between VA_BITS and page size/number of translation levels" | |
366 | #endif | |
367 | ||
368 | /* | |
369 | * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the | |
5dfe9d7d | 370 | * entire ID map region can be mapped. As T0SZ == (64 - #bits used), |
dd006da2 | 371 | * this number conveniently equals the number of leading zeroes in |
5dfe9d7d | 372 | * the physical address of __idmap_text_end. |
dd006da2 | 373 | */ |
5dfe9d7d | 374 | adrp x5, __idmap_text_end |
dd006da2 AB |
375 | clz x5, x5 |
376 | cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough? | |
377 | b.ge 1f // .. then skip additional level | |
378 | ||
0c20856c MR |
379 | adr_l x6, idmap_t0sz |
380 | str x5, [x6] | |
381 | dmb sy | |
382 | dc ivac, x6 // Invalidate potentially stale cache line | |
dd006da2 AB |
383 | |
384 | create_table_entry x0, x3, EXTRA_SHIFT, EXTRA_PTRS, x5, x6 | |
385 | 1: | |
386 | #endif | |
387 | ||
034edabe | 388 | create_pgd_entry x0, x3, x5, x6 |
5dfe9d7d AB |
389 | mov x5, x3 // __pa(__idmap_text_start) |
390 | adr_l x6, __idmap_text_end // __pa(__idmap_text_end) | |
034edabe LA |
391 | create_block_map x0, x7, x3, x5, x6 |
392 | ||
393 | /* | |
394 | * Map the kernel image (starting with PHYS_OFFSET). | |
395 | */ | |
396 | mov x0, x26 // swapper_pg_dir | |
18b9c0d6 | 397 | mov_q x5, KIMAGE_VADDR + TEXT_OFFSET // compile time __va(_text) |
f80fb3a3 | 398 | add x5, x5, x23 // add KASLR displacement |
034edabe | 399 | create_pgd_entry x0, x5, x3, x6 |
18b9c0d6 AB |
400 | adrp x6, _end // runtime __pa(_end) |
401 | adrp x3, _text // runtime __pa(_text) | |
402 | sub x6, x6, x3 // _end - _text | |
403 | add x6, x6, x5 // runtime __va(_end) | |
034edabe LA |
404 | create_block_map x0, x7, x3, x5, x6 |
405 | ||
034edabe LA |
406 | /* |
407 | * Since the page tables have been populated with non-cacheable | |
408 | * accesses (MMU disabled), invalidate the idmap and swapper page | |
409 | * tables again to remove any speculatively loaded cache lines. | |
410 | */ | |
411 | mov x0, x25 | |
412 | add x1, x26, #SWAPPER_DIR_SIZE | |
91d57155 | 413 | dmb sy |
034edabe LA |
414 | bl __inval_cache_range |
415 | ||
f80fb3a3 | 416 | ret x28 |
034edabe LA |
417 | ENDPROC(__create_page_tables) |
418 | .ltorg | |
419 | ||
034edabe | 420 | /* |
a871d354 | 421 | * The following fragment of code is executed with the MMU enabled. |
034edabe | 422 | */ |
a871d354 | 423 | .set initial_sp, init_thread_union + THREAD_START_SP |
0cd3defe | 424 | __primary_switched: |
f80fb3a3 | 425 | mov x28, lr // preserve LR |
2bf31a4a AB |
426 | adr_l x8, vectors // load VBAR_EL1 with virtual |
427 | msr vbar_el1, x8 // vector table address | |
428 | isb | |
429 | ||
2a803c4d MR |
430 | // Clear BSS |
431 | adr_l x0, __bss_start | |
432 | mov x1, xzr | |
433 | adr_l x2, __bss_stop | |
434 | sub x2, x2, x0 | |
435 | bl __pi_memset | |
5227cfa7 | 436 | dsb ishst // Make zero page visible to PTW |
2a803c4d | 437 | |
a871d354 | 438 | adr_l sp, initial_sp, x4 |
6cdf9c7c JL |
439 | mov x4, sp |
440 | and x4, x4, #~(THREAD_SIZE - 1) | |
441 | msr sp_el0, x4 // Save thread_info | |
a871d354 | 442 | str_l x21, __fdt_pointer, x5 // Save FDT pointer |
a7f8de16 | 443 | |
f80fb3a3 | 444 | ldr_l x4, kimage_vaddr // Save the offset between |
a7f8de16 AB |
445 | sub x4, x4, x24 // the kernel virtual and |
446 | str_l x4, kimage_voffset, x5 // physical mappings | |
447 | ||
034edabe | 448 | mov x29, #0 |
39d114dd AR |
449 | #ifdef CONFIG_KASAN |
450 | bl kasan_early_init | |
f80fb3a3 AB |
451 | #endif |
452 | #ifdef CONFIG_RANDOMIZE_BASE | |
08cdac61 AB |
453 | tst x23, ~(MIN_KIMG_ALIGN - 1) // already running randomized? |
454 | b.ne 0f | |
f80fb3a3 | 455 | mov x0, x21 // pass FDT address in x0 |
08cdac61 | 456 | mov x1, x23 // pass modulo offset in x1 |
f80fb3a3 AB |
457 | bl kaslr_early_init // parse FDT for KASLR options |
458 | cbz x0, 0f // KASLR disabled? just proceed | |
08cdac61 | 459 | orr x23, x23, x0 // record KASLR offset |
f80fb3a3 AB |
460 | ret x28 // we must enable KASLR, return |
461 | // to __enable_mmu() | |
462 | 0: | |
39d114dd | 463 | #endif |
034edabe | 464 | b start_kernel |
0cd3defe | 465 | ENDPROC(__primary_switched) |
034edabe LA |
466 | |
467 | /* | |
468 | * end early head section, begin head code that is also used for | |
469 | * hotplug and needs to have the same protections as the text region | |
470 | */ | |
471 | .section ".text","ax" | |
f80fb3a3 AB |
472 | |
473 | ENTRY(kimage_vaddr) | |
474 | .quad _text - TEXT_OFFSET | |
475 | ||
9703d9d7 CM |
476 | /* |
477 | * If we're fortunate enough to boot at EL2, ensure that the world is | |
478 | * sane before dropping to EL1. | |
828e9834 ML |
479 | * |
480 | * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x20 if | |
481 | * booted in EL1 or EL2 respectively. | |
9703d9d7 CM |
482 | */ |
483 | ENTRY(el2_setup) | |
484 | mrs x0, CurrentEL | |
974c8e45 | 485 | cmp x0, #CurrentEL_EL2 |
9cf71728 ML |
486 | b.ne 1f |
487 | mrs x0, sctlr_el2 | |
488 | CPU_BE( orr x0, x0, #(1 << 25) ) // Set the EE bit for EL2 | |
489 | CPU_LE( bic x0, x0, #(1 << 25) ) // Clear the EE bit for EL2 | |
490 | msr sctlr_el2, x0 | |
491 | b 2f | |
492 | 1: mrs x0, sctlr_el1 | |
493 | CPU_BE( orr x0, x0, #(3 << 24) ) // Set the EE and E0E bits for EL1 | |
494 | CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1 | |
495 | msr sctlr_el1, x0 | |
828e9834 | 496 | mov w20, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1 |
9cf71728 | 497 | isb |
9703d9d7 CM |
498 | ret |
499 | ||
1f364c8c MZ |
500 | 2: |
501 | #ifdef CONFIG_ARM64_VHE | |
502 | /* | |
503 | * Check for VHE being present. For the rest of the EL2 setup, | |
504 | * x2 being non-zero indicates that we do have VHE, and that the | |
505 | * kernel is intended to run at EL2. | |
506 | */ | |
507 | mrs x2, id_aa64mmfr1_el1 | |
508 | ubfx x2, x2, #8, #4 | |
509 | #else | |
510 | mov x2, xzr | |
511 | #endif | |
512 | ||
9703d9d7 | 513 | /* Hyp configuration. */ |
1f364c8c MZ |
514 | mov x0, #HCR_RW // 64-bit EL1 |
515 | cbz x2, set_hcr | |
516 | orr x0, x0, #HCR_TGE // Enable Host Extensions | |
517 | orr x0, x0, #HCR_E2H | |
518 | set_hcr: | |
9703d9d7 | 519 | msr hcr_el2, x0 |
1f364c8c | 520 | isb |
9703d9d7 CM |
521 | |
522 | /* Generic timers. */ | |
523 | mrs x0, cnthctl_el2 | |
524 | orr x0, x0, #3 // Enable EL1 physical timers | |
525 | msr cnthctl_el2, x0 | |
1f75ff0a | 526 | msr cntvoff_el2, xzr // Clear virtual offset |
9703d9d7 | 527 | |
021f6537 MZ |
528 | #ifdef CONFIG_ARM_GIC_V3 |
529 | /* GICv3 system register access */ | |
530 | mrs x0, id_aa64pfr0_el1 | |
531 | ubfx x0, x0, #24, #4 | |
532 | cmp x0, #1 | |
533 | b.ne 3f | |
534 | ||
72c58395 | 535 | mrs_s x0, ICC_SRE_EL2 |
021f6537 MZ |
536 | orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1 |
537 | orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1 | |
72c58395 | 538 | msr_s ICC_SRE_EL2, x0 |
021f6537 | 539 | isb // Make sure SRE is now set |
d271976d MZ |
540 | mrs_s x0, ICC_SRE_EL2 // Read SRE back, |
541 | tbz x0, #0, 3f // and check that it sticks | |
72c58395 | 542 | msr_s ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults |
021f6537 MZ |
543 | |
544 | 3: | |
545 | #endif | |
546 | ||
9703d9d7 CM |
547 | /* Populate ID registers. */ |
548 | mrs x0, midr_el1 | |
549 | mrs x1, mpidr_el1 | |
550 | msr vpidr_el2, x0 | |
551 | msr vmpidr_el2, x1 | |
552 | ||
553 | /* sctlr_el1 */ | |
554 | mov x0, #0x0800 // Set/clear RES{1,0} bits | |
9cf71728 ML |
555 | CPU_BE( movk x0, #0x33d0, lsl #16 ) // Set EE and E0E on BE systems |
556 | CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems | |
9703d9d7 CM |
557 | msr sctlr_el1, x0 |
558 | ||
559 | /* Coprocessor traps. */ | |
560 | mov x0, #0x33ff | |
561 | msr cptr_el2, x0 // Disable copro. traps to EL2 | |
562 | ||
563 | #ifdef CONFIG_COMPAT | |
564 | msr hstr_el2, xzr // Disable CP15 traps to EL2 | |
565 | #endif | |
566 | ||
d10bcd47 | 567 | /* EL2 debug */ |
f436b2ac LP |
568 | mrs x0, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer |
569 | sbfx x0, x0, #8, #4 | |
570 | cmp x0, #1 | |
571 | b.lt 4f // Skip if no PMU present | |
d10bcd47 WD |
572 | mrs x0, pmcr_el0 // Disable debug access traps |
573 | ubfx x0, x0, #11, #5 // to EL2 and allow access to | |
574 | msr mdcr_el2, x0 // all PMU counters from EL1 | |
f436b2ac | 575 | 4: |
d10bcd47 | 576 | |
7dbfbe5b MZ |
577 | /* Stage-2 translation */ |
578 | msr vttbr_el2, xzr | |
579 | ||
1f364c8c MZ |
580 | cbz x2, install_el2_stub |
581 | ||
582 | mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 | |
583 | isb | |
584 | ret | |
585 | ||
586 | install_el2_stub: | |
712c6ff4 | 587 | /* Hypervisor stub */ |
ac2dec5f LA |
588 | adrp x0, __hyp_stub_vectors |
589 | add x0, x0, #:lo12:__hyp_stub_vectors | |
712c6ff4 MZ |
590 | msr vbar_el2, x0 |
591 | ||
9703d9d7 CM |
592 | /* spsr */ |
593 | mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\ | |
594 | PSR_MODE_EL1h) | |
595 | msr spsr_el2, x0 | |
596 | msr elr_el2, lr | |
828e9834 | 597 | mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 |
9703d9d7 CM |
598 | eret |
599 | ENDPROC(el2_setup) | |
600 | ||
828e9834 ML |
601 | /* |
602 | * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed | |
603 | * in x20. See arch/arm64/include/asm/virt.h for more info. | |
604 | */ | |
190c056f | 605 | set_cpu_boot_mode_flag: |
6f4d57fa | 606 | adr_l x1, __boot_cpu_mode |
828e9834 ML |
607 | cmp w20, #BOOT_CPU_MODE_EL2 |
608 | b.ne 1f | |
609 | add x1, x1, #4 | |
d0488597 WD |
610 | 1: str w20, [x1] // This CPU has booted in EL1 |
611 | dmb sy | |
612 | dc ivac, x1 // Invalidate potentially stale cache line | |
828e9834 ML |
613 | ret |
614 | ENDPROC(set_cpu_boot_mode_flag) | |
615 | ||
f35a9205 MZ |
616 | /* |
617 | * We need to find out the CPU boot mode long after boot, so we need to | |
618 | * store it in a writable variable. | |
619 | * | |
620 | * This is not in .bss, because we set it sufficiently early that the boot-time | |
621 | * zeroing of .bss would clobber it. | |
622 | */ | |
c218bca7 | 623 | .pushsection .data..cacheline_aligned |
c218bca7 | 624 | .align L1_CACHE_SHIFT |
947bb758 | 625 | ENTRY(__boot_cpu_mode) |
f35a9205 | 626 | .long BOOT_CPU_MODE_EL2 |
424a3838 | 627 | .long BOOT_CPU_MODE_EL1 |
f35a9205 MZ |
628 | .popsection |
629 | ||
9703d9d7 CM |
630 | /* |
631 | * This provides a "holding pen" for platforms to hold all secondary | |
632 | * cores are held until we're ready for them to initialise. | |
633 | */ | |
634 | ENTRY(secondary_holding_pen) | |
828e9834 | 635 | bl el2_setup // Drop to EL1, w20=cpu_boot_mode |
828e9834 | 636 | bl set_cpu_boot_mode_flag |
9703d9d7 | 637 | mrs x0, mpidr_el1 |
b03cc885 | 638 | mov_q x1, MPIDR_HWID_BITMASK |
0359b0e2 | 639 | and x0, x0, x1 |
b1c98297 | 640 | adr_l x3, secondary_holding_pen_release |
9703d9d7 CM |
641 | pen: ldr x4, [x3] |
642 | cmp x4, x0 | |
643 | b.eq secondary_startup | |
644 | wfe | |
645 | b pen | |
646 | ENDPROC(secondary_holding_pen) | |
652af899 MR |
647 | |
648 | /* | |
649 | * Secondary entry point that jumps straight into the kernel. Only to | |
650 | * be used where CPUs are brought online dynamically by the kernel. | |
651 | */ | |
652 | ENTRY(secondary_entry) | |
652af899 | 653 | bl el2_setup // Drop to EL1 |
85cc00ea | 654 | bl set_cpu_boot_mode_flag |
652af899 MR |
655 | b secondary_startup |
656 | ENDPROC(secondary_entry) | |
9703d9d7 | 657 | |
190c056f | 658 | secondary_startup: |
9703d9d7 CM |
659 | /* |
660 | * Common entry point for secondary CPUs. | |
661 | */ | |
6f4d57fa AB |
662 | adrp x25, idmap_pg_dir |
663 | adrp x26, swapper_pg_dir | |
a591ede4 | 664 | bl __cpu_setup // initialise processor |
9703d9d7 | 665 | |
e5ebeec8 | 666 | adr_l x27, __secondary_switch // address to jump to after enabling the MMU |
9703d9d7 CM |
667 | b __enable_mmu |
668 | ENDPROC(secondary_startup) | |
669 | ||
190c056f | 670 | __secondary_switched: |
2bf31a4a AB |
671 | adr_l x5, vectors |
672 | msr vbar_el1, x5 | |
673 | isb | |
674 | ||
bb905274 SP |
675 | adr_l x0, secondary_data |
676 | ldr x0, [x0, #CPU_BOOT_STACK] // get secondary_data.stack | |
9703d9d7 | 677 | mov sp, x0 |
6cdf9c7c JL |
678 | and x0, x0, #~(THREAD_SIZE - 1) |
679 | msr sp_el0, x0 // save thread_info | |
9703d9d7 CM |
680 | mov x29, #0 |
681 | b secondary_start_kernel | |
682 | ENDPROC(__secondary_switched) | |
9703d9d7 | 683 | |
bb905274 SP |
684 | /* |
685 | * The booting CPU updates the failed status @__early_cpu_boot_status, | |
686 | * with MMU turned off. | |
687 | * | |
688 | * update_early_cpu_boot_status tmp, status | |
689 | * - Corrupts tmp1, tmp2 | |
690 | * - Writes 'status' to __early_cpu_boot_status and makes sure | |
691 | * it is committed to memory. | |
692 | */ | |
693 | ||
694 | .macro update_early_cpu_boot_status status, tmp1, tmp2 | |
695 | mov \tmp2, #\status | |
696 | str_l \tmp2, __early_cpu_boot_status, \tmp1 | |
697 | dmb sy | |
698 | dc ivac, \tmp1 // Invalidate potentially stale cache line | |
699 | .endm | |
700 | ||
701 | .pushsection .data..cacheline_aligned | |
702 | .align L1_CACHE_SHIFT | |
703 | ENTRY(__early_cpu_boot_status) | |
704 | .long 0 | |
705 | .popsection | |
706 | ||
9703d9d7 | 707 | /* |
8b0a9575 | 708 | * Enable the MMU. |
9703d9d7 | 709 | * |
8b0a9575 AB |
710 | * x0 = SCTLR_EL1 value for turning on the MMU. |
711 | * x27 = *virtual* address to jump to upon completion | |
712 | * | |
4bf8b96e SP |
713 | * Other registers depend on the function called upon completion. |
714 | * | |
715 | * Checks if the selected granule size is supported by the CPU. | |
716 | * If it isn't, park the CPU | |
9703d9d7 | 717 | */ |
5dfe9d7d | 718 | .section ".idmap.text", "ax" |
9703d9d7 | 719 | __enable_mmu: |
d5e57437 | 720 | mrs x22, sctlr_el1 // preserve old SCTLR_EL1 value |
4bf8b96e SP |
721 | mrs x1, ID_AA64MMFR0_EL1 |
722 | ubfx x2, x1, #ID_AA64MMFR0_TGRAN_SHIFT, 4 | |
723 | cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED | |
724 | b.ne __no_granule_support | |
bb905274 | 725 | update_early_cpu_boot_status 0, x1, x2 |
9703d9d7 CM |
726 | msr ttbr0_el1, x25 // load TTBR0 |
727 | msr ttbr1_el1, x26 // load TTBR1 | |
728 | isb | |
9703d9d7 CM |
729 | msr sctlr_el1, x0 |
730 | isb | |
8ec41987 WD |
731 | /* |
732 | * Invalidate the local I-cache so that any instructions fetched | |
733 | * speculatively from the PoC are discarded, since they may have | |
734 | * been dynamically patched at the PoU. | |
735 | */ | |
736 | ic iallu | |
737 | dsb nsh | |
738 | isb | |
f80fb3a3 AB |
739 | #ifdef CONFIG_RANDOMIZE_BASE |
740 | mov x19, x0 // preserve new SCTLR_EL1 value | |
741 | blr x27 | |
742 | ||
743 | /* | |
744 | * If we return here, we have a KASLR displacement in x23 which we need | |
745 | * to take into account by discarding the current kernel mapping and | |
746 | * creating a new one. | |
747 | */ | |
d5e57437 | 748 | msr sctlr_el1, x22 // disable the MMU |
f80fb3a3 AB |
749 | isb |
750 | bl __create_page_tables // recreate kernel mapping | |
751 | ||
752 | msr sctlr_el1, x19 // re-enable the MMU | |
753 | isb | |
b90b4a60 MR |
754 | ic iallu // flush instructions fetched |
755 | dsb nsh // via old mapping | |
756 | isb | |
f80fb3a3 | 757 | #endif |
9703d9d7 | 758 | br x27 |
8b0a9575 | 759 | ENDPROC(__enable_mmu) |
4bf8b96e SP |
760 | |
761 | __no_granule_support: | |
bb905274 SP |
762 | /* Indicate that this CPU can't boot and is stuck in the kernel */ |
763 | update_early_cpu_boot_status CPU_STUCK_IN_KERNEL, x1, x2 | |
764 | 1: | |
4bf8b96e | 765 | wfe |
bb905274 SP |
766 | wfi |
767 | b 1b | |
4bf8b96e | 768 | ENDPROC(__no_granule_support) |
e5ebeec8 | 769 | |
0cd3defe AB |
770 | __primary_switch: |
771 | #ifdef CONFIG_RELOCATABLE | |
772 | /* | |
773 | * Iterate over each entry in the relocation table, and apply the | |
774 | * relocations in place. | |
775 | */ | |
776 | ldr w8, =__dynsym_offset // offset to symbol table | |
777 | ldr w9, =__rela_offset // offset to reloc table | |
778 | ldr w10, =__rela_size // size of reloc table | |
779 | ||
b03cc885 | 780 | mov_q x11, KIMAGE_VADDR // default virtual offset |
0cd3defe AB |
781 | add x11, x11, x23 // actual virtual offset |
782 | add x8, x8, x11 // __va(.dynsym) | |
783 | add x9, x9, x11 // __va(.rela) | |
784 | add x10, x9, x10 // __va(.rela) + sizeof(.rela) | |
785 | ||
786 | 0: cmp x9, x10 | |
787 | b.hs 2f | |
788 | ldp x11, x12, [x9], #24 | |
789 | ldr x13, [x9, #-8] | |
790 | cmp w12, #R_AARCH64_RELATIVE | |
791 | b.ne 1f | |
792 | add x13, x13, x23 // relocate | |
793 | str x13, [x11, x23] | |
794 | b 0b | |
795 | ||
796 | 1: cmp w12, #R_AARCH64_ABS64 | |
797 | b.ne 0b | |
798 | add x12, x12, x12, lsl #1 // symtab offset: 24x top word | |
799 | add x12, x8, x12, lsr #(32 - 3) // ... shifted into bottom word | |
800 | ldrsh w14, [x12, #6] // Elf64_Sym::st_shndx | |
801 | ldr x15, [x12, #8] // Elf64_Sym::st_value | |
802 | cmp w14, #-0xf // SHN_ABS (0xfff1) ? | |
803 | add x14, x15, x23 // relocate | |
804 | csel x15, x14, x15, ne | |
805 | add x15, x13, x15 | |
806 | str x15, [x11, x23] | |
807 | b 0b | |
808 | ||
809 | 2: | |
810 | #endif | |
811 | ldr x8, =__primary_switched | |
812 | br x8 | |
813 | ENDPROC(__primary_switch) | |
814 | ||
e5ebeec8 AB |
815 | __secondary_switch: |
816 | ldr x8, =__secondary_switched | |
817 | br x8 | |
818 | ENDPROC(__secondary_switch) |