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1/*
2 * Low-level CPU initialisation
3 * Based on arch/arm/kernel/head.S
4 *
5 * Copyright (C) 1994-2002 Russell King
6 * Copyright (C) 2003-2012 ARM Ltd.
7 * Authors: Catalin Marinas <catalin.marinas@arm.com>
8 * Will Deacon <will.deacon@arm.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#include <linux/linkage.h>
24#include <linux/init.h>
25
26#include <asm/assembler.h>
27#include <asm/ptrace.h>
28#include <asm/asm-offsets.h>
0359b0e2 29#include <asm/cputype.h>
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30#include <asm/memory.h>
31#include <asm/thread_info.h>
32#include <asm/pgtable-hwdef.h>
33#include <asm/pgtable.h>
34#include <asm/page.h>
f35a9205 35#include <asm/virt.h>
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36
37/*
38 * swapper_pg_dir is the virtual address of the initial page table. We place
39 * the page tables 3 * PAGE_SIZE below KERNEL_RAM_VADDR. The idmap_pg_dir has
40 * 2 pages and is placed below swapper_pg_dir.
41 */
42#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
43
44#if (KERNEL_RAM_VADDR & 0xfffff) != 0x80000
45#error KERNEL_RAM_VADDR must start at 0xXXX80000
46#endif
47
48#define SWAPPER_DIR_SIZE (3 * PAGE_SIZE)
49#define IDMAP_DIR_SIZE (2 * PAGE_SIZE)
50
51 .globl swapper_pg_dir
52 .equ swapper_pg_dir, KERNEL_RAM_VADDR - SWAPPER_DIR_SIZE
53
54 .globl idmap_pg_dir
55 .equ idmap_pg_dir, swapper_pg_dir - IDMAP_DIR_SIZE
56
57 .macro pgtbl, ttb0, ttb1, phys
58 add \ttb1, \phys, #TEXT_OFFSET - SWAPPER_DIR_SIZE
59 sub \ttb0, \ttb1, #IDMAP_DIR_SIZE
60 .endm
61
62#ifdef CONFIG_ARM64_64K_PAGES
63#define BLOCK_SHIFT PAGE_SHIFT
64#define BLOCK_SIZE PAGE_SIZE
65#else
66#define BLOCK_SHIFT SECTION_SHIFT
67#define BLOCK_SIZE SECTION_SIZE
68#endif
69
70#define KERNEL_START KERNEL_RAM_VADDR
71#define KERNEL_END _end
72
73/*
74 * Initial memory map attributes.
75 */
76#ifndef CONFIG_SMP
77#define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF
78#define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF
79#else
80#define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF | PTE_SHARED
81#define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S
82#endif
83
84#ifdef CONFIG_ARM64_64K_PAGES
85#define MM_MMUFLAGS PTE_ATTRINDX(MT_NORMAL) | PTE_FLAGS
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86#else
87#define MM_MMUFLAGS PMD_ATTRINDX(MT_NORMAL) | PMD_FLAGS
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88#endif
89
90/*
91 * Kernel startup entry point.
92 * ---------------------------
93 *
94 * The requirements are:
95 * MMU = off, D-cache = off, I-cache = on or off,
96 * x0 = physical address to the FDT blob.
97 *
98 * This code is mostly position independent so you call this at
99 * __pa(PAGE_OFFSET + TEXT_OFFSET).
100 *
101 * Note that the callee-saved registers are used for storing variables
102 * that are useful before the MMU is enabled. The allocations are described
103 * in the entry routines.
104 */
105 __HEAD
106
107 /*
108 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
109 */
110 b stext // branch to kernel start, magic
111 .long 0 // reserved
112 .quad TEXT_OFFSET // Image load offset from start of RAM
113 .quad 0 // reserved
114 .quad 0 // reserved
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115 .quad 0 // reserved
116 .quad 0 // reserved
117 .quad 0 // reserved
118 .byte 0x41 // Magic number, "ARM\x64"
119 .byte 0x52
120 .byte 0x4d
121 .byte 0x64
122 .word 0 // reserved
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123
124ENTRY(stext)
125 mov x21, x0 // x21=FDT
f35a9205 126 bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
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127 bl el2_setup // Drop to EL1
128 mrs x22, midr_el1 // x22=cpuid
129 mov x0, x22
130 bl lookup_processor_type
131 mov x23, x0 // x23=current cpu_table
132 cbz x23, __error_p // invalid processor (x23=0)?
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133 bl __vet_fdt
134 bl __create_page_tables // x25=TTBR0, x26=TTBR1
135 /*
136 * The following calls CPU specific code in a position independent
137 * manner. See arch/arm64/mm/proc.S for details. x23 = base of
138 * cpu_info structure selected by lookup_processor_type above.
139 * On return, the CPU will be ready for the MMU to be turned on and
140 * the TCR will have been set.
141 */
142 ldr x27, __switch_data // address to jump to after
143 // MMU has been enabled
144 adr lr, __enable_mmu // return (PIC) address
145 ldr x12, [x23, #CPU_INFO_SETUP]
146 add x12, x12, x28 // __virt_to_phys
147 br x12 // initialise processor
148ENDPROC(stext)
149
150/*
151 * If we're fortunate enough to boot at EL2, ensure that the world is
152 * sane before dropping to EL1.
153 */
154ENTRY(el2_setup)
155 mrs x0, CurrentEL
156 cmp x0, #PSR_MODE_EL2t
157 ccmp x0, #PSR_MODE_EL2h, #0x4, ne
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158 ldr x0, =__boot_cpu_mode // Compute __boot_cpu_mode
159 add x0, x0, x28
9703d9d7 160 b.eq 1f
f35a9205 161 str wzr, [x0] // Remember we don't have EL2...
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162 ret
163
164 /* Hyp configuration. */
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1651: ldr w1, =BOOT_CPU_MODE_EL2
166 str w1, [x0, #4] // This CPU has EL2
167 mov x0, #(1 << 31) // 64-bit EL1
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168 msr hcr_el2, x0
169
170 /* Generic timers. */
171 mrs x0, cnthctl_el2
172 orr x0, x0, #3 // Enable EL1 physical timers
173 msr cnthctl_el2, x0
1f75ff0a 174 msr cntvoff_el2, xzr // Clear virtual offset
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175
176 /* Populate ID registers. */
177 mrs x0, midr_el1
178 mrs x1, mpidr_el1
179 msr vpidr_el2, x0
180 msr vmpidr_el2, x1
181
182 /* sctlr_el1 */
183 mov x0, #0x0800 // Set/clear RES{1,0} bits
184 movk x0, #0x30d0, lsl #16
185 msr sctlr_el1, x0
186
187 /* Coprocessor traps. */
188 mov x0, #0x33ff
189 msr cptr_el2, x0 // Disable copro. traps to EL2
190
191#ifdef CONFIG_COMPAT
192 msr hstr_el2, xzr // Disable CP15 traps to EL2
193#endif
194
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195 /* Stage-2 translation */
196 msr vttbr_el2, xzr
197
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198 /* Hypervisor stub */
199 adr x0, __hyp_stub_vectors
200 msr vbar_el2, x0
201
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202 /* spsr */
203 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
204 PSR_MODE_EL1h)
205 msr spsr_el2, x0
206 msr elr_el2, lr
207 eret
208ENDPROC(el2_setup)
209
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210/*
211 * We need to find out the CPU boot mode long after boot, so we need to
212 * store it in a writable variable.
213 *
214 * This is not in .bss, because we set it sufficiently early that the boot-time
215 * zeroing of .bss would clobber it.
216 */
217 .pushsection .data
218ENTRY(__boot_cpu_mode)
219 .long BOOT_CPU_MODE_EL2
220 .long 0
221 .popsection
222
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223 .align 3
2242: .quad .
225 .quad PAGE_OFFSET
226
227#ifdef CONFIG_SMP
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228 .align 3
2291: .quad .
230 .quad secondary_holding_pen_release
231
232 /*
233 * This provides a "holding pen" for platforms to hold all secondary
234 * cores are held until we're ready for them to initialise.
235 */
236ENTRY(secondary_holding_pen)
f35a9205 237 bl __calc_phys_offset // x24=phys offset
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238 bl el2_setup // Drop to EL1
239 mrs x0, mpidr_el1
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240 ldr x1, =MPIDR_HWID_BITMASK
241 and x0, x0, x1
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242 adr x1, 1b
243 ldp x2, x3, [x1]
244 sub x1, x1, x2
245 add x3, x3, x1
246pen: ldr x4, [x3]
247 cmp x4, x0
248 b.eq secondary_startup
249 wfe
250 b pen
251ENDPROC(secondary_holding_pen)
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252
253 /*
254 * Secondary entry point that jumps straight into the kernel. Only to
255 * be used where CPUs are brought online dynamically by the kernel.
256 */
257ENTRY(secondary_entry)
258 bl __calc_phys_offset // x2=phys offset
259 bl el2_setup // Drop to EL1
260 b secondary_startup
261ENDPROC(secondary_entry)
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262
263ENTRY(secondary_startup)
264 /*
265 * Common entry point for secondary CPUs.
266 */
267 mrs x22, midr_el1 // x22=cpuid
268 mov x0, x22
269 bl lookup_processor_type
270 mov x23, x0 // x23=current cpu_table
271 cbz x23, __error_p // invalid processor (x23=0)?
272
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273 pgtbl x25, x26, x24 // x25=TTBR0, x26=TTBR1
274 ldr x12, [x23, #CPU_INFO_SETUP]
275 add x12, x12, x28 // __virt_to_phys
276 blr x12 // initialise processor
277
278 ldr x21, =secondary_data
279 ldr x27, =__secondary_switched // address to jump to after enabling the MMU
280 b __enable_mmu
281ENDPROC(secondary_startup)
282
283ENTRY(__secondary_switched)
284 ldr x0, [x21] // get secondary_data.stack
285 mov sp, x0
286 mov x29, #0
287 b secondary_start_kernel
288ENDPROC(__secondary_switched)
289#endif /* CONFIG_SMP */
290
291/*
292 * Setup common bits before finally enabling the MMU. Essentially this is just
293 * loading the page table pointer and vector base registers.
294 *
295 * On entry to this code, x0 must contain the SCTLR_EL1 value for turning on
296 * the MMU.
297 */
298__enable_mmu:
299 ldr x5, =vectors
300 msr vbar_el1, x5
301 msr ttbr0_el1, x25 // load TTBR0
302 msr ttbr1_el1, x26 // load TTBR1
303 isb
304 b __turn_mmu_on
305ENDPROC(__enable_mmu)
306
307/*
308 * Enable the MMU. This completely changes the structure of the visible memory
309 * space. You will not be able to trace execution through this.
310 *
311 * x0 = system control register
312 * x27 = *virtual* address to jump to upon completion
313 *
314 * other registers depend on the function called upon completion
315 */
316 .align 6
317__turn_mmu_on:
318 msr sctlr_el1, x0
319 isb
320 br x27
321ENDPROC(__turn_mmu_on)
322
323/*
324 * Calculate the start of physical memory.
325 */
326__calc_phys_offset:
327 adr x0, 1f
328 ldp x1, x2, [x0]
329 sub x28, x0, x1 // x28 = PHYS_OFFSET - PAGE_OFFSET
330 add x24, x2, x28 // x24 = PHYS_OFFSET
331 ret
332ENDPROC(__calc_phys_offset)
333
334 .align 3
3351: .quad .
336 .quad PAGE_OFFSET
337
338/*
339 * Macro to populate the PGD for the corresponding block entry in the next
340 * level (tbl) for the given virtual address.
341 *
342 * Preserves: pgd, tbl, virt
343 * Corrupts: tmp1, tmp2
344 */
345 .macro create_pgd_entry, pgd, tbl, virt, tmp1, tmp2
346 lsr \tmp1, \virt, #PGDIR_SHIFT
347 and \tmp1, \tmp1, #PTRS_PER_PGD - 1 // PGD index
348 orr \tmp2, \tbl, #3 // PGD entry table type
349 str \tmp2, [\pgd, \tmp1, lsl #3]
350 .endm
351
352/*
353 * Macro to populate block entries in the page table for the start..end
354 * virtual range (inclusive).
355 *
356 * Preserves: tbl, flags
357 * Corrupts: phys, start, end, pstate
358 */
359 .macro create_block_map, tbl, flags, phys, start, end, idmap=0
360 lsr \phys, \phys, #BLOCK_SHIFT
361 .if \idmap
362 and \start, \phys, #PTRS_PER_PTE - 1 // table index
363 .else
364 lsr \start, \start, #BLOCK_SHIFT
365 and \start, \start, #PTRS_PER_PTE - 1 // table index
366 .endif
367 orr \phys, \flags, \phys, lsl #BLOCK_SHIFT // table entry
368 .ifnc \start,\end
369 lsr \end, \end, #BLOCK_SHIFT
370 and \end, \end, #PTRS_PER_PTE - 1 // table end index
371 .endif
3729999: str \phys, [\tbl, \start, lsl #3] // store the entry
373 .ifnc \start,\end
374 add \start, \start, #1 // next entry
375 add \phys, \phys, #BLOCK_SIZE // next block
376 cmp \start, \end
377 b.ls 9999b
378 .endif
379 .endm
380
381/*
382 * Setup the initial page tables. We only setup the barest amount which is
383 * required to get the kernel running. The following sections are required:
384 * - identity mapping to enable the MMU (low address, TTBR0)
385 * - first few MB of the kernel linear mapping to jump to once the MMU has
386 * been enabled, including the FDT blob (TTBR1)
2475ff9d 387 * - UART mapping if CONFIG_EARLY_PRINTK is enabled (TTBR1)
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388 */
389__create_page_tables:
390 pgtbl x25, x26, x24 // idmap_pg_dir and swapper_pg_dir addresses
391
392 /*
393 * Clear the idmap and swapper page tables.
394 */
395 mov x0, x25
396 add x6, x26, #SWAPPER_DIR_SIZE
3971: stp xzr, xzr, [x0], #16
398 stp xzr, xzr, [x0], #16
399 stp xzr, xzr, [x0], #16
400 stp xzr, xzr, [x0], #16
401 cmp x0, x6
402 b.lo 1b
403
404 ldr x7, =MM_MMUFLAGS
405
406 /*
407 * Create the identity mapping.
408 */
409 add x0, x25, #PAGE_SIZE // section table address
410 adr x3, __turn_mmu_on // virtual/physical address
411 create_pgd_entry x25, x0, x3, x5, x6
412 create_block_map x0, x7, x3, x5, x5, idmap=1
413
414 /*
415 * Map the kernel image (starting with PHYS_OFFSET).
416 */
417 add x0, x26, #PAGE_SIZE // section table address
418 mov x5, #PAGE_OFFSET
419 create_pgd_entry x26, x0, x5, x3, x6
420 ldr x6, =KERNEL_END - 1
421 mov x3, x24 // phys offset
422 create_block_map x0, x7, x3, x5, x6
423
424 /*
425 * Map the FDT blob (maximum 2MB; must be within 512MB of
426 * PHYS_OFFSET).
427 */
428 mov x3, x21 // FDT phys address
429 and x3, x3, #~((1 << 21) - 1) // 2MB aligned
430 mov x6, #PAGE_OFFSET
431 sub x5, x3, x24 // subtract PHYS_OFFSET
432 tst x5, #~((1 << 29) - 1) // within 512MB?
433 csel x21, xzr, x21, ne // zero the FDT pointer
434 b.ne 1f
435 add x5, x5, x6 // __va(FDT blob)
436 add x6, x5, #1 << 21 // 2MB for the FDT blob
437 sub x6, x6, #1 // inclusive range
438 create_block_map x0, x7, x3, x5, x6
4391:
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440#ifdef CONFIG_EARLY_PRINTK
441 /*
442 * Create the pgd entry for the UART mapping. The full mapping is done
443 * later based earlyprintk kernel parameter.
444 */
445 ldr x5, =EARLYCON_IOBASE // UART virtual address
446 add x0, x26, #2 * PAGE_SIZE // section table address
447 create_pgd_entry x26, x0, x5, x6, x7
448#endif
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449 ret
450ENDPROC(__create_page_tables)
451 .ltorg
452
453 .align 3
454 .type __switch_data, %object
455__switch_data:
456 .quad __mmap_switched
457 .quad __data_loc // x4
458 .quad _data // x5
459 .quad __bss_start // x6
460 .quad _end // x7
461 .quad processor_id // x4
462 .quad __fdt_pointer // x5
463 .quad memstart_addr // x6
464 .quad init_thread_union + THREAD_START_SP // sp
465
466/*
467 * The following fragment of code is executed with the MMU on in MMU mode, and
468 * uses absolute addresses; this is not position independent.
469 */
470__mmap_switched:
471 adr x3, __switch_data + 8
472
473 ldp x4, x5, [x3], #16
474 ldp x6, x7, [x3], #16
475 cmp x4, x5 // Copy data segment if needed
4761: ccmp x5, x6, #4, ne
477 b.eq 2f
478 ldr x16, [x4], #8
479 str x16, [x5], #8
480 b 1b
4812:
4821: cmp x6, x7
483 b.hs 2f
484 str xzr, [x6], #8 // Clear BSS
485 b 1b
4862:
487 ldp x4, x5, [x3], #16
488 ldr x6, [x3], #8
489 ldr x16, [x3]
490 mov sp, x16
491 str x22, [x4] // Save processor ID
492 str x21, [x5] // Save FDT pointer
493 str x24, [x6] // Save PHYS_OFFSET
494 mov x29, #0
495 b start_kernel
496ENDPROC(__mmap_switched)
497
498/*
499 * Exception handling. Something went wrong and we can't proceed. We ought to
500 * tell the user, but since we don't have any guarantee that we're even
501 * running on the right architecture, we do virtually nothing.
502 */
503__error_p:
504ENDPROC(__error_p)
505
506__error:
5071: nop
508 b 1b
509ENDPROC(__error)
510
511/*
512 * This function gets the processor ID in w0 and searches the cpu_table[] for
513 * a match. It returns a pointer to the struct cpu_info it found. The
514 * cpu_table[] must end with an empty (all zeros) structure.
515 *
516 * This routine can be called via C code and it needs to work with the MMU
517 * both disabled and enabled (the offset is calculated automatically).
518 */
519ENTRY(lookup_processor_type)
520 adr x1, __lookup_processor_type_data
521 ldp x2, x3, [x1]
522 sub x1, x1, x2 // get offset between VA and PA
523 add x3, x3, x1 // convert VA to PA
5241:
525 ldp w5, w6, [x3] // load cpu_id_val and cpu_id_mask
526 cbz w5, 2f // end of list?
527 and w6, w6, w0
528 cmp w5, w6
529 b.eq 3f
530 add x3, x3, #CPU_INFO_SZ
531 b 1b
5322:
533 mov x3, #0 // unknown processor
5343:
535 mov x0, x3
536 ret
537ENDPROC(lookup_processor_type)
538
539 .align 3
540 .type __lookup_processor_type_data, %object
541__lookup_processor_type_data:
542 .quad .
543 .quad cpu_table
544 .size __lookup_processor_type_data, . - __lookup_processor_type_data
545
546/*
547 * Determine validity of the x21 FDT pointer.
548 * The dtb must be 8-byte aligned and live in the first 512M of memory.
549 */
550__vet_fdt:
551 tst x21, #0x7
552 b.ne 1f
553 cmp x21, x24
554 b.lt 1f
555 mov x0, #(1 << 29)
556 add x0, x0, x24
557 cmp x21, x0
558 b.ge 1f
559 ret
5601:
561 mov x21, #0
562 ret
563ENDPROC(__vet_fdt)