[mirror_ubuntu-focal-kernel.git] / arch / arm64 / kernel / module.c

/*
 * AArch64 loadable module support.
 *
 * Copyright (C) 2012 ARM Limited
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 * Author: Will Deacon <will.deacon@arm.com>
 */

#include <linux/bitops.h>
#include <linux/elf.h>
#include <linux/gfp.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/moduleloader.h>
#include <linux/vmalloc.h>
#include <asm/insn.h>
#include <asm/sections.h>

#define	AARCH64_INSN_IMM_MOVNZ		AARCH64_INSN_IMM_MAX
#define	AARCH64_INSN_IMM_MOVK		AARCH64_INSN_IMM_16

void *module_alloc(unsigned long size)
{
	return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END,
				    GFP_KERNEL, PAGE_KERNEL_EXEC, NUMA_NO_NODE,
				    __builtin_return_address(0));
}

enum aarch64_reloc_op {
	RELOC_OP_NONE,
	RELOC_OP_ABS,
	RELOC_OP_PREL,
	RELOC_OP_PAGE,
};

static u64 do_reloc(enum aarch64_reloc_op reloc_op, void *place, u64 val)
{
	switch (reloc_op) {
	case RELOC_OP_ABS:
		return val;
	case RELOC_OP_PREL:
		return val - (u64)place;
	case RELOC_OP_PAGE:
		return (val & ~0xfff) - ((u64)place & ~0xfff);
	case RELOC_OP_NONE:
		return 0;
	}

	pr_err("do_reloc: unknown relocation operation %d\n", reloc_op);
	return 0;
}

static int reloc_data(enum aarch64_reloc_op op, void *place, u64 val, int len)
{
	u64 imm_mask = (1 << len) - 1;
	s64 sval = do_reloc(op, place, val);

	switch (len) {
	case 16:
		*(s16 *)place = sval;
		break;
	case 32:
		*(s32 *)place = sval;
		break;
	case 64:
		*(s64 *)place = sval;
		break;
	default:
		pr_err("Invalid length (%d) for data relocation\n", len);
		return 0;
	}

	/*
	 * Extract the upper value bits (including the sign bit) and
	 * shift them to bit 0.
	 */
	sval = (s64)(sval & ~(imm_mask >> 1)) >> (len - 1);

	/*
	 * Overflow has occurred if the value is not representable in
	 * len bits (i.e the bottom len bits are not sign-extended and
	 * the top bits are not all zero).
	 */
	if ((u64)(sval + 1) > 2)
		return -ERANGE;

	return 0;
}

static int reloc_insn_movw(enum aarch64_reloc_op op, void *place, u64 val,
			   int lsb, enum aarch64_insn_imm_type imm_type)
{
	u64 imm, limit = 0;
	s64 sval;
	u32 insn = le32_to_cpu(*(u32 *)place);

	sval = do_reloc(op, place, val);
	sval >>= lsb;
	imm = sval & 0xffff;

	if (imm_type == AARCH64_INSN_IMM_MOVNZ) {
		/*
		 * For signed MOVW relocations, we have to manipulate the
		 * instruction encoding depending on whether or not the
		 * immediate is less than zero.
		 */
		insn &= ~(3 << 29);
		if ((s64)imm >= 0) {
			/* >=0: Set the instruction to MOVZ (opcode 10b). */
			insn |= 2 << 29;
		} else {
			/*
			 * <0: Set the instruction to MOVN (opcode 00b).
			 *     Since we've masked the opcode already, we
			 *     don't need to do anything other than
			 *     inverting the new immediate field.
			 */
			imm = ~imm;
		}
		imm_type = AARCH64_INSN_IMM_MOVK;
	}

	/* Update the instruction with the new encoding. */
	insn = aarch64_insn_encode_immediate(imm_type, insn, imm);
	*(u32 *)place = cpu_to_le32(insn);

	/* Shift out the immediate field. */
	sval >>= 16;

	/*
	 * For unsigned immediates, the overflow check is straightforward.
	 * For signed immediates, the sign bit is actually the bit past the
	 * most significant bit of the field.
	 * The AARCH64_INSN_IMM_16 immediate type is unsigned.
	 */
	if (imm_type != AARCH64_INSN_IMM_16) {
		sval++;
		limit++;
	}

	/* Check the upper bits depending on the sign of the immediate. */
	if ((u64)sval > limit)
		return -ERANGE;

	return 0;
}

static int reloc_insn_imm(enum aarch64_reloc_op op, void *place, u64 val,
			  int lsb, int len, enum aarch64_insn_imm_type imm_type)
{
	u64 imm, imm_mask;
	s64 sval;
	u32 insn = le32_to_cpu(*(u32 *)place);

	/* Calculate the relocation value. */
	sval = do_reloc(op, place, val);
	sval >>= lsb;

	/* Extract the value bits and shift them to bit 0. */
	imm_mask = (BIT(lsb + len) - 1) >> lsb;
	imm = sval & imm_mask;

	/* Update the instruction's immediate field. */
	insn = aarch64_insn_encode_immediate(imm_type, insn, imm);
	*(u32 *)place = cpu_to_le32(insn);

	/*
	 * Extract the upper value bits (including the sign bit) and
	 * shift them to bit 0.
	 */
	sval = (s64)(sval & ~(imm_mask >> 1)) >> (len - 1);

	/*
	 * Overflow has occurred if the upper bits are not all equal to
	 * the sign bit of the value.
	 */
	if ((u64)(sval + 1) >= 2)
		return -ERANGE;

	return 0;
}

int apply_relocate_add(Elf64_Shdr *sechdrs,
		       const char *strtab,
		       unsigned int symindex,
		       unsigned int relsec,
		       struct module *me)
{
	unsigned int i;
	int ovf;
	bool overflow_check;
	Elf64_Sym *sym;
	void *loc;
	u64 val;
	Elf64_Rela *rel = (void *)sechdrs[relsec].sh_addr;

	for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
		/* loc corresponds to P in the AArch64 ELF document. */
		loc = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
			+ rel[i].r_offset;

		/* sym is the ELF symbol we're referring to. */
		sym = (Elf64_Sym *)sechdrs[symindex].sh_addr
			+ ELF64_R_SYM(rel[i].r_info);

		/* val corresponds to (S + A) in the AArch64 ELF document. */
		val = sym->st_value + rel[i].r_addend;

		/* Check for overflow by default. */
		overflow_check = true;

		/* Perform the static relocation. */
		switch (ELF64_R_TYPE(rel[i].r_info)) {
		/* Null relocations. */
		case R_ARM_NONE:
		case R_AARCH64_NONE:
			ovf = 0;
			break;

		/* Data relocations. */
		case R_AARCH64_ABS64:
			overflow_check = false;
			ovf = reloc_data(RELOC_OP_ABS, loc, val, 64);
			break;
		case R_AARCH64_ABS32:
			ovf = reloc_data(RELOC_OP_ABS, loc, val, 32);
			break;
		case R_AARCH64_ABS16:
			ovf = reloc_data(RELOC_OP_ABS, loc, val, 16);
			break;
		case R_AARCH64_PREL64:
			overflow_check = false;
			ovf = reloc_data(RELOC_OP_PREL, loc, val, 64);
			break;
		case R_AARCH64_PREL32:
			ovf = reloc_data(RELOC_OP_PREL, loc, val, 32);
			break;
		case R_AARCH64_PREL16:
			ovf = reloc_data(RELOC_OP_PREL, loc, val, 16);
			break;

		/* MOVW instruction relocations. */
		case R_AARCH64_MOVW_UABS_G0_NC:
			overflow_check = false;
		case R_AARCH64_MOVW_UABS_G0:
			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
					      AARCH64_INSN_IMM_16);
			break;
		case R_AARCH64_MOVW_UABS_G1_NC:
			overflow_check = false;
		case R_AARCH64_MOVW_UABS_G1:
			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
					      AARCH64_INSN_IMM_16);
			break;
		case R_AARCH64_MOVW_UABS_G2_NC:
			overflow_check = false;
		case R_AARCH64_MOVW_UABS_G2:
			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
					      AARCH64_INSN_IMM_16);
			break;
		case R_AARCH64_MOVW_UABS_G3:
			/* We're using the top bits so we can't overflow. */
			overflow_check = false;
			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 48,
					      AARCH64_INSN_IMM_16);
			break;
		case R_AARCH64_MOVW_SABS_G0:
			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
					      AARCH64_INSN_IMM_MOVNZ);
			break;
		case R_AARCH64_MOVW_SABS_G1:
			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
					      AARCH64_INSN_IMM_MOVNZ);
			break;
		case R_AARCH64_MOVW_SABS_G2:
			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
					      AARCH64_INSN_IMM_MOVNZ);
			break;
		case R_AARCH64_MOVW_PREL_G0_NC:
			overflow_check = false;
			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
					      AARCH64_INSN_IMM_MOVK);
			break;
		case R_AARCH64_MOVW_PREL_G0:
			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
					      AARCH64_INSN_IMM_MOVNZ);
			break;
		case R_AARCH64_MOVW_PREL_G1_NC:
			overflow_check = false;
			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
					      AARCH64_INSN_IMM_MOVK);
			break;
		case R_AARCH64_MOVW_PREL_G1:
			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
					      AARCH64_INSN_IMM_MOVNZ);
			break;
		case R_AARCH64_MOVW_PREL_G2_NC:
			overflow_check = false;
			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
					      AARCH64_INSN_IMM_MOVK);
			break;
		case R_AARCH64_MOVW_PREL_G2:
			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
					      AARCH64_INSN_IMM_MOVNZ);
			break;
		case R_AARCH64_MOVW_PREL_G3:
			/* We're using the top bits so we can't overflow. */
			overflow_check = false;
			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 48,
					      AARCH64_INSN_IMM_MOVNZ);
			break;

		/* Immediate instruction relocations. */
		case R_AARCH64_LD_PREL_LO19:
			ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
					     AARCH64_INSN_IMM_19);
			break;
		case R_AARCH64_ADR_PREL_LO21:
			ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 0, 21,
					     AARCH64_INSN_IMM_ADR);
			break;
		case R_AARCH64_ADR_PREL_PG_HI21_NC:
			overflow_check = false;
		case R_AARCH64_ADR_PREL_PG_HI21:
			ovf = reloc_insn_imm(RELOC_OP_PAGE, loc, val, 12, 21,
					     AARCH64_INSN_IMM_ADR);
			break;
		case R_AARCH64_ADD_ABS_LO12_NC:
		case R_AARCH64_LDST8_ABS_LO12_NC:
			overflow_check = false;
			ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 0, 12,
					     AARCH64_INSN_IMM_12);
			break;
		case R_AARCH64_LDST16_ABS_LO12_NC:
			overflow_check = false;
			ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 1, 11,
					     AARCH64_INSN_IMM_12);
			break;
		case R_AARCH64_LDST32_ABS_LO12_NC:
			overflow_check = false;
			ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 2, 10,
					     AARCH64_INSN_IMM_12);
			break;
		case R_AARCH64_LDST64_ABS_LO12_NC:
			overflow_check = false;
			ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 3, 9,
					     AARCH64_INSN_IMM_12);
			break;
		case R_AARCH64_LDST128_ABS_LO12_NC:
			overflow_check = false;
			ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 4, 8,
					     AARCH64_INSN_IMM_12);
			break;
		case R_AARCH64_TSTBR14:
			ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 14,
					     AARCH64_INSN_IMM_14);
			break;
		case R_AARCH64_CONDBR19:
			ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
					     AARCH64_INSN_IMM_19);
			break;
		case R_AARCH64_JUMP26:
		case R_AARCH64_CALL26:
			ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 26,
					     AARCH64_INSN_IMM_26);
			break;

		default:
			pr_err("module %s: unsupported RELA relocation: %llu\n",
			       me->name, ELF64_R_TYPE(rel[i].r_info));
			return -ENOEXEC;
		}

		if (overflow_check && ovf == -ERANGE)
			goto overflow;

	}

	return 0;

overflow:
	pr_err("module %s: overflow in relocation type %d val %Lx\n",
	       me->name, (int)ELF64_R_TYPE(rel[i].r_info), val);
	return -ENOEXEC;
}

int module_finalize(const Elf_Ehdr *hdr,
		    const Elf_Shdr *sechdrs,
		    struct module *me)
{
	const Elf_Shdr *s, *se;
	const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;

	for (s = sechdrs, se = sechdrs + hdr->e_shnum; s < se; s++) {
		if (strcmp(".altinstructions", secstrs + s->sh_name) == 0) {
			apply_alternatives((void *)s->sh_addr, s->sh_size);
			return 0;
		}
	}

	return 0;
}
Commit	Line	Data
257cb251 WD	1	/*
	2	* AArch64 loadable module support.
	3	*
	4	* Copyright (C) 2012 ARM Limited
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	17	*
	18	* Author: Will Deacon <will.deacon@arm.com>
	19	*/
	20
	21	#include <linux/bitops.h>
	22	#include <linux/elf.h>
	23	#include <linux/gfp.h>
	24	#include <linux/kernel.h>
	25	#include <linux/mm.h>
	26	#include <linux/moduleloader.h>
	27	#include <linux/vmalloc.h>
c84fced8	28	#include <asm/insn.h>
932ded4b	29	#include <asm/sections.h>
c84fced8 JL	30
	31	#define AARCH64_INSN_IMM_MOVNZ AARCH64_INSN_IMM_MAX
	32	#define AARCH64_INSN_IMM_MOVK AARCH64_INSN_IMM_16
257cb251 WD	33
	34	void *module_alloc(unsigned long size)
	35	{
	36	return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END,
40c3baa7	37	GFP_KERNEL, PAGE_KERNEL_EXEC, NUMA_NO_NODE,
257cb251 WD	38	__builtin_return_address(0));
	39	}
	40
	41	enum aarch64_reloc_op {
	42	RELOC_OP_NONE,
	43	RELOC_OP_ABS,
	44	RELOC_OP_PREL,
	45	RELOC_OP_PAGE,
	46	};
	47
	48	static u64 do_reloc(enum aarch64_reloc_op reloc_op, void *place, u64 val)
	49	{
	50	switch (reloc_op) {
	51	case RELOC_OP_ABS:
	52	return val;
	53	case RELOC_OP_PREL:
	54	return val - (u64)place;
	55	case RELOC_OP_PAGE:
	56	return (val & ~0xfff) - ((u64)place & ~0xfff);
	57	case RELOC_OP_NONE:
	58	return 0;
	59	}
	60
	61	pr_err("do_reloc: unknown relocation operation %d\n", reloc_op);
	62	return 0;
	63	}
	64
	65	static int reloc_data(enum aarch64_reloc_op op, void *place, u64 val, int len)
	66	{
	67	u64 imm_mask = (1 << len) - 1;
	68	s64 sval = do_reloc(op, place, val);
	69
	70	switch (len) {
	71	case 16:
	72	(s16 )place = sval;
	73	break;
	74	case 32:
	75	(s32 )place = sval;
	76	break;
	77	case 64:
	78	(s64 )place = sval;
	79	break;
	80	default:
	81	pr_err("Invalid length (%d) for data relocation\n", len);
	82	return 0;
	83	}
	84
	85	/*
	86	* Extract the upper value bits (including the sign bit) and
	87	* shift them to bit 0.
	88	*/
	89	sval = (s64)(sval & ~(imm_mask >> 1)) >> (len - 1);
	90
	91	/*
	92	* Overflow has occurred if the value is not representable in
	93	* len bits (i.e the bottom len bits are not sign-extended and
	94	* the top bits are not all zero).
	95	*/
	96	if ((u64)(sval + 1) > 2)
	97	return -ERANGE;
	98
	99	return 0;
	100	}
	101
c84fced8 JL	102	static int reloc_insn_movw(enum aarch64_reloc_op op, void *place, u64 val,
c84fced8 JL	103	int lsb, enum aarch64_insn_imm_type imm_type)
257cb251	104	{
c84fced8 JL	105	u64 imm, limit = 0;
	106	s64 sval;
	107	u32 insn = le32_to_cpu((u32 )place);
257cb251	108
c84fced8 JL	109	sval = do_reloc(op, place, val);
	110	sval >>= lsb;
	111	imm = sval & 0xffff;
122e2fa0	112
c84fced8	113	if (imm_type == AARCH64_INSN_IMM_MOVNZ) {
257cb251 WD	114	/*
	115	* For signed MOVW relocations, we have to manipulate the
	116	* instruction encoding depending on whether or not the
	117	* immediate is less than zero.
	118	*/
	119	insn &= ~(3 << 29);
	120	if ((s64)imm >= 0) {
	121	/* >=0: Set the instruction to MOVZ (opcode 10b). */
	122	insn \|= 2 << 29;
	123	} else {
	124	/*
	125	* <0: Set the instruction to MOVN (opcode 00b).
	126	* Since we've masked the opcode already, we
	127	* don't need to do anything other than
	128	* inverting the new immediate field.
	129	*/
	130	imm = ~imm;
	131	}
c84fced8	132	imm_type = AARCH64_INSN_IMM_MOVK;
257cb251 WD	133	}
257cb251 WD	134
257cb251	135	/* Update the instruction with the new encoding. */
c84fced8 JL	136	insn = aarch64_insn_encode_immediate(imm_type, insn, imm);
c84fced8 JL	137	(u32 )place = cpu_to_le32(insn);
257cb251 WD	138
	139	/* Shift out the immediate field. */
	140	sval >>= 16;
	141
	142	/*
	143	* For unsigned immediates, the overflow check is straightforward.
	144	* For signed immediates, the sign bit is actually the bit past the
	145	* most significant bit of the field.
c84fced8	146	* The AARCH64_INSN_IMM_16 immediate type is unsigned.
257cb251	147	*/
c84fced8	148	if (imm_type != AARCH64_INSN_IMM_16) {
257cb251 WD	149	sval++;
	150	limit++;
	151	}
	152
	153	/* Check the upper bits depending on the sign of the immediate. */
	154	if ((u64)sval > limit)
	155	return -ERANGE;
	156
	157	return 0;
	158	}
	159
	160	static int reloc_insn_imm(enum aarch64_reloc_op op, void *place, u64 val,
c84fced8	161	int lsb, int len, enum aarch64_insn_imm_type imm_type)
257cb251 WD	162	{
	163	u64 imm, imm_mask;
	164	s64 sval;
c84fced8	165	u32 insn = le32_to_cpu((u32 )place);
257cb251 WD	166
	167	/* Calculate the relocation value. */
	168	sval = do_reloc(op, place, val);
	169	sval >>= lsb;
	170
	171	/* Extract the value bits and shift them to bit 0. */
	172	imm_mask = (BIT(lsb + len) - 1) >> lsb;
	173	imm = sval & imm_mask;
	174
	175	/* Update the instruction's immediate field. */
c84fced8 JL	176	insn = aarch64_insn_encode_immediate(imm_type, insn, imm);
c84fced8 JL	177	(u32 )place = cpu_to_le32(insn);
257cb251 WD	178
	179	/*
	180	* Extract the upper value bits (including the sign bit) and
	181	* shift them to bit 0.
	182	*/
	183	sval = (s64)(sval & ~(imm_mask >> 1)) >> (len - 1);
	184
	185	/*
	186	* Overflow has occurred if the upper bits are not all equal to
	187	* the sign bit of the value.
	188	*/
	189	if ((u64)(sval + 1) >= 2)
	190	return -ERANGE;
	191
	192	return 0;
	193	}
	194
	195	int apply_relocate_add(Elf64_Shdr *sechdrs,
	196	const char *strtab,
	197	unsigned int symindex,
	198	unsigned int relsec,
	199	struct module *me)
	200	{
	201	unsigned int i;
	202	int ovf;
	203	bool overflow_check;
	204	Elf64_Sym *sym;
	205	void *loc;
	206	u64 val;
	207	Elf64_Rela rel = (void )sechdrs[relsec].sh_addr;
	208
	209	for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
	210	/* loc corresponds to P in the AArch64 ELF document. */
	211	loc = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
	212	+ rel[i].r_offset;
	213
	214	/* sym is the ELF symbol we're referring to. */
	215	sym = (Elf64_Sym *)sechdrs[symindex].sh_addr
	216	+ ELF64_R_SYM(rel[i].r_info);
	217
	218	/* val corresponds to (S + A) in the AArch64 ELF document. */
	219	val = sym->st_value + rel[i].r_addend;
	220
	221	/* Check for overflow by default. */
	222	overflow_check = true;
	223
	224	/* Perform the static relocation. */
	225	switch (ELF64_R_TYPE(rel[i].r_info)) {
	226	/* Null relocations. */
	227	case R_ARM_NONE:
	228	case R_AARCH64_NONE:
	229	ovf = 0;
	230	break;
	231
	232	/* Data relocations. */
	233	case R_AARCH64_ABS64:
	234	overflow_check = false;
	235	ovf = reloc_data(RELOC_OP_ABS, loc, val, 64);
	236	break;
	237	case R_AARCH64_ABS32:
	238	ovf = reloc_data(RELOC_OP_ABS, loc, val, 32);
	239	break;
	240	case R_AARCH64_ABS16:
	241	ovf = reloc_data(RELOC_OP_ABS, loc, val, 16);
242	break;
243	case R_AARCH64_PREL64:
244	overflow_check = false;
245	ovf = reloc_data(RELOC_OP_PREL, loc, val, 64);
246	break;
247	case R_AARCH64_PREL32:
248	ovf = reloc_data(RELOC_OP_PREL, loc, val, 32);
249	break;
250	case R_AARCH64_PREL16:
251	ovf = reloc_data(RELOC_OP_PREL, loc, val, 16);
252	break;
253
254	/* MOVW instruction relocations. */
255	case R_AARCH64_MOVW_UABS_G0_NC:
256	overflow_check = false;
257	case R_AARCH64_MOVW_UABS_G0:
258	ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
c84fced8	259	AARCH64_INSN_IMM_16);
257cb251 WD	260	break;
	261	case R_AARCH64_MOVW_UABS_G1_NC:
	262	overflow_check = false;
	263	case R_AARCH64_MOVW_UABS_G1:
	264	ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
c84fced8	265	AARCH64_INSN_IMM_16);
257cb251 WD	266	break;
	267	case R_AARCH64_MOVW_UABS_G2_NC:
	268	overflow_check = false;
	269	case R_AARCH64_MOVW_UABS_G2:
	270	ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
c84fced8	271	AARCH64_INSN_IMM_16);
257cb251 WD	272	break;
	273	case R_AARCH64_MOVW_UABS_G3:
	274	/* We're using the top bits so we can't overflow. */
	275	overflow_check = false;
	276	ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 48,
c84fced8	277	AARCH64_INSN_IMM_16);
257cb251 WD	278	break;
	279	case R_AARCH64_MOVW_SABS_G0:
	280	ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
c84fced8	281	AARCH64_INSN_IMM_MOVNZ);
257cb251 WD	282	break;
	283	case R_AARCH64_MOVW_SABS_G1:
	284	ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
c84fced8	285	AARCH64_INSN_IMM_MOVNZ);
257cb251 WD	286	break;
	287	case R_AARCH64_MOVW_SABS_G2:
	288	ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
c84fced8	289	AARCH64_INSN_IMM_MOVNZ);
257cb251 WD	290	break;
	291	case R_AARCH64_MOVW_PREL_G0_NC:
	292	overflow_check = false;
	293	ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
c84fced8	294	AARCH64_INSN_IMM_MOVK);
257cb251 WD	295	break;
	296	case R_AARCH64_MOVW_PREL_G0:
	297	ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
c84fced8	298	AARCH64_INSN_IMM_MOVNZ);
257cb251 WD	299	break;
	300	case R_AARCH64_MOVW_PREL_G1_NC:
	301	overflow_check = false;
	302	ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
c84fced8	303	AARCH64_INSN_IMM_MOVK);
257cb251 WD	304	break;
	305	case R_AARCH64_MOVW_PREL_G1:
	306	ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
c84fced8	307	AARCH64_INSN_IMM_MOVNZ);
257cb251 WD	308	break;
	309	case R_AARCH64_MOVW_PREL_G2_NC:
	310	overflow_check = false;
	311	ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
c84fced8	312	AARCH64_INSN_IMM_MOVK);
257cb251 WD	313	break;
	314	case R_AARCH64_MOVW_PREL_G2:
	315	ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
c84fced8	316	AARCH64_INSN_IMM_MOVNZ);
257cb251 WD	317	break;
	318	case R_AARCH64_MOVW_PREL_G3:
	319	/* We're using the top bits so we can't overflow. */
	320	overflow_check = false;
	321	ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 48,
c84fced8	322	AARCH64_INSN_IMM_MOVNZ);
257cb251 WD	323	break;
	324
	325	/* Immediate instruction relocations. */
	326	case R_AARCH64_LD_PREL_LO19:
	327	ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
c84fced8	328	AARCH64_INSN_IMM_19);
257cb251 WD	329	break;
	330	case R_AARCH64_ADR_PREL_LO21:
	331	ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 0, 21,
c84fced8	332	AARCH64_INSN_IMM_ADR);
257cb251 WD	333	break;
	334	case R_AARCH64_ADR_PREL_PG_HI21_NC:
	335	overflow_check = false;
	336	case R_AARCH64_ADR_PREL_PG_HI21:
	337	ovf = reloc_insn_imm(RELOC_OP_PAGE, loc, val, 12, 21,
c84fced8	338	AARCH64_INSN_IMM_ADR);
257cb251 WD	339	break;
	340	case R_AARCH64_ADD_ABS_LO12_NC:
	341	case R_AARCH64_LDST8_ABS_LO12_NC:
	342	overflow_check = false;
	343	ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 0, 12,
c84fced8	344	AARCH64_INSN_IMM_12);
257cb251 WD	345	break;
	346	case R_AARCH64_LDST16_ABS_LO12_NC:
	347	overflow_check = false;
	348	ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 1, 11,
c84fced8	349	AARCH64_INSN_IMM_12);
257cb251 WD	350	break;
	351	case R_AARCH64_LDST32_ABS_LO12_NC:
	352	overflow_check = false;
	353	ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 2, 10,
c84fced8	354	AARCH64_INSN_IMM_12);
257cb251 WD	355	break;
	356	case R_AARCH64_LDST64_ABS_LO12_NC:
	357	overflow_check = false;
	358	ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 3, 9,
c84fced8	359	AARCH64_INSN_IMM_12);
257cb251 WD	360	break;
	361	case R_AARCH64_LDST128_ABS_LO12_NC:
	362	overflow_check = false;
	363	ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 4, 8,
c84fced8	364	AARCH64_INSN_IMM_12);
257cb251 WD	365	break;
	366	case R_AARCH64_TSTBR14:
	367	ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 14,
c84fced8	368	AARCH64_INSN_IMM_14);
257cb251 WD	369	break;
	370	case R_AARCH64_CONDBR19:
	371	ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
c84fced8	372	AARCH64_INSN_IMM_19);
257cb251 WD	373	break;
	374	case R_AARCH64_JUMP26:
	375	case R_AARCH64_CALL26:
	376	ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 26,
c84fced8	377	AARCH64_INSN_IMM_26);
257cb251 WD	378	break;
	379
	380	default:
	381	pr_err("module %s: unsupported RELA relocation: %llu\n",
	382	me->name, ELF64_R_TYPE(rel[i].r_info));
	383	return -ENOEXEC;
	384	}
	385
	386	if (overflow_check && ovf == -ERANGE)
	387	goto overflow;
	388
	389	}
	390
	391	return 0;
	392
	393	overflow:
	394	pr_err("module %s: overflow in relocation type %d val %Lx\n",
	395	me->name, (int)ELF64_R_TYPE(rel[i].r_info), val);
	396	return -ENOEXEC;
	397	}
932ded4b AP	398
	399	int module_finalize(const Elf_Ehdr *hdr,
	400	const Elf_Shdr *sechdrs,
	401	struct module *me)
	402	{
	403	const Elf_Shdr s, se;
	404	const char secstrs = (void )hdr + sechdrs[hdr->e_shstrndx].sh_offset;
	405
	406	for (s = sechdrs, se = sechdrs + hdr->e_shnum; s < se; s++) {
	407	if (strcmp(".altinstructions", secstrs + s->sh_name) == 0) {
	408	apply_alternatives((void *)s->sh_addr, s->sh_size);
	409	return 0;
	410	}
	411	}
	412
	413	return 0;
	414	}