[mirror_ubuntu-focal-kernel.git] / arch / arm64 / kernel / module.c

/*
 * AArch64 loadable module support.
 *
 * Copyright (C) 2012 ARM Limited
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 * Author: Will Deacon <will.deacon@arm.com>
 */

#include <linux/bitops.h>
#include <linux/elf.h>
#include <linux/gfp.h>
#include <linux/kasan.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/moduleloader.h>
#include <linux/vmalloc.h>
#include <asm/alternative.h>
#include <asm/insn.h>
#include <asm/sections.h>

void *module_alloc(unsigned long size)
{
	gfp_t gfp_mask = GFP_KERNEL;
	void *p;

	/* Silence the initial allocation */
	if (IS_ENABLED(CONFIG_ARM64_MODULE_PLTS))
		gfp_mask |= __GFP_NOWARN;

	p = __vmalloc_node_range(size, MODULE_ALIGN, module_alloc_base,
				module_alloc_base + MODULES_VSIZE,
				gfp_mask, PAGE_KERNEL_EXEC, 0,
				NUMA_NO_NODE, __builtin_return_address(0));

	if (!p && IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) &&
	    !IS_ENABLED(CONFIG_KASAN))
		/*
		 * KASAN can only deal with module allocations being served
		 * from the reserved module region, since the remainder of
		 * the vmalloc region is already backed by zero shadow pages,
		 * and punching holes into it is non-trivial. Since the module
		 * region is not randomized when KASAN is enabled, it is even
		 * less likely that the module region gets exhausted, so we
		 * can simply omit this fallback in that case.
		 */
		p = __vmalloc_node_range(size, MODULE_ALIGN, module_alloc_base,
				module_alloc_base + SZ_2G, GFP_KERNEL,
				PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE,
				__builtin_return_address(0));

	if (p && (kasan_module_alloc(p, size) < 0)) {
		vfree(p);
		return NULL;
	}

	return p;
}

enum aarch64_reloc_op {
	RELOC_OP_NONE,
	RELOC_OP_ABS,
	RELOC_OP_PREL,
	RELOC_OP_PAGE,
};

static u64 do_reloc(enum aarch64_reloc_op reloc_op, __le32 *place, u64 val)
{
	switch (reloc_op) {
	case RELOC_OP_ABS:
		return val;
	case RELOC_OP_PREL:
		return val - (u64)place;
	case RELOC_OP_PAGE:
		return (val & ~0xfff) - ((u64)place & ~0xfff);
	case RELOC_OP_NONE:
		return 0;
	}

	pr_err("do_reloc: unknown relocation operation %d\n", reloc_op);
	return 0;
}

static int reloc_data(enum aarch64_reloc_op op, void *place, u64 val, int len)
{
	s64 sval = do_reloc(op, place, val);

	/*
	 * The ELF psABI for AArch64 documents the 16-bit and 32-bit place
	 * relative and absolute relocations as having a range of [-2^15, 2^16)
	 * or [-2^31, 2^32), respectively. However, in order to be able to
	 * detect overflows reliably, we have to choose whether we interpret
	 * such quantities as signed or as unsigned, and stick with it.
	 * The way we organize our address space requires a signed
	 * interpretation of 32-bit relative references, so let's use that
	 * for all R_AARCH64_PRELxx relocations. This means our upper
	 * bound for overflow detection should be Sxx_MAX rather than Uxx_MAX.
	 */

	switch (len) {
	case 16:
		*(s16 *)place = sval;
		switch (op) {
		case RELOC_OP_ABS:
			if (sval < 0 || sval > U16_MAX)
				return -ERANGE;
			break;
		case RELOC_OP_PREL:
			if (sval < S16_MIN || sval > S16_MAX)
				return -ERANGE;
			break;
		default:
			pr_err("Invalid 16-bit data relocation (%d)\n", op);
			return 0;
		}
		break;
	case 32:
		*(s32 *)place = sval;
		switch (op) {
		case RELOC_OP_ABS:
			if (sval < 0 || sval > U32_MAX)
				return -ERANGE;
			break;
		case RELOC_OP_PREL:
			if (sval < S32_MIN || sval > S32_MAX)
				return -ERANGE;
			break;
		default:
			pr_err("Invalid 32-bit data relocation (%d)\n", op);
			return 0;
		}
		break;
	case 64:
		*(s64 *)place = sval;
		break;
	default:
		pr_err("Invalid length (%d) for data relocation\n", len);
		return 0;
	}
	return 0;
}

enum aarch64_insn_movw_imm_type {
	AARCH64_INSN_IMM_MOVNZ,
	AARCH64_INSN_IMM_MOVKZ,
};

static int reloc_insn_movw(enum aarch64_reloc_op op, __le32 *place, u64 val,
			   int lsb, enum aarch64_insn_movw_imm_type imm_type)
{
	u64 imm;
	s64 sval;
	u32 insn = le32_to_cpu(*place);

	sval = do_reloc(op, place, val);
	imm = sval >> lsb;

	if (imm_type == AARCH64_INSN_IMM_MOVNZ) {
		/*
		 * For signed MOVW relocations, we have to manipulate the
		 * instruction encoding depending on whether or not the
		 * immediate is less than zero.
		 */
		insn &= ~(3 << 29);
		if (sval >= 0) {
			/* >=0: Set the instruction to MOVZ (opcode 10b). */
			insn |= 2 << 29;
		} else {
			/*
			 * <0: Set the instruction to MOVN (opcode 00b).
			 *     Since we've masked the opcode already, we
			 *     don't need to do anything other than
			 *     inverting the new immediate field.
			 */
			imm = ~imm;
		}
	}

	/* Update the instruction with the new encoding. */
	insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm);
	*place = cpu_to_le32(insn);

	if (imm > U16_MAX)
		return -ERANGE;

	return 0;
}

static int reloc_insn_imm(enum aarch64_reloc_op op, __le32 *place, u64 val,
			  int lsb, int len, enum aarch64_insn_imm_type imm_type)
{
	u64 imm, imm_mask;
	s64 sval;
	u32 insn = le32_to_cpu(*place);

	/* Calculate the relocation value. */
	sval = do_reloc(op, place, val);
	sval >>= lsb;

	/* Extract the value bits and shift them to bit 0. */
	imm_mask = (BIT(lsb + len) - 1) >> lsb;
	imm = sval & imm_mask;

	/* Update the instruction's immediate field. */
	insn = aarch64_insn_encode_immediate(imm_type, insn, imm);
	*place = cpu_to_le32(insn);

	/*
	 * Extract the upper value bits (including the sign bit) and
	 * shift them to bit 0.
	 */
	sval = (s64)(sval & ~(imm_mask >> 1)) >> (len - 1);

	/*
	 * Overflow has occurred if the upper bits are not all equal to
	 * the sign bit of the value.
	 */
	if ((u64)(sval + 1) >= 2)
		return -ERANGE;

	return 0;
}

static int reloc_insn_adrp(struct module *mod, Elf64_Shdr *sechdrs,
			   __le32 *place, u64 val)
{
	u32 insn;

	if (!is_forbidden_offset_for_adrp(place))
		return reloc_insn_imm(RELOC_OP_PAGE, place, val, 12, 21,
				      AARCH64_INSN_IMM_ADR);

	/* patch ADRP to ADR if it is in range */
	if (!reloc_insn_imm(RELOC_OP_PREL, place, val & ~0xfff, 0, 21,
			    AARCH64_INSN_IMM_ADR)) {
		insn = le32_to_cpu(*place);
		insn &= ~BIT(31);
	} else {
		/* out of range for ADR -> emit a veneer */
		val = module_emit_veneer_for_adrp(mod, sechdrs, place, val & ~0xfff);
		if (!val)
			return -ENOEXEC;
		insn = aarch64_insn_gen_branch_imm((u64)place, val,
						   AARCH64_INSN_BRANCH_NOLINK);
	}

	*place = cpu_to_le32(insn);
	return 0;
}

int apply_relocate_add(Elf64_Shdr *sechdrs,
		       const char *strtab,
		       unsigned int symindex,
		       unsigned int relsec,
		       struct module *me)
{
	unsigned int i;
	int ovf;
	bool overflow_check;
	Elf64_Sym *sym;
	void *loc;
	u64 val;
	Elf64_Rela *rel = (void *)sechdrs[relsec].sh_addr;

	for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
		/* loc corresponds to P in the AArch64 ELF document. */
		loc = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
			+ rel[i].r_offset;

		/* sym is the ELF symbol we're referring to. */
		sym = (Elf64_Sym *)sechdrs[symindex].sh_addr
			+ ELF64_R_SYM(rel[i].r_info);

		/* val corresponds to (S + A) in the AArch64 ELF document. */
		val = sym->st_value + rel[i].r_addend;

		/* Check for overflow by default. */
		overflow_check = true;

		/* Perform the static relocation. */
		switch (ELF64_R_TYPE(rel[i].r_info)) {
		/* Null relocations. */
		case R_ARM_NONE:
		case R_AARCH64_NONE:
			ovf = 0;
			break;

		/* Data relocations. */
		case R_AARCH64_ABS64:
			overflow_check = false;
			ovf = reloc_data(RELOC_OP_ABS, loc, val, 64);
			break;
		case R_AARCH64_ABS32:
			ovf = reloc_data(RELOC_OP_ABS, loc, val, 32);
			break;
		case R_AARCH64_ABS16:
			ovf = reloc_data(RELOC_OP_ABS, loc, val, 16);
			break;
		case R_AARCH64_PREL64:
			overflow_check = false;
			ovf = reloc_data(RELOC_OP_PREL, loc, val, 64);
			break;
		case R_AARCH64_PREL32:
			ovf = reloc_data(RELOC_OP_PREL, loc, val, 32);
			break;
		case R_AARCH64_PREL16:
			ovf = reloc_data(RELOC_OP_PREL, loc, val, 16);
			break;

		/* MOVW instruction relocations. */
		case R_AARCH64_MOVW_UABS_G0_NC:
			overflow_check = false;
		case R_AARCH64_MOVW_UABS_G0:
			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
					      AARCH64_INSN_IMM_MOVKZ);
			break;
		case R_AARCH64_MOVW_UABS_G1_NC:
			overflow_check = false;
		case R_AARCH64_MOVW_UABS_G1:
			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
					      AARCH64_INSN_IMM_MOVKZ);
			break;
		case R_AARCH64_MOVW_UABS_G2_NC:
			overflow_check = false;
		case R_AARCH64_MOVW_UABS_G2:
			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
					      AARCH64_INSN_IMM_MOVKZ);
			break;
		case R_AARCH64_MOVW_UABS_G3:
			/* We're using the top bits so we can't overflow. */
			overflow_check = false;
			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 48,
					      AARCH64_INSN_IMM_MOVKZ);
			break;
		case R_AARCH64_MOVW_SABS_G0:
			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
					      AARCH64_INSN_IMM_MOVNZ);
			break;
		case R_AARCH64_MOVW_SABS_G1:
			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
					      AARCH64_INSN_IMM_MOVNZ);
			break;
		case R_AARCH64_MOVW_SABS_G2:
			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
					      AARCH64_INSN_IMM_MOVNZ);
			break;
		case R_AARCH64_MOVW_PREL_G0_NC:
			overflow_check = false;
			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
					      AARCH64_INSN_IMM_MOVKZ);
			break;
		case R_AARCH64_MOVW_PREL_G0:
			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
					      AARCH64_INSN_IMM_MOVNZ);
			break;
		case R_AARCH64_MOVW_PREL_G1_NC:
			overflow_check = false;
			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
					      AARCH64_INSN_IMM_MOVKZ);
			break;
		case R_AARCH64_MOVW_PREL_G1:
			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
					      AARCH64_INSN_IMM_MOVNZ);
			break;
		case R_AARCH64_MOVW_PREL_G2_NC:
			overflow_check = false;
			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
					      AARCH64_INSN_IMM_MOVKZ);
			break;
		case R_AARCH64_MOVW_PREL_G2:
			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
					      AARCH64_INSN_IMM_MOVNZ);
			break;
		case R_AARCH64_MOVW_PREL_G3:
			/* We're using the top bits so we can't overflow. */
			overflow_check = false;
			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 48,
					      AARCH64_INSN_IMM_MOVNZ);
			break;

		/* Immediate instruction relocations. */
		case R_AARCH64_LD_PREL_LO19:
			ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
					     AARCH64_INSN_IMM_19);
			break;
		case R_AARCH64_ADR_PREL_LO21:
			ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 0, 21,
					     AARCH64_INSN_IMM_ADR);
			break;
		case R_AARCH64_ADR_PREL_PG_HI21_NC:
			overflow_check = false;
		case R_AARCH64_ADR_PREL_PG_HI21:
			ovf = reloc_insn_adrp(me, sechdrs, loc, val);
			if (ovf && ovf != -ERANGE)
				return ovf;
			break;
		case R_AARCH64_ADD_ABS_LO12_NC:
		case R_AARCH64_LDST8_ABS_LO12_NC:
			overflow_check = false;
			ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 0, 12,
					     AARCH64_INSN_IMM_12);
			break;
		case R_AARCH64_LDST16_ABS_LO12_NC:
			overflow_check = false;
			ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 1, 11,
					     AARCH64_INSN_IMM_12);
			break;
		case R_AARCH64_LDST32_ABS_LO12_NC:
			overflow_check = false;
			ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 2, 10,
					     AARCH64_INSN_IMM_12);
			break;
		case R_AARCH64_LDST64_ABS_LO12_NC:
			overflow_check = false;
			ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 3, 9,
					     AARCH64_INSN_IMM_12);
			break;
		case R_AARCH64_LDST128_ABS_LO12_NC:
			overflow_check = false;
			ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 4, 8,
					     AARCH64_INSN_IMM_12);
			break;
		case R_AARCH64_TSTBR14:
			ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 14,
					     AARCH64_INSN_IMM_14);
			break;
		case R_AARCH64_CONDBR19:
			ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
					     AARCH64_INSN_IMM_19);
			break;
		case R_AARCH64_JUMP26:
		case R_AARCH64_CALL26:
			ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 26,
					     AARCH64_INSN_IMM_26);

			if (IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) &&
			    ovf == -ERANGE) {
				val = module_emit_plt_entry(me, sechdrs, loc, &rel[i], sym);
				if (!val)
					return -ENOEXEC;
				ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2,
						     26, AARCH64_INSN_IMM_26);
			}
			break;

		default:
			pr_err("module %s: unsupported RELA relocation: %llu\n",
			       me->name, ELF64_R_TYPE(rel[i].r_info));
			return -ENOEXEC;
		}

		if (overflow_check && ovf == -ERANGE)
			goto overflow;

	}

	return 0;

overflow:
	pr_err("module %s: overflow in relocation type %d val %Lx\n",
	       me->name, (int)ELF64_R_TYPE(rel[i].r_info), val);
	return -ENOEXEC;
}

int module_finalize(const Elf_Ehdr *hdr,
		    const Elf_Shdr *sechdrs,
		    struct module *me)
{
	const Elf_Shdr *s, *se;
	const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;

	for (s = sechdrs, se = sechdrs + hdr->e_shnum; s < se; s++) {
		if (strcmp(".altinstructions", secstrs + s->sh_name) == 0)
			apply_alternatives_module((void *)s->sh_addr, s->sh_size);
#ifdef CONFIG_ARM64_MODULE_PLTS
		if (IS_ENABLED(CONFIG_DYNAMIC_FTRACE) &&
		    !strcmp(".text.ftrace_trampoline", secstrs + s->sh_name))
			me->arch.ftrace_trampoline = (void *)s->sh_addr;
#endif
	}

	return 0;
}
Commit	Line	Data
257cb251 WD	1	/*
	2	* AArch64 loadable module support.
	3	*
	4	* Copyright (C) 2012 ARM Limited
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	17	*
	18	* Author: Will Deacon <will.deacon@arm.com>
	19	*/
	20
	21	#include <linux/bitops.h>
	22	#include <linux/elf.h>
	23	#include <linux/gfp.h>
39d114dd	24	#include <linux/kasan.h>
257cb251 WD	25	#include <linux/kernel.h>
	26	#include <linux/mm.h>
	27	#include <linux/moduleloader.h>
	28	#include <linux/vmalloc.h>
2c2b282d	29	#include <asm/alternative.h>
c84fced8	30	#include <asm/insn.h>
932ded4b	31	#include <asm/sections.h>
c84fced8	32
257cb251 WD	33	void *module_alloc(unsigned long size)
257cb251 WD	34	{
0c2cf6d9	35	gfp_t gfp_mask = GFP_KERNEL;
39d114dd AR	36	void *p;
39d114dd AR	37
0c2cf6d9 FF	38	/* Silence the initial allocation */
	39	if (IS_ENABLED(CONFIG_ARM64_MODULE_PLTS))
	40	gfp_mask \|= __GFP_NOWARN;
	41
f80fb3a3 AB	42	p = __vmalloc_node_range(size, MODULE_ALIGN, module_alloc_base,
f80fb3a3 AB	43	module_alloc_base + MODULES_VSIZE,
0c2cf6d9	44	gfp_mask, PAGE_KERNEL_EXEC, 0,
39d114dd AR	45	NUMA_NO_NODE, __builtin_return_address(0));
39d114dd AR	46
fd045f6c AB	47	if (!p && IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) &&
	48	!IS_ENABLED(CONFIG_KASAN))
	49	/*
	50	* KASAN can only deal with module allocations being served
	51	* from the reserved module region, since the remainder of
	52	* the vmalloc region is already backed by zero shadow pages,
	53	* and punching holes into it is non-trivial. Since the module
	54	* region is not randomized when KASAN is enabled, it is even
	55	* less likely that the module region gets exhausted, so we
	56	* can simply omit this fallback in that case.
	57	*/
f2b9ba87	58	p = __vmalloc_node_range(size, MODULE_ALIGN, module_alloc_base,
b2eed9b5	59	module_alloc_base + SZ_2G, GFP_KERNEL,
f2b9ba87 AB	60	PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE,
f2b9ba87 AB	61	__builtin_return_address(0));
fd045f6c	62
39d114dd AR	63	if (p && (kasan_module_alloc(p, size) < 0)) {
	64	vfree(p);
	65	return NULL;
	66	}
	67
	68	return p;
257cb251 WD	69	}
	70
	71	enum aarch64_reloc_op {
	72	RELOC_OP_NONE,
	73	RELOC_OP_ABS,
	74	RELOC_OP_PREL,
	75	RELOC_OP_PAGE,
	76	};
	77
02129ae5	78	static u64 do_reloc(enum aarch64_reloc_op reloc_op, __le32 *place, u64 val)
257cb251 WD	79	{
	80	switch (reloc_op) {
	81	case RELOC_OP_ABS:
	82	return val;
	83	case RELOC_OP_PREL:
	84	return val - (u64)place;
	85	case RELOC_OP_PAGE:
	86	return (val & ~0xfff) - ((u64)place & ~0xfff);
	87	case RELOC_OP_NONE:
	88	return 0;
	89	}
	90
	91	pr_err("do_reloc: unknown relocation operation %d\n", reloc_op);
	92	return 0;
	93	}
	94
	95	static int reloc_data(enum aarch64_reloc_op op, void *place, u64 val, int len)
	96	{
257cb251 WD	97	s64 sval = do_reloc(op, place, val);
257cb251 WD	98
1cf24a2c AB	99	/*
1cf24a2c AB	100	* The ELF psABI for AArch64 documents the 16-bit and 32-bit place
3fd00beb AB	101	* relative and absolute relocations as having a range of [-2^15, 2^16)
	102	* or [-2^31, 2^32), respectively. However, in order to be able to
	103	* detect overflows reliably, we have to choose whether we interpret
	104	* such quantities as signed or as unsigned, and stick with it.
1cf24a2c AB	105	* The way we organize our address space requires a signed
	106	* interpretation of 32-bit relative references, so let's use that
	107	* for all R_AARCH64_PRELxx relocations. This means our upper
	108	* bound for overflow detection should be Sxx_MAX rather than Uxx_MAX.
	109	*/
	110
257cb251 WD	111	switch (len) {
	112	case 16:
	113	(s16 )place = sval;
3fd00beb AB	114	switch (op) {
	115	case RELOC_OP_ABS:
	116	if (sval < 0 \|\| sval > U16_MAX)
	117	return -ERANGE;
	118	break;
	119	case RELOC_OP_PREL:
	120	if (sval < S16_MIN \|\| sval > S16_MAX)
	121	return -ERANGE;
	122	break;
	123	default:
	124	pr_err("Invalid 16-bit data relocation (%d)\n", op);
	125	return 0;
	126	}
257cb251 WD	127	break;
	128	case 32:
	129	(s32 )place = sval;
3fd00beb AB	130	switch (op) {
	131	case RELOC_OP_ABS:
	132	if (sval < 0 \|\| sval > U32_MAX)
	133	return -ERANGE;
	134	break;
	135	case RELOC_OP_PREL:
	136	if (sval < S32_MIN \|\| sval > S32_MAX)
	137	return -ERANGE;
	138	break;
	139	default:
	140	pr_err("Invalid 32-bit data relocation (%d)\n", op);
	141	return 0;
	142	}
257cb251 WD	143	break;
	144	case 64:
	145	(s64 )place = sval;
	146	break;
	147	default:
	148	pr_err("Invalid length (%d) for data relocation\n", len);
	149	return 0;
	150	}
257cb251 WD	151	return 0;
	152	}
	153
b24a5575 AB	154	enum aarch64_insn_movw_imm_type {
	155	AARCH64_INSN_IMM_MOVNZ,
	156	AARCH64_INSN_IMM_MOVKZ,
	157	};
	158
02129ae5	159	static int reloc_insn_movw(enum aarch64_reloc_op op, __le32 *place, u64 val,
b24a5575	160	int lsb, enum aarch64_insn_movw_imm_type imm_type)
257cb251	161	{
b24a5575	162	u64 imm;
c84fced8	163	s64 sval;
02129ae5	164	u32 insn = le32_to_cpu(*place);
257cb251	165
c84fced8	166	sval = do_reloc(op, place, val);
b24a5575	167	imm = sval >> lsb;
122e2fa0	168
c84fced8	169	if (imm_type == AARCH64_INSN_IMM_MOVNZ) {
257cb251 WD	170	/*
	171	* For signed MOVW relocations, we have to manipulate the
	172	* instruction encoding depending on whether or not the
	173	* immediate is less than zero.
	174	*/
	175	insn &= ~(3 << 29);
b24a5575	176	if (sval >= 0) {
257cb251 WD	177	/* >=0: Set the instruction to MOVZ (opcode 10b). */
	178	insn \|= 2 << 29;
	179	} else {
	180	/*
	181	* <0: Set the instruction to MOVN (opcode 00b).
	182	* Since we've masked the opcode already, we
	183	* don't need to do anything other than
	184	* inverting the new immediate field.
	185	*/
	186	imm = ~imm;
	187	}
257cb251 WD	188	}
257cb251 WD	189
257cb251	190	/* Update the instruction with the new encoding. */
b24a5575	191	insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm);
02129ae5	192	*place = cpu_to_le32(insn);
257cb251	193
b24a5575	194	if (imm > U16_MAX)
257cb251 WD	195	return -ERANGE;
	196
	197	return 0;
	198	}
	199
02129ae5	200	static int reloc_insn_imm(enum aarch64_reloc_op op, __le32 *place, u64 val,
c84fced8	201	int lsb, int len, enum aarch64_insn_imm_type imm_type)
257cb251 WD	202	{
	203	u64 imm, imm_mask;
	204	s64 sval;
02129ae5	205	u32 insn = le32_to_cpu(*place);
257cb251 WD	206
	207	/* Calculate the relocation value. */
	208	sval = do_reloc(op, place, val);
	209	sval >>= lsb;
	210
	211	/* Extract the value bits and shift them to bit 0. */
	212	imm_mask = (BIT(lsb + len) - 1) >> lsb;
	213	imm = sval & imm_mask;
	214
	215	/* Update the instruction's immediate field. */
c84fced8	216	insn = aarch64_insn_encode_immediate(imm_type, insn, imm);
02129ae5	217	*place = cpu_to_le32(insn);
257cb251 WD	218
	219	/*
	220	* Extract the upper value bits (including the sign bit) and
	221	* shift them to bit 0.
	222	*/
	223	sval = (s64)(sval & ~(imm_mask >> 1)) >> (len - 1);
	224
	225	/*
	226	* Overflow has occurred if the upper bits are not all equal to
	227	* the sign bit of the value.
	228	*/
	229	if ((u64)(sval + 1) >= 2)
	230	return -ERANGE;
	231
	232	return 0;
	233	}
	234
c8ebf64e JY	235	static int reloc_insn_adrp(struct module mod, Elf64_Shdr sechdrs,
c8ebf64e JY	236	__le32 *place, u64 val)
a257e025 AB	237	{
	238	u32 insn;
	239
bdb85cd1	240	if (!is_forbidden_offset_for_adrp(place))
a257e025 AB	241	return reloc_insn_imm(RELOC_OP_PAGE, place, val, 12, 21,
	242	AARCH64_INSN_IMM_ADR);
	243
	244	/* patch ADRP to ADR if it is in range */
	245	if (!reloc_insn_imm(RELOC_OP_PREL, place, val & ~0xfff, 0, 21,
	246	AARCH64_INSN_IMM_ADR)) {
	247	insn = le32_to_cpu(*place);
	248	insn &= ~BIT(31);
	249	} else {
	250	/* out of range for ADR -> emit a veneer */
c8ebf64e	251	val = module_emit_veneer_for_adrp(mod, sechdrs, place, val & ~0xfff);
a257e025 AB	252	if (!val)
	253	return -ENOEXEC;
	254	insn = aarch64_insn_gen_branch_imm((u64)place, val,
	255	AARCH64_INSN_BRANCH_NOLINK);
	256	}
	257
	258	*place = cpu_to_le32(insn);
	259	return 0;
	260	}
	261
257cb251 WD	262	int apply_relocate_add(Elf64_Shdr *sechdrs,
	263	const char *strtab,
	264	unsigned int symindex,
	265	unsigned int relsec,
	266	struct module *me)
	267	{
	268	unsigned int i;
	269	int ovf;
	270	bool overflow_check;
	271	Elf64_Sym *sym;
	272	void *loc;
	273	u64 val;
	274	Elf64_Rela rel = (void )sechdrs[relsec].sh_addr;
	275
	276	for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
	277	/* loc corresponds to P in the AArch64 ELF document. */
	278	loc = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
	279	+ rel[i].r_offset;
	280
	281	/* sym is the ELF symbol we're referring to. */
	282	sym = (Elf64_Sym *)sechdrs[symindex].sh_addr
	283	+ ELF64_R_SYM(rel[i].r_info);
	284
	285	/* val corresponds to (S + A) in the AArch64 ELF document. */
	286	val = sym->st_value + rel[i].r_addend;
	287
	288	/* Check for overflow by default. */
	289	overflow_check = true;
	290
	291	/* Perform the static relocation. */
	292	switch (ELF64_R_TYPE(rel[i].r_info)) {
	293	/* Null relocations. */
	294	case R_ARM_NONE:
	295	case R_AARCH64_NONE:
	296	ovf = 0;
	297	break;
	298
	299	/* Data relocations. */
	300	case R_AARCH64_ABS64:
	301	overflow_check = false;
	302	ovf = reloc_data(RELOC_OP_ABS, loc, val, 64);
	303	break;
	304	case R_AARCH64_ABS32:
	305	ovf = reloc_data(RELOC_OP_ABS, loc, val, 32);
	306	break;
	307	case R_AARCH64_ABS16:
	308	ovf = reloc_data(RELOC_OP_ABS, loc, val, 16);
	309	break;
	310	case R_AARCH64_PREL64:
	311	overflow_check = false;
	312	ovf = reloc_data(RELOC_OP_PREL, loc, val, 64);
	313	break;
	314	case R_AARCH64_PREL32:
	315	ovf = reloc_data(RELOC_OP_PREL, loc, val, 32);
	316	break;
	317	case R_AARCH64_PREL16:
	318	ovf = reloc_data(RELOC_OP_PREL, loc, val, 16);
	319	break;
	320
	321	/* MOVW instruction relocations. */
	322	case R_AARCH64_MOVW_UABS_G0_NC:
	323	overflow_check = false;
	324	case R_AARCH64_MOVW_UABS_G0:
	325	ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
b24a5575	326	AARCH64_INSN_IMM_MOVKZ);
257cb251 WD	327	break;
	328	case R_AARCH64_MOVW_UABS_G1_NC:
	329	overflow_check = false;
	330	case R_AARCH64_MOVW_UABS_G1:
	331	ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
b24a5575	332	AARCH64_INSN_IMM_MOVKZ);
257cb251 WD	333	break;
	334	case R_AARCH64_MOVW_UABS_G2_NC:
	335	overflow_check = false;
	336	case R_AARCH64_MOVW_UABS_G2:
	337	ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
b24a5575	338	AARCH64_INSN_IMM_MOVKZ);
257cb251 WD	339	break;
	340	case R_AARCH64_MOVW_UABS_G3:
	341	/* We're using the top bits so we can't overflow. */
	342	overflow_check = false;
	343	ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 48,
b24a5575	344	AARCH64_INSN_IMM_MOVKZ);
257cb251 WD	345	break;
	346	case R_AARCH64_MOVW_SABS_G0:
	347	ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
c84fced8	348	AARCH64_INSN_IMM_MOVNZ);
257cb251 WD	349	break;
	350	case R_AARCH64_MOVW_SABS_G1:
	351	ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
c84fced8	352	AARCH64_INSN_IMM_MOVNZ);
257cb251 WD	353	break;
	354	case R_AARCH64_MOVW_SABS_G2:
	355	ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
c84fced8	356	AARCH64_INSN_IMM_MOVNZ);
257cb251 WD	357	break;
	358	case R_AARCH64_MOVW_PREL_G0_NC:
	359	overflow_check = false;
	360	ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
b24a5575	361	AARCH64_INSN_IMM_MOVKZ);
257cb251 WD	362	break;
	363	case R_AARCH64_MOVW_PREL_G0:
	364	ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
c84fced8	365	AARCH64_INSN_IMM_MOVNZ);
257cb251 WD	366	break;
	367	case R_AARCH64_MOVW_PREL_G1_NC:
	368	overflow_check = false;
	369	ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
b24a5575	370	AARCH64_INSN_IMM_MOVKZ);
257cb251 WD	371	break;
	372	case R_AARCH64_MOVW_PREL_G1:
	373	ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
c84fced8	374	AARCH64_INSN_IMM_MOVNZ);
257cb251 WD	375	break;
	376	case R_AARCH64_MOVW_PREL_G2_NC:
	377	overflow_check = false;
	378	ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
b24a5575	379	AARCH64_INSN_IMM_MOVKZ);
257cb251 WD	380	break;
	381	case R_AARCH64_MOVW_PREL_G2:
	382	ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
c84fced8	383	AARCH64_INSN_IMM_MOVNZ);
257cb251 WD	384	break;
	385	case R_AARCH64_MOVW_PREL_G3:
	386	/* We're using the top bits so we can't overflow. */
	387	overflow_check = false;
	388	ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 48,
c84fced8	389	AARCH64_INSN_IMM_MOVNZ);
257cb251 WD	390	break;
	391
	392	/* Immediate instruction relocations. */
	393	case R_AARCH64_LD_PREL_LO19:
	394	ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
c84fced8	395	AARCH64_INSN_IMM_19);
257cb251 WD	396	break;
	397	case R_AARCH64_ADR_PREL_LO21:
	398	ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 0, 21,
c84fced8	399	AARCH64_INSN_IMM_ADR);
257cb251 WD	400	break;
	401	case R_AARCH64_ADR_PREL_PG_HI21_NC:
	402	overflow_check = false;
	403	case R_AARCH64_ADR_PREL_PG_HI21:
c8ebf64e	404	ovf = reloc_insn_adrp(me, sechdrs, loc, val);
a257e025 AB	405	if (ovf && ovf != -ERANGE)
a257e025 AB	406	return ovf;
257cb251 WD	407	break;
	408	case R_AARCH64_ADD_ABS_LO12_NC:
	409	case R_AARCH64_LDST8_ABS_LO12_NC:
	410	overflow_check = false;
	411	ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 0, 12,
c84fced8	412	AARCH64_INSN_IMM_12);
257cb251 WD	413	break;
	414	case R_AARCH64_LDST16_ABS_LO12_NC:
	415	overflow_check = false;
	416	ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 1, 11,
c84fced8	417	AARCH64_INSN_IMM_12);
257cb251 WD	418	break;
	419	case R_AARCH64_LDST32_ABS_LO12_NC:
	420	overflow_check = false;
	421	ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 2, 10,
c84fced8	422	AARCH64_INSN_IMM_12);
257cb251 WD	423	break;
	424	case R_AARCH64_LDST64_ABS_LO12_NC:
	425	overflow_check = false;
	426	ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 3, 9,
c84fced8	427	AARCH64_INSN_IMM_12);
257cb251 WD	428	break;
	429	case R_AARCH64_LDST128_ABS_LO12_NC:
	430	overflow_check = false;
	431	ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 4, 8,
c84fced8	432	AARCH64_INSN_IMM_12);
257cb251 WD	433	break;
	434	case R_AARCH64_TSTBR14:
	435	ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 14,
c84fced8	436	AARCH64_INSN_IMM_14);
257cb251 WD	437	break;
	438	case R_AARCH64_CONDBR19:
	439	ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
c84fced8	440	AARCH64_INSN_IMM_19);
257cb251 WD	441	break;
	442	case R_AARCH64_JUMP26:
	443	case R_AARCH64_CALL26:
	444	ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 26,
c84fced8	445	AARCH64_INSN_IMM_26);
fd045f6c AB	446
	447	if (IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) &&
	448	ovf == -ERANGE) {
c8ebf64e	449	val = module_emit_plt_entry(me, sechdrs, loc, &rel[i], sym);
5e8307b9 AB	450	if (!val)
5e8307b9 AB	451	return -ENOEXEC;
fd045f6c AB	452	ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2,
	453	26, AARCH64_INSN_IMM_26);
	454	}
257cb251 WD	455	break;
	456
	457	default:
	458	pr_err("module %s: unsupported RELA relocation: %llu\n",
	459	me->name, ELF64_R_TYPE(rel[i].r_info));
	460	return -ENOEXEC;
	461	}
	462
	463	if (overflow_check && ovf == -ERANGE)
	464	goto overflow;
	465
	466	}
	467
	468	return 0;
	469
	470	overflow:
	471	pr_err("module %s: overflow in relocation type %d val %Lx\n",
	472	me->name, (int)ELF64_R_TYPE(rel[i].r_info), val);
	473	return -ENOEXEC;
	474	}
932ded4b AP	475
	476	int module_finalize(const Elf_Ehdr *hdr,
	477	const Elf_Shdr *sechdrs,
	478	struct module *me)
	479	{
	480	const Elf_Shdr s, se;
	481	const char secstrs = (void )hdr + sechdrs[hdr->e_shstrndx].sh_offset;
	482
	483	for (s = sechdrs, se = sechdrs + hdr->e_shnum; s < se; s++) {
42938868 WD	484	if (strcmp(".altinstructions", secstrs + s->sh_name) == 0)
42938868 WD	485	apply_alternatives_module((void *)s->sh_addr, s->sh_size);
e71a4e1b AB	486	#ifdef CONFIG_ARM64_MODULE_PLTS
	487	if (IS_ENABLED(CONFIG_DYNAMIC_FTRACE) &&
	488	!strcmp(".text.ftrace_trampoline", secstrs + s->sh_name))
	489	me->arch.ftrace_trampoline = (void *)s->sh_addr;
	490	#endif
932ded4b AP	491	}
	492
	493	return 0;
	494	}