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257cb251 WD |
1 | /* |
2 | * AArch64 loadable module support. | |
3 | * | |
4 | * Copyright (C) 2012 ARM Limited | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
18 | * Author: Will Deacon <will.deacon@arm.com> | |
19 | */ | |
20 | ||
21 | #include <linux/bitops.h> | |
22 | #include <linux/elf.h> | |
23 | #include <linux/gfp.h> | |
39d114dd | 24 | #include <linux/kasan.h> |
257cb251 WD |
25 | #include <linux/kernel.h> |
26 | #include <linux/mm.h> | |
27 | #include <linux/moduleloader.h> | |
28 | #include <linux/vmalloc.h> | |
2c2b282d | 29 | #include <asm/alternative.h> |
c84fced8 | 30 | #include <asm/insn.h> |
932ded4b | 31 | #include <asm/sections.h> |
c84fced8 | 32 | |
257cb251 WD |
33 | void *module_alloc(unsigned long size) |
34 | { | |
0c2cf6d9 | 35 | gfp_t gfp_mask = GFP_KERNEL; |
39d114dd AR |
36 | void *p; |
37 | ||
0c2cf6d9 FF |
38 | /* Silence the initial allocation */ |
39 | if (IS_ENABLED(CONFIG_ARM64_MODULE_PLTS)) | |
40 | gfp_mask |= __GFP_NOWARN; | |
41 | ||
f80fb3a3 AB |
42 | p = __vmalloc_node_range(size, MODULE_ALIGN, module_alloc_base, |
43 | module_alloc_base + MODULES_VSIZE, | |
0c2cf6d9 | 44 | gfp_mask, PAGE_KERNEL_EXEC, 0, |
39d114dd AR |
45 | NUMA_NO_NODE, __builtin_return_address(0)); |
46 | ||
fd045f6c AB |
47 | if (!p && IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) && |
48 | !IS_ENABLED(CONFIG_KASAN)) | |
49 | /* | |
50 | * KASAN can only deal with module allocations being served | |
51 | * from the reserved module region, since the remainder of | |
52 | * the vmalloc region is already backed by zero shadow pages, | |
53 | * and punching holes into it is non-trivial. Since the module | |
54 | * region is not randomized when KASAN is enabled, it is even | |
55 | * less likely that the module region gets exhausted, so we | |
56 | * can simply omit this fallback in that case. | |
57 | */ | |
f2b9ba87 AB |
58 | p = __vmalloc_node_range(size, MODULE_ALIGN, module_alloc_base, |
59 | module_alloc_base + SZ_4G, GFP_KERNEL, | |
60 | PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE, | |
61 | __builtin_return_address(0)); | |
fd045f6c | 62 | |
39d114dd AR |
63 | if (p && (kasan_module_alloc(p, size) < 0)) { |
64 | vfree(p); | |
65 | return NULL; | |
66 | } | |
67 | ||
68 | return p; | |
257cb251 WD |
69 | } |
70 | ||
71 | enum aarch64_reloc_op { | |
72 | RELOC_OP_NONE, | |
73 | RELOC_OP_ABS, | |
74 | RELOC_OP_PREL, | |
75 | RELOC_OP_PAGE, | |
76 | }; | |
77 | ||
02129ae5 | 78 | static u64 do_reloc(enum aarch64_reloc_op reloc_op, __le32 *place, u64 val) |
257cb251 WD |
79 | { |
80 | switch (reloc_op) { | |
81 | case RELOC_OP_ABS: | |
82 | return val; | |
83 | case RELOC_OP_PREL: | |
84 | return val - (u64)place; | |
85 | case RELOC_OP_PAGE: | |
86 | return (val & ~0xfff) - ((u64)place & ~0xfff); | |
87 | case RELOC_OP_NONE: | |
88 | return 0; | |
89 | } | |
90 | ||
91 | pr_err("do_reloc: unknown relocation operation %d\n", reloc_op); | |
92 | return 0; | |
93 | } | |
94 | ||
95 | static int reloc_data(enum aarch64_reloc_op op, void *place, u64 val, int len) | |
96 | { | |
257cb251 WD |
97 | s64 sval = do_reloc(op, place, val); |
98 | ||
99 | switch (len) { | |
100 | case 16: | |
101 | *(s16 *)place = sval; | |
f9308969 AB |
102 | if (sval < S16_MIN || sval > U16_MAX) |
103 | return -ERANGE; | |
257cb251 WD |
104 | break; |
105 | case 32: | |
106 | *(s32 *)place = sval; | |
f9308969 AB |
107 | if (sval < S32_MIN || sval > U32_MAX) |
108 | return -ERANGE; | |
257cb251 WD |
109 | break; |
110 | case 64: | |
111 | *(s64 *)place = sval; | |
112 | break; | |
113 | default: | |
114 | pr_err("Invalid length (%d) for data relocation\n", len); | |
115 | return 0; | |
116 | } | |
257cb251 WD |
117 | return 0; |
118 | } | |
119 | ||
b24a5575 AB |
120 | enum aarch64_insn_movw_imm_type { |
121 | AARCH64_INSN_IMM_MOVNZ, | |
122 | AARCH64_INSN_IMM_MOVKZ, | |
123 | }; | |
124 | ||
02129ae5 | 125 | static int reloc_insn_movw(enum aarch64_reloc_op op, __le32 *place, u64 val, |
b24a5575 | 126 | int lsb, enum aarch64_insn_movw_imm_type imm_type) |
257cb251 | 127 | { |
b24a5575 | 128 | u64 imm; |
c84fced8 | 129 | s64 sval; |
02129ae5 | 130 | u32 insn = le32_to_cpu(*place); |
257cb251 | 131 | |
c84fced8 | 132 | sval = do_reloc(op, place, val); |
b24a5575 | 133 | imm = sval >> lsb; |
122e2fa0 | 134 | |
c84fced8 | 135 | if (imm_type == AARCH64_INSN_IMM_MOVNZ) { |
257cb251 WD |
136 | /* |
137 | * For signed MOVW relocations, we have to manipulate the | |
138 | * instruction encoding depending on whether or not the | |
139 | * immediate is less than zero. | |
140 | */ | |
141 | insn &= ~(3 << 29); | |
b24a5575 | 142 | if (sval >= 0) { |
257cb251 WD |
143 | /* >=0: Set the instruction to MOVZ (opcode 10b). */ |
144 | insn |= 2 << 29; | |
145 | } else { | |
146 | /* | |
147 | * <0: Set the instruction to MOVN (opcode 00b). | |
148 | * Since we've masked the opcode already, we | |
149 | * don't need to do anything other than | |
150 | * inverting the new immediate field. | |
151 | */ | |
152 | imm = ~imm; | |
153 | } | |
257cb251 WD |
154 | } |
155 | ||
257cb251 | 156 | /* Update the instruction with the new encoding. */ |
b24a5575 | 157 | insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm); |
02129ae5 | 158 | *place = cpu_to_le32(insn); |
257cb251 | 159 | |
b24a5575 | 160 | if (imm > U16_MAX) |
257cb251 WD |
161 | return -ERANGE; |
162 | ||
163 | return 0; | |
164 | } | |
165 | ||
02129ae5 | 166 | static int reloc_insn_imm(enum aarch64_reloc_op op, __le32 *place, u64 val, |
c84fced8 | 167 | int lsb, int len, enum aarch64_insn_imm_type imm_type) |
257cb251 WD |
168 | { |
169 | u64 imm, imm_mask; | |
170 | s64 sval; | |
02129ae5 | 171 | u32 insn = le32_to_cpu(*place); |
257cb251 WD |
172 | |
173 | /* Calculate the relocation value. */ | |
174 | sval = do_reloc(op, place, val); | |
175 | sval >>= lsb; | |
176 | ||
177 | /* Extract the value bits and shift them to bit 0. */ | |
178 | imm_mask = (BIT(lsb + len) - 1) >> lsb; | |
179 | imm = sval & imm_mask; | |
180 | ||
181 | /* Update the instruction's immediate field. */ | |
c84fced8 | 182 | insn = aarch64_insn_encode_immediate(imm_type, insn, imm); |
02129ae5 | 183 | *place = cpu_to_le32(insn); |
257cb251 WD |
184 | |
185 | /* | |
186 | * Extract the upper value bits (including the sign bit) and | |
187 | * shift them to bit 0. | |
188 | */ | |
189 | sval = (s64)(sval & ~(imm_mask >> 1)) >> (len - 1); | |
190 | ||
191 | /* | |
192 | * Overflow has occurred if the upper bits are not all equal to | |
193 | * the sign bit of the value. | |
194 | */ | |
195 | if ((u64)(sval + 1) >= 2) | |
196 | return -ERANGE; | |
197 | ||
198 | return 0; | |
199 | } | |
200 | ||
201 | int apply_relocate_add(Elf64_Shdr *sechdrs, | |
202 | const char *strtab, | |
203 | unsigned int symindex, | |
204 | unsigned int relsec, | |
205 | struct module *me) | |
206 | { | |
207 | unsigned int i; | |
208 | int ovf; | |
209 | bool overflow_check; | |
210 | Elf64_Sym *sym; | |
211 | void *loc; | |
212 | u64 val; | |
213 | Elf64_Rela *rel = (void *)sechdrs[relsec].sh_addr; | |
214 | ||
215 | for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { | |
216 | /* loc corresponds to P in the AArch64 ELF document. */ | |
217 | loc = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr | |
218 | + rel[i].r_offset; | |
219 | ||
220 | /* sym is the ELF symbol we're referring to. */ | |
221 | sym = (Elf64_Sym *)sechdrs[symindex].sh_addr | |
222 | + ELF64_R_SYM(rel[i].r_info); | |
223 | ||
224 | /* val corresponds to (S + A) in the AArch64 ELF document. */ | |
225 | val = sym->st_value + rel[i].r_addend; | |
226 | ||
227 | /* Check for overflow by default. */ | |
228 | overflow_check = true; | |
229 | ||
230 | /* Perform the static relocation. */ | |
231 | switch (ELF64_R_TYPE(rel[i].r_info)) { | |
232 | /* Null relocations. */ | |
233 | case R_ARM_NONE: | |
234 | case R_AARCH64_NONE: | |
235 | ovf = 0; | |
236 | break; | |
237 | ||
238 | /* Data relocations. */ | |
239 | case R_AARCH64_ABS64: | |
240 | overflow_check = false; | |
241 | ovf = reloc_data(RELOC_OP_ABS, loc, val, 64); | |
242 | break; | |
243 | case R_AARCH64_ABS32: | |
244 | ovf = reloc_data(RELOC_OP_ABS, loc, val, 32); | |
245 | break; | |
246 | case R_AARCH64_ABS16: | |
247 | ovf = reloc_data(RELOC_OP_ABS, loc, val, 16); | |
248 | break; | |
249 | case R_AARCH64_PREL64: | |
250 | overflow_check = false; | |
251 | ovf = reloc_data(RELOC_OP_PREL, loc, val, 64); | |
252 | break; | |
253 | case R_AARCH64_PREL32: | |
254 | ovf = reloc_data(RELOC_OP_PREL, loc, val, 32); | |
255 | break; | |
256 | case R_AARCH64_PREL16: | |
257 | ovf = reloc_data(RELOC_OP_PREL, loc, val, 16); | |
258 | break; | |
259 | ||
260 | /* MOVW instruction relocations. */ | |
261 | case R_AARCH64_MOVW_UABS_G0_NC: | |
262 | overflow_check = false; | |
263 | case R_AARCH64_MOVW_UABS_G0: | |
264 | ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0, | |
b24a5575 | 265 | AARCH64_INSN_IMM_MOVKZ); |
257cb251 WD |
266 | break; |
267 | case R_AARCH64_MOVW_UABS_G1_NC: | |
268 | overflow_check = false; | |
269 | case R_AARCH64_MOVW_UABS_G1: | |
270 | ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16, | |
b24a5575 | 271 | AARCH64_INSN_IMM_MOVKZ); |
257cb251 WD |
272 | break; |
273 | case R_AARCH64_MOVW_UABS_G2_NC: | |
274 | overflow_check = false; | |
275 | case R_AARCH64_MOVW_UABS_G2: | |
276 | ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32, | |
b24a5575 | 277 | AARCH64_INSN_IMM_MOVKZ); |
257cb251 WD |
278 | break; |
279 | case R_AARCH64_MOVW_UABS_G3: | |
280 | /* We're using the top bits so we can't overflow. */ | |
281 | overflow_check = false; | |
282 | ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 48, | |
b24a5575 | 283 | AARCH64_INSN_IMM_MOVKZ); |
257cb251 WD |
284 | break; |
285 | case R_AARCH64_MOVW_SABS_G0: | |
286 | ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0, | |
c84fced8 | 287 | AARCH64_INSN_IMM_MOVNZ); |
257cb251 WD |
288 | break; |
289 | case R_AARCH64_MOVW_SABS_G1: | |
290 | ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16, | |
c84fced8 | 291 | AARCH64_INSN_IMM_MOVNZ); |
257cb251 WD |
292 | break; |
293 | case R_AARCH64_MOVW_SABS_G2: | |
294 | ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32, | |
c84fced8 | 295 | AARCH64_INSN_IMM_MOVNZ); |
257cb251 WD |
296 | break; |
297 | case R_AARCH64_MOVW_PREL_G0_NC: | |
298 | overflow_check = false; | |
299 | ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0, | |
b24a5575 | 300 | AARCH64_INSN_IMM_MOVKZ); |
257cb251 WD |
301 | break; |
302 | case R_AARCH64_MOVW_PREL_G0: | |
303 | ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0, | |
c84fced8 | 304 | AARCH64_INSN_IMM_MOVNZ); |
257cb251 WD |
305 | break; |
306 | case R_AARCH64_MOVW_PREL_G1_NC: | |
307 | overflow_check = false; | |
308 | ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16, | |
b24a5575 | 309 | AARCH64_INSN_IMM_MOVKZ); |
257cb251 WD |
310 | break; |
311 | case R_AARCH64_MOVW_PREL_G1: | |
312 | ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16, | |
c84fced8 | 313 | AARCH64_INSN_IMM_MOVNZ); |
257cb251 WD |
314 | break; |
315 | case R_AARCH64_MOVW_PREL_G2_NC: | |
316 | overflow_check = false; | |
317 | ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32, | |
b24a5575 | 318 | AARCH64_INSN_IMM_MOVKZ); |
257cb251 WD |
319 | break; |
320 | case R_AARCH64_MOVW_PREL_G2: | |
321 | ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32, | |
c84fced8 | 322 | AARCH64_INSN_IMM_MOVNZ); |
257cb251 WD |
323 | break; |
324 | case R_AARCH64_MOVW_PREL_G3: | |
325 | /* We're using the top bits so we can't overflow. */ | |
326 | overflow_check = false; | |
327 | ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 48, | |
c84fced8 | 328 | AARCH64_INSN_IMM_MOVNZ); |
257cb251 WD |
329 | break; |
330 | ||
331 | /* Immediate instruction relocations. */ | |
332 | case R_AARCH64_LD_PREL_LO19: | |
333 | ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19, | |
c84fced8 | 334 | AARCH64_INSN_IMM_19); |
257cb251 WD |
335 | break; |
336 | case R_AARCH64_ADR_PREL_LO21: | |
337 | ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 0, 21, | |
c84fced8 | 338 | AARCH64_INSN_IMM_ADR); |
257cb251 | 339 | break; |
df057cc7 | 340 | #ifndef CONFIG_ARM64_ERRATUM_843419 |
257cb251 WD |
341 | case R_AARCH64_ADR_PREL_PG_HI21_NC: |
342 | overflow_check = false; | |
343 | case R_AARCH64_ADR_PREL_PG_HI21: | |
344 | ovf = reloc_insn_imm(RELOC_OP_PAGE, loc, val, 12, 21, | |
c84fced8 | 345 | AARCH64_INSN_IMM_ADR); |
257cb251 | 346 | break; |
df057cc7 | 347 | #endif |
257cb251 WD |
348 | case R_AARCH64_ADD_ABS_LO12_NC: |
349 | case R_AARCH64_LDST8_ABS_LO12_NC: | |
350 | overflow_check = false; | |
351 | ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 0, 12, | |
c84fced8 | 352 | AARCH64_INSN_IMM_12); |
257cb251 WD |
353 | break; |
354 | case R_AARCH64_LDST16_ABS_LO12_NC: | |
355 | overflow_check = false; | |
356 | ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 1, 11, | |
c84fced8 | 357 | AARCH64_INSN_IMM_12); |
257cb251 WD |
358 | break; |
359 | case R_AARCH64_LDST32_ABS_LO12_NC: | |
360 | overflow_check = false; | |
361 | ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 2, 10, | |
c84fced8 | 362 | AARCH64_INSN_IMM_12); |
257cb251 WD |
363 | break; |
364 | case R_AARCH64_LDST64_ABS_LO12_NC: | |
365 | overflow_check = false; | |
366 | ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 3, 9, | |
c84fced8 | 367 | AARCH64_INSN_IMM_12); |
257cb251 WD |
368 | break; |
369 | case R_AARCH64_LDST128_ABS_LO12_NC: | |
370 | overflow_check = false; | |
371 | ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 4, 8, | |
c84fced8 | 372 | AARCH64_INSN_IMM_12); |
257cb251 WD |
373 | break; |
374 | case R_AARCH64_TSTBR14: | |
375 | ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 14, | |
c84fced8 | 376 | AARCH64_INSN_IMM_14); |
257cb251 WD |
377 | break; |
378 | case R_AARCH64_CONDBR19: | |
379 | ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19, | |
c84fced8 | 380 | AARCH64_INSN_IMM_19); |
257cb251 WD |
381 | break; |
382 | case R_AARCH64_JUMP26: | |
383 | case R_AARCH64_CALL26: | |
384 | ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 26, | |
c84fced8 | 385 | AARCH64_INSN_IMM_26); |
fd045f6c AB |
386 | |
387 | if (IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) && | |
388 | ovf == -ERANGE) { | |
24af6c4e | 389 | val = module_emit_plt_entry(me, loc, &rel[i], sym); |
5e8307b9 AB |
390 | if (!val) |
391 | return -ENOEXEC; | |
fd045f6c AB |
392 | ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, |
393 | 26, AARCH64_INSN_IMM_26); | |
394 | } | |
257cb251 WD |
395 | break; |
396 | ||
397 | default: | |
398 | pr_err("module %s: unsupported RELA relocation: %llu\n", | |
399 | me->name, ELF64_R_TYPE(rel[i].r_info)); | |
400 | return -ENOEXEC; | |
401 | } | |
402 | ||
403 | if (overflow_check && ovf == -ERANGE) | |
404 | goto overflow; | |
405 | ||
406 | } | |
407 | ||
408 | return 0; | |
409 | ||
410 | overflow: | |
411 | pr_err("module %s: overflow in relocation type %d val %Lx\n", | |
412 | me->name, (int)ELF64_R_TYPE(rel[i].r_info), val); | |
413 | return -ENOEXEC; | |
414 | } | |
932ded4b AP |
415 | |
416 | int module_finalize(const Elf_Ehdr *hdr, | |
417 | const Elf_Shdr *sechdrs, | |
418 | struct module *me) | |
419 | { | |
420 | const Elf_Shdr *s, *se; | |
421 | const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset; | |
422 | ||
423 | for (s = sechdrs, se = sechdrs + hdr->e_shnum; s < se; s++) { | |
424 | if (strcmp(".altinstructions", secstrs + s->sh_name) == 0) { | |
425 | apply_alternatives((void *)s->sh_addr, s->sh_size); | |
932ded4b | 426 | } |
e71a4e1b AB |
427 | #ifdef CONFIG_ARM64_MODULE_PLTS |
428 | if (IS_ENABLED(CONFIG_DYNAMIC_FTRACE) && | |
429 | !strcmp(".text.ftrace_trampoline", secstrs + s->sh_name)) | |
430 | me->arch.ftrace_trampoline = (void *)s->sh_addr; | |
431 | #endif | |
932ded4b AP |
432 | } |
433 | ||
434 | return 0; | |
435 | } |