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arm64: KVM: pmu: Fix AArch32 cycle counter access
[mirror_ubuntu-bionic-kernel.git] / arch / arm64 / kernel / perf_event.c
CommitLineData
03089688
WD		 1/*
2 * PMU support
3 *
4 * Copyright (C) 2012 ARM Limited
5 * Author: Will Deacon <will.deacon@arm.com>
6 *
7 * This code is based heavily on the ARMv7 perf event code.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
03089688 21
03089688 22#include <asm/irq_regs.h>
b8cfadfc 23#include <asm/perf_event.h>
bf2d4782 24#include <asm/sysreg.h>
d98ecdac 25#include <asm/virt.h>
03089688 26
dbee3a74 27#include <linux/acpi.h>
6475b2d8
MR		 28#include <linux/of.h>
29#include <linux/perf/arm_pmu.h>
30#include <linux/platform_device.h>
03089688
WD		 31
32/*
33 * ARMv8 PMUv3 Performance Events handling code.
34 * Common event types.
35 */
03089688 36
90381cba 37/* Required events. */
03598fdb
AK		 38#define ARMV8_PMUV3_PERFCTR_SW_INCR 0x00
39#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL 0x03
40#define ARMV8_PMUV3_PERFCTR_L1D_CACHE 0x04
41#define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED 0x10
42#define ARMV8_PMUV3_PERFCTR_CPU_CYCLES 0x11
43#define ARMV8_PMUV3_PERFCTR_BR_PRED 0x12
03089688 44
90381cba 45/* At least one of the following is required. */
03598fdb
AK		 46#define ARMV8_PMUV3_PERFCTR_INST_RETIRED 0x08
47#define ARMV8_PMUV3_PERFCTR_INST_SPEC 0x1B
03089688 48
90381cba 49/* Common architectural events. */
03598fdb
AK		 50#define ARMV8_PMUV3_PERFCTR_LD_RETIRED 0x06
51#define ARMV8_PMUV3_PERFCTR_ST_RETIRED 0x07
90381cba 52#define ARMV8_PMUV3_PERFCTR_EXC_TAKEN 0x09
03598fdb
AK		 53#define ARMV8_PMUV3_PERFCTR_EXC_RETURN 0x0A
54#define ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED 0x0B
55#define ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED 0x0C
56#define ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED 0x0D
57#define ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED 0x0E
58#define ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED 0x0F
59#define ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED 0x1C
9e9caa6a
DR		 60#define ARMV8_PMUV3_PERFCTR_CHAIN 0x1E
61#define ARMV8_PMUV3_PERFCTR_BR_RETIRED 0x21
90381cba
DR		 62
63/* Common microarchitectural events. */
03598fdb
AK		 64#define ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL 0x01
65#define ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL 0x02
66#define ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL 0x05
90381cba 67#define ARMV8_PMUV3_PERFCTR_MEM_ACCESS 0x13
03598fdb
AK		 68#define ARMV8_PMUV3_PERFCTR_L1I_CACHE 0x14
69#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB 0x15
70#define ARMV8_PMUV3_PERFCTR_L2D_CACHE 0x16
71#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL 0x17
72#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB 0x18
90381cba 73#define ARMV8_PMUV3_PERFCTR_BUS_ACCESS 0x19
03598fdb 74#define ARMV8_PMUV3_PERFCTR_MEMORY_ERROR 0x1A
90381cba 75#define ARMV8_PMUV3_PERFCTR_BUS_CYCLES 0x1D
9e9caa6a
DR		 76#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE 0x1F
77#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE 0x20
78#define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED 0x22
79#define ARMV8_PMUV3_PERFCTR_STALL_FRONTEND 0x23
80#define ARMV8_PMUV3_PERFCTR_STALL_BACKEND 0x24
81#define ARMV8_PMUV3_PERFCTR_L1D_TLB 0x25
82#define ARMV8_PMUV3_PERFCTR_L1I_TLB 0x26
83#define ARMV8_PMUV3_PERFCTR_L2I_CACHE 0x27
84#define ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL 0x28
85#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE 0x29
86#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL 0x2A
87#define ARMV8_PMUV3_PERFCTR_L3D_CACHE 0x2B
88#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB 0x2C
89#define ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL 0x2D
03598fdb 90#define ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL 0x2E
9e9caa6a 91#define ARMV8_PMUV3_PERFCTR_L2D_TLB 0x2F
03598fdb
AK		 92#define ARMV8_PMUV3_PERFCTR_L2I_TLB 0x30
93
94/* ARMv8 recommended implementation defined event types */
95#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD 0x40
96#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR 0x41
97#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD 0x42
98#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR 0x43
0893f745
AK		 99#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_INNER 0x44
100#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_OUTER 0x45
101#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_VICTIM 0x46
102#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_CLEAN 0x47
103#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_INVAL 0x48
104
03598fdb
AK		 105#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD 0x4C
106#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR 0x4D
107#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD 0x4E
108#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR 0x4F
0893f745
AK		 109#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_RD 0x50
110#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WR 0x51
111#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_RD 0x52
112#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_WR 0x53
113
114#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_VICTIM 0x56
115#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_CLEAN 0x57
116#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_INVAL 0x58
117
118#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_RD 0x5C
119#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_WR 0x5D
120#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_RD 0x5E
121#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_WR 0x5F
122
123#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD 0x60
124#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR 0x61
125#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_SHARED 0x62
126#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NOT_SHARED 0x63
127#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NORMAL 0x64
128#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_PERIPH 0x65
129
130#define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_RD 0x66
131#define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_WR 0x67
132#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LD_SPEC 0x68
133#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_ST_SPEC 0x69
134#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LDST_SPEC 0x6A
135
136#define ARMV8_IMPDEF_PERFCTR_LDREX_SPEC 0x6C
137#define ARMV8_IMPDEF_PERFCTR_STREX_PASS_SPEC 0x6D
138#define ARMV8_IMPDEF_PERFCTR_STREX_FAIL_SPEC 0x6E
139#define ARMV8_IMPDEF_PERFCTR_STREX_SPEC 0x6F
140#define ARMV8_IMPDEF_PERFCTR_LD_SPEC 0x70
141#define ARMV8_IMPDEF_PERFCTR_ST_SPEC 0x71
142#define ARMV8_IMPDEF_PERFCTR_LDST_SPEC 0x72
143#define ARMV8_IMPDEF_PERFCTR_DP_SPEC 0x73
144#define ARMV8_IMPDEF_PERFCTR_ASE_SPEC 0x74
145#define ARMV8_IMPDEF_PERFCTR_VFP_SPEC 0x75
146#define ARMV8_IMPDEF_PERFCTR_PC_WRITE_SPEC 0x76
147#define ARMV8_IMPDEF_PERFCTR_CRYPTO_SPEC 0x77
148#define ARMV8_IMPDEF_PERFCTR_BR_IMMED_SPEC 0x78
149#define ARMV8_IMPDEF_PERFCTR_BR_RETURN_SPEC 0x79
150#define ARMV8_IMPDEF_PERFCTR_BR_INDIRECT_SPEC 0x7A
151
152#define ARMV8_IMPDEF_PERFCTR_ISB_SPEC 0x7C
153#define ARMV8_IMPDEF_PERFCTR_DSB_SPEC 0x7D
154#define ARMV8_IMPDEF_PERFCTR_DMB_SPEC 0x7E
155
156#define ARMV8_IMPDEF_PERFCTR_EXC_UNDEF 0x81
157#define ARMV8_IMPDEF_PERFCTR_EXC_SVC 0x82
158#define ARMV8_IMPDEF_PERFCTR_EXC_PABORT 0x83
159#define ARMV8_IMPDEF_PERFCTR_EXC_DABORT 0x84
160
161#define ARMV8_IMPDEF_PERFCTR_EXC_IRQ 0x86
162#define ARMV8_IMPDEF_PERFCTR_EXC_FIQ 0x87
163#define ARMV8_IMPDEF_PERFCTR_EXC_SMC 0x88
164
165#define ARMV8_IMPDEF_PERFCTR_EXC_HVC 0x8A
166#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_PABORT 0x8B
167#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_DABORT 0x8C
168#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_OTHER 0x8D
169#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_IRQ 0x8E
170#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_FIQ 0x8F
171#define ARMV8_IMPDEF_PERFCTR_RC_LD_SPEC 0x90
172#define ARMV8_IMPDEF_PERFCTR_RC_ST_SPEC 0x91
173
174#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_RD 0xA0
175#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WR 0xA1
176#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_RD 0xA2
177#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_WR 0xA3
178
179#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_VICTIM 0xA6
180#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_CLEAN 0xA7
181#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_INVAL 0xA8
5f140cce 182
ac82d127 183/* ARMv8 Cortex-A53 specific event types. */
03598fdb 184#define ARMV8_A53_PERFCTR_PREF_LINEFILL 0xC2
ac82d127 185
d0aa2bff 186/* ARMv8 Cavium ThunderX specific event types. */
03598fdb
AK		 187#define ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST 0xE9
188#define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS 0xEA
189#define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS 0xEB
190#define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS 0xEC
191#define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS 0xED
62a4dda9 192
03089688 193/* PMUv3 HW events mapping. */
236b9b91
JL		 194
195/*
196 * ARMv8 Architectural defined events, not all of these may
197 * be supported on any given implementation. Undefined events will
198 * be disabled at run-time.
199 */
03089688 200static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
ae2fb7ec 201 PERF_MAP_ALL_UNSUPPORTED,
03598fdb
AK		 202 [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
203 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
204 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
205 [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
236b9b91 206 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
03598fdb 207 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
236b9b91
JL		 208 [PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
209 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
210 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
03089688
WD		 211};
212
ac82d127
MR		 213/* ARM Cortex-A53 HW events mapping. */
214static const unsigned armv8_a53_perf_map[PERF_COUNT_HW_MAX] = {
215 PERF_MAP_ALL_UNSUPPORTED,
03598fdb
AK		 216 [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
217 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
218 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
219 [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
220 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
221 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
ac82d127
MR		 222 [PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
223};
224
5d7ee877 225/* ARM Cortex-A57 and Cortex-A72 events mapping. */
62a4dda9
MR		 226static const unsigned armv8_a57_perf_map[PERF_COUNT_HW_MAX] = {
227 PERF_MAP_ALL_UNSUPPORTED,
03598fdb
AK		 228 [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
229 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
230 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
231 [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
232 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
62a4dda9
MR		 233 [PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
234};
235
d0aa2bff
JG		 236static const unsigned armv8_thunder_perf_map[PERF_COUNT_HW_MAX] = {
237 PERF_MAP_ALL_UNSUPPORTED,
03598fdb
AK		 238 [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
239 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
240 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
241 [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
242 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
243 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
d0aa2bff
JG		 244 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
245 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
246};
247
201a72b2
AK		 248/* Broadcom Vulcan events mapping */
249static const unsigned armv8_vulcan_perf_map[PERF_COUNT_HW_MAX] = {
250 PERF_MAP_ALL_UNSUPPORTED,
251 [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
252 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
253 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
254 [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
255 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_BR_RETIRED,
256 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
257 [PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
258 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
259 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
260};
261
03089688
WD		 262static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
263 [PERF_COUNT_HW_CACHE_OP_MAX]
264 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
ae2fb7ec
MR		 265 PERF_CACHE_MAP_ALL_UNSUPPORTED,
266
03598fdb
AK		 267 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
268 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
269 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
270 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
ae2fb7ec 271
236b9b91
JL		 272 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
273 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
274
275 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
276 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB,
277
278 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
279 [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB,
280
03598fdb
AK		 281 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
282 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
283 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
284 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
03089688
WD		 285};
286
ac82d127
MR		 287static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
288 [PERF_COUNT_HW_CACHE_OP_MAX]
289 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
290 PERF_CACHE_MAP_ALL_UNSUPPORTED,
291
03598fdb
AK		 292 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
293 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
294 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
295 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
296 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREF_LINEFILL,
ac82d127 297
03598fdb
AK		 298 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
299 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
ac82d127 300
03598fdb 301 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
ac82d127 302
03598fdb
AK		 303 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
304 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
305 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
306 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
ac82d127
MR		 307};
308
62a4dda9
MR		 309static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
310 [PERF_COUNT_HW_CACHE_OP_MAX]
311 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
312 PERF_CACHE_MAP_ALL_UNSUPPORTED,
313
03598fdb
AK		 314 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
315 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
316 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
317 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
62a4dda9 318
03598fdb
AK		 319 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
320 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
62a4dda9 321
03598fdb
AK		 322 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
323 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
62a4dda9 324
03598fdb 325 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
62a4dda9 326
03598fdb
AK		 327 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
328 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
329 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
330 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
62a4dda9
MR		 331};
332
d0aa2bff
JG		 333static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
334 [PERF_COUNT_HW_CACHE_OP_MAX]
335 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
336 PERF_CACHE_MAP_ALL_UNSUPPORTED,
337
03598fdb
AK		 338 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
339 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
340 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
341 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST,
342 [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS,
343 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS,
344
345 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
346 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
347 [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS,
348 [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS,
349
350 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
351 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
352 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
353 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
354
355 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
356
357 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
358 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
359 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
360 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
62a4dda9
MR		 361};
362
201a72b2
AK		 363static const unsigned armv8_vulcan_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
364 [PERF_COUNT_HW_CACHE_OP_MAX]
365 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
366 PERF_CACHE_MAP_ALL_UNSUPPORTED,
367
368 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
369 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
370 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
371 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
372
373 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
374 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
375
376 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
377 [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB,
378
379 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
380 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
381 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
382 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
383
384 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
385 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
386 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
387 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
388
389 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
390 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
391};
4b1a9e69
AK		 392
393static ssize_t
394armv8pmu_events_sysfs_show(struct device *dev,
395 struct device_attribute *attr, char *page)
396{
397 struct perf_pmu_events_attr *pmu_attr;
398
399 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
400
401 return sprintf(page, "event=0x%03llx\n", pmu_attr->id);
402}
403
9e9caa6a
DR		 404#define ARMV8_EVENT_ATTR_RESOLVE(m) #m
405#define ARMV8_EVENT_ATTR(name, config) \
4b1a9e69
AK		 406 PMU_EVENT_ATTR(name, armv8_event_attr_##name, \
407 config, armv8pmu_events_sysfs_show)
9e9caa6a 408
03598fdb
AK		 409ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_SW_INCR);
410ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL);
411ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL);
412ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL);
413ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1D_CACHE);
414ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL);
415ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_LD_RETIRED);
416ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_ST_RETIRED);
417ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INST_RETIRED);
9e9caa6a 418ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN);
03598fdb
AK		 419ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_RETURN);
420ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED);
421ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED);
422ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED);
423ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED);
424ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED);
425ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED);
426ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CPU_CYCLES);
427ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_BR_PRED);
9e9caa6a 428ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS);
03598fdb
AK		 429ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1I_CACHE);
430ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB);
431ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2D_CACHE);
432ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL);
433ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB);
9e9caa6a 434ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS);
03598fdb
AK		 435ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEMORY_ERROR);
436ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_INST_SPEC);
437ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED);
9e9caa6a 438ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES);
4ba2578f 439/* Don't expose the chain event in /sys, since it's useless in isolation */
9e9caa6a
DR		 440ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE);
441ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE);
442ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED);
443ARMV8_EVENT_ATTR(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED);
444ARMV8_EVENT_ATTR(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND);
445ARMV8_EVENT_ATTR(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND);
446ARMV8_EVENT_ATTR(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB);
447ARMV8_EVENT_ATTR(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB);
448ARMV8_EVENT_ATTR(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE);
449ARMV8_EVENT_ATTR(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL);
450ARMV8_EVENT_ATTR(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE);
451ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL);
452ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE);
453ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB);
454ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL);
03598fdb 455ARMV8_EVENT_ATTR(l2i_tlb_refill, ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL);
9e9caa6a 456ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB);
03598fdb 457ARMV8_EVENT_ATTR(l2i_tlb, ARMV8_PMUV3_PERFCTR_L2I_TLB);
9e9caa6a
DR		 458
459static struct attribute *armv8_pmuv3_event_attrs[] = {
460 &armv8_event_attr_sw_incr.attr.attr,
461 &armv8_event_attr_l1i_cache_refill.attr.attr,
462 &armv8_event_attr_l1i_tlb_refill.attr.attr,
463 &armv8_event_attr_l1d_cache_refill.attr.attr,
464 &armv8_event_attr_l1d_cache.attr.attr,
465 &armv8_event_attr_l1d_tlb_refill.attr.attr,
466 &armv8_event_attr_ld_retired.attr.attr,
467 &armv8_event_attr_st_retired.attr.attr,
468 &armv8_event_attr_inst_retired.attr.attr,
469 &armv8_event_attr_exc_taken.attr.attr,
470 &armv8_event_attr_exc_return.attr.attr,
471 &armv8_event_attr_cid_write_retired.attr.attr,
472 &armv8_event_attr_pc_write_retired.attr.attr,
473 &armv8_event_attr_br_immed_retired.attr.attr,
474 &armv8_event_attr_br_return_retired.attr.attr,
475 &armv8_event_attr_unaligned_ldst_retired.attr.attr,
476 &armv8_event_attr_br_mis_pred.attr.attr,
477 &armv8_event_attr_cpu_cycles.attr.attr,
478 &armv8_event_attr_br_pred.attr.attr,
479 &armv8_event_attr_mem_access.attr.attr,
480 &armv8_event_attr_l1i_cache.attr.attr,
481 &armv8_event_attr_l1d_cache_wb.attr.attr,
482 &armv8_event_attr_l2d_cache.attr.attr,
483 &armv8_event_attr_l2d_cache_refill.attr.attr,
484 &armv8_event_attr_l2d_cache_wb.attr.attr,
485 &armv8_event_attr_bus_access.attr.attr,
486 &armv8_event_attr_memory_error.attr.attr,
487 &armv8_event_attr_inst_spec.attr.attr,
488 &armv8_event_attr_ttbr_write_retired.attr.attr,
489 &armv8_event_attr_bus_cycles.attr.attr,
9e9caa6a
DR		 490 &armv8_event_attr_l1d_cache_allocate.attr.attr,
491 &armv8_event_attr_l2d_cache_allocate.attr.attr,
492 &armv8_event_attr_br_retired.attr.attr,
493 &armv8_event_attr_br_mis_pred_retired.attr.attr,
494 &armv8_event_attr_stall_frontend.attr.attr,
495 &armv8_event_attr_stall_backend.attr.attr,
496 &armv8_event_attr_l1d_tlb.attr.attr,
497 &armv8_event_attr_l1i_tlb.attr.attr,
498 &armv8_event_attr_l2i_cache.attr.attr,
499 &armv8_event_attr_l2i_cache_refill.attr.attr,
500 &armv8_event_attr_l3d_cache_allocate.attr.attr,
501 &armv8_event_attr_l3d_cache_refill.attr.attr,
502 &armv8_event_attr_l3d_cache.attr.attr,
503 &armv8_event_attr_l3d_cache_wb.attr.attr,
504 &armv8_event_attr_l2d_tlb_refill.attr.attr,
03598fdb 505 &armv8_event_attr_l2i_tlb_refill.attr.attr,
9e9caa6a 506 &armv8_event_attr_l2d_tlb.attr.attr,
03598fdb 507 &armv8_event_attr_l2i_tlb.attr.attr,
57d74123 508 NULL,
9e9caa6a
DR		 509};
510
4b1a9e69
AK		 511static umode_t
512armv8pmu_event_attr_is_visible(struct kobject *kobj,
513 struct attribute *attr, int unused)
514{
515 struct device *dev = kobj_to_dev(kobj);
516 struct pmu *pmu = dev_get_drvdata(dev);
517 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
518 struct perf_pmu_events_attr *pmu_attr;
519
520 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
521
522 if (test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap))
523 return attr->mode;
524
525 return 0;
526}
527
9e9caa6a
DR		 528static struct attribute_group armv8_pmuv3_events_attr_group = {
529 .name = "events",
530 .attrs = armv8_pmuv3_event_attrs,
4b1a9e69 531 .is_visible = armv8pmu_event_attr_is_visible,
9e9caa6a
DR		 532};
533
57d74123
WD		 534PMU_FORMAT_ATTR(event, "config:0-9");
535
536static struct attribute *armv8_pmuv3_format_attrs[] = {
537 &format_attr_event.attr,
538 NULL,
539};
540
541static struct attribute_group armv8_pmuv3_format_attr_group = {
542 .name = "format",
543 .attrs = armv8_pmuv3_format_attrs,
544};
545
03089688
WD		 546/*
547 * Perf Events' indices
548 */
549#define ARMV8_IDX_CYCLE_COUNTER 0
550#define ARMV8_IDX_COUNTER0 1
6475b2d8
MR		 551#define ARMV8_IDX_COUNTER_LAST(cpu_pmu) \
552 (ARMV8_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
03089688 553
03089688
WD		 554/*
555 * ARMv8 low level PMU access
556 */
557
558/*
559 * Perf Event to low level counters mapping
560 */
561#define ARMV8_IDX_TO_COUNTER(x) \
b8cfadfc 562 (((x) - ARMV8_IDX_COUNTER0) & ARMV8_PMU_COUNTER_MASK)
03089688
WD		 563
564static inline u32 armv8pmu_pmcr_read(void)
565{
bf2d4782 566 return read_sysreg(pmcr_el0);
03089688
WD		 567}
568
569static inline void armv8pmu_pmcr_write(u32 val)
570{
b8cfadfc 571 val &= ARMV8_PMU_PMCR_MASK;
03089688 572 isb();
bf2d4782 573 write_sysreg(val, pmcr_el0);
03089688
WD		 574}
575
576static inline int armv8pmu_has_overflowed(u32 pmovsr)
577{
b8cfadfc 578 return pmovsr & ARMV8_PMU_OVERFLOWED_MASK;
03089688
WD		 579}
580
6475b2d8 581static inline int armv8pmu_counter_valid(struct arm_pmu *cpu_pmu, int idx)
03089688 582{
6475b2d8
MR		 583 return idx >= ARMV8_IDX_CYCLE_COUNTER &&
584 idx <= ARMV8_IDX_COUNTER_LAST(cpu_pmu);
03089688
WD		 585}
586
587static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
588{
6475b2d8 589 return pmnc & BIT(ARMV8_IDX_TO_COUNTER(idx));
03089688
WD		 590}
591
592static inline int armv8pmu_select_counter(int idx)
593{
6475b2d8 594 u32 counter = ARMV8_IDX_TO_COUNTER(idx);
bf2d4782 595 write_sysreg(counter, pmselr_el0);
03089688
WD		 596 isb();
597
598 return idx;
599}
600
6475b2d8 601static inline u32 armv8pmu_read_counter(struct perf_event *event)
03089688 602{
6475b2d8
MR		 603 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
604 struct hw_perf_event *hwc = &event->hw;
605 int idx = hwc->idx;
03089688
WD		 606 u32 value = 0;
607
6475b2d8 608 if (!armv8pmu_counter_valid(cpu_pmu, idx))
03089688
WD		 609 pr_err("CPU%u reading wrong counter %d\n",
610 smp_processor_id(), idx);
611 else if (idx == ARMV8_IDX_CYCLE_COUNTER)
bf2d4782 612 value = read_sysreg(pmccntr_el0);
03089688 613 else if (armv8pmu_select_counter(idx) == idx)
bf2d4782 614 value = read_sysreg(pmxevcntr_el0);
03089688
WD		 615
616 return value;
617}
618
6475b2d8 619static inline void armv8pmu_write_counter(struct perf_event *event, u32 value)
03089688 620{
6475b2d8
MR		 621 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
622 struct hw_perf_event *hwc = &event->hw;
623 int idx = hwc->idx;
624
625 if (!armv8pmu_counter_valid(cpu_pmu, idx))
03089688
WD		 626 pr_err("CPU%u writing wrong counter %d\n",
627 smp_processor_id(), idx);
7175f059
JG		 628 else if (idx == ARMV8_IDX_CYCLE_COUNTER) {
629 /*
630 * Set the upper 32bits as this is a 64bit counter but we only
631 * count using the lower 32bits and we want an interrupt when
632 * it overflows.
633 */
634 u64 value64 = 0xffffffff00000000ULL | value;
635
bf2d4782 636 write_sysreg(value64, pmccntr_el0);
7175f059 637 } else if (armv8pmu_select_counter(idx) == idx)
bf2d4782 638 write_sysreg(value, pmxevcntr_el0);
03089688
WD		 639}
640
641static inline void armv8pmu_write_evtype(int idx, u32 val)
642{
643 if (armv8pmu_select_counter(idx) == idx) {
b8cfadfc 644 val &= ARMV8_PMU_EVTYPE_MASK;
bf2d4782 645 write_sysreg(val, pmxevtyper_el0);
03089688
WD		 646 }
647}
648
649static inline int armv8pmu_enable_counter(int idx)
650{
6475b2d8 651 u32 counter = ARMV8_IDX_TO_COUNTER(idx);
bf2d4782 652 write_sysreg(BIT(counter), pmcntenset_el0);
03089688
WD		 653 return idx;
654}
655
656static inline int armv8pmu_disable_counter(int idx)
657{
6475b2d8 658 u32 counter = ARMV8_IDX_TO_COUNTER(idx);
bf2d4782 659 write_sysreg(BIT(counter), pmcntenclr_el0);
03089688
WD		 660 return idx;
661}
662
663static inline int armv8pmu_enable_intens(int idx)
664{
6475b2d8 665 u32 counter = ARMV8_IDX_TO_COUNTER(idx);
bf2d4782 666 write_sysreg(BIT(counter), pmintenset_el1);
03089688
WD		 667 return idx;
668}
669
670static inline int armv8pmu_disable_intens(int idx)
671{
6475b2d8 672 u32 counter = ARMV8_IDX_TO_COUNTER(idx);
bf2d4782 673 write_sysreg(BIT(counter), pmintenclr_el1);
03089688
WD		 674 isb();
675 /* Clear the overflow flag in case an interrupt is pending. */
bf2d4782 676 write_sysreg(BIT(counter), pmovsclr_el0);
03089688 677 isb();
6475b2d8 678
03089688
WD		 679 return idx;
680}
681
682static inline u32 armv8pmu_getreset_flags(void)
683{
684 u32 value;
685
686 /* Read */
bf2d4782 687 value = read_sysreg(pmovsclr_el0);
03089688
WD		 688
689 /* Write to clear flags */
b8cfadfc 690 value &= ARMV8_PMU_OVSR_MASK;
bf2d4782 691 write_sysreg(value, pmovsclr_el0);
03089688
WD		 692
693 return value;
694}
695
6475b2d8 696static void armv8pmu_enable_event(struct perf_event *event)
03089688
WD		 697{
698 unsigned long flags;
6475b2d8
MR		 699 struct hw_perf_event *hwc = &event->hw;
700 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
701 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
702 int idx = hwc->idx;
03089688
WD		 703
704 /*
705 * Enable counter and interrupt, and set the counter to count
706 * the event that we're interested in.
707 */
708 raw_spin_lock_irqsave(&events->pmu_lock, flags);
709
710 /*
711 * Disable counter
712 */
713 armv8pmu_disable_counter(idx);
714
715 /*
716 * Set event (if destined for PMNx counters).
717 */
718 armv8pmu_write_evtype(idx, hwc->config_base);
719
720 /*
721 * Enable interrupt for this counter
722 */
723 armv8pmu_enable_intens(idx);
724
725 /*
726 * Enable counter
727 */
728 armv8pmu_enable_counter(idx);
729
730 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
731}
732
6475b2d8 733static void armv8pmu_disable_event(struct perf_event *event)
03089688
WD		 734{
735 unsigned long flags;
6475b2d8
MR		 736 struct hw_perf_event *hwc = &event->hw;
737 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
738 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
739 int idx = hwc->idx;
03089688
WD		 740
741 /*
742 * Disable counter and interrupt
743 */
744 raw_spin_lock_irqsave(&events->pmu_lock, flags);
745
746 /*
747 * Disable counter
748 */
749 armv8pmu_disable_counter(idx);
750
751 /*
752 * Disable interrupt for this counter
753 */
754 armv8pmu_disable_intens(idx);
755
756 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
757}
758
759static irqreturn_t armv8pmu_handle_irq(int irq_num, void *dev)
760{
761 u32 pmovsr;
762 struct perf_sample_data data;
6475b2d8
MR		 763 struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev;
764 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
03089688
WD		 765 struct pt_regs *regs;
766 int idx;
767
768 /*
769 * Get and reset the IRQ flags
770 */
771 pmovsr = armv8pmu_getreset_flags();
772
773 /*
774 * Did an overflow occur?
775 */
776 if (!armv8pmu_has_overflowed(pmovsr))
777 return IRQ_NONE;
778
779 /*
780 * Handle the counter(s) overflow(s)
781 */
782 regs = get_irq_regs();
783
03089688
WD		 784 for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
785 struct perf_event *event = cpuc->events[idx];
786 struct hw_perf_event *hwc;
787
788 /* Ignore if we don't have an event. */
789 if (!event)
790 continue;
791
792 /*
793 * We have a single interrupt for all counters. Check that
794 * each counter has overflowed before we process it.
795 */
796 if (!armv8pmu_counter_has_overflowed(pmovsr, idx))
797 continue;
798
799 hwc = &event->hw;
6475b2d8 800 armpmu_event_update(event);
03089688 801 perf_sample_data_init(&data, 0, hwc->last_period);
6475b2d8 802 if (!armpmu_event_set_period(event))
03089688
WD		 803 continue;
804
805 if (perf_event_overflow(event, &data, regs))
6475b2d8 806 cpu_pmu->disable(event);
03089688
WD		 807 }
808
809 /*
810 * Handle the pending perf events.
811 *
812 * Note: this call *must* be run with interrupts disabled. For
813 * platforms that can have the PMU interrupts raised as an NMI, this
814 * will not work.
815 */
816 irq_work_run();
817
818 return IRQ_HANDLED;
819}
820
6475b2d8 821static void armv8pmu_start(struct arm_pmu *cpu_pmu)
03089688
WD		 822{
823 unsigned long flags;
6475b2d8 824 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
03089688
WD		 825
826 raw_spin_lock_irqsave(&events->pmu_lock, flags);
827 /* Enable all counters */
b8cfadfc 828 armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E);
03089688
WD		 829 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
830}
831
6475b2d8 832static void armv8pmu_stop(struct arm_pmu *cpu_pmu)
03089688
WD		 833{
834 unsigned long flags;
6475b2d8 835 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
03089688
WD		 836
837 raw_spin_lock_irqsave(&events->pmu_lock, flags);
838 /* Disable all counters */
b8cfadfc 839 armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E);
03089688
WD		 840 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
841}
842
843static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
6475b2d8 844 struct perf_event *event)
03089688
WD		 845{
846 int idx;
6475b2d8
MR		 847 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
848 struct hw_perf_event *hwc = &event->hw;
b8cfadfc 849 unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT;
03089688
WD		 850
851 /* Always place a cycle counter into the cycle counter. */
03598fdb 852 if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) {
03089688
WD		 853 if (test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask))
854 return -EAGAIN;
855
856 return ARMV8_IDX_CYCLE_COUNTER;
857 }
858
859 /*
860 * For anything other than a cycle counter, try and use
861 * the events counters
862 */
863 for (idx = ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; ++idx) {
864 if (!test_and_set_bit(idx, cpuc->used_mask))
865 return idx;
866 }
867
868 /* The counters are all in use. */
869 return -EAGAIN;
870}
871
872/*
873 * Add an event filter to a given event. This will only work for PMUv2 PMUs.
874 */
875static int armv8pmu_set_event_filter(struct hw_perf_event *event,
876 struct perf_event_attr *attr)
877{
878 unsigned long config_base = 0;
879
880 if (attr->exclude_idle)
881 return -EPERM;
d98ecdac
MZ		 882 if (is_kernel_in_hyp_mode() &&
883 attr->exclude_kernel != attr->exclude_hv)
884 return -EINVAL;
03089688 885 if (attr->exclude_user)
b8cfadfc 886 config_base |= ARMV8_PMU_EXCLUDE_EL0;
d98ecdac 887 if (!is_kernel_in_hyp_mode() && attr->exclude_kernel)
b8cfadfc 888 config_base |= ARMV8_PMU_EXCLUDE_EL1;
03089688 889 if (!attr->exclude_hv)
b8cfadfc 890 config_base |= ARMV8_PMU_INCLUDE_EL2;
03089688
WD		 891
892 /*
893 * Install the filter into config_base as this is used to
894 * construct the event type.
895 */
896 event->config_base = config_base;
897
898 return 0;
899}
900
901static void armv8pmu_reset(void *info)
902{
6475b2d8 903 struct arm_pmu *cpu_pmu = (struct arm_pmu *)info;
03089688
WD		 904 u32 idx, nb_cnt = cpu_pmu->num_events;
905
906 /* The counter and interrupt enable registers are unknown at reset. */
6475b2d8
MR		 907 for (idx = ARMV8_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) {
908 armv8pmu_disable_counter(idx);
909 armv8pmu_disable_intens(idx);
910 }
03089688 911
7175f059
JG		 912 /*
913 * Initialize & Reset PMNC. Request overflow interrupt for
914 * 64 bit cycle counter but cheat in armv8pmu_write_counter().
915 */
b8cfadfc
SZ		 916 armv8pmu_pmcr_write(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C |
917 ARMV8_PMU_PMCR_LC);
03089688
WD		 918}
919
920static int armv8_pmuv3_map_event(struct perf_event *event)
921{
236b9b91
JL		 922 int hw_event_id;
923 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
924
925 hw_event_id = armpmu_map_event(event, &armv8_pmuv3_perf_map,
926 &armv8_pmuv3_perf_cache_map,
927 ARMV8_PMU_EVTYPE_EVENT);
928 if (hw_event_id < 0)
929 return hw_event_id;
930
931 /* disable micro/arch events not supported by this PMU */
932 if ((hw_event_id < ARMV8_PMUV3_MAX_COMMON_EVENTS) &&
933 !test_bit(hw_event_id, armpmu->pmceid_bitmap)) {
934 return -EOPNOTSUPP;
935 }
936
937 return hw_event_id;
03089688
WD		 938}
939
ac82d127
MR		 940static int armv8_a53_map_event(struct perf_event *event)
941{
942 return armpmu_map_event(event, &armv8_a53_perf_map,
943 &armv8_a53_perf_cache_map,
b8cfadfc 944 ARMV8_PMU_EVTYPE_EVENT);
ac82d127
MR		 945}
946
62a4dda9
MR		 947static int armv8_a57_map_event(struct perf_event *event)
948{
949 return armpmu_map_event(event, &armv8_a57_perf_map,
950 &armv8_a57_perf_cache_map,
b8cfadfc 951 ARMV8_PMU_EVTYPE_EVENT);
62a4dda9
MR		 952}
953
d0aa2bff
JG		 954static int armv8_thunder_map_event(struct perf_event *event)
955{
956 return armpmu_map_event(event, &armv8_thunder_perf_map,
957 &armv8_thunder_perf_cache_map,
b8cfadfc 958 ARMV8_PMU_EVTYPE_EVENT);
d0aa2bff
JG		 959}
960
201a72b2
AK		 961static int armv8_vulcan_map_event(struct perf_event *event)
962{
963 return armpmu_map_event(event, &armv8_vulcan_perf_map,
964 &armv8_vulcan_perf_cache_map,
965 ARMV8_PMU_EVTYPE_EVENT);
966}
967
4b1a9e69 968static void __armv8pmu_probe_pmu(void *info)
03089688 969{
4b1a9e69
AK		 970 struct arm_pmu *cpu_pmu = info;
971 u32 pmceid[2];
03089688
WD		 972
973 /* Read the nb of CNTx counters supported from PMNC */
4b1a9e69
AK		 974 cpu_pmu->num_events = (armv8pmu_pmcr_read() >> ARMV8_PMU_PMCR_N_SHIFT)
975 & ARMV8_PMU_PMCR_N_MASK;
03089688 976
6475b2d8 977 /* Add the CPU cycles counter */
4b1a9e69
AK		 978 cpu_pmu->num_events += 1;
979
980 pmceid[0] = read_sysreg(pmceid0_el0);
981 pmceid[1] = read_sysreg(pmceid1_el0);
982
983 bitmap_from_u32array(cpu_pmu->pmceid_bitmap,
984 ARMV8_PMUV3_MAX_COMMON_EVENTS, pmceid,
985 ARRAY_SIZE(pmceid));
03089688
WD		 986}
987
4b1a9e69 988static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu)
03089688 989{
4b1a9e69
AK		 990 return smp_call_function_any(&cpu_pmu->supported_cpus,
991 __armv8pmu_probe_pmu,
992 cpu_pmu, 1);
03089688
WD		 993}
994
ac82d127 995static void armv8_pmu_init(struct arm_pmu *cpu_pmu)
03089688 996{
6475b2d8
MR		 997 cpu_pmu->handle_irq = armv8pmu_handle_irq,
998 cpu_pmu->enable = armv8pmu_enable_event,
999 cpu_pmu->disable = armv8pmu_disable_event,
1000 cpu_pmu->read_counter = armv8pmu_read_counter,
1001 cpu_pmu->write_counter = armv8pmu_write_counter,
1002 cpu_pmu->get_event_idx = armv8pmu_get_event_idx,
1003 cpu_pmu->start = armv8pmu_start,
1004 cpu_pmu->stop = armv8pmu_stop,
1005 cpu_pmu->reset = armv8pmu_reset,
1006 cpu_pmu->max_period = (1LLU << 32) - 1,
ac82d127
MR		 1007 cpu_pmu->set_event_filter = armv8pmu_set_event_filter;
1008}
1009
1010static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)
1011{
1012 armv8_pmu_init(cpu_pmu);
6475b2d8
MR		 1013 cpu_pmu->name = "armv8_pmuv3";
1014 cpu_pmu->map_event = armv8_pmuv3_map_event;
569de902
MR		 1015 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1016 &armv8_pmuv3_events_attr_group;
1017 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1018 &armv8_pmuv3_format_attr_group;
4b1a9e69 1019 return armv8pmu_probe_pmu(cpu_pmu);
ac82d127
MR		 1020}
1021
1022static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
1023{
1024 armv8_pmu_init(cpu_pmu);
1025 cpu_pmu->name = "armv8_cortex_a53";
1026 cpu_pmu->map_event = armv8_a53_map_event;
569de902
MR		 1027 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1028 &armv8_pmuv3_events_attr_group;
1029 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1030 &armv8_pmuv3_format_attr_group;
4b1a9e69 1031 return armv8pmu_probe_pmu(cpu_pmu);
03089688 1032}
03089688 1033
62a4dda9
MR		 1034static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
1035{
1036 armv8_pmu_init(cpu_pmu);
1037 cpu_pmu->name = "armv8_cortex_a57";
1038 cpu_pmu->map_event = armv8_a57_map_event;
569de902
MR		 1039 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1040 &armv8_pmuv3_events_attr_group;
1041 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1042 &armv8_pmuv3_format_attr_group;
4b1a9e69 1043 return armv8pmu_probe_pmu(cpu_pmu);
62a4dda9
MR		 1044}
1045
5d7ee877
WD		 1046static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
1047{
1048 armv8_pmu_init(cpu_pmu);
1049 cpu_pmu->name = "armv8_cortex_a72";
1050 cpu_pmu->map_event = armv8_a57_map_event;
569de902
MR		 1051 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1052 &armv8_pmuv3_events_attr_group;
1053 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1054 &armv8_pmuv3_format_attr_group;
4b1a9e69 1055 return armv8pmu_probe_pmu(cpu_pmu);
5d7ee877
WD		 1056}
1057
d0aa2bff
JG		 1058static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
1059{
1060 armv8_pmu_init(cpu_pmu);
1061 cpu_pmu->name = "armv8_cavium_thunder";
1062 cpu_pmu->map_event = armv8_thunder_map_event;
569de902
MR		 1063 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1064 &armv8_pmuv3_events_attr_group;
1065 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1066 &armv8_pmuv3_format_attr_group;
4b1a9e69 1067 return armv8pmu_probe_pmu(cpu_pmu);
d0aa2bff
JG		 1068}
1069
201a72b2
AK		 1070static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
1071{
1072 armv8_pmu_init(cpu_pmu);
1073 cpu_pmu->name = "armv8_brcm_vulcan";
1074 cpu_pmu->map_event = armv8_vulcan_map_event;
569de902
MR		 1075 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1076 &armv8_pmuv3_events_attr_group;
1077 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1078 &armv8_pmuv3_format_attr_group;
201a72b2
AK		 1079 return armv8pmu_probe_pmu(cpu_pmu);
1080}
1081
6475b2d8
MR		 1082static const struct of_device_id armv8_pmu_of_device_ids[] = {
1083 {.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_init},
ac82d127 1084 {.compatible = "arm,cortex-a53-pmu", .data = armv8_a53_pmu_init},
62a4dda9 1085 {.compatible = "arm,cortex-a57-pmu", .data = armv8_a57_pmu_init},
5d7ee877 1086 {.compatible = "arm,cortex-a72-pmu", .data = armv8_a72_pmu_init},
d0aa2bff 1087 {.compatible = "cavium,thunder-pmu", .data = armv8_thunder_pmu_init},
201a72b2 1088 {.compatible = "brcm,vulcan-pmu", .data = armv8_vulcan_pmu_init},
03089688
WD		 1089 {},
1090};
1091
236b9b91
JL		 1092/*
1093 * Non DT systems have their micro/arch events probed at run-time.
1094 * A fairly complete list of generic events are provided and ones that
1095 * aren't supported by the current PMU are disabled.
1096 */
dbee3a74 1097static const struct pmu_probe_info armv8_pmu_probe_table[] = {
236b9b91 1098 PMU_PROBE(0, 0, armv8_pmuv3_init), /* enable all defined counters */
dbee3a74
MS		 1099 { /* sentinel value */ }
1100};
1101
6475b2d8 1102static int armv8_pmu_device_probe(struct platform_device *pdev)
03089688 1103{
dbee3a74
MS		 1104 if (acpi_disabled)
1105 return arm_pmu_device_probe(pdev, armv8_pmu_of_device_ids,
1106 NULL);
1107
1108 return arm_pmu_device_probe(pdev, armv8_pmu_of_device_ids,
1109 armv8_pmu_probe_table);
03089688
WD		 1110}
1111
6475b2d8 1112static struct platform_driver armv8_pmu_driver = {
03089688 1113 .driver = {
85023b2e 1114 .name = ARMV8_PMU_PDEV_NAME,
6475b2d8 1115 .of_match_table = armv8_pmu_of_device_ids,
03089688 1116 },
6475b2d8 1117 .probe = armv8_pmu_device_probe,
03089688
WD		 1118};
1119
826d0562 1120builtin_platform_driver(armv8_pmu_driver);
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