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Commit | Line | Data |
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b3901d54 CM |
1 | /* |
2 | * Based on arch/arm/kernel/process.c | |
3 | * | |
4 | * Original Copyright (C) 1995 Linus Torvalds | |
5 | * Copyright (C) 1996-2000 Russell King - Converted to ARM. | |
6 | * Copyright (C) 2012 ARM Ltd. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include <stdarg.h> | |
22 | ||
fd92d4a5 | 23 | #include <linux/compat.h> |
60c0d45a | 24 | #include <linux/efi.h> |
b3901d54 CM |
25 | #include <linux/export.h> |
26 | #include <linux/sched.h> | |
b17b0153 | 27 | #include <linux/sched/debug.h> |
b3901d54 CM |
28 | #include <linux/kernel.h> |
29 | #include <linux/mm.h> | |
30 | #include <linux/stddef.h> | |
31 | #include <linux/unistd.h> | |
32 | #include <linux/user.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/reboot.h> | |
35 | #include <linux/interrupt.h> | |
36 | #include <linux/kallsyms.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/cpu.h> | |
39 | #include <linux/elfcore.h> | |
40 | #include <linux/pm.h> | |
41 | #include <linux/tick.h> | |
42 | #include <linux/utsname.h> | |
43 | #include <linux/uaccess.h> | |
44 | #include <linux/random.h> | |
45 | #include <linux/hw_breakpoint.h> | |
46 | #include <linux/personality.h> | |
47 | #include <linux/notifier.h> | |
096b3224 | 48 | #include <trace/events/power.h> |
c02433dd | 49 | #include <linux/percpu.h> |
b3901d54 | 50 | |
57f4959b | 51 | #include <asm/alternative.h> |
b3901d54 CM |
52 | #include <asm/compat.h> |
53 | #include <asm/cacheflush.h> | |
d0854412 | 54 | #include <asm/exec.h> |
ec45d1cf WD |
55 | #include <asm/fpsimd.h> |
56 | #include <asm/mmu_context.h> | |
b3901d54 CM |
57 | #include <asm/processor.h> |
58 | #include <asm/stacktrace.h> | |
b3901d54 | 59 | |
c0c264ae LA |
60 | #ifdef CONFIG_CC_STACKPROTECTOR |
61 | #include <linux/stackprotector.h> | |
62 | unsigned long __stack_chk_guard __read_mostly; | |
63 | EXPORT_SYMBOL(__stack_chk_guard); | |
64 | #endif | |
65 | ||
b3901d54 CM |
66 | /* |
67 | * Function pointers to optional machine specific functions | |
68 | */ | |
69 | void (*pm_power_off)(void); | |
70 | EXPORT_SYMBOL_GPL(pm_power_off); | |
71 | ||
b0946fc8 | 72 | void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd); |
b3901d54 | 73 | |
b3901d54 CM |
74 | /* |
75 | * This is our default idle handler. | |
76 | */ | |
0087298f | 77 | void arch_cpu_idle(void) |
b3901d54 CM |
78 | { |
79 | /* | |
80 | * This should do all the clock switching and wait for interrupt | |
81 | * tricks | |
82 | */ | |
096b3224 | 83 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
6990566b NP |
84 | cpu_do_idle(); |
85 | local_irq_enable(); | |
096b3224 | 86 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
b3901d54 CM |
87 | } |
88 | ||
9327e2c6 MR |
89 | #ifdef CONFIG_HOTPLUG_CPU |
90 | void arch_cpu_idle_dead(void) | |
91 | { | |
92 | cpu_die(); | |
93 | } | |
94 | #endif | |
95 | ||
90f51a09 AK |
96 | /* |
97 | * Called by kexec, immediately prior to machine_kexec(). | |
98 | * | |
99 | * This must completely disable all secondary CPUs; simply causing those CPUs | |
100 | * to execute e.g. a RAM-based pin loop is not sufficient. This allows the | |
101 | * kexec'd kernel to use any and all RAM as it sees fit, without having to | |
102 | * avoid any code or data used by any SW CPU pin loop. The CPU hotplug | |
103 | * functionality embodied in disable_nonboot_cpus() to achieve this. | |
104 | */ | |
b3901d54 CM |
105 | void machine_shutdown(void) |
106 | { | |
90f51a09 | 107 | disable_nonboot_cpus(); |
b3901d54 CM |
108 | } |
109 | ||
90f51a09 AK |
110 | /* |
111 | * Halting simply requires that the secondary CPUs stop performing any | |
112 | * activity (executing tasks, handling interrupts). smp_send_stop() | |
113 | * achieves this. | |
114 | */ | |
b3901d54 CM |
115 | void machine_halt(void) |
116 | { | |
b9acc49e | 117 | local_irq_disable(); |
90f51a09 | 118 | smp_send_stop(); |
b3901d54 CM |
119 | while (1); |
120 | } | |
121 | ||
90f51a09 AK |
122 | /* |
123 | * Power-off simply requires that the secondary CPUs stop performing any | |
124 | * activity (executing tasks, handling interrupts). smp_send_stop() | |
125 | * achieves this. When the system power is turned off, it will take all CPUs | |
126 | * with it. | |
127 | */ | |
b3901d54 CM |
128 | void machine_power_off(void) |
129 | { | |
b9acc49e | 130 | local_irq_disable(); |
90f51a09 | 131 | smp_send_stop(); |
b3901d54 CM |
132 | if (pm_power_off) |
133 | pm_power_off(); | |
134 | } | |
135 | ||
90f51a09 AK |
136 | /* |
137 | * Restart requires that the secondary CPUs stop performing any activity | |
68234df4 | 138 | * while the primary CPU resets the system. Systems with multiple CPUs must |
90f51a09 AK |
139 | * provide a HW restart implementation, to ensure that all CPUs reset at once. |
140 | * This is required so that any code running after reset on the primary CPU | |
141 | * doesn't have to co-ordinate with other CPUs to ensure they aren't still | |
142 | * executing pre-reset code, and using RAM that the primary CPU's code wishes | |
143 | * to use. Implementing such co-ordination would be essentially impossible. | |
144 | */ | |
b3901d54 CM |
145 | void machine_restart(char *cmd) |
146 | { | |
b3901d54 CM |
147 | /* Disable interrupts first */ |
148 | local_irq_disable(); | |
b9acc49e | 149 | smp_send_stop(); |
b3901d54 | 150 | |
60c0d45a AB |
151 | /* |
152 | * UpdateCapsule() depends on the system being reset via | |
153 | * ResetSystem(). | |
154 | */ | |
155 | if (efi_enabled(EFI_RUNTIME_SERVICES)) | |
156 | efi_reboot(reboot_mode, NULL); | |
157 | ||
b3901d54 | 158 | /* Now call the architecture specific reboot code. */ |
aa1e8ec1 | 159 | if (arm_pm_restart) |
ff701306 | 160 | arm_pm_restart(reboot_mode, cmd); |
1c7ffc32 GR |
161 | else |
162 | do_kernel_restart(cmd); | |
b3901d54 CM |
163 | |
164 | /* | |
165 | * Whoops - the architecture was unable to reboot. | |
166 | */ | |
167 | printk("Reboot failed -- System halted\n"); | |
168 | while (1); | |
169 | } | |
170 | ||
171 | void __show_regs(struct pt_regs *regs) | |
172 | { | |
6ca68e80 CM |
173 | int i, top_reg; |
174 | u64 lr, sp; | |
175 | ||
176 | if (compat_user_mode(regs)) { | |
177 | lr = regs->compat_lr; | |
178 | sp = regs->compat_sp; | |
179 | top_reg = 12; | |
180 | } else { | |
181 | lr = regs->regs[30]; | |
182 | sp = regs->sp; | |
183 | top_reg = 29; | |
184 | } | |
b3901d54 | 185 | |
a43cb95d | 186 | show_regs_print_info(KERN_DEFAULT); |
b3901d54 | 187 | print_symbol("PC is at %s\n", instruction_pointer(regs)); |
6ca68e80 | 188 | print_symbol("LR is at %s\n", lr); |
b3901d54 | 189 | printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n", |
6ca68e80 CM |
190 | regs->pc, lr, regs->pstate); |
191 | printk("sp : %016llx\n", sp); | |
db4b0710 MR |
192 | |
193 | i = top_reg; | |
194 | ||
195 | while (i >= 0) { | |
b3901d54 | 196 | printk("x%-2d: %016llx ", i, regs->regs[i]); |
db4b0710 MR |
197 | i--; |
198 | ||
199 | if (i % 2 == 0) { | |
200 | pr_cont("x%-2d: %016llx ", i, regs->regs[i]); | |
201 | i--; | |
202 | } | |
203 | ||
204 | pr_cont("\n"); | |
b3901d54 CM |
205 | } |
206 | printk("\n"); | |
207 | } | |
208 | ||
209 | void show_regs(struct pt_regs * regs) | |
210 | { | |
211 | printk("\n"); | |
b3901d54 CM |
212 | __show_regs(regs); |
213 | } | |
214 | ||
eb35bdd7 WD |
215 | static void tls_thread_flush(void) |
216 | { | |
adf75899 | 217 | write_sysreg(0, tpidr_el0); |
eb35bdd7 WD |
218 | |
219 | if (is_compat_task()) { | |
220 | current->thread.tp_value = 0; | |
221 | ||
222 | /* | |
223 | * We need to ensure ordering between the shadow state and the | |
224 | * hardware state, so that we don't corrupt the hardware state | |
225 | * with a stale shadow state during context switch. | |
226 | */ | |
227 | barrier(); | |
adf75899 | 228 | write_sysreg(0, tpidrro_el0); |
eb35bdd7 WD |
229 | } |
230 | } | |
231 | ||
b3901d54 CM |
232 | void flush_thread(void) |
233 | { | |
234 | fpsimd_flush_thread(); | |
eb35bdd7 | 235 | tls_thread_flush(); |
b3901d54 CM |
236 | flush_ptrace_hw_breakpoint(current); |
237 | } | |
238 | ||
239 | void release_thread(struct task_struct *dead_task) | |
240 | { | |
241 | } | |
242 | ||
243 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) | |
244 | { | |
6eb6c801 JL |
245 | if (current->mm) |
246 | fpsimd_preserve_current_state(); | |
b3901d54 CM |
247 | *dst = *src; |
248 | return 0; | |
249 | } | |
250 | ||
251 | asmlinkage void ret_from_fork(void) asm("ret_from_fork"); | |
252 | ||
253 | int copy_thread(unsigned long clone_flags, unsigned long stack_start, | |
afa86fc4 | 254 | unsigned long stk_sz, struct task_struct *p) |
b3901d54 CM |
255 | { |
256 | struct pt_regs *childregs = task_pt_regs(p); | |
b3901d54 | 257 | |
c34501d2 | 258 | memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context)); |
b3901d54 | 259 | |
9ac08002 AV |
260 | if (likely(!(p->flags & PF_KTHREAD))) { |
261 | *childregs = *current_pt_regs(); | |
c34501d2 | 262 | childregs->regs[0] = 0; |
d00a3810 WD |
263 | |
264 | /* | |
265 | * Read the current TLS pointer from tpidr_el0 as it may be | |
266 | * out-of-sync with the saved value. | |
267 | */ | |
adf75899 | 268 | *task_user_tls(p) = read_sysreg(tpidr_el0); |
d00a3810 WD |
269 | |
270 | if (stack_start) { | |
271 | if (is_compat_thread(task_thread_info(p))) | |
e0fd18ce | 272 | childregs->compat_sp = stack_start; |
d00a3810 | 273 | else |
e0fd18ce | 274 | childregs->sp = stack_start; |
c34501d2 | 275 | } |
d00a3810 | 276 | |
b3901d54 | 277 | /* |
c34501d2 CM |
278 | * If a TLS pointer was passed to clone (4th argument), use it |
279 | * for the new thread. | |
b3901d54 | 280 | */ |
c34501d2 | 281 | if (clone_flags & CLONE_SETTLS) |
d00a3810 | 282 | p->thread.tp_value = childregs->regs[3]; |
c34501d2 CM |
283 | } else { |
284 | memset(childregs, 0, sizeof(struct pt_regs)); | |
285 | childregs->pstate = PSR_MODE_EL1h; | |
57f4959b | 286 | if (IS_ENABLED(CONFIG_ARM64_UAO) && |
a4023f68 | 287 | cpus_have_const_cap(ARM64_HAS_UAO)) |
57f4959b | 288 | childregs->pstate |= PSR_UAO_BIT; |
c34501d2 CM |
289 | p->thread.cpu_context.x19 = stack_start; |
290 | p->thread.cpu_context.x20 = stk_sz; | |
b3901d54 | 291 | } |
b3901d54 | 292 | p->thread.cpu_context.pc = (unsigned long)ret_from_fork; |
c34501d2 | 293 | p->thread.cpu_context.sp = (unsigned long)childregs; |
b3901d54 CM |
294 | |
295 | ptrace_hw_copy_thread(p); | |
296 | ||
297 | return 0; | |
298 | } | |
299 | ||
300 | static void tls_thread_switch(struct task_struct *next) | |
301 | { | |
302 | unsigned long tpidr, tpidrro; | |
303 | ||
adf75899 | 304 | tpidr = read_sysreg(tpidr_el0); |
d00a3810 | 305 | *task_user_tls(current) = tpidr; |
b3901d54 | 306 | |
d00a3810 WD |
307 | tpidr = *task_user_tls(next); |
308 | tpidrro = is_compat_thread(task_thread_info(next)) ? | |
309 | next->thread.tp_value : 0; | |
b3901d54 | 310 | |
adf75899 MR |
311 | write_sysreg(tpidr, tpidr_el0); |
312 | write_sysreg(tpidrro, tpidrro_el0); | |
b3901d54 CM |
313 | } |
314 | ||
57f4959b | 315 | /* Restore the UAO state depending on next's addr_limit */ |
d0854412 | 316 | void uao_thread_switch(struct task_struct *next) |
57f4959b | 317 | { |
e950631e CM |
318 | if (IS_ENABLED(CONFIG_ARM64_UAO)) { |
319 | if (task_thread_info(next)->addr_limit == KERNEL_DS) | |
320 | asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO)); | |
321 | else | |
322 | asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO)); | |
323 | } | |
57f4959b JM |
324 | } |
325 | ||
c02433dd MR |
326 | /* |
327 | * We store our current task in sp_el0, which is clobbered by userspace. Keep a | |
328 | * shadow copy so that we can restore this upon entry from userspace. | |
329 | * | |
330 | * This is *only* for exception entry from EL0, and is not valid until we | |
331 | * __switch_to() a user task. | |
332 | */ | |
333 | DEFINE_PER_CPU(struct task_struct *, __entry_task); | |
334 | ||
335 | static void entry_task_switch(struct task_struct *next) | |
336 | { | |
337 | __this_cpu_write(__entry_task, next); | |
338 | } | |
339 | ||
b3901d54 CM |
340 | /* |
341 | * Thread switching. | |
342 | */ | |
8f4b326d | 343 | __notrace_funcgraph struct task_struct *__switch_to(struct task_struct *prev, |
b3901d54 CM |
344 | struct task_struct *next) |
345 | { | |
346 | struct task_struct *last; | |
347 | ||
348 | fpsimd_thread_switch(next); | |
349 | tls_thread_switch(next); | |
350 | hw_breakpoint_thread_switch(next); | |
3325732f | 351 | contextidr_thread_switch(next); |
c02433dd | 352 | entry_task_switch(next); |
57f4959b | 353 | uao_thread_switch(next); |
b3901d54 | 354 | |
5108c67c CM |
355 | /* |
356 | * Complete any pending TLB or cache maintenance on this CPU in case | |
357 | * the thread migrates to a different CPU. | |
358 | */ | |
98f7685e | 359 | dsb(ish); |
b3901d54 CM |
360 | |
361 | /* the actual thread switch */ | |
362 | last = cpu_switch_to(prev, next); | |
363 | ||
364 | return last; | |
365 | } | |
366 | ||
b3901d54 CM |
367 | unsigned long get_wchan(struct task_struct *p) |
368 | { | |
369 | struct stackframe frame; | |
9bbd4c56 | 370 | unsigned long stack_page, ret = 0; |
b3901d54 CM |
371 | int count = 0; |
372 | if (!p || p == current || p->state == TASK_RUNNING) | |
373 | return 0; | |
374 | ||
9bbd4c56 MR |
375 | stack_page = (unsigned long)try_get_task_stack(p); |
376 | if (!stack_page) | |
377 | return 0; | |
378 | ||
b3901d54 CM |
379 | frame.fp = thread_saved_fp(p); |
380 | frame.sp = thread_saved_sp(p); | |
381 | frame.pc = thread_saved_pc(p); | |
20380bb3 AT |
382 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
383 | frame.graph = p->curr_ret_stack; | |
384 | #endif | |
b3901d54 | 385 | do { |
408c3658 KK |
386 | if (frame.sp < stack_page || |
387 | frame.sp >= stack_page + THREAD_SIZE || | |
fe13f95b | 388 | unwind_frame(p, &frame)) |
9bbd4c56 MR |
389 | goto out; |
390 | if (!in_sched_functions(frame.pc)) { | |
391 | ret = frame.pc; | |
392 | goto out; | |
393 | } | |
b3901d54 | 394 | } while (count ++ < 16); |
9bbd4c56 MR |
395 | |
396 | out: | |
397 | put_task_stack(p); | |
398 | return ret; | |
b3901d54 CM |
399 | } |
400 | ||
401 | unsigned long arch_align_stack(unsigned long sp) | |
402 | { | |
403 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
404 | sp -= get_random_int() & ~PAGE_MASK; | |
405 | return sp & ~0xf; | |
406 | } | |
407 | ||
b3901d54 CM |
408 | unsigned long arch_randomize_brk(struct mm_struct *mm) |
409 | { | |
61462c8a | 410 | if (is_compat_task()) |
ffe3d1e4 | 411 | return randomize_page(mm->brk, SZ_32M); |
61462c8a | 412 | else |
ffe3d1e4 | 413 | return randomize_page(mm->brk, SZ_1G); |
b3901d54 | 414 | } |