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9703d9d7 CM |
1 | /* |
2 | * Based on arch/arm/kernel/setup.c | |
3 | * | |
4 | * Copyright (C) 1995-2001 Russell King | |
5 | * Copyright (C) 2012 ARM Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include <linux/export.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/stddef.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/utsname.h> | |
26 | #include <linux/initrd.h> | |
27 | #include <linux/console.h> | |
28 | #include <linux/bootmem.h> | |
29 | #include <linux/seq_file.h> | |
30 | #include <linux/screen_info.h> | |
31 | #include <linux/init.h> | |
32 | #include <linux/kexec.h> | |
33 | #include <linux/crash_dump.h> | |
34 | #include <linux/root_dev.h> | |
de79a64d | 35 | #include <linux/clk-provider.h> |
9703d9d7 CM |
36 | #include <linux/cpu.h> |
37 | #include <linux/interrupt.h> | |
38 | #include <linux/smp.h> | |
39 | #include <linux/fs.h> | |
40 | #include <linux/proc_fs.h> | |
41 | #include <linux/memblock.h> | |
42 | #include <linux/of_fdt.h> | |
d6bafb9b | 43 | #include <linux/of_platform.h> |
f84d0275 | 44 | #include <linux/efi.h> |
9703d9d7 | 45 | |
bf4b558e | 46 | #include <asm/fixmap.h> |
9703d9d7 CM |
47 | #include <asm/cputype.h> |
48 | #include <asm/elf.h> | |
49 | #include <asm/cputable.h> | |
e8765b26 | 50 | #include <asm/cpu_ops.h> |
9703d9d7 CM |
51 | #include <asm/sections.h> |
52 | #include <asm/setup.h> | |
4c7aa002 | 53 | #include <asm/smp_plat.h> |
9703d9d7 CM |
54 | #include <asm/cacheflush.h> |
55 | #include <asm/tlbflush.h> | |
56 | #include <asm/traps.h> | |
57 | #include <asm/memblock.h> | |
e790f1de | 58 | #include <asm/psci.h> |
f84d0275 | 59 | #include <asm/efi.h> |
9703d9d7 CM |
60 | |
61 | unsigned int processor_id; | |
62 | EXPORT_SYMBOL(processor_id); | |
63 | ||
25804e6a | 64 | unsigned long elf_hwcap __read_mostly; |
9703d9d7 CM |
65 | EXPORT_SYMBOL_GPL(elf_hwcap); |
66 | ||
46efe547 SH |
67 | #ifdef CONFIG_COMPAT |
68 | #define COMPAT_ELF_HWCAP_DEFAULT \ | |
69 | (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ | |
70 | COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ | |
71 | COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\ | |
72 | COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\ | |
73 | COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV) | |
74 | unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; | |
28964d32 | 75 | unsigned int compat_elf_hwcap2 __read_mostly; |
46efe547 SH |
76 | #endif |
77 | ||
9703d9d7 CM |
78 | static const char *cpu_name; |
79 | static const char *machine_name; | |
80 | phys_addr_t __fdt_pointer __initdata; | |
81 | ||
82 | /* | |
83 | * Standard memory resources | |
84 | */ | |
85 | static struct resource mem_res[] = { | |
86 | { | |
87 | .name = "Kernel code", | |
88 | .start = 0, | |
89 | .end = 0, | |
90 | .flags = IORESOURCE_MEM | |
91 | }, | |
92 | { | |
93 | .name = "Kernel data", | |
94 | .start = 0, | |
95 | .end = 0, | |
96 | .flags = IORESOURCE_MEM | |
97 | } | |
98 | }; | |
99 | ||
100 | #define kernel_code mem_res[0] | |
101 | #define kernel_data mem_res[1] | |
102 | ||
103 | void __init early_print(const char *str, ...) | |
104 | { | |
105 | char buf[256]; | |
106 | va_list ap; | |
107 | ||
108 | va_start(ap, str); | |
109 | vsnprintf(buf, sizeof(buf), str, ap); | |
110 | va_end(ap); | |
111 | ||
112 | printk("%s", buf); | |
113 | } | |
114 | ||
71586276 WD |
115 | void __init smp_setup_processor_id(void) |
116 | { | |
117 | /* | |
118 | * clear __my_cpu_offset on boot CPU to avoid hang caused by | |
119 | * using percpu variable early, for example, lockdep will | |
120 | * access percpu variable inside lock_release | |
121 | */ | |
122 | set_my_cpu_offset(0); | |
123 | } | |
124 | ||
6e15d0e0 SH |
125 | bool arch_match_cpu_phys_id(int cpu, u64 phys_id) |
126 | { | |
127 | return phys_id == cpu_logical_map(cpu); | |
128 | } | |
129 | ||
976d7d3f LP |
130 | struct mpidr_hash mpidr_hash; |
131 | #ifdef CONFIG_SMP | |
132 | /** | |
133 | * smp_build_mpidr_hash - Pre-compute shifts required at each affinity | |
134 | * level in order to build a linear index from an | |
135 | * MPIDR value. Resulting algorithm is a collision | |
136 | * free hash carried out through shifting and ORing | |
137 | */ | |
138 | static void __init smp_build_mpidr_hash(void) | |
139 | { | |
140 | u32 i, affinity, fs[4], bits[4], ls; | |
141 | u64 mask = 0; | |
142 | /* | |
143 | * Pre-scan the list of MPIDRS and filter out bits that do | |
144 | * not contribute to affinity levels, ie they never toggle. | |
145 | */ | |
146 | for_each_possible_cpu(i) | |
147 | mask |= (cpu_logical_map(i) ^ cpu_logical_map(0)); | |
148 | pr_debug("mask of set bits %#llx\n", mask); | |
149 | /* | |
150 | * Find and stash the last and first bit set at all affinity levels to | |
151 | * check how many bits are required to represent them. | |
152 | */ | |
153 | for (i = 0; i < 4; i++) { | |
154 | affinity = MPIDR_AFFINITY_LEVEL(mask, i); | |
155 | /* | |
156 | * Find the MSB bit and LSB bits position | |
157 | * to determine how many bits are required | |
158 | * to express the affinity level. | |
159 | */ | |
160 | ls = fls(affinity); | |
161 | fs[i] = affinity ? ffs(affinity) - 1 : 0; | |
162 | bits[i] = ls - fs[i]; | |
163 | } | |
164 | /* | |
165 | * An index can be created from the MPIDR_EL1 by isolating the | |
166 | * significant bits at each affinity level and by shifting | |
167 | * them in order to compress the 32 bits values space to a | |
168 | * compressed set of values. This is equivalent to hashing | |
169 | * the MPIDR_EL1 through shifting and ORing. It is a collision free | |
170 | * hash though not minimal since some levels might contain a number | |
171 | * of CPUs that is not an exact power of 2 and their bit | |
172 | * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}. | |
173 | */ | |
174 | mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0]; | |
175 | mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0]; | |
176 | mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] - | |
177 | (bits[1] + bits[0]); | |
178 | mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) + | |
179 | fs[3] - (bits[2] + bits[1] + bits[0]); | |
180 | mpidr_hash.mask = mask; | |
181 | mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0]; | |
182 | pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n", | |
183 | mpidr_hash.shift_aff[0], | |
184 | mpidr_hash.shift_aff[1], | |
185 | mpidr_hash.shift_aff[2], | |
186 | mpidr_hash.shift_aff[3], | |
187 | mpidr_hash.mask, | |
188 | mpidr_hash.bits); | |
189 | /* | |
190 | * 4x is an arbitrary value used to warn on a hash table much bigger | |
191 | * than expected on most systems. | |
192 | */ | |
193 | if (mpidr_hash_size() > 4 * num_possible_cpus()) | |
194 | pr_warn("Large number of MPIDR hash buckets detected\n"); | |
195 | __flush_dcache_area(&mpidr_hash, sizeof(struct mpidr_hash)); | |
196 | } | |
197 | #endif | |
198 | ||
9703d9d7 CM |
199 | static void __init setup_processor(void) |
200 | { | |
201 | struct cpu_info *cpu_info; | |
4bff28cc | 202 | u64 features, block; |
9703d9d7 | 203 | |
9703d9d7 CM |
204 | cpu_info = lookup_processor_type(read_cpuid_id()); |
205 | if (!cpu_info) { | |
206 | printk("CPU configuration botched (ID %08x), unable to continue.\n", | |
207 | read_cpuid_id()); | |
208 | while (1); | |
209 | } | |
210 | ||
211 | cpu_name = cpu_info->cpu_name; | |
212 | ||
213 | printk("CPU: %s [%08x] revision %d\n", | |
214 | cpu_name, read_cpuid_id(), read_cpuid_id() & 15); | |
215 | ||
94ed1f2c | 216 | sprintf(init_utsname()->machine, ELF_PLATFORM); |
9703d9d7 | 217 | elf_hwcap = 0; |
4bff28cc SC |
218 | |
219 | /* | |
220 | * ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks. | |
221 | * The blocks we test below represent incremental functionality | |
222 | * for non-negative values. Negative values are reserved. | |
223 | */ | |
224 | features = read_cpuid(ID_AA64ISAR0_EL1); | |
225 | block = (features >> 4) & 0xf; | |
226 | if (!(block & 0x8)) { | |
227 | switch (block) { | |
228 | default: | |
229 | case 2: | |
230 | elf_hwcap |= HWCAP_PMULL; | |
231 | case 1: | |
232 | elf_hwcap |= HWCAP_AES; | |
233 | case 0: | |
234 | break; | |
235 | } | |
236 | } | |
237 | ||
238 | block = (features >> 8) & 0xf; | |
239 | if (block && !(block & 0x8)) | |
240 | elf_hwcap |= HWCAP_SHA1; | |
241 | ||
242 | block = (features >> 12) & 0xf; | |
243 | if (block && !(block & 0x8)) | |
244 | elf_hwcap |= HWCAP_SHA2; | |
245 | ||
246 | block = (features >> 16) & 0xf; | |
247 | if (block && !(block & 0x8)) | |
248 | elf_hwcap |= HWCAP_CRC32; | |
4cf761cd AB |
249 | |
250 | #ifdef CONFIG_COMPAT | |
251 | /* | |
252 | * ID_ISAR5_EL1 carries similar information as above, but pertaining to | |
253 | * the Aarch32 32-bit execution state. | |
254 | */ | |
255 | features = read_cpuid(ID_ISAR5_EL1); | |
256 | block = (features >> 4) & 0xf; | |
257 | if (!(block & 0x8)) { | |
258 | switch (block) { | |
259 | default: | |
260 | case 2: | |
261 | compat_elf_hwcap2 |= COMPAT_HWCAP2_PMULL; | |
262 | case 1: | |
263 | compat_elf_hwcap2 |= COMPAT_HWCAP2_AES; | |
264 | case 0: | |
265 | break; | |
266 | } | |
267 | } | |
268 | ||
269 | block = (features >> 8) & 0xf; | |
270 | if (block && !(block & 0x8)) | |
271 | compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA1; | |
272 | ||
273 | block = (features >> 12) & 0xf; | |
274 | if (block && !(block & 0x8)) | |
275 | compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA2; | |
276 | ||
277 | block = (features >> 16) & 0xf; | |
278 | if (block && !(block & 0x8)) | |
279 | compat_elf_hwcap2 |= COMPAT_HWCAP2_CRC32; | |
280 | #endif | |
9703d9d7 CM |
281 | } |
282 | ||
283 | static void __init setup_machine_fdt(phys_addr_t dt_phys) | |
284 | { | |
d5189cc5 | 285 | if (!dt_phys || !early_init_dt_scan(phys_to_virt(dt_phys))) { |
9703d9d7 CM |
286 | early_print("\n" |
287 | "Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n" | |
d5189cc5 | 288 | "The dtb must be 8-byte aligned and passed in the first 512MB of memory\n" |
9703d9d7 | 289 | "\nPlease check your bootloader.\n", |
d5189cc5 | 290 | dt_phys, phys_to_virt(dt_phys)); |
9703d9d7 CM |
291 | |
292 | while (true) | |
293 | cpu_relax(); | |
294 | } | |
295 | ||
f2b99bcc | 296 | machine_name = of_flat_dt_get_machine_name(); |
9703d9d7 CM |
297 | } |
298 | ||
9703d9d7 CM |
299 | /* |
300 | * Limit the memory size that was specified via FDT. | |
301 | */ | |
302 | static int __init early_mem(char *p) | |
303 | { | |
304 | phys_addr_t limit; | |
305 | ||
306 | if (!p) | |
307 | return 1; | |
308 | ||
309 | limit = memparse(p, &p) & PAGE_MASK; | |
310 | pr_notice("Memory limited to %lldMB\n", limit >> 20); | |
311 | ||
312 | memblock_enforce_memory_limit(limit); | |
313 | ||
314 | return 0; | |
315 | } | |
316 | early_param("mem", early_mem); | |
317 | ||
318 | static void __init request_standard_resources(void) | |
319 | { | |
320 | struct memblock_region *region; | |
321 | struct resource *res; | |
322 | ||
323 | kernel_code.start = virt_to_phys(_text); | |
324 | kernel_code.end = virt_to_phys(_etext - 1); | |
325 | kernel_data.start = virt_to_phys(_sdata); | |
326 | kernel_data.end = virt_to_phys(_end - 1); | |
327 | ||
328 | for_each_memblock(memory, region) { | |
329 | res = alloc_bootmem_low(sizeof(*res)); | |
330 | res->name = "System RAM"; | |
331 | res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region)); | |
332 | res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1; | |
333 | res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
334 | ||
335 | request_resource(&iomem_resource, res); | |
336 | ||
337 | if (kernel_code.start >= res->start && | |
338 | kernel_code.end <= res->end) | |
339 | request_resource(res, &kernel_code); | |
340 | if (kernel_data.start >= res->start && | |
341 | kernel_data.end <= res->end) | |
342 | request_resource(res, &kernel_data); | |
343 | } | |
344 | } | |
345 | ||
4c7aa002 JM |
346 | u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID }; |
347 | ||
9703d9d7 CM |
348 | void __init setup_arch(char **cmdline_p) |
349 | { | |
b3bf6aa7 CM |
350 | /* |
351 | * Unmask asynchronous aborts early to catch possible system errors. | |
352 | */ | |
353 | local_async_enable(); | |
354 | ||
9703d9d7 CM |
355 | setup_processor(); |
356 | ||
357 | setup_machine_fdt(__fdt_pointer); | |
358 | ||
359 | init_mm.start_code = (unsigned long) _text; | |
360 | init_mm.end_code = (unsigned long) _etext; | |
361 | init_mm.end_data = (unsigned long) _edata; | |
362 | init_mm.brk = (unsigned long) _end; | |
363 | ||
364 | *cmdline_p = boot_command_line; | |
365 | ||
0bf757c7 | 366 | init_mem_pgprot(); |
bf4b558e | 367 | early_ioremap_init(); |
0bf757c7 | 368 | |
9703d9d7 CM |
369 | parse_early_param(); |
370 | ||
f84d0275 | 371 | efi_init(); |
9703d9d7 CM |
372 | arm64_memblock_init(); |
373 | ||
374 | paging_init(); | |
375 | request_standard_resources(); | |
376 | ||
f84d0275 MS |
377 | efi_idmap_init(); |
378 | ||
9703d9d7 CM |
379 | unflatten_device_tree(); |
380 | ||
e790f1de WD |
381 | psci_init(); |
382 | ||
4c7aa002 | 383 | cpu_logical_map(0) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; |
e8765b26 | 384 | cpu_read_bootcpu_ops(); |
9703d9d7 CM |
385 | #ifdef CONFIG_SMP |
386 | smp_init_cpus(); | |
976d7d3f | 387 | smp_build_mpidr_hash(); |
9703d9d7 CM |
388 | #endif |
389 | ||
390 | #ifdef CONFIG_VT | |
391 | #if defined(CONFIG_VGA_CONSOLE) | |
392 | conswitchp = &vga_con; | |
393 | #elif defined(CONFIG_DUMMY_CONSOLE) | |
394 | conswitchp = &dummy_con; | |
395 | #endif | |
396 | #endif | |
397 | } | |
398 | ||
c560ecfe | 399 | static int __init arm64_device_init(void) |
de79a64d CM |
400 | { |
401 | of_clk_init(NULL); | |
c560ecfe | 402 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
de79a64d CM |
403 | return 0; |
404 | } | |
c560ecfe | 405 | arch_initcall(arm64_device_init); |
de79a64d | 406 | |
9703d9d7 CM |
407 | static DEFINE_PER_CPU(struct cpu, cpu_data); |
408 | ||
409 | static int __init topology_init(void) | |
410 | { | |
411 | int i; | |
412 | ||
413 | for_each_possible_cpu(i) { | |
414 | struct cpu *cpu = &per_cpu(cpu_data, i); | |
415 | cpu->hotpluggable = 1; | |
416 | register_cpu(cpu, i); | |
417 | } | |
418 | ||
419 | return 0; | |
420 | } | |
421 | subsys_initcall(topology_init); | |
422 | ||
423 | static const char *hwcap_str[] = { | |
424 | "fp", | |
425 | "asimd", | |
46efe547 | 426 | "evtstrm", |
4bff28cc SC |
427 | "aes", |
428 | "pmull", | |
429 | "sha1", | |
430 | "sha2", | |
431 | "crc32", | |
9703d9d7 CM |
432 | NULL |
433 | }; | |
434 | ||
435 | static int c_show(struct seq_file *m, void *v) | |
436 | { | |
437 | int i; | |
438 | ||
439 | seq_printf(m, "Processor\t: %s rev %d (%s)\n", | |
440 | cpu_name, read_cpuid_id() & 15, ELF_PLATFORM); | |
441 | ||
442 | for_each_online_cpu(i) { | |
443 | /* | |
444 | * glibc reads /proc/cpuinfo to determine the number of | |
445 | * online processors, looking for lines beginning with | |
446 | * "processor". Give glibc what it expects. | |
447 | */ | |
448 | #ifdef CONFIG_SMP | |
449 | seq_printf(m, "processor\t: %d\n", i); | |
450 | #endif | |
9703d9d7 CM |
451 | } |
452 | ||
453 | /* dump out the processor features */ | |
454 | seq_puts(m, "Features\t: "); | |
455 | ||
456 | for (i = 0; hwcap_str[i]; i++) | |
457 | if (elf_hwcap & (1 << i)) | |
458 | seq_printf(m, "%s ", hwcap_str[i]); | |
459 | ||
460 | seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24); | |
461 | seq_printf(m, "CPU architecture: AArch64\n"); | |
462 | seq_printf(m, "CPU variant\t: 0x%x\n", (read_cpuid_id() >> 20) & 15); | |
463 | seq_printf(m, "CPU part\t: 0x%03x\n", (read_cpuid_id() >> 4) & 0xfff); | |
464 | seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15); | |
465 | ||
466 | seq_puts(m, "\n"); | |
467 | ||
468 | seq_printf(m, "Hardware\t: %s\n", machine_name); | |
469 | ||
470 | return 0; | |
471 | } | |
472 | ||
473 | static void *c_start(struct seq_file *m, loff_t *pos) | |
474 | { | |
475 | return *pos < 1 ? (void *)1 : NULL; | |
476 | } | |
477 | ||
478 | static void *c_next(struct seq_file *m, void *v, loff_t *pos) | |
479 | { | |
480 | ++*pos; | |
481 | return NULL; | |
482 | } | |
483 | ||
484 | static void c_stop(struct seq_file *m, void *v) | |
485 | { | |
486 | } | |
487 | ||
488 | const struct seq_operations cpuinfo_op = { | |
489 | .start = c_start, | |
490 | .next = c_next, | |
491 | .stop = c_stop, | |
492 | .show = c_show | |
493 | }; |