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9703d9d7 CM |
1 | /* |
2 | * Based on arch/arm/kernel/setup.c | |
3 | * | |
4 | * Copyright (C) 1995-2001 Russell King | |
5 | * Copyright (C) 2012 ARM Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include <linux/export.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/stddef.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/utsname.h> | |
26 | #include <linux/initrd.h> | |
27 | #include <linux/console.h> | |
a41dc0e8 | 28 | #include <linux/cache.h> |
9703d9d7 CM |
29 | #include <linux/bootmem.h> |
30 | #include <linux/seq_file.h> | |
31 | #include <linux/screen_info.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/kexec.h> | |
34 | #include <linux/crash_dump.h> | |
35 | #include <linux/root_dev.h> | |
de79a64d | 36 | #include <linux/clk-provider.h> |
9703d9d7 CM |
37 | #include <linux/cpu.h> |
38 | #include <linux/interrupt.h> | |
39 | #include <linux/smp.h> | |
40 | #include <linux/fs.h> | |
41 | #include <linux/proc_fs.h> | |
42 | #include <linux/memblock.h> | |
43 | #include <linux/of_fdt.h> | |
d6bafb9b | 44 | #include <linux/of_platform.h> |
f84d0275 | 45 | #include <linux/efi.h> |
9703d9d7 | 46 | |
bf4b558e | 47 | #include <asm/fixmap.h> |
df857416 | 48 | #include <asm/cpu.h> |
9703d9d7 CM |
49 | #include <asm/cputype.h> |
50 | #include <asm/elf.h> | |
51 | #include <asm/cputable.h> | |
e8765b26 | 52 | #include <asm/cpu_ops.h> |
9703d9d7 CM |
53 | #include <asm/sections.h> |
54 | #include <asm/setup.h> | |
4c7aa002 | 55 | #include <asm/smp_plat.h> |
9703d9d7 CM |
56 | #include <asm/cacheflush.h> |
57 | #include <asm/tlbflush.h> | |
58 | #include <asm/traps.h> | |
59 | #include <asm/memblock.h> | |
e790f1de | 60 | #include <asm/psci.h> |
f84d0275 | 61 | #include <asm/efi.h> |
9703d9d7 CM |
62 | |
63 | unsigned int processor_id; | |
64 | EXPORT_SYMBOL(processor_id); | |
65 | ||
25804e6a | 66 | unsigned long elf_hwcap __read_mostly; |
9703d9d7 CM |
67 | EXPORT_SYMBOL_GPL(elf_hwcap); |
68 | ||
46efe547 SH |
69 | #ifdef CONFIG_COMPAT |
70 | #define COMPAT_ELF_HWCAP_DEFAULT \ | |
71 | (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ | |
72 | COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ | |
73 | COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\ | |
74 | COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\ | |
75 | COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV) | |
76 | unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; | |
28964d32 | 77 | unsigned int compat_elf_hwcap2 __read_mostly; |
46efe547 SH |
78 | #endif |
79 | ||
9703d9d7 | 80 | static const char *cpu_name; |
5e39977e | 81 | static const char *machine_name; |
9703d9d7 CM |
82 | phys_addr_t __fdt_pointer __initdata; |
83 | ||
84 | /* | |
85 | * Standard memory resources | |
86 | */ | |
87 | static struct resource mem_res[] = { | |
88 | { | |
89 | .name = "Kernel code", | |
90 | .start = 0, | |
91 | .end = 0, | |
92 | .flags = IORESOURCE_MEM | |
93 | }, | |
94 | { | |
95 | .name = "Kernel data", | |
96 | .start = 0, | |
97 | .end = 0, | |
98 | .flags = IORESOURCE_MEM | |
99 | } | |
100 | }; | |
101 | ||
102 | #define kernel_code mem_res[0] | |
103 | #define kernel_data mem_res[1] | |
104 | ||
105 | void __init early_print(const char *str, ...) | |
106 | { | |
107 | char buf[256]; | |
108 | va_list ap; | |
109 | ||
110 | va_start(ap, str); | |
111 | vsnprintf(buf, sizeof(buf), str, ap); | |
112 | va_end(ap); | |
113 | ||
114 | printk("%s", buf); | |
115 | } | |
116 | ||
71586276 WD |
117 | void __init smp_setup_processor_id(void) |
118 | { | |
119 | /* | |
120 | * clear __my_cpu_offset on boot CPU to avoid hang caused by | |
121 | * using percpu variable early, for example, lockdep will | |
122 | * access percpu variable inside lock_release | |
123 | */ | |
124 | set_my_cpu_offset(0); | |
125 | } | |
126 | ||
6e15d0e0 SH |
127 | bool arch_match_cpu_phys_id(int cpu, u64 phys_id) |
128 | { | |
129 | return phys_id == cpu_logical_map(cpu); | |
130 | } | |
131 | ||
976d7d3f LP |
132 | struct mpidr_hash mpidr_hash; |
133 | #ifdef CONFIG_SMP | |
134 | /** | |
135 | * smp_build_mpidr_hash - Pre-compute shifts required at each affinity | |
136 | * level in order to build a linear index from an | |
137 | * MPIDR value. Resulting algorithm is a collision | |
138 | * free hash carried out through shifting and ORing | |
139 | */ | |
140 | static void __init smp_build_mpidr_hash(void) | |
141 | { | |
142 | u32 i, affinity, fs[4], bits[4], ls; | |
143 | u64 mask = 0; | |
144 | /* | |
145 | * Pre-scan the list of MPIDRS and filter out bits that do | |
146 | * not contribute to affinity levels, ie they never toggle. | |
147 | */ | |
148 | for_each_possible_cpu(i) | |
149 | mask |= (cpu_logical_map(i) ^ cpu_logical_map(0)); | |
150 | pr_debug("mask of set bits %#llx\n", mask); | |
151 | /* | |
152 | * Find and stash the last and first bit set at all affinity levels to | |
153 | * check how many bits are required to represent them. | |
154 | */ | |
155 | for (i = 0; i < 4; i++) { | |
156 | affinity = MPIDR_AFFINITY_LEVEL(mask, i); | |
157 | /* | |
158 | * Find the MSB bit and LSB bits position | |
159 | * to determine how many bits are required | |
160 | * to express the affinity level. | |
161 | */ | |
162 | ls = fls(affinity); | |
163 | fs[i] = affinity ? ffs(affinity) - 1 : 0; | |
164 | bits[i] = ls - fs[i]; | |
165 | } | |
166 | /* | |
167 | * An index can be created from the MPIDR_EL1 by isolating the | |
168 | * significant bits at each affinity level and by shifting | |
169 | * them in order to compress the 32 bits values space to a | |
170 | * compressed set of values. This is equivalent to hashing | |
171 | * the MPIDR_EL1 through shifting and ORing. It is a collision free | |
172 | * hash though not minimal since some levels might contain a number | |
173 | * of CPUs that is not an exact power of 2 and their bit | |
174 | * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}. | |
175 | */ | |
176 | mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0]; | |
177 | mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0]; | |
178 | mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] - | |
179 | (bits[1] + bits[0]); | |
180 | mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) + | |
181 | fs[3] - (bits[2] + bits[1] + bits[0]); | |
182 | mpidr_hash.mask = mask; | |
183 | mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0]; | |
184 | pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n", | |
185 | mpidr_hash.shift_aff[0], | |
186 | mpidr_hash.shift_aff[1], | |
187 | mpidr_hash.shift_aff[2], | |
188 | mpidr_hash.shift_aff[3], | |
189 | mpidr_hash.mask, | |
190 | mpidr_hash.bits); | |
191 | /* | |
192 | * 4x is an arbitrary value used to warn on a hash table much bigger | |
193 | * than expected on most systems. | |
194 | */ | |
195 | if (mpidr_hash_size() > 4 * num_possible_cpus()) | |
196 | pr_warn("Large number of MPIDR hash buckets detected\n"); | |
197 | __flush_dcache_area(&mpidr_hash, sizeof(struct mpidr_hash)); | |
198 | } | |
199 | #endif | |
200 | ||
9703d9d7 CM |
201 | static void __init setup_processor(void) |
202 | { | |
203 | struct cpu_info *cpu_info; | |
4bff28cc | 204 | u64 features, block; |
a41dc0e8 CM |
205 | u32 cwg; |
206 | int cls; | |
9703d9d7 | 207 | |
9703d9d7 CM |
208 | cpu_info = lookup_processor_type(read_cpuid_id()); |
209 | if (!cpu_info) { | |
210 | printk("CPU configuration botched (ID %08x), unable to continue.\n", | |
211 | read_cpuid_id()); | |
212 | while (1); | |
213 | } | |
214 | ||
215 | cpu_name = cpu_info->cpu_name; | |
216 | ||
217 | printk("CPU: %s [%08x] revision %d\n", | |
218 | cpu_name, read_cpuid_id(), read_cpuid_id() & 15); | |
219 | ||
94ed1f2c | 220 | sprintf(init_utsname()->machine, ELF_PLATFORM); |
9703d9d7 | 221 | elf_hwcap = 0; |
4bff28cc | 222 | |
df857416 MR |
223 | cpuinfo_store_boot_cpu(); |
224 | ||
a41dc0e8 CM |
225 | /* |
226 | * Check for sane CTR_EL0.CWG value. | |
227 | */ | |
228 | cwg = cache_type_cwg(); | |
229 | cls = cache_line_size(); | |
230 | if (!cwg) | |
231 | pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n", | |
232 | cls); | |
233 | if (L1_CACHE_BYTES < cls) | |
234 | pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n", | |
235 | L1_CACHE_BYTES, cls); | |
236 | ||
4bff28cc SC |
237 | /* |
238 | * ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks. | |
239 | * The blocks we test below represent incremental functionality | |
240 | * for non-negative values. Negative values are reserved. | |
241 | */ | |
242 | features = read_cpuid(ID_AA64ISAR0_EL1); | |
243 | block = (features >> 4) & 0xf; | |
244 | if (!(block & 0x8)) { | |
245 | switch (block) { | |
246 | default: | |
247 | case 2: | |
248 | elf_hwcap |= HWCAP_PMULL; | |
249 | case 1: | |
250 | elf_hwcap |= HWCAP_AES; | |
251 | case 0: | |
252 | break; | |
253 | } | |
254 | } | |
255 | ||
256 | block = (features >> 8) & 0xf; | |
257 | if (block && !(block & 0x8)) | |
258 | elf_hwcap |= HWCAP_SHA1; | |
259 | ||
260 | block = (features >> 12) & 0xf; | |
261 | if (block && !(block & 0x8)) | |
262 | elf_hwcap |= HWCAP_SHA2; | |
263 | ||
264 | block = (features >> 16) & 0xf; | |
265 | if (block && !(block & 0x8)) | |
266 | elf_hwcap |= HWCAP_CRC32; | |
4cf761cd AB |
267 | |
268 | #ifdef CONFIG_COMPAT | |
269 | /* | |
270 | * ID_ISAR5_EL1 carries similar information as above, but pertaining to | |
271 | * the Aarch32 32-bit execution state. | |
272 | */ | |
273 | features = read_cpuid(ID_ISAR5_EL1); | |
274 | block = (features >> 4) & 0xf; | |
275 | if (!(block & 0x8)) { | |
276 | switch (block) { | |
277 | default: | |
278 | case 2: | |
279 | compat_elf_hwcap2 |= COMPAT_HWCAP2_PMULL; | |
280 | case 1: | |
281 | compat_elf_hwcap2 |= COMPAT_HWCAP2_AES; | |
282 | case 0: | |
283 | break; | |
284 | } | |
285 | } | |
286 | ||
287 | block = (features >> 8) & 0xf; | |
288 | if (block && !(block & 0x8)) | |
289 | compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA1; | |
290 | ||
291 | block = (features >> 12) & 0xf; | |
292 | if (block && !(block & 0x8)) | |
293 | compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA2; | |
294 | ||
295 | block = (features >> 16) & 0xf; | |
296 | if (block && !(block & 0x8)) | |
297 | compat_elf_hwcap2 |= COMPAT_HWCAP2_CRC32; | |
298 | #endif | |
9703d9d7 CM |
299 | } |
300 | ||
301 | static void __init setup_machine_fdt(phys_addr_t dt_phys) | |
302 | { | |
d5189cc5 | 303 | if (!dt_phys || !early_init_dt_scan(phys_to_virt(dt_phys))) { |
9703d9d7 CM |
304 | early_print("\n" |
305 | "Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n" | |
d5189cc5 | 306 | "The dtb must be 8-byte aligned and passed in the first 512MB of memory\n" |
9703d9d7 | 307 | "\nPlease check your bootloader.\n", |
d5189cc5 | 308 | dt_phys, phys_to_virt(dt_phys)); |
9703d9d7 CM |
309 | |
310 | while (true) | |
311 | cpu_relax(); | |
312 | } | |
5e39977e WD |
313 | |
314 | machine_name = of_flat_dt_get_machine_name(); | |
9703d9d7 CM |
315 | } |
316 | ||
9703d9d7 CM |
317 | /* |
318 | * Limit the memory size that was specified via FDT. | |
319 | */ | |
320 | static int __init early_mem(char *p) | |
321 | { | |
322 | phys_addr_t limit; | |
323 | ||
324 | if (!p) | |
325 | return 1; | |
326 | ||
327 | limit = memparse(p, &p) & PAGE_MASK; | |
328 | pr_notice("Memory limited to %lldMB\n", limit >> 20); | |
329 | ||
330 | memblock_enforce_memory_limit(limit); | |
331 | ||
332 | return 0; | |
333 | } | |
334 | early_param("mem", early_mem); | |
335 | ||
336 | static void __init request_standard_resources(void) | |
337 | { | |
338 | struct memblock_region *region; | |
339 | struct resource *res; | |
340 | ||
341 | kernel_code.start = virt_to_phys(_text); | |
342 | kernel_code.end = virt_to_phys(_etext - 1); | |
343 | kernel_data.start = virt_to_phys(_sdata); | |
344 | kernel_data.end = virt_to_phys(_end - 1); | |
345 | ||
346 | for_each_memblock(memory, region) { | |
347 | res = alloc_bootmem_low(sizeof(*res)); | |
348 | res->name = "System RAM"; | |
349 | res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region)); | |
350 | res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1; | |
351 | res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
352 | ||
353 | request_resource(&iomem_resource, res); | |
354 | ||
355 | if (kernel_code.start >= res->start && | |
356 | kernel_code.end <= res->end) | |
357 | request_resource(res, &kernel_code); | |
358 | if (kernel_data.start >= res->start && | |
359 | kernel_data.end <= res->end) | |
360 | request_resource(res, &kernel_data); | |
361 | } | |
362 | } | |
363 | ||
4c7aa002 JM |
364 | u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID }; |
365 | ||
9703d9d7 CM |
366 | void __init setup_arch(char **cmdline_p) |
367 | { | |
b3bf6aa7 CM |
368 | /* |
369 | * Unmask asynchronous aborts early to catch possible system errors. | |
370 | */ | |
371 | local_async_enable(); | |
372 | ||
9703d9d7 CM |
373 | setup_processor(); |
374 | ||
375 | setup_machine_fdt(__fdt_pointer); | |
376 | ||
377 | init_mm.start_code = (unsigned long) _text; | |
378 | init_mm.end_code = (unsigned long) _etext; | |
379 | init_mm.end_data = (unsigned long) _edata; | |
380 | init_mm.brk = (unsigned long) _end; | |
381 | ||
382 | *cmdline_p = boot_command_line; | |
383 | ||
bf4b558e | 384 | early_ioremap_init(); |
0bf757c7 | 385 | |
9703d9d7 CM |
386 | parse_early_param(); |
387 | ||
f84d0275 | 388 | efi_init(); |
9703d9d7 CM |
389 | arm64_memblock_init(); |
390 | ||
391 | paging_init(); | |
392 | request_standard_resources(); | |
393 | ||
f84d0275 MS |
394 | efi_idmap_init(); |
395 | ||
9703d9d7 CM |
396 | unflatten_device_tree(); |
397 | ||
e790f1de WD |
398 | psci_init(); |
399 | ||
4c7aa002 | 400 | cpu_logical_map(0) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; |
e8765b26 | 401 | cpu_read_bootcpu_ops(); |
9703d9d7 CM |
402 | #ifdef CONFIG_SMP |
403 | smp_init_cpus(); | |
976d7d3f | 404 | smp_build_mpidr_hash(); |
9703d9d7 CM |
405 | #endif |
406 | ||
407 | #ifdef CONFIG_VT | |
408 | #if defined(CONFIG_VGA_CONSOLE) | |
409 | conswitchp = &vga_con; | |
410 | #elif defined(CONFIG_DUMMY_CONSOLE) | |
411 | conswitchp = &dummy_con; | |
412 | #endif | |
413 | #endif | |
414 | } | |
415 | ||
c560ecfe | 416 | static int __init arm64_device_init(void) |
de79a64d | 417 | { |
c560ecfe | 418 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
de79a64d CM |
419 | return 0; |
420 | } | |
6ecba8eb | 421 | arch_initcall_sync(arm64_device_init); |
de79a64d | 422 | |
9703d9d7 CM |
423 | static int __init topology_init(void) |
424 | { | |
425 | int i; | |
426 | ||
427 | for_each_possible_cpu(i) { | |
df857416 | 428 | struct cpu *cpu = &per_cpu(cpu_data.cpu, i); |
9703d9d7 CM |
429 | cpu->hotpluggable = 1; |
430 | register_cpu(cpu, i); | |
431 | } | |
432 | ||
433 | return 0; | |
434 | } | |
435 | subsys_initcall(topology_init); | |
436 | ||
437 | static const char *hwcap_str[] = { | |
438 | "fp", | |
439 | "asimd", | |
46efe547 | 440 | "evtstrm", |
4bff28cc SC |
441 | "aes", |
442 | "pmull", | |
443 | "sha1", | |
444 | "sha2", | |
445 | "crc32", | |
9703d9d7 CM |
446 | NULL |
447 | }; | |
448 | ||
449 | static int c_show(struct seq_file *m, void *v) | |
450 | { | |
451 | int i; | |
452 | ||
5e39977e WD |
453 | seq_printf(m, "Processor\t: %s rev %d (%s)\n", |
454 | cpu_name, read_cpuid_id() & 15, ELF_PLATFORM); | |
9703d9d7 CM |
455 | |
456 | for_each_online_cpu(i) { | |
457 | /* | |
458 | * glibc reads /proc/cpuinfo to determine the number of | |
459 | * online processors, looking for lines beginning with | |
460 | * "processor". Give glibc what it expects. | |
461 | */ | |
462 | #ifdef CONFIG_SMP | |
463 | seq_printf(m, "processor\t: %d\n", i); | |
464 | #endif | |
9703d9d7 CM |
465 | } |
466 | ||
5e39977e WD |
467 | /* dump out the processor features */ |
468 | seq_puts(m, "Features\t: "); | |
469 | ||
470 | for (i = 0; hwcap_str[i]; i++) | |
471 | if (elf_hwcap & (1 << i)) | |
472 | seq_printf(m, "%s ", hwcap_str[i]); | |
473 | ||
474 | seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24); | |
475 | seq_printf(m, "CPU architecture: AArch64\n"); | |
476 | seq_printf(m, "CPU variant\t: 0x%x\n", (read_cpuid_id() >> 20) & 15); | |
477 | seq_printf(m, "CPU part\t: 0x%03x\n", (read_cpuid_id() >> 4) & 0xfff); | |
478 | seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15); | |
479 | ||
480 | seq_puts(m, "\n"); | |
481 | ||
482 | seq_printf(m, "Hardware\t: %s\n", machine_name); | |
483 | ||
9703d9d7 CM |
484 | return 0; |
485 | } | |
486 | ||
487 | static void *c_start(struct seq_file *m, loff_t *pos) | |
488 | { | |
489 | return *pos < 1 ? (void *)1 : NULL; | |
490 | } | |
491 | ||
492 | static void *c_next(struct seq_file *m, void *v, loff_t *pos) | |
493 | { | |
494 | ++*pos; | |
495 | return NULL; | |
496 | } | |
497 | ||
498 | static void c_stop(struct seq_file *m, void *v) | |
499 | { | |
500 | } | |
501 | ||
502 | const struct seq_operations cpuinfo_op = { | |
503 | .start = c_start, | |
504 | .next = c_next, | |
505 | .stop = c_stop, | |
506 | .show = c_show | |
507 | }; |