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Commit | Line | Data |
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08e875c1 CM |
1 | /* |
2 | * SMP initialisation and IPI support | |
3 | * Based on arch/arm/kernel/smp.c | |
4 | * | |
5 | * Copyright (C) 2012 ARM Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
0f078336 | 20 | #include <linux/acpi.h> |
08e875c1 CM |
21 | #include <linux/delay.h> |
22 | #include <linux/init.h> | |
23 | #include <linux/spinlock.h> | |
24 | #include <linux/sched.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/cache.h> | |
27 | #include <linux/profile.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/mm.h> | |
30 | #include <linux/err.h> | |
31 | #include <linux/cpu.h> | |
32 | #include <linux/smp.h> | |
33 | #include <linux/seq_file.h> | |
34 | #include <linux/irq.h> | |
35 | #include <linux/percpu.h> | |
36 | #include <linux/clockchips.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/of.h> | |
eb631bb5 | 39 | #include <linux/irq_work.h> |
08e875c1 | 40 | |
e039ee4e | 41 | #include <asm/alternative.h> |
08e875c1 CM |
42 | #include <asm/atomic.h> |
43 | #include <asm/cacheflush.h> | |
df857416 | 44 | #include <asm/cpu.h> |
08e875c1 | 45 | #include <asm/cputype.h> |
cd1aebf5 | 46 | #include <asm/cpu_ops.h> |
08e875c1 CM |
47 | #include <asm/mmu_context.h> |
48 | #include <asm/pgtable.h> | |
49 | #include <asm/pgalloc.h> | |
50 | #include <asm/processor.h> | |
4c7aa002 | 51 | #include <asm/smp_plat.h> |
08e875c1 CM |
52 | #include <asm/sections.h> |
53 | #include <asm/tlbflush.h> | |
54 | #include <asm/ptrace.h> | |
377bcff9 | 55 | #include <asm/virt.h> |
08e875c1 | 56 | |
45ed695a NP |
57 | #define CREATE_TRACE_POINTS |
58 | #include <trace/events/ipi.h> | |
59 | ||
08e875c1 CM |
60 | /* |
61 | * as from 2.5, kernels no longer have an init_tasks structure | |
62 | * so we need some other way of telling a new secondary core | |
63 | * where to place its SVC stack | |
64 | */ | |
65 | struct secondary_data secondary_data; | |
08e875c1 CM |
66 | |
67 | enum ipi_msg_type { | |
68 | IPI_RESCHEDULE, | |
69 | IPI_CALL_FUNC, | |
08e875c1 | 70 | IPI_CPU_STOP, |
1f85008e | 71 | IPI_TIMER, |
eb631bb5 | 72 | IPI_IRQ_WORK, |
08e875c1 CM |
73 | }; |
74 | ||
08e875c1 CM |
75 | /* |
76 | * Boot a secondary CPU, and assign it the specified idle task. | |
77 | * This also gives us the initial stack to use for this CPU. | |
78 | */ | |
b8c6453a | 79 | static int boot_secondary(unsigned int cpu, struct task_struct *idle) |
08e875c1 | 80 | { |
652af899 MR |
81 | if (cpu_ops[cpu]->cpu_boot) |
82 | return cpu_ops[cpu]->cpu_boot(cpu); | |
08e875c1 | 83 | |
652af899 | 84 | return -EOPNOTSUPP; |
08e875c1 CM |
85 | } |
86 | ||
87 | static DECLARE_COMPLETION(cpu_running); | |
88 | ||
b8c6453a | 89 | int __cpu_up(unsigned int cpu, struct task_struct *idle) |
08e875c1 CM |
90 | { |
91 | int ret; | |
92 | ||
93 | /* | |
94 | * We need to tell the secondary core where to find its stack and the | |
95 | * page tables. | |
96 | */ | |
97 | secondary_data.stack = task_stack_page(idle) + THREAD_START_SP; | |
98 | __flush_dcache_area(&secondary_data, sizeof(secondary_data)); | |
99 | ||
100 | /* | |
101 | * Now bring the CPU into our world. | |
102 | */ | |
103 | ret = boot_secondary(cpu, idle); | |
104 | if (ret == 0) { | |
105 | /* | |
106 | * CPU was successfully started, wait for it to come online or | |
107 | * time out. | |
108 | */ | |
109 | wait_for_completion_timeout(&cpu_running, | |
110 | msecs_to_jiffies(1000)); | |
111 | ||
112 | if (!cpu_online(cpu)) { | |
113 | pr_crit("CPU%u: failed to come online\n", cpu); | |
114 | ret = -EIO; | |
115 | } | |
116 | } else { | |
117 | pr_err("CPU%u: failed to boot: %d\n", cpu, ret); | |
118 | } | |
119 | ||
120 | secondary_data.stack = NULL; | |
121 | ||
122 | return ret; | |
123 | } | |
124 | ||
f6e763b9 MB |
125 | static void smp_store_cpu_info(unsigned int cpuid) |
126 | { | |
127 | store_cpu_topology(cpuid); | |
128 | } | |
129 | ||
08e875c1 CM |
130 | /* |
131 | * This is the secondary CPU boot entry. We're using this CPUs | |
132 | * idle thread stack, but a set of temporary page tables. | |
133 | */ | |
b8c6453a | 134 | asmlinkage void secondary_start_kernel(void) |
08e875c1 CM |
135 | { |
136 | struct mm_struct *mm = &init_mm; | |
137 | unsigned int cpu = smp_processor_id(); | |
138 | ||
08e875c1 CM |
139 | /* |
140 | * All kernel threads share the same mm context; grab a | |
141 | * reference and switch to it. | |
142 | */ | |
143 | atomic_inc(&mm->mm_count); | |
144 | current->active_mm = mm; | |
08e875c1 | 145 | |
71586276 | 146 | set_my_cpu_offset(per_cpu_offset(smp_processor_id())); |
71586276 | 147 | |
08e875c1 CM |
148 | /* |
149 | * TTBR0 is only used for the identity mapping at this stage. Make it | |
150 | * point to zero page to avoid speculatively fetching new entries. | |
151 | */ | |
152 | cpu_set_reserved_ttbr0(); | |
8e63d388 | 153 | local_flush_tlb_all(); |
dd006da2 | 154 | cpu_set_default_tcr_t0sz(); |
08e875c1 CM |
155 | |
156 | preempt_disable(); | |
157 | trace_hardirqs_off(); | |
158 | ||
652af899 MR |
159 | if (cpu_ops[cpu]->cpu_postboot) |
160 | cpu_ops[cpu]->cpu_postboot(); | |
08e875c1 | 161 | |
df857416 MR |
162 | /* |
163 | * Log the CPU info before it is marked online and might get read. | |
164 | */ | |
165 | cpuinfo_store_cpu(); | |
166 | ||
7ade67b5 MZ |
167 | /* |
168 | * Enable GIC and timers. | |
169 | */ | |
170 | notify_cpu_starting(cpu); | |
171 | ||
f6e763b9 MB |
172 | smp_store_cpu_info(cpu); |
173 | ||
08e875c1 CM |
174 | /* |
175 | * OK, now it's safe to let the boot CPU continue. Wait for | |
176 | * the CPU migration code to notice that the CPU is online | |
177 | * before we continue. | |
178 | */ | |
64f17818 SP |
179 | pr_info("CPU%u: Booted secondary processor [%08x]\n", |
180 | cpu, read_cpuid_id()); | |
08e875c1 | 181 | set_cpu_online(cpu, true); |
b3770b32 | 182 | complete(&cpu_running); |
08e875c1 | 183 | |
d8ed442a | 184 | local_dbg_enable(); |
53ae3acd | 185 | local_irq_enable(); |
b3bf6aa7 | 186 | local_async_enable(); |
53ae3acd | 187 | |
08e875c1 CM |
188 | /* |
189 | * OK, it's off to the idle thread for us | |
190 | */ | |
0087298f | 191 | cpu_startup_entry(CPUHP_ONLINE); |
08e875c1 CM |
192 | } |
193 | ||
9327e2c6 MR |
194 | #ifdef CONFIG_HOTPLUG_CPU |
195 | static int op_cpu_disable(unsigned int cpu) | |
196 | { | |
197 | /* | |
198 | * If we don't have a cpu_die method, abort before we reach the point | |
199 | * of no return. CPU0 may not have an cpu_ops, so test for it. | |
200 | */ | |
201 | if (!cpu_ops[cpu] || !cpu_ops[cpu]->cpu_die) | |
202 | return -EOPNOTSUPP; | |
203 | ||
204 | /* | |
205 | * We may need to abort a hot unplug for some other mechanism-specific | |
206 | * reason. | |
207 | */ | |
208 | if (cpu_ops[cpu]->cpu_disable) | |
209 | return cpu_ops[cpu]->cpu_disable(cpu); | |
210 | ||
211 | return 0; | |
212 | } | |
213 | ||
214 | /* | |
215 | * __cpu_disable runs on the processor to be shutdown. | |
216 | */ | |
217 | int __cpu_disable(void) | |
218 | { | |
219 | unsigned int cpu = smp_processor_id(); | |
220 | int ret; | |
221 | ||
222 | ret = op_cpu_disable(cpu); | |
223 | if (ret) | |
224 | return ret; | |
225 | ||
226 | /* | |
227 | * Take this CPU offline. Once we clear this, we can't return, | |
228 | * and we must not schedule until we're ready to give up the cpu. | |
229 | */ | |
230 | set_cpu_online(cpu, false); | |
231 | ||
232 | /* | |
233 | * OK - migrate IRQs away from this CPU | |
234 | */ | |
217d453d YY |
235 | irq_migrate_all_off_this_cpu(); |
236 | ||
9327e2c6 MR |
237 | return 0; |
238 | } | |
239 | ||
c814ca02 AC |
240 | static int op_cpu_kill(unsigned int cpu) |
241 | { | |
242 | /* | |
243 | * If we have no means of synchronising with the dying CPU, then assume | |
244 | * that it is really dead. We can only wait for an arbitrary length of | |
245 | * time and hope that it's dead, so let's skip the wait and just hope. | |
246 | */ | |
247 | if (!cpu_ops[cpu]->cpu_kill) | |
6b99c68c | 248 | return 0; |
c814ca02 AC |
249 | |
250 | return cpu_ops[cpu]->cpu_kill(cpu); | |
251 | } | |
252 | ||
9327e2c6 MR |
253 | /* |
254 | * called on the thread which is asking for a CPU to be shutdown - | |
255 | * waits until shutdown has completed, or it is timed out. | |
256 | */ | |
257 | void __cpu_die(unsigned int cpu) | |
258 | { | |
6b99c68c MR |
259 | int err; |
260 | ||
05981277 | 261 | if (!cpu_wait_death(cpu, 5)) { |
9327e2c6 MR |
262 | pr_crit("CPU%u: cpu didn't die\n", cpu); |
263 | return; | |
264 | } | |
265 | pr_notice("CPU%u: shutdown\n", cpu); | |
c814ca02 AC |
266 | |
267 | /* | |
268 | * Now that the dying CPU is beyond the point of no return w.r.t. | |
269 | * in-kernel synchronisation, try to get the firwmare to help us to | |
270 | * verify that it has really left the kernel before we consider | |
271 | * clobbering anything it might still be using. | |
272 | */ | |
6b99c68c MR |
273 | err = op_cpu_kill(cpu); |
274 | if (err) | |
275 | pr_warn("CPU%d may not have shut down cleanly: %d\n", | |
276 | cpu, err); | |
9327e2c6 MR |
277 | } |
278 | ||
279 | /* | |
280 | * Called from the idle thread for the CPU which has been shutdown. | |
281 | * | |
282 | * Note that we disable IRQs here, but do not re-enable them | |
283 | * before returning to the caller. This is also the behaviour | |
284 | * of the other hotplug-cpu capable cores, so presumably coming | |
285 | * out of idle fixes this. | |
286 | */ | |
287 | void cpu_die(void) | |
288 | { | |
289 | unsigned int cpu = smp_processor_id(); | |
290 | ||
291 | idle_task_exit(); | |
292 | ||
293 | local_irq_disable(); | |
294 | ||
295 | /* Tell __cpu_die() that this CPU is now safe to dispose of */ | |
05981277 | 296 | (void)cpu_report_death(); |
9327e2c6 MR |
297 | |
298 | /* | |
299 | * Actually shutdown the CPU. This must never fail. The specific hotplug | |
300 | * mechanism must perform all required cache maintenance to ensure that | |
301 | * no dirty lines are lost in the process of shutting down the CPU. | |
302 | */ | |
303 | cpu_ops[cpu]->cpu_die(cpu); | |
304 | ||
305 | BUG(); | |
306 | } | |
307 | #endif | |
308 | ||
377bcff9 JR |
309 | static void __init hyp_mode_check(void) |
310 | { | |
311 | if (is_hyp_mode_available()) | |
312 | pr_info("CPU: All CPU(s) started at EL2\n"); | |
313 | else if (is_hyp_mode_mismatched()) | |
314 | WARN_TAINT(1, TAINT_CPU_OUT_OF_SPEC, | |
315 | "CPU: CPUs started in inconsistent modes"); | |
316 | else | |
317 | pr_info("CPU: All CPU(s) started at EL1\n"); | |
318 | } | |
319 | ||
08e875c1 CM |
320 | void __init smp_cpus_done(unsigned int max_cpus) |
321 | { | |
326b16db | 322 | pr_info("SMP: Total of %d processors activated.\n", num_online_cpus()); |
3a75578e | 323 | setup_cpu_features(); |
377bcff9 JR |
324 | hyp_mode_check(); |
325 | apply_alternatives_all(); | |
08e875c1 CM |
326 | } |
327 | ||
328 | void __init smp_prepare_boot_cpu(void) | |
329 | { | |
71586276 | 330 | set_my_cpu_offset(per_cpu_offset(smp_processor_id())); |
08e875c1 CM |
331 | } |
332 | ||
0f078336 LP |
333 | static u64 __init of_get_cpu_mpidr(struct device_node *dn) |
334 | { | |
335 | const __be32 *cell; | |
336 | u64 hwid; | |
337 | ||
338 | /* | |
339 | * A cpu node with missing "reg" property is | |
340 | * considered invalid to build a cpu_logical_map | |
341 | * entry. | |
342 | */ | |
343 | cell = of_get_property(dn, "reg", NULL); | |
344 | if (!cell) { | |
345 | pr_err("%s: missing reg property\n", dn->full_name); | |
346 | return INVALID_HWID; | |
347 | } | |
348 | ||
349 | hwid = of_read_number(cell, of_n_addr_cells(dn)); | |
350 | /* | |
351 | * Non affinity bits must be set to 0 in the DT | |
352 | */ | |
353 | if (hwid & ~MPIDR_HWID_BITMASK) { | |
354 | pr_err("%s: invalid reg property\n", dn->full_name); | |
355 | return INVALID_HWID; | |
356 | } | |
357 | return hwid; | |
358 | } | |
359 | ||
360 | /* | |
361 | * Duplicate MPIDRs are a recipe for disaster. Scan all initialized | |
362 | * entries and check for duplicates. If any is found just ignore the | |
363 | * cpu. cpu_logical_map was initialized to INVALID_HWID to avoid | |
364 | * matching valid MPIDR values. | |
365 | */ | |
366 | static bool __init is_mpidr_duplicate(unsigned int cpu, u64 hwid) | |
367 | { | |
368 | unsigned int i; | |
369 | ||
370 | for (i = 1; (i < cpu) && (i < NR_CPUS); i++) | |
371 | if (cpu_logical_map(i) == hwid) | |
372 | return true; | |
373 | return false; | |
374 | } | |
375 | ||
819a8826 LP |
376 | /* |
377 | * Initialize cpu operations for a logical cpu and | |
378 | * set it in the possible mask on success | |
379 | */ | |
380 | static int __init smp_cpu_setup(int cpu) | |
381 | { | |
382 | if (cpu_read_ops(cpu)) | |
383 | return -ENODEV; | |
384 | ||
385 | if (cpu_ops[cpu]->cpu_init(cpu)) | |
386 | return -ENODEV; | |
387 | ||
388 | set_cpu_possible(cpu, true); | |
389 | ||
390 | return 0; | |
391 | } | |
392 | ||
0f078336 LP |
393 | static bool bootcpu_valid __initdata; |
394 | static unsigned int cpu_count = 1; | |
395 | ||
396 | #ifdef CONFIG_ACPI | |
397 | /* | |
398 | * acpi_map_gic_cpu_interface - parse processor MADT entry | |
399 | * | |
400 | * Carry out sanity checks on MADT processor entry and initialize | |
401 | * cpu_logical_map on success | |
402 | */ | |
403 | static void __init | |
404 | acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor) | |
405 | { | |
406 | u64 hwid = processor->arm_mpidr; | |
407 | ||
f9058929 HG |
408 | if (!(processor->flags & ACPI_MADT_ENABLED)) { |
409 | pr_debug("skipping disabled CPU entry with 0x%llx MPIDR\n", hwid); | |
0f078336 LP |
410 | return; |
411 | } | |
412 | ||
f9058929 HG |
413 | if (hwid & ~MPIDR_HWID_BITMASK || hwid == INVALID_HWID) { |
414 | pr_err("skipping CPU entry with invalid MPIDR 0x%llx\n", hwid); | |
0f078336 LP |
415 | return; |
416 | } | |
417 | ||
418 | if (is_mpidr_duplicate(cpu_count, hwid)) { | |
419 | pr_err("duplicate CPU MPIDR 0x%llx in MADT\n", hwid); | |
420 | return; | |
421 | } | |
422 | ||
423 | /* Check if GICC structure of boot CPU is available in the MADT */ | |
424 | if (cpu_logical_map(0) == hwid) { | |
425 | if (bootcpu_valid) { | |
426 | pr_err("duplicate boot CPU MPIDR: 0x%llx in MADT\n", | |
427 | hwid); | |
428 | return; | |
429 | } | |
430 | bootcpu_valid = true; | |
431 | return; | |
432 | } | |
433 | ||
434 | if (cpu_count >= NR_CPUS) | |
435 | return; | |
436 | ||
437 | /* map the logical cpu id to cpu MPIDR */ | |
438 | cpu_logical_map(cpu_count) = hwid; | |
439 | ||
440 | cpu_count++; | |
441 | } | |
442 | ||
443 | static int __init | |
444 | acpi_parse_gic_cpu_interface(struct acpi_subtable_header *header, | |
445 | const unsigned long end) | |
446 | { | |
447 | struct acpi_madt_generic_interrupt *processor; | |
448 | ||
449 | processor = (struct acpi_madt_generic_interrupt *)header; | |
99e3e3ae | 450 | if (BAD_MADT_GICC_ENTRY(processor, end)) |
0f078336 LP |
451 | return -EINVAL; |
452 | ||
453 | acpi_table_print_madt_entry(header); | |
454 | ||
455 | acpi_map_gic_cpu_interface(processor); | |
456 | ||
457 | return 0; | |
458 | } | |
459 | #else | |
460 | #define acpi_table_parse_madt(...) do { } while (0) | |
461 | #endif | |
462 | ||
08e875c1 | 463 | /* |
4c7aa002 JM |
464 | * Enumerate the possible CPU set from the device tree and build the |
465 | * cpu logical map array containing MPIDR values related to logical | |
466 | * cpus. Assumes that cpu_logical_map(0) has already been initialized. | |
08e875c1 | 467 | */ |
0f078336 | 468 | void __init of_parse_and_init_cpus(void) |
08e875c1 | 469 | { |
08e875c1 | 470 | struct device_node *dn = NULL; |
08e875c1 CM |
471 | |
472 | while ((dn = of_find_node_by_type(dn, "cpu"))) { | |
0f078336 | 473 | u64 hwid = of_get_cpu_mpidr(dn); |
4c7aa002 | 474 | |
0f078336 | 475 | if (hwid == INVALID_HWID) |
4c7aa002 | 476 | goto next; |
4c7aa002 | 477 | |
0f078336 LP |
478 | if (is_mpidr_duplicate(cpu_count, hwid)) { |
479 | pr_err("%s: duplicate cpu reg properties in the DT\n", | |
480 | dn->full_name); | |
4c7aa002 JM |
481 | goto next; |
482 | } | |
483 | ||
4c7aa002 JM |
484 | /* |
485 | * The numbering scheme requires that the boot CPU | |
486 | * must be assigned logical id 0. Record it so that | |
487 | * the logical map built from DT is validated and can | |
488 | * be used. | |
489 | */ | |
490 | if (hwid == cpu_logical_map(0)) { | |
491 | if (bootcpu_valid) { | |
492 | pr_err("%s: duplicate boot cpu reg property in DT\n", | |
493 | dn->full_name); | |
494 | goto next; | |
495 | } | |
496 | ||
497 | bootcpu_valid = true; | |
498 | ||
499 | /* | |
500 | * cpu_logical_map has already been | |
501 | * initialized and the boot cpu doesn't need | |
502 | * the enable-method so continue without | |
503 | * incrementing cpu. | |
504 | */ | |
505 | continue; | |
506 | } | |
507 | ||
0f078336 | 508 | if (cpu_count >= NR_CPUS) |
08e875c1 CM |
509 | goto next; |
510 | ||
4c7aa002 | 511 | pr_debug("cpu logical map 0x%llx\n", hwid); |
0f078336 | 512 | cpu_logical_map(cpu_count) = hwid; |
08e875c1 | 513 | next: |
0f078336 | 514 | cpu_count++; |
08e875c1 | 515 | } |
0f078336 LP |
516 | } |
517 | ||
518 | /* | |
519 | * Enumerate the possible CPU set from the device tree or ACPI and build the | |
520 | * cpu logical map array containing MPIDR values related to logical | |
521 | * cpus. Assumes that cpu_logical_map(0) has already been initialized. | |
522 | */ | |
523 | void __init smp_init_cpus(void) | |
524 | { | |
525 | int i; | |
526 | ||
527 | if (acpi_disabled) | |
528 | of_parse_and_init_cpus(); | |
529 | else | |
530 | /* | |
531 | * do a walk of MADT to determine how many CPUs | |
532 | * we have including disabled CPUs, and get information | |
533 | * we need for SMP init | |
534 | */ | |
535 | acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, | |
536 | acpi_parse_gic_cpu_interface, 0); | |
08e875c1 | 537 | |
0f078336 LP |
538 | if (cpu_count > NR_CPUS) |
539 | pr_warn("no. of cores (%d) greater than configured maximum of %d - clipping\n", | |
540 | cpu_count, NR_CPUS); | |
4c7aa002 JM |
541 | |
542 | if (!bootcpu_valid) { | |
0f078336 | 543 | pr_err("missing boot CPU MPIDR, not enabling secondaries\n"); |
4c7aa002 JM |
544 | return; |
545 | } | |
546 | ||
547 | /* | |
819a8826 LP |
548 | * We need to set the cpu_logical_map entries before enabling |
549 | * the cpus so that cpu processor description entries (DT cpu nodes | |
550 | * and ACPI MADT entries) can be retrieved by matching the cpu hwid | |
551 | * with entries in cpu_logical_map while initializing the cpus. | |
552 | * If the cpu set-up fails, invalidate the cpu_logical_map entry. | |
4c7aa002 | 553 | */ |
819a8826 LP |
554 | for (i = 1; i < NR_CPUS; i++) { |
555 | if (cpu_logical_map(i) != INVALID_HWID) { | |
556 | if (smp_cpu_setup(i)) | |
557 | cpu_logical_map(i) = INVALID_HWID; | |
558 | } | |
559 | } | |
08e875c1 CM |
560 | } |
561 | ||
562 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
563 | { | |
cd1aebf5 MR |
564 | int err; |
565 | unsigned int cpu, ncores = num_possible_cpus(); | |
08e875c1 | 566 | |
f6e763b9 MB |
567 | init_cpu_topology(); |
568 | ||
569 | smp_store_cpu_info(smp_processor_id()); | |
570 | ||
08e875c1 CM |
571 | /* |
572 | * are we trying to boot more cores than exist? | |
573 | */ | |
574 | if (max_cpus > ncores) | |
575 | max_cpus = ncores; | |
576 | ||
d329de3f MZ |
577 | /* Don't bother if we're effectively UP */ |
578 | if (max_cpus <= 1) | |
579 | return; | |
580 | ||
08e875c1 CM |
581 | /* |
582 | * Initialise the present map (which describes the set of CPUs | |
583 | * actually populated at the present time) and release the | |
584 | * secondaries from the bootloader. | |
d329de3f MZ |
585 | * |
586 | * Make sure we online at most (max_cpus - 1) additional CPUs. | |
08e875c1 | 587 | */ |
d329de3f | 588 | max_cpus--; |
08e875c1 CM |
589 | for_each_possible_cpu(cpu) { |
590 | if (max_cpus == 0) | |
591 | break; | |
592 | ||
d329de3f MZ |
593 | if (cpu == smp_processor_id()) |
594 | continue; | |
595 | ||
cd1aebf5 | 596 | if (!cpu_ops[cpu]) |
08e875c1 CM |
597 | continue; |
598 | ||
cd1aebf5 | 599 | err = cpu_ops[cpu]->cpu_prepare(cpu); |
d329de3f MZ |
600 | if (err) |
601 | continue; | |
08e875c1 CM |
602 | |
603 | set_cpu_present(cpu, true); | |
604 | max_cpus--; | |
605 | } | |
08e875c1 CM |
606 | } |
607 | ||
36310736 | 608 | void (*__smp_cross_call)(const struct cpumask *, unsigned int); |
08e875c1 CM |
609 | |
610 | void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int)) | |
611 | { | |
45ed695a | 612 | __smp_cross_call = fn; |
08e875c1 CM |
613 | } |
614 | ||
45ed695a NP |
615 | static const char *ipi_types[NR_IPI] __tracepoint_string = { |
616 | #define S(x,s) [x] = s | |
08e875c1 CM |
617 | S(IPI_RESCHEDULE, "Rescheduling interrupts"), |
618 | S(IPI_CALL_FUNC, "Function call interrupts"), | |
08e875c1 | 619 | S(IPI_CPU_STOP, "CPU stop interrupts"), |
1f85008e | 620 | S(IPI_TIMER, "Timer broadcast interrupts"), |
eb631bb5 | 621 | S(IPI_IRQ_WORK, "IRQ work interrupts"), |
08e875c1 CM |
622 | }; |
623 | ||
45ed695a NP |
624 | static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) |
625 | { | |
626 | trace_ipi_raise(target, ipi_types[ipinr]); | |
627 | __smp_cross_call(target, ipinr); | |
628 | } | |
629 | ||
08e875c1 CM |
630 | void show_ipi_list(struct seq_file *p, int prec) |
631 | { | |
632 | unsigned int cpu, i; | |
633 | ||
634 | for (i = 0; i < NR_IPI; i++) { | |
45ed695a | 635 | seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i, |
08e875c1 | 636 | prec >= 4 ? " " : ""); |
67317c26 | 637 | for_each_online_cpu(cpu) |
08e875c1 CM |
638 | seq_printf(p, "%10u ", |
639 | __get_irq_stat(cpu, ipi_irqs[i])); | |
640 | seq_printf(p, " %s\n", ipi_types[i]); | |
641 | } | |
642 | } | |
643 | ||
644 | u64 smp_irq_stat_cpu(unsigned int cpu) | |
645 | { | |
646 | u64 sum = 0; | |
647 | int i; | |
648 | ||
649 | for (i = 0; i < NR_IPI; i++) | |
650 | sum += __get_irq_stat(cpu, ipi_irqs[i]); | |
651 | ||
652 | return sum; | |
653 | } | |
654 | ||
45ed695a NP |
655 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
656 | { | |
657 | smp_cross_call(mask, IPI_CALL_FUNC); | |
658 | } | |
659 | ||
660 | void arch_send_call_function_single_ipi(int cpu) | |
661 | { | |
0aaf0dae | 662 | smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC); |
45ed695a NP |
663 | } |
664 | ||
665 | #ifdef CONFIG_IRQ_WORK | |
666 | void arch_irq_work_raise(void) | |
667 | { | |
668 | if (__smp_cross_call) | |
669 | smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK); | |
670 | } | |
671 | #endif | |
672 | ||
08e875c1 CM |
673 | static DEFINE_RAW_SPINLOCK(stop_lock); |
674 | ||
675 | /* | |
676 | * ipi_cpu_stop - handle IPI from smp_send_stop() | |
677 | */ | |
678 | static void ipi_cpu_stop(unsigned int cpu) | |
679 | { | |
680 | if (system_state == SYSTEM_BOOTING || | |
681 | system_state == SYSTEM_RUNNING) { | |
682 | raw_spin_lock(&stop_lock); | |
683 | pr_crit("CPU%u: stopping\n", cpu); | |
684 | dump_stack(); | |
685 | raw_spin_unlock(&stop_lock); | |
686 | } | |
687 | ||
688 | set_cpu_online(cpu, false); | |
689 | ||
08e875c1 CM |
690 | local_irq_disable(); |
691 | ||
692 | while (1) | |
693 | cpu_relax(); | |
694 | } | |
695 | ||
696 | /* | |
697 | * Main handler for inter-processor interrupts | |
698 | */ | |
699 | void handle_IPI(int ipinr, struct pt_regs *regs) | |
700 | { | |
701 | unsigned int cpu = smp_processor_id(); | |
702 | struct pt_regs *old_regs = set_irq_regs(regs); | |
703 | ||
45ed695a | 704 | if ((unsigned)ipinr < NR_IPI) { |
be081d9b | 705 | trace_ipi_entry_rcuidle(ipi_types[ipinr]); |
45ed695a NP |
706 | __inc_irq_stat(cpu, ipi_irqs[ipinr]); |
707 | } | |
08e875c1 CM |
708 | |
709 | switch (ipinr) { | |
710 | case IPI_RESCHEDULE: | |
711 | scheduler_ipi(); | |
712 | break; | |
713 | ||
714 | case IPI_CALL_FUNC: | |
715 | irq_enter(); | |
716 | generic_smp_call_function_interrupt(); | |
717 | irq_exit(); | |
718 | break; | |
719 | ||
08e875c1 CM |
720 | case IPI_CPU_STOP: |
721 | irq_enter(); | |
722 | ipi_cpu_stop(cpu); | |
723 | irq_exit(); | |
724 | break; | |
725 | ||
1f85008e LP |
726 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
727 | case IPI_TIMER: | |
728 | irq_enter(); | |
729 | tick_receive_broadcast(); | |
730 | irq_exit(); | |
731 | break; | |
732 | #endif | |
733 | ||
eb631bb5 LB |
734 | #ifdef CONFIG_IRQ_WORK |
735 | case IPI_IRQ_WORK: | |
736 | irq_enter(); | |
737 | irq_work_run(); | |
738 | irq_exit(); | |
739 | break; | |
740 | #endif | |
741 | ||
08e875c1 CM |
742 | default: |
743 | pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr); | |
744 | break; | |
745 | } | |
45ed695a NP |
746 | |
747 | if ((unsigned)ipinr < NR_IPI) | |
be081d9b | 748 | trace_ipi_exit_rcuidle(ipi_types[ipinr]); |
08e875c1 CM |
749 | set_irq_regs(old_regs); |
750 | } | |
751 | ||
752 | void smp_send_reschedule(int cpu) | |
753 | { | |
754 | smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); | |
755 | } | |
756 | ||
1f85008e LP |
757 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
758 | void tick_broadcast(const struct cpumask *mask) | |
759 | { | |
760 | smp_cross_call(mask, IPI_TIMER); | |
761 | } | |
762 | #endif | |
763 | ||
08e875c1 CM |
764 | void smp_send_stop(void) |
765 | { | |
766 | unsigned long timeout; | |
767 | ||
768 | if (num_online_cpus() > 1) { | |
769 | cpumask_t mask; | |
770 | ||
771 | cpumask_copy(&mask, cpu_online_mask); | |
434ed7f4 | 772 | cpumask_clear_cpu(smp_processor_id(), &mask); |
08e875c1 CM |
773 | |
774 | smp_cross_call(&mask, IPI_CPU_STOP); | |
775 | } | |
776 | ||
777 | /* Wait up to one second for other CPUs to stop */ | |
778 | timeout = USEC_PER_SEC; | |
779 | while (num_online_cpus() > 1 && timeout--) | |
780 | udelay(1); | |
781 | ||
782 | if (num_online_cpus() > 1) | |
783 | pr_warning("SMP: failed to stop secondary CPUs\n"); | |
784 | } | |
785 | ||
786 | /* | |
787 | * not supported here | |
788 | */ | |
789 | int setup_profiling_timer(unsigned int multiplier) | |
790 | { | |
791 | return -EINVAL; | |
792 | } |