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Commit | Line | Data |
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08e875c1 CM |
1 | /* |
2 | * SMP initialisation and IPI support | |
3 | * Based on arch/arm/kernel/smp.c | |
4 | * | |
5 | * Copyright (C) 2012 ARM Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
0f078336 | 20 | #include <linux/acpi.h> |
08e875c1 CM |
21 | #include <linux/delay.h> |
22 | #include <linux/init.h> | |
23 | #include <linux/spinlock.h> | |
68e21be2 | 24 | #include <linux/sched/mm.h> |
ef8bd77f | 25 | #include <linux/sched/hotplug.h> |
68db0cf1 | 26 | #include <linux/sched/task_stack.h> |
08e875c1 CM |
27 | #include <linux/interrupt.h> |
28 | #include <linux/cache.h> | |
29 | #include <linux/profile.h> | |
30 | #include <linux/errno.h> | |
31 | #include <linux/mm.h> | |
32 | #include <linux/err.h> | |
33 | #include <linux/cpu.h> | |
34 | #include <linux/smp.h> | |
35 | #include <linux/seq_file.h> | |
36 | #include <linux/irq.h> | |
37 | #include <linux/percpu.h> | |
38 | #include <linux/clockchips.h> | |
39 | #include <linux/completion.h> | |
40 | #include <linux/of.h> | |
eb631bb5 | 41 | #include <linux/irq_work.h> |
78fd584c | 42 | #include <linux/kexec.h> |
08e875c1 | 43 | |
e039ee4e | 44 | #include <asm/alternative.h> |
08e875c1 CM |
45 | #include <asm/atomic.h> |
46 | #include <asm/cacheflush.h> | |
df857416 | 47 | #include <asm/cpu.h> |
08e875c1 | 48 | #include <asm/cputype.h> |
cd1aebf5 | 49 | #include <asm/cpu_ops.h> |
08e875c1 | 50 | #include <asm/mmu_context.h> |
1a2db300 | 51 | #include <asm/numa.h> |
08e875c1 CM |
52 | #include <asm/pgtable.h> |
53 | #include <asm/pgalloc.h> | |
54 | #include <asm/processor.h> | |
4c7aa002 | 55 | #include <asm/smp_plat.h> |
08e875c1 CM |
56 | #include <asm/sections.h> |
57 | #include <asm/tlbflush.h> | |
58 | #include <asm/ptrace.h> | |
377bcff9 | 59 | #include <asm/virt.h> |
08e875c1 | 60 | |
45ed695a NP |
61 | #define CREATE_TRACE_POINTS |
62 | #include <trace/events/ipi.h> | |
63 | ||
57c82954 MR |
64 | DEFINE_PER_CPU_READ_MOSTLY(int, cpu_number); |
65 | EXPORT_PER_CPU_SYMBOL(cpu_number); | |
66 | ||
08e875c1 CM |
67 | /* |
68 | * as from 2.5, kernels no longer have an init_tasks structure | |
69 | * so we need some other way of telling a new secondary core | |
70 | * where to place its SVC stack | |
71 | */ | |
72 | struct secondary_data secondary_data; | |
bb905274 SP |
73 | /* Number of CPUs which aren't online, but looping in kernel text. */ |
74 | int cpus_stuck_in_kernel; | |
08e875c1 CM |
75 | |
76 | enum ipi_msg_type { | |
77 | IPI_RESCHEDULE, | |
78 | IPI_CALL_FUNC, | |
08e875c1 | 79 | IPI_CPU_STOP, |
78fd584c | 80 | IPI_CPU_CRASH_STOP, |
1f85008e | 81 | IPI_TIMER, |
eb631bb5 | 82 | IPI_IRQ_WORK, |
5e89c55e | 83 | IPI_WAKEUP |
08e875c1 CM |
84 | }; |
85 | ||
ac1ad20f SP |
86 | #ifdef CONFIG_ARM64_VHE |
87 | ||
88 | /* Whether the boot CPU is running in HYP mode or not*/ | |
89 | static bool boot_cpu_hyp_mode; | |
90 | ||
91 | static inline void save_boot_cpu_run_el(void) | |
92 | { | |
93 | boot_cpu_hyp_mode = is_kernel_in_hyp_mode(); | |
94 | } | |
95 | ||
96 | static inline bool is_boot_cpu_in_hyp_mode(void) | |
97 | { | |
98 | return boot_cpu_hyp_mode; | |
99 | } | |
100 | ||
101 | /* | |
102 | * Verify that a secondary CPU is running the kernel at the same | |
103 | * EL as that of the boot CPU. | |
104 | */ | |
105 | void verify_cpu_run_el(void) | |
106 | { | |
107 | bool in_el2 = is_kernel_in_hyp_mode(); | |
108 | bool boot_cpu_el2 = is_boot_cpu_in_hyp_mode(); | |
109 | ||
110 | if (in_el2 ^ boot_cpu_el2) { | |
111 | pr_crit("CPU%d: mismatched Exception Level(EL%d) with boot CPU(EL%d)\n", | |
112 | smp_processor_id(), | |
113 | in_el2 ? 2 : 1, | |
114 | boot_cpu_el2 ? 2 : 1); | |
115 | cpu_panic_kernel(); | |
116 | } | |
117 | } | |
118 | ||
119 | #else | |
120 | static inline void save_boot_cpu_run_el(void) {} | |
121 | #endif | |
122 | ||
bb905274 SP |
123 | #ifdef CONFIG_HOTPLUG_CPU |
124 | static int op_cpu_kill(unsigned int cpu); | |
125 | #else | |
126 | static inline int op_cpu_kill(unsigned int cpu) | |
127 | { | |
128 | return -ENOSYS; | |
129 | } | |
130 | #endif | |
131 | ||
132 | ||
08e875c1 CM |
133 | /* |
134 | * Boot a secondary CPU, and assign it the specified idle task. | |
135 | * This also gives us the initial stack to use for this CPU. | |
136 | */ | |
b8c6453a | 137 | static int boot_secondary(unsigned int cpu, struct task_struct *idle) |
08e875c1 | 138 | { |
652af899 MR |
139 | if (cpu_ops[cpu]->cpu_boot) |
140 | return cpu_ops[cpu]->cpu_boot(cpu); | |
08e875c1 | 141 | |
652af899 | 142 | return -EOPNOTSUPP; |
08e875c1 CM |
143 | } |
144 | ||
145 | static DECLARE_COMPLETION(cpu_running); | |
146 | ||
b8c6453a | 147 | int __cpu_up(unsigned int cpu, struct task_struct *idle) |
08e875c1 CM |
148 | { |
149 | int ret; | |
bb905274 | 150 | long status; |
08e875c1 CM |
151 | |
152 | /* | |
153 | * We need to tell the secondary core where to find its stack and the | |
154 | * page tables. | |
155 | */ | |
c02433dd | 156 | secondary_data.task = idle; |
08e875c1 | 157 | secondary_data.stack = task_stack_page(idle) + THREAD_START_SP; |
bb905274 | 158 | update_cpu_boot_status(CPU_MMU_OFF); |
08e875c1 CM |
159 | __flush_dcache_area(&secondary_data, sizeof(secondary_data)); |
160 | ||
161 | /* | |
162 | * Now bring the CPU into our world. | |
163 | */ | |
164 | ret = boot_secondary(cpu, idle); | |
165 | if (ret == 0) { | |
166 | /* | |
167 | * CPU was successfully started, wait for it to come online or | |
168 | * time out. | |
169 | */ | |
170 | wait_for_completion_timeout(&cpu_running, | |
171 | msecs_to_jiffies(1000)); | |
172 | ||
173 | if (!cpu_online(cpu)) { | |
174 | pr_crit("CPU%u: failed to come online\n", cpu); | |
175 | ret = -EIO; | |
176 | } | |
177 | } else { | |
178 | pr_err("CPU%u: failed to boot: %d\n", cpu, ret); | |
179 | } | |
180 | ||
c02433dd | 181 | secondary_data.task = NULL; |
08e875c1 | 182 | secondary_data.stack = NULL; |
bb905274 SP |
183 | status = READ_ONCE(secondary_data.status); |
184 | if (ret && status) { | |
185 | ||
186 | if (status == CPU_MMU_OFF) | |
187 | status = READ_ONCE(__early_cpu_boot_status); | |
188 | ||
189 | switch (status) { | |
190 | default: | |
191 | pr_err("CPU%u: failed in unknown state : 0x%lx\n", | |
192 | cpu, status); | |
193 | break; | |
194 | case CPU_KILL_ME: | |
195 | if (!op_cpu_kill(cpu)) { | |
196 | pr_crit("CPU%u: died during early boot\n", cpu); | |
197 | break; | |
198 | } | |
199 | /* Fall through */ | |
200 | pr_crit("CPU%u: may not have shut down cleanly\n", cpu); | |
201 | case CPU_STUCK_IN_KERNEL: | |
202 | pr_crit("CPU%u: is stuck in kernel\n", cpu); | |
203 | cpus_stuck_in_kernel++; | |
204 | break; | |
205 | case CPU_PANIC_KERNEL: | |
206 | panic("CPU%u detected unsupported configuration\n", cpu); | |
207 | } | |
208 | } | |
08e875c1 CM |
209 | |
210 | return ret; | |
211 | } | |
212 | ||
213 | /* | |
214 | * This is the secondary CPU boot entry. We're using this CPUs | |
215 | * idle thread stack, but a set of temporary page tables. | |
216 | */ | |
b8c6453a | 217 | asmlinkage void secondary_start_kernel(void) |
08e875c1 CM |
218 | { |
219 | struct mm_struct *mm = &init_mm; | |
580efaa7 MR |
220 | unsigned int cpu; |
221 | ||
222 | cpu = task_cpu(current); | |
223 | set_my_cpu_offset(per_cpu_offset(cpu)); | |
08e875c1 | 224 | |
08e875c1 CM |
225 | /* |
226 | * All kernel threads share the same mm context; grab a | |
227 | * reference and switch to it. | |
228 | */ | |
f1f10076 | 229 | mmgrab(mm); |
08e875c1 | 230 | current->active_mm = mm; |
08e875c1 CM |
231 | |
232 | /* | |
233 | * TTBR0 is only used for the identity mapping at this stage. Make it | |
234 | * point to zero page to avoid speculatively fetching new entries. | |
235 | */ | |
9e8e865b | 236 | cpu_uninstall_idmap(); |
08e875c1 CM |
237 | |
238 | preempt_disable(); | |
239 | trace_hardirqs_off(); | |
240 | ||
dbb4e152 SP |
241 | /* |
242 | * If the system has established the capabilities, make sure | |
243 | * this CPU ticks all of those. If it doesn't, the CPU will | |
244 | * fail to come online. | |
245 | */ | |
c47a1900 | 246 | check_local_cpu_capabilities(); |
dbb4e152 | 247 | |
652af899 MR |
248 | if (cpu_ops[cpu]->cpu_postboot) |
249 | cpu_ops[cpu]->cpu_postboot(); | |
08e875c1 | 250 | |
df857416 MR |
251 | /* |
252 | * Log the CPU info before it is marked online and might get read. | |
253 | */ | |
254 | cpuinfo_store_cpu(); | |
255 | ||
7ade67b5 MZ |
256 | /* |
257 | * Enable GIC and timers. | |
258 | */ | |
259 | notify_cpu_starting(cpu); | |
260 | ||
c18df0ad | 261 | store_cpu_topology(cpu); |
f6e763b9 | 262 | |
08e875c1 CM |
263 | /* |
264 | * OK, now it's safe to let the boot CPU continue. Wait for | |
265 | * the CPU migration code to notice that the CPU is online | |
266 | * before we continue. | |
267 | */ | |
64f17818 SP |
268 | pr_info("CPU%u: Booted secondary processor [%08x]\n", |
269 | cpu, read_cpuid_id()); | |
bb905274 | 270 | update_cpu_boot_status(CPU_BOOT_SUCCESS); |
08e875c1 | 271 | set_cpu_online(cpu, true); |
b3770b32 | 272 | complete(&cpu_running); |
08e875c1 | 273 | |
53ae3acd | 274 | local_irq_enable(); |
b3bf6aa7 | 275 | local_async_enable(); |
53ae3acd | 276 | |
08e875c1 CM |
277 | /* |
278 | * OK, it's off to the idle thread for us | |
279 | */ | |
fc6d73d6 | 280 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
08e875c1 CM |
281 | } |
282 | ||
9327e2c6 MR |
283 | #ifdef CONFIG_HOTPLUG_CPU |
284 | static int op_cpu_disable(unsigned int cpu) | |
285 | { | |
286 | /* | |
287 | * If we don't have a cpu_die method, abort before we reach the point | |
288 | * of no return. CPU0 may not have an cpu_ops, so test for it. | |
289 | */ | |
290 | if (!cpu_ops[cpu] || !cpu_ops[cpu]->cpu_die) | |
291 | return -EOPNOTSUPP; | |
292 | ||
293 | /* | |
294 | * We may need to abort a hot unplug for some other mechanism-specific | |
295 | * reason. | |
296 | */ | |
297 | if (cpu_ops[cpu]->cpu_disable) | |
298 | return cpu_ops[cpu]->cpu_disable(cpu); | |
299 | ||
300 | return 0; | |
301 | } | |
302 | ||
303 | /* | |
304 | * __cpu_disable runs on the processor to be shutdown. | |
305 | */ | |
306 | int __cpu_disable(void) | |
307 | { | |
308 | unsigned int cpu = smp_processor_id(); | |
309 | int ret; | |
310 | ||
311 | ret = op_cpu_disable(cpu); | |
312 | if (ret) | |
313 | return ret; | |
314 | ||
315 | /* | |
316 | * Take this CPU offline. Once we clear this, we can't return, | |
317 | * and we must not schedule until we're ready to give up the cpu. | |
318 | */ | |
319 | set_cpu_online(cpu, false); | |
320 | ||
321 | /* | |
322 | * OK - migrate IRQs away from this CPU | |
323 | */ | |
217d453d YY |
324 | irq_migrate_all_off_this_cpu(); |
325 | ||
9327e2c6 MR |
326 | return 0; |
327 | } | |
328 | ||
c814ca02 AC |
329 | static int op_cpu_kill(unsigned int cpu) |
330 | { | |
331 | /* | |
332 | * If we have no means of synchronising with the dying CPU, then assume | |
333 | * that it is really dead. We can only wait for an arbitrary length of | |
334 | * time and hope that it's dead, so let's skip the wait and just hope. | |
335 | */ | |
336 | if (!cpu_ops[cpu]->cpu_kill) | |
6b99c68c | 337 | return 0; |
c814ca02 AC |
338 | |
339 | return cpu_ops[cpu]->cpu_kill(cpu); | |
340 | } | |
341 | ||
9327e2c6 MR |
342 | /* |
343 | * called on the thread which is asking for a CPU to be shutdown - | |
344 | * waits until shutdown has completed, or it is timed out. | |
345 | */ | |
346 | void __cpu_die(unsigned int cpu) | |
347 | { | |
6b99c68c MR |
348 | int err; |
349 | ||
05981277 | 350 | if (!cpu_wait_death(cpu, 5)) { |
9327e2c6 MR |
351 | pr_crit("CPU%u: cpu didn't die\n", cpu); |
352 | return; | |
353 | } | |
354 | pr_notice("CPU%u: shutdown\n", cpu); | |
c814ca02 AC |
355 | |
356 | /* | |
357 | * Now that the dying CPU is beyond the point of no return w.r.t. | |
358 | * in-kernel synchronisation, try to get the firwmare to help us to | |
359 | * verify that it has really left the kernel before we consider | |
360 | * clobbering anything it might still be using. | |
361 | */ | |
6b99c68c MR |
362 | err = op_cpu_kill(cpu); |
363 | if (err) | |
364 | pr_warn("CPU%d may not have shut down cleanly: %d\n", | |
365 | cpu, err); | |
9327e2c6 MR |
366 | } |
367 | ||
368 | /* | |
369 | * Called from the idle thread for the CPU which has been shutdown. | |
370 | * | |
371 | * Note that we disable IRQs here, but do not re-enable them | |
372 | * before returning to the caller. This is also the behaviour | |
373 | * of the other hotplug-cpu capable cores, so presumably coming | |
374 | * out of idle fixes this. | |
375 | */ | |
376 | void cpu_die(void) | |
377 | { | |
378 | unsigned int cpu = smp_processor_id(); | |
379 | ||
380 | idle_task_exit(); | |
381 | ||
382 | local_irq_disable(); | |
383 | ||
384 | /* Tell __cpu_die() that this CPU is now safe to dispose of */ | |
05981277 | 385 | (void)cpu_report_death(); |
9327e2c6 MR |
386 | |
387 | /* | |
388 | * Actually shutdown the CPU. This must never fail. The specific hotplug | |
389 | * mechanism must perform all required cache maintenance to ensure that | |
390 | * no dirty lines are lost in the process of shutting down the CPU. | |
391 | */ | |
392 | cpu_ops[cpu]->cpu_die(cpu); | |
393 | ||
394 | BUG(); | |
395 | } | |
396 | #endif | |
397 | ||
fce6361f SP |
398 | /* |
399 | * Kill the calling secondary CPU, early in bringup before it is turned | |
400 | * online. | |
401 | */ | |
402 | void cpu_die_early(void) | |
403 | { | |
404 | int cpu = smp_processor_id(); | |
405 | ||
406 | pr_crit("CPU%d: will not boot\n", cpu); | |
407 | ||
408 | /* Mark this CPU absent */ | |
409 | set_cpu_present(cpu, 0); | |
410 | ||
411 | #ifdef CONFIG_HOTPLUG_CPU | |
bb905274 | 412 | update_cpu_boot_status(CPU_KILL_ME); |
fce6361f SP |
413 | /* Check if we can park ourselves */ |
414 | if (cpu_ops[cpu] && cpu_ops[cpu]->cpu_die) | |
415 | cpu_ops[cpu]->cpu_die(cpu); | |
416 | #endif | |
bb905274 | 417 | update_cpu_boot_status(CPU_STUCK_IN_KERNEL); |
fce6361f SP |
418 | |
419 | cpu_park_loop(); | |
420 | } | |
421 | ||
377bcff9 JR |
422 | static void __init hyp_mode_check(void) |
423 | { | |
424 | if (is_hyp_mode_available()) | |
425 | pr_info("CPU: All CPU(s) started at EL2\n"); | |
426 | else if (is_hyp_mode_mismatched()) | |
427 | WARN_TAINT(1, TAINT_CPU_OUT_OF_SPEC, | |
428 | "CPU: CPUs started in inconsistent modes"); | |
429 | else | |
430 | pr_info("CPU: All CPU(s) started at EL1\n"); | |
431 | } | |
432 | ||
08e875c1 CM |
433 | void __init smp_cpus_done(unsigned int max_cpus) |
434 | { | |
326b16db | 435 | pr_info("SMP: Total of %d processors activated.\n", num_online_cpus()); |
3a75578e | 436 | setup_cpu_features(); |
377bcff9 JR |
437 | hyp_mode_check(); |
438 | apply_alternatives_all(); | |
5ea5306c | 439 | mark_linear_text_alias_ro(); |
08e875c1 CM |
440 | } |
441 | ||
442 | void __init smp_prepare_boot_cpu(void) | |
443 | { | |
9113c2aa | 444 | set_my_cpu_offset(per_cpu_offset(smp_processor_id())); |
efd9e03f CM |
445 | /* |
446 | * Initialise the static keys early as they may be enabled by the | |
447 | * cpufeature code. | |
448 | */ | |
449 | jump_label_init(); | |
4b998ff1 | 450 | cpuinfo_store_boot_cpu(); |
ac1ad20f | 451 | save_boot_cpu_run_el(); |
c47a1900 SP |
452 | /* |
453 | * Run the errata work around checks on the boot CPU, once we have | |
454 | * initialised the cpu feature infrastructure from | |
455 | * cpuinfo_store_boot_cpu() above. | |
456 | */ | |
457 | update_cpu_errata_workarounds(); | |
08e875c1 CM |
458 | } |
459 | ||
0f078336 LP |
460 | static u64 __init of_get_cpu_mpidr(struct device_node *dn) |
461 | { | |
462 | const __be32 *cell; | |
463 | u64 hwid; | |
464 | ||
465 | /* | |
466 | * A cpu node with missing "reg" property is | |
467 | * considered invalid to build a cpu_logical_map | |
468 | * entry. | |
469 | */ | |
470 | cell = of_get_property(dn, "reg", NULL); | |
471 | if (!cell) { | |
a270f327 | 472 | pr_err("%pOF: missing reg property\n", dn); |
0f078336 LP |
473 | return INVALID_HWID; |
474 | } | |
475 | ||
476 | hwid = of_read_number(cell, of_n_addr_cells(dn)); | |
477 | /* | |
478 | * Non affinity bits must be set to 0 in the DT | |
479 | */ | |
480 | if (hwid & ~MPIDR_HWID_BITMASK) { | |
a270f327 | 481 | pr_err("%pOF: invalid reg property\n", dn); |
0f078336 LP |
482 | return INVALID_HWID; |
483 | } | |
484 | return hwid; | |
485 | } | |
486 | ||
487 | /* | |
488 | * Duplicate MPIDRs are a recipe for disaster. Scan all initialized | |
489 | * entries and check for duplicates. If any is found just ignore the | |
490 | * cpu. cpu_logical_map was initialized to INVALID_HWID to avoid | |
491 | * matching valid MPIDR values. | |
492 | */ | |
493 | static bool __init is_mpidr_duplicate(unsigned int cpu, u64 hwid) | |
494 | { | |
495 | unsigned int i; | |
496 | ||
497 | for (i = 1; (i < cpu) && (i < NR_CPUS); i++) | |
498 | if (cpu_logical_map(i) == hwid) | |
499 | return true; | |
500 | return false; | |
501 | } | |
502 | ||
819a8826 LP |
503 | /* |
504 | * Initialize cpu operations for a logical cpu and | |
505 | * set it in the possible mask on success | |
506 | */ | |
507 | static int __init smp_cpu_setup(int cpu) | |
508 | { | |
509 | if (cpu_read_ops(cpu)) | |
510 | return -ENODEV; | |
511 | ||
512 | if (cpu_ops[cpu]->cpu_init(cpu)) | |
513 | return -ENODEV; | |
514 | ||
515 | set_cpu_possible(cpu, true); | |
516 | ||
517 | return 0; | |
518 | } | |
519 | ||
0f078336 LP |
520 | static bool bootcpu_valid __initdata; |
521 | static unsigned int cpu_count = 1; | |
522 | ||
523 | #ifdef CONFIG_ACPI | |
e0013aed MR |
524 | static struct acpi_madt_generic_interrupt cpu_madt_gicc[NR_CPUS]; |
525 | ||
526 | struct acpi_madt_generic_interrupt *acpi_cpu_get_madt_gicc(int cpu) | |
527 | { | |
528 | return &cpu_madt_gicc[cpu]; | |
529 | } | |
530 | ||
0f078336 LP |
531 | /* |
532 | * acpi_map_gic_cpu_interface - parse processor MADT entry | |
533 | * | |
534 | * Carry out sanity checks on MADT processor entry and initialize | |
535 | * cpu_logical_map on success | |
536 | */ | |
537 | static void __init | |
538 | acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor) | |
539 | { | |
540 | u64 hwid = processor->arm_mpidr; | |
541 | ||
f9058929 HG |
542 | if (!(processor->flags & ACPI_MADT_ENABLED)) { |
543 | pr_debug("skipping disabled CPU entry with 0x%llx MPIDR\n", hwid); | |
0f078336 LP |
544 | return; |
545 | } | |
546 | ||
f9058929 HG |
547 | if (hwid & ~MPIDR_HWID_BITMASK || hwid == INVALID_HWID) { |
548 | pr_err("skipping CPU entry with invalid MPIDR 0x%llx\n", hwid); | |
0f078336 LP |
549 | return; |
550 | } | |
551 | ||
552 | if (is_mpidr_duplicate(cpu_count, hwid)) { | |
553 | pr_err("duplicate CPU MPIDR 0x%llx in MADT\n", hwid); | |
554 | return; | |
555 | } | |
556 | ||
557 | /* Check if GICC structure of boot CPU is available in the MADT */ | |
558 | if (cpu_logical_map(0) == hwid) { | |
559 | if (bootcpu_valid) { | |
560 | pr_err("duplicate boot CPU MPIDR: 0x%llx in MADT\n", | |
561 | hwid); | |
562 | return; | |
563 | } | |
564 | bootcpu_valid = true; | |
e0013aed | 565 | cpu_madt_gicc[0] = *processor; |
baa5567c | 566 | early_map_cpu_to_node(0, acpi_numa_get_nid(0, hwid)); |
0f078336 LP |
567 | return; |
568 | } | |
569 | ||
570 | if (cpu_count >= NR_CPUS) | |
571 | return; | |
572 | ||
573 | /* map the logical cpu id to cpu MPIDR */ | |
574 | cpu_logical_map(cpu_count) = hwid; | |
575 | ||
e0013aed MR |
576 | cpu_madt_gicc[cpu_count] = *processor; |
577 | ||
5e89c55e LP |
578 | /* |
579 | * Set-up the ACPI parking protocol cpu entries | |
580 | * while initializing the cpu_logical_map to | |
581 | * avoid parsing MADT entries multiple times for | |
582 | * nothing (ie a valid cpu_logical_map entry should | |
583 | * contain a valid parking protocol data set to | |
584 | * initialize the cpu if the parking protocol is | |
585 | * the only available enable method). | |
586 | */ | |
587 | acpi_set_mailbox_entry(cpu_count, processor); | |
588 | ||
d8b47fca HG |
589 | early_map_cpu_to_node(cpu_count, acpi_numa_get_nid(cpu_count, hwid)); |
590 | ||
0f078336 LP |
591 | cpu_count++; |
592 | } | |
593 | ||
594 | static int __init | |
595 | acpi_parse_gic_cpu_interface(struct acpi_subtable_header *header, | |
596 | const unsigned long end) | |
597 | { | |
598 | struct acpi_madt_generic_interrupt *processor; | |
599 | ||
600 | processor = (struct acpi_madt_generic_interrupt *)header; | |
99e3e3ae | 601 | if (BAD_MADT_GICC_ENTRY(processor, end)) |
0f078336 LP |
602 | return -EINVAL; |
603 | ||
604 | acpi_table_print_madt_entry(header); | |
605 | ||
606 | acpi_map_gic_cpu_interface(processor); | |
607 | ||
608 | return 0; | |
609 | } | |
610 | #else | |
611 | #define acpi_table_parse_madt(...) do { } while (0) | |
612 | #endif | |
613 | ||
08e875c1 | 614 | /* |
4c7aa002 JM |
615 | * Enumerate the possible CPU set from the device tree and build the |
616 | * cpu logical map array containing MPIDR values related to logical | |
617 | * cpus. Assumes that cpu_logical_map(0) has already been initialized. | |
08e875c1 | 618 | */ |
29b8302b | 619 | static void __init of_parse_and_init_cpus(void) |
08e875c1 | 620 | { |
3d29a9a0 | 621 | struct device_node *dn; |
08e875c1 | 622 | |
3d29a9a0 | 623 | for_each_node_by_type(dn, "cpu") { |
0f078336 | 624 | u64 hwid = of_get_cpu_mpidr(dn); |
4c7aa002 | 625 | |
0f078336 | 626 | if (hwid == INVALID_HWID) |
4c7aa002 | 627 | goto next; |
4c7aa002 | 628 | |
0f078336 | 629 | if (is_mpidr_duplicate(cpu_count, hwid)) { |
a270f327 RH |
630 | pr_err("%pOF: duplicate cpu reg properties in the DT\n", |
631 | dn); | |
4c7aa002 JM |
632 | goto next; |
633 | } | |
634 | ||
4c7aa002 JM |
635 | /* |
636 | * The numbering scheme requires that the boot CPU | |
637 | * must be assigned logical id 0. Record it so that | |
638 | * the logical map built from DT is validated and can | |
639 | * be used. | |
640 | */ | |
641 | if (hwid == cpu_logical_map(0)) { | |
642 | if (bootcpu_valid) { | |
a270f327 RH |
643 | pr_err("%pOF: duplicate boot cpu reg property in DT\n", |
644 | dn); | |
4c7aa002 JM |
645 | goto next; |
646 | } | |
647 | ||
648 | bootcpu_valid = true; | |
7ba5f605 | 649 | early_map_cpu_to_node(0, of_node_to_nid(dn)); |
4c7aa002 JM |
650 | |
651 | /* | |
652 | * cpu_logical_map has already been | |
653 | * initialized and the boot cpu doesn't need | |
654 | * the enable-method so continue without | |
655 | * incrementing cpu. | |
656 | */ | |
657 | continue; | |
658 | } | |
659 | ||
0f078336 | 660 | if (cpu_count >= NR_CPUS) |
08e875c1 CM |
661 | goto next; |
662 | ||
4c7aa002 | 663 | pr_debug("cpu logical map 0x%llx\n", hwid); |
0f078336 | 664 | cpu_logical_map(cpu_count) = hwid; |
1a2db300 GK |
665 | |
666 | early_map_cpu_to_node(cpu_count, of_node_to_nid(dn)); | |
08e875c1 | 667 | next: |
0f078336 | 668 | cpu_count++; |
08e875c1 | 669 | } |
0f078336 LP |
670 | } |
671 | ||
672 | /* | |
673 | * Enumerate the possible CPU set from the device tree or ACPI and build the | |
674 | * cpu logical map array containing MPIDR values related to logical | |
675 | * cpus. Assumes that cpu_logical_map(0) has already been initialized. | |
676 | */ | |
677 | void __init smp_init_cpus(void) | |
678 | { | |
679 | int i; | |
680 | ||
681 | if (acpi_disabled) | |
682 | of_parse_and_init_cpus(); | |
683 | else | |
684 | /* | |
685 | * do a walk of MADT to determine how many CPUs | |
686 | * we have including disabled CPUs, and get information | |
687 | * we need for SMP init | |
688 | */ | |
689 | acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, | |
690 | acpi_parse_gic_cpu_interface, 0); | |
08e875c1 | 691 | |
50ee91bd KW |
692 | if (cpu_count > nr_cpu_ids) |
693 | pr_warn("Number of cores (%d) exceeds configured maximum of %d - clipping\n", | |
694 | cpu_count, nr_cpu_ids); | |
4c7aa002 JM |
695 | |
696 | if (!bootcpu_valid) { | |
0f078336 | 697 | pr_err("missing boot CPU MPIDR, not enabling secondaries\n"); |
4c7aa002 JM |
698 | return; |
699 | } | |
700 | ||
701 | /* | |
819a8826 LP |
702 | * We need to set the cpu_logical_map entries before enabling |
703 | * the cpus so that cpu processor description entries (DT cpu nodes | |
704 | * and ACPI MADT entries) can be retrieved by matching the cpu hwid | |
705 | * with entries in cpu_logical_map while initializing the cpus. | |
706 | * If the cpu set-up fails, invalidate the cpu_logical_map entry. | |
4c7aa002 | 707 | */ |
50ee91bd | 708 | for (i = 1; i < nr_cpu_ids; i++) { |
819a8826 LP |
709 | if (cpu_logical_map(i) != INVALID_HWID) { |
710 | if (smp_cpu_setup(i)) | |
711 | cpu_logical_map(i) = INVALID_HWID; | |
712 | } | |
713 | } | |
08e875c1 CM |
714 | } |
715 | ||
716 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
717 | { | |
cd1aebf5 | 718 | int err; |
44dbcc93 | 719 | unsigned int cpu; |
c18df0ad | 720 | unsigned int this_cpu; |
08e875c1 | 721 | |
f6e763b9 MB |
722 | init_cpu_topology(); |
723 | ||
c18df0ad DD |
724 | this_cpu = smp_processor_id(); |
725 | store_cpu_topology(this_cpu); | |
726 | numa_store_cpu_info(this_cpu); | |
f6e763b9 | 727 | |
e75118a7 SP |
728 | /* |
729 | * If UP is mandated by "nosmp" (which implies "maxcpus=0"), don't set | |
730 | * secondary CPUs present. | |
731 | */ | |
732 | if (max_cpus == 0) | |
733 | return; | |
734 | ||
08e875c1 CM |
735 | /* |
736 | * Initialise the present map (which describes the set of CPUs | |
737 | * actually populated at the present time) and release the | |
738 | * secondaries from the bootloader. | |
739 | */ | |
740 | for_each_possible_cpu(cpu) { | |
08e875c1 | 741 | |
57c82954 MR |
742 | per_cpu(cpu_number, cpu) = cpu; |
743 | ||
d329de3f MZ |
744 | if (cpu == smp_processor_id()) |
745 | continue; | |
746 | ||
cd1aebf5 | 747 | if (!cpu_ops[cpu]) |
08e875c1 CM |
748 | continue; |
749 | ||
cd1aebf5 | 750 | err = cpu_ops[cpu]->cpu_prepare(cpu); |
d329de3f MZ |
751 | if (err) |
752 | continue; | |
08e875c1 CM |
753 | |
754 | set_cpu_present(cpu, true); | |
c18df0ad | 755 | numa_store_cpu_info(cpu); |
08e875c1 | 756 | } |
08e875c1 CM |
757 | } |
758 | ||
36310736 | 759 | void (*__smp_cross_call)(const struct cpumask *, unsigned int); |
08e875c1 CM |
760 | |
761 | void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int)) | |
762 | { | |
45ed695a | 763 | __smp_cross_call = fn; |
08e875c1 CM |
764 | } |
765 | ||
45ed695a NP |
766 | static const char *ipi_types[NR_IPI] __tracepoint_string = { |
767 | #define S(x,s) [x] = s | |
08e875c1 CM |
768 | S(IPI_RESCHEDULE, "Rescheduling interrupts"), |
769 | S(IPI_CALL_FUNC, "Function call interrupts"), | |
08e875c1 | 770 | S(IPI_CPU_STOP, "CPU stop interrupts"), |
78fd584c | 771 | S(IPI_CPU_CRASH_STOP, "CPU stop (for crash dump) interrupts"), |
1f85008e | 772 | S(IPI_TIMER, "Timer broadcast interrupts"), |
eb631bb5 | 773 | S(IPI_IRQ_WORK, "IRQ work interrupts"), |
5e89c55e | 774 | S(IPI_WAKEUP, "CPU wake-up interrupts"), |
08e875c1 CM |
775 | }; |
776 | ||
45ed695a NP |
777 | static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) |
778 | { | |
779 | trace_ipi_raise(target, ipi_types[ipinr]); | |
780 | __smp_cross_call(target, ipinr); | |
781 | } | |
782 | ||
08e875c1 CM |
783 | void show_ipi_list(struct seq_file *p, int prec) |
784 | { | |
785 | unsigned int cpu, i; | |
786 | ||
787 | for (i = 0; i < NR_IPI; i++) { | |
45ed695a | 788 | seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i, |
08e875c1 | 789 | prec >= 4 ? " " : ""); |
67317c26 | 790 | for_each_online_cpu(cpu) |
08e875c1 CM |
791 | seq_printf(p, "%10u ", |
792 | __get_irq_stat(cpu, ipi_irqs[i])); | |
793 | seq_printf(p, " %s\n", ipi_types[i]); | |
794 | } | |
795 | } | |
796 | ||
797 | u64 smp_irq_stat_cpu(unsigned int cpu) | |
798 | { | |
799 | u64 sum = 0; | |
800 | int i; | |
801 | ||
802 | for (i = 0; i < NR_IPI; i++) | |
803 | sum += __get_irq_stat(cpu, ipi_irqs[i]); | |
804 | ||
805 | return sum; | |
806 | } | |
807 | ||
45ed695a NP |
808 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
809 | { | |
810 | smp_cross_call(mask, IPI_CALL_FUNC); | |
811 | } | |
812 | ||
813 | void arch_send_call_function_single_ipi(int cpu) | |
814 | { | |
0aaf0dae | 815 | smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC); |
45ed695a NP |
816 | } |
817 | ||
5e89c55e LP |
818 | #ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL |
819 | void arch_send_wakeup_ipi_mask(const struct cpumask *mask) | |
820 | { | |
821 | smp_cross_call(mask, IPI_WAKEUP); | |
822 | } | |
823 | #endif | |
824 | ||
45ed695a NP |
825 | #ifdef CONFIG_IRQ_WORK |
826 | void arch_irq_work_raise(void) | |
827 | { | |
828 | if (__smp_cross_call) | |
829 | smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK); | |
830 | } | |
831 | #endif | |
832 | ||
08e875c1 CM |
833 | /* |
834 | * ipi_cpu_stop - handle IPI from smp_send_stop() | |
835 | */ | |
836 | static void ipi_cpu_stop(unsigned int cpu) | |
837 | { | |
08e875c1 CM |
838 | set_cpu_online(cpu, false); |
839 | ||
08e875c1 CM |
840 | local_irq_disable(); |
841 | ||
842 | while (1) | |
843 | cpu_relax(); | |
844 | } | |
845 | ||
78fd584c AT |
846 | #ifdef CONFIG_KEXEC_CORE |
847 | static atomic_t waiting_for_crash_ipi = ATOMIC_INIT(0); | |
848 | #endif | |
849 | ||
850 | static void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs) | |
851 | { | |
852 | #ifdef CONFIG_KEXEC_CORE | |
853 | crash_save_cpu(regs, cpu); | |
854 | ||
855 | atomic_dec(&waiting_for_crash_ipi); | |
856 | ||
857 | local_irq_disable(); | |
858 | ||
859 | #ifdef CONFIG_HOTPLUG_CPU | |
860 | if (cpu_ops[cpu]->cpu_die) | |
861 | cpu_ops[cpu]->cpu_die(cpu); | |
862 | #endif | |
863 | ||
864 | /* just in case */ | |
865 | cpu_park_loop(); | |
866 | #endif | |
867 | } | |
868 | ||
08e875c1 CM |
869 | /* |
870 | * Main handler for inter-processor interrupts | |
871 | */ | |
872 | void handle_IPI(int ipinr, struct pt_regs *regs) | |
873 | { | |
874 | unsigned int cpu = smp_processor_id(); | |
875 | struct pt_regs *old_regs = set_irq_regs(regs); | |
876 | ||
45ed695a | 877 | if ((unsigned)ipinr < NR_IPI) { |
be081d9b | 878 | trace_ipi_entry_rcuidle(ipi_types[ipinr]); |
45ed695a NP |
879 | __inc_irq_stat(cpu, ipi_irqs[ipinr]); |
880 | } | |
08e875c1 CM |
881 | |
882 | switch (ipinr) { | |
883 | case IPI_RESCHEDULE: | |
884 | scheduler_ipi(); | |
885 | break; | |
886 | ||
887 | case IPI_CALL_FUNC: | |
888 | irq_enter(); | |
889 | generic_smp_call_function_interrupt(); | |
890 | irq_exit(); | |
891 | break; | |
892 | ||
08e875c1 CM |
893 | case IPI_CPU_STOP: |
894 | irq_enter(); | |
895 | ipi_cpu_stop(cpu); | |
896 | irq_exit(); | |
897 | break; | |
898 | ||
78fd584c AT |
899 | case IPI_CPU_CRASH_STOP: |
900 | if (IS_ENABLED(CONFIG_KEXEC_CORE)) { | |
901 | irq_enter(); | |
902 | ipi_cpu_crash_stop(cpu, regs); | |
903 | ||
904 | unreachable(); | |
905 | } | |
906 | break; | |
907 | ||
1f85008e LP |
908 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
909 | case IPI_TIMER: | |
910 | irq_enter(); | |
911 | tick_receive_broadcast(); | |
912 | irq_exit(); | |
913 | break; | |
914 | #endif | |
915 | ||
eb631bb5 LB |
916 | #ifdef CONFIG_IRQ_WORK |
917 | case IPI_IRQ_WORK: | |
918 | irq_enter(); | |
919 | irq_work_run(); | |
920 | irq_exit(); | |
921 | break; | |
922 | #endif | |
923 | ||
5e89c55e LP |
924 | #ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL |
925 | case IPI_WAKEUP: | |
926 | WARN_ONCE(!acpi_parking_protocol_valid(cpu), | |
927 | "CPU%u: Wake-up IPI outside the ACPI parking protocol\n", | |
928 | cpu); | |
929 | break; | |
930 | #endif | |
931 | ||
08e875c1 CM |
932 | default: |
933 | pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr); | |
934 | break; | |
935 | } | |
45ed695a NP |
936 | |
937 | if ((unsigned)ipinr < NR_IPI) | |
be081d9b | 938 | trace_ipi_exit_rcuidle(ipi_types[ipinr]); |
08e875c1 CM |
939 | set_irq_regs(old_regs); |
940 | } | |
941 | ||
942 | void smp_send_reschedule(int cpu) | |
943 | { | |
944 | smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); | |
945 | } | |
946 | ||
1f85008e LP |
947 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
948 | void tick_broadcast(const struct cpumask *mask) | |
949 | { | |
950 | smp_cross_call(mask, IPI_TIMER); | |
951 | } | |
952 | #endif | |
953 | ||
08e875c1 CM |
954 | void smp_send_stop(void) |
955 | { | |
956 | unsigned long timeout; | |
957 | ||
958 | if (num_online_cpus() > 1) { | |
959 | cpumask_t mask; | |
960 | ||
961 | cpumask_copy(&mask, cpu_online_mask); | |
434ed7f4 | 962 | cpumask_clear_cpu(smp_processor_id(), &mask); |
08e875c1 | 963 | |
ef284f5c | 964 | if (system_state <= SYSTEM_RUNNING) |
82611c14 | 965 | pr_crit("SMP: stopping secondary CPUs\n"); |
08e875c1 CM |
966 | smp_cross_call(&mask, IPI_CPU_STOP); |
967 | } | |
968 | ||
969 | /* Wait up to one second for other CPUs to stop */ | |
970 | timeout = USEC_PER_SEC; | |
971 | while (num_online_cpus() > 1 && timeout--) | |
972 | udelay(1); | |
973 | ||
974 | if (num_online_cpus() > 1) | |
82611c14 JG |
975 | pr_warning("SMP: failed to stop secondary CPUs %*pbl\n", |
976 | cpumask_pr_args(cpu_online_mask)); | |
08e875c1 CM |
977 | } |
978 | ||
78fd584c AT |
979 | #ifdef CONFIG_KEXEC_CORE |
980 | void smp_send_crash_stop(void) | |
981 | { | |
982 | cpumask_t mask; | |
983 | unsigned long timeout; | |
984 | ||
985 | if (num_online_cpus() == 1) | |
986 | return; | |
987 | ||
988 | cpumask_copy(&mask, cpu_online_mask); | |
989 | cpumask_clear_cpu(smp_processor_id(), &mask); | |
990 | ||
991 | atomic_set(&waiting_for_crash_ipi, num_online_cpus() - 1); | |
992 | ||
993 | pr_crit("SMP: stopping secondary CPUs\n"); | |
994 | smp_cross_call(&mask, IPI_CPU_CRASH_STOP); | |
995 | ||
996 | /* Wait up to one second for other CPUs to stop */ | |
997 | timeout = USEC_PER_SEC; | |
998 | while ((atomic_read(&waiting_for_crash_ipi) > 0) && timeout--) | |
999 | udelay(1); | |
1000 | ||
1001 | if (atomic_read(&waiting_for_crash_ipi) > 0) | |
1002 | pr_warning("SMP: failed to stop secondary CPUs %*pbl\n", | |
1003 | cpumask_pr_args(&mask)); | |
1004 | } | |
1005 | ||
1006 | bool smp_crash_stop_failed(void) | |
1007 | { | |
1008 | return (atomic_read(&waiting_for_crash_ipi) > 0); | |
1009 | } | |
1010 | #endif | |
1011 | ||
08e875c1 CM |
1012 | /* |
1013 | * not supported here | |
1014 | */ | |
1015 | int setup_profiling_timer(unsigned int multiplier) | |
1016 | { | |
1017 | return -EINVAL; | |
1018 | } | |
5c492c3f JM |
1019 | |
1020 | static bool have_cpu_die(void) | |
1021 | { | |
1022 | #ifdef CONFIG_HOTPLUG_CPU | |
1023 | int any_cpu = raw_smp_processor_id(); | |
1024 | ||
335d2c2d | 1025 | if (cpu_ops[any_cpu] && cpu_ops[any_cpu]->cpu_die) |
5c492c3f JM |
1026 | return true; |
1027 | #endif | |
1028 | return false; | |
1029 | } | |
1030 | ||
1031 | bool cpus_are_stuck_in_kernel(void) | |
1032 | { | |
1033 | bool smp_spin_tables = (num_possible_cpus() > 1 && !have_cpu_die()); | |
1034 | ||
1035 | return !!cpus_stuck_in_kernel || smp_spin_tables; | |
1036 | } |