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08e875c1
CM
1/*
2 * SMP initialisation and IPI support
3 * Based on arch/arm/kernel/smp.c
4 *
5 * Copyright (C) 2012 ARM Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <linux/delay.h>
21#include <linux/init.h>
22#include <linux/spinlock.h>
23#include <linux/sched.h>
24#include <linux/interrupt.h>
25#include <linux/cache.h>
26#include <linux/profile.h>
27#include <linux/errno.h>
28#include <linux/mm.h>
29#include <linux/err.h>
30#include <linux/cpu.h>
31#include <linux/smp.h>
32#include <linux/seq_file.h>
33#include <linux/irq.h>
34#include <linux/percpu.h>
35#include <linux/clockchips.h>
36#include <linux/completion.h>
37#include <linux/of.h>
eb631bb5 38#include <linux/irq_work.h>
08e875c1
CM
39
40#include <asm/atomic.h>
41#include <asm/cacheflush.h>
df857416 42#include <asm/cpu.h>
08e875c1 43#include <asm/cputype.h>
cd1aebf5 44#include <asm/cpu_ops.h>
08e875c1
CM
45#include <asm/mmu_context.h>
46#include <asm/pgtable.h>
47#include <asm/pgalloc.h>
48#include <asm/processor.h>
4c7aa002 49#include <asm/smp_plat.h>
08e875c1
CM
50#include <asm/sections.h>
51#include <asm/tlbflush.h>
52#include <asm/ptrace.h>
08e875c1 53
45ed695a
NP
54#define CREATE_TRACE_POINTS
55#include <trace/events/ipi.h>
56
08e875c1
CM
57/*
58 * as from 2.5, kernels no longer have an init_tasks structure
59 * so we need some other way of telling a new secondary core
60 * where to place its SVC stack
61 */
62struct secondary_data secondary_data;
08e875c1
CM
63
64enum ipi_msg_type {
65 IPI_RESCHEDULE,
66 IPI_CALL_FUNC,
67 IPI_CALL_FUNC_SINGLE,
68 IPI_CPU_STOP,
1f85008e 69 IPI_TIMER,
eb631bb5 70 IPI_IRQ_WORK,
08e875c1
CM
71};
72
08e875c1
CM
73/*
74 * Boot a secondary CPU, and assign it the specified idle task.
75 * This also gives us the initial stack to use for this CPU.
76 */
b8c6453a 77static int boot_secondary(unsigned int cpu, struct task_struct *idle)
08e875c1 78{
652af899
MR
79 if (cpu_ops[cpu]->cpu_boot)
80 return cpu_ops[cpu]->cpu_boot(cpu);
08e875c1 81
652af899 82 return -EOPNOTSUPP;
08e875c1
CM
83}
84
85static DECLARE_COMPLETION(cpu_running);
86
b8c6453a 87int __cpu_up(unsigned int cpu, struct task_struct *idle)
08e875c1
CM
88{
89 int ret;
90
91 /*
92 * We need to tell the secondary core where to find its stack and the
93 * page tables.
94 */
95 secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
96 __flush_dcache_area(&secondary_data, sizeof(secondary_data));
97
98 /*
99 * Now bring the CPU into our world.
100 */
101 ret = boot_secondary(cpu, idle);
102 if (ret == 0) {
103 /*
104 * CPU was successfully started, wait for it to come online or
105 * time out.
106 */
107 wait_for_completion_timeout(&cpu_running,
108 msecs_to_jiffies(1000));
109
110 if (!cpu_online(cpu)) {
111 pr_crit("CPU%u: failed to come online\n", cpu);
112 ret = -EIO;
113 }
114 } else {
115 pr_err("CPU%u: failed to boot: %d\n", cpu, ret);
116 }
117
118 secondary_data.stack = NULL;
119
120 return ret;
121}
122
f6e763b9
MB
123static void smp_store_cpu_info(unsigned int cpuid)
124{
125 store_cpu_topology(cpuid);
126}
127
08e875c1
CM
128/*
129 * This is the secondary CPU boot entry. We're using this CPUs
130 * idle thread stack, but a set of temporary page tables.
131 */
b8c6453a 132asmlinkage void secondary_start_kernel(void)
08e875c1
CM
133{
134 struct mm_struct *mm = &init_mm;
135 unsigned int cpu = smp_processor_id();
136
08e875c1
CM
137 /*
138 * All kernel threads share the same mm context; grab a
139 * reference and switch to it.
140 */
141 atomic_inc(&mm->mm_count);
142 current->active_mm = mm;
143 cpumask_set_cpu(cpu, mm_cpumask(mm));
144
71586276
WD
145 set_my_cpu_offset(per_cpu_offset(smp_processor_id()));
146 printk("CPU%u: Booted secondary processor\n", cpu);
147
08e875c1
CM
148 /*
149 * TTBR0 is only used for the identity mapping at this stage. Make it
150 * point to zero page to avoid speculatively fetching new entries.
151 */
152 cpu_set_reserved_ttbr0();
153 flush_tlb_all();
154
155 preempt_disable();
156 trace_hardirqs_off();
157
652af899
MR
158 if (cpu_ops[cpu]->cpu_postboot)
159 cpu_ops[cpu]->cpu_postboot();
08e875c1 160
df857416
MR
161 /*
162 * Log the CPU info before it is marked online and might get read.
163 */
164 cpuinfo_store_cpu();
165
7ade67b5
MZ
166 /*
167 * Enable GIC and timers.
168 */
169 notify_cpu_starting(cpu);
170
f6e763b9
MB
171 smp_store_cpu_info(cpu);
172
08e875c1
CM
173 /*
174 * OK, now it's safe to let the boot CPU continue. Wait for
175 * the CPU migration code to notice that the CPU is online
176 * before we continue.
177 */
178 set_cpu_online(cpu, true);
b3770b32 179 complete(&cpu_running);
08e875c1 180
d8ed442a 181 local_dbg_enable();
53ae3acd 182 local_irq_enable();
b3bf6aa7 183 local_async_enable();
53ae3acd 184
08e875c1
CM
185 /*
186 * OK, it's off to the idle thread for us
187 */
0087298f 188 cpu_startup_entry(CPUHP_ONLINE);
08e875c1
CM
189}
190
9327e2c6
MR
191#ifdef CONFIG_HOTPLUG_CPU
192static int op_cpu_disable(unsigned int cpu)
193{
194 /*
195 * If we don't have a cpu_die method, abort before we reach the point
196 * of no return. CPU0 may not have an cpu_ops, so test for it.
197 */
198 if (!cpu_ops[cpu] || !cpu_ops[cpu]->cpu_die)
199 return -EOPNOTSUPP;
200
201 /*
202 * We may need to abort a hot unplug for some other mechanism-specific
203 * reason.
204 */
205 if (cpu_ops[cpu]->cpu_disable)
206 return cpu_ops[cpu]->cpu_disable(cpu);
207
208 return 0;
209}
210
211/*
212 * __cpu_disable runs on the processor to be shutdown.
213 */
214int __cpu_disable(void)
215{
216 unsigned int cpu = smp_processor_id();
217 int ret;
218
219 ret = op_cpu_disable(cpu);
220 if (ret)
221 return ret;
222
223 /*
224 * Take this CPU offline. Once we clear this, we can't return,
225 * and we must not schedule until we're ready to give up the cpu.
226 */
227 set_cpu_online(cpu, false);
228
229 /*
230 * OK - migrate IRQs away from this CPU
231 */
232 migrate_irqs();
233
234 /*
235 * Remove this CPU from the vm mask set of all processes.
236 */
237 clear_tasks_mm_cpumask(cpu);
238
239 return 0;
240}
241
c814ca02
AC
242static int op_cpu_kill(unsigned int cpu)
243{
244 /*
245 * If we have no means of synchronising with the dying CPU, then assume
246 * that it is really dead. We can only wait for an arbitrary length of
247 * time and hope that it's dead, so let's skip the wait and just hope.
248 */
249 if (!cpu_ops[cpu]->cpu_kill)
250 return 1;
251
252 return cpu_ops[cpu]->cpu_kill(cpu);
253}
254
9327e2c6
MR
255static DECLARE_COMPLETION(cpu_died);
256
257/*
258 * called on the thread which is asking for a CPU to be shutdown -
259 * waits until shutdown has completed, or it is timed out.
260 */
261void __cpu_die(unsigned int cpu)
262{
263 if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) {
264 pr_crit("CPU%u: cpu didn't die\n", cpu);
265 return;
266 }
267 pr_notice("CPU%u: shutdown\n", cpu);
c814ca02
AC
268
269 /*
270 * Now that the dying CPU is beyond the point of no return w.r.t.
271 * in-kernel synchronisation, try to get the firwmare to help us to
272 * verify that it has really left the kernel before we consider
273 * clobbering anything it might still be using.
274 */
275 if (!op_cpu_kill(cpu))
276 pr_warn("CPU%d may not have shut down cleanly\n", cpu);
9327e2c6
MR
277}
278
279/*
280 * Called from the idle thread for the CPU which has been shutdown.
281 *
282 * Note that we disable IRQs here, but do not re-enable them
283 * before returning to the caller. This is also the behaviour
284 * of the other hotplug-cpu capable cores, so presumably coming
285 * out of idle fixes this.
286 */
287void cpu_die(void)
288{
289 unsigned int cpu = smp_processor_id();
290
291 idle_task_exit();
292
293 local_irq_disable();
294
295 /* Tell __cpu_die() that this CPU is now safe to dispose of */
296 complete(&cpu_died);
297
298 /*
299 * Actually shutdown the CPU. This must never fail. The specific hotplug
300 * mechanism must perform all required cache maintenance to ensure that
301 * no dirty lines are lost in the process of shutting down the CPU.
302 */
303 cpu_ops[cpu]->cpu_die(cpu);
304
305 BUG();
306}
307#endif
308
08e875c1
CM
309void __init smp_cpus_done(unsigned int max_cpus)
310{
326b16db 311 pr_info("SMP: Total of %d processors activated.\n", num_online_cpus());
08e875c1
CM
312}
313
314void __init smp_prepare_boot_cpu(void)
315{
71586276 316 set_my_cpu_offset(per_cpu_offset(smp_processor_id()));
08e875c1
CM
317}
318
08e875c1 319/*
4c7aa002
JM
320 * Enumerate the possible CPU set from the device tree and build the
321 * cpu logical map array containing MPIDR values related to logical
322 * cpus. Assumes that cpu_logical_map(0) has already been initialized.
08e875c1
CM
323 */
324void __init smp_init_cpus(void)
325{
08e875c1 326 struct device_node *dn = NULL;
cd1aebf5 327 unsigned int i, cpu = 1;
4c7aa002 328 bool bootcpu_valid = false;
08e875c1
CM
329
330 while ((dn = of_find_node_by_type(dn, "cpu"))) {
72aea393 331 const u32 *cell;
4c7aa002
JM
332 u64 hwid;
333
334 /*
335 * A cpu node with missing "reg" property is
336 * considered invalid to build a cpu_logical_map
337 * entry.
338 */
72aea393
WD
339 cell = of_get_property(dn, "reg", NULL);
340 if (!cell) {
4c7aa002
JM
341 pr_err("%s: missing reg property\n", dn->full_name);
342 goto next;
343 }
72aea393 344 hwid = of_read_number(cell, of_n_addr_cells(dn));
4c7aa002
JM
345
346 /*
347 * Non affinity bits must be set to 0 in the DT
348 */
349 if (hwid & ~MPIDR_HWID_BITMASK) {
350 pr_err("%s: invalid reg property\n", dn->full_name);
351 goto next;
352 }
353
354 /*
355 * Duplicate MPIDRs are a recipe for disaster. Scan
356 * all initialized entries and check for
357 * duplicates. If any is found just ignore the cpu.
358 * cpu_logical_map was initialized to INVALID_HWID to
359 * avoid matching valid MPIDR values.
360 */
361 for (i = 1; (i < cpu) && (i < NR_CPUS); i++) {
362 if (cpu_logical_map(i) == hwid) {
363 pr_err("%s: duplicate cpu reg properties in the DT\n",
364 dn->full_name);
365 goto next;
366 }
367 }
368
369 /*
370 * The numbering scheme requires that the boot CPU
371 * must be assigned logical id 0. Record it so that
372 * the logical map built from DT is validated and can
373 * be used.
374 */
375 if (hwid == cpu_logical_map(0)) {
376 if (bootcpu_valid) {
377 pr_err("%s: duplicate boot cpu reg property in DT\n",
378 dn->full_name);
379 goto next;
380 }
381
382 bootcpu_valid = true;
383
384 /*
385 * cpu_logical_map has already been
386 * initialized and the boot cpu doesn't need
387 * the enable-method so continue without
388 * incrementing cpu.
389 */
390 continue;
391 }
392
08e875c1
CM
393 if (cpu >= NR_CPUS)
394 goto next;
395
e8765b26 396 if (cpu_read_ops(dn, cpu) != 0)
08e875c1 397 goto next;
08e875c1 398
cd1aebf5 399 if (cpu_ops[cpu]->cpu_init(dn, cpu))
d329de3f
MZ
400 goto next;
401
4c7aa002
JM
402 pr_debug("cpu logical map 0x%llx\n", hwid);
403 cpu_logical_map(cpu) = hwid;
08e875c1
CM
404next:
405 cpu++;
406 }
407
408 /* sanity check */
409 if (cpu > NR_CPUS)
410 pr_warning("no. of cores (%d) greater than configured maximum of %d - clipping\n",
411 cpu, NR_CPUS);
4c7aa002
JM
412
413 if (!bootcpu_valid) {
414 pr_err("DT missing boot CPU MPIDR, not enabling secondaries\n");
415 return;
416 }
417
418 /*
419 * All the cpus that made it to the cpu_logical_map have been
420 * validated so set them as possible cpus.
421 */
422 for (i = 0; i < NR_CPUS; i++)
423 if (cpu_logical_map(i) != INVALID_HWID)
424 set_cpu_possible(i, true);
08e875c1
CM
425}
426
427void __init smp_prepare_cpus(unsigned int max_cpus)
428{
cd1aebf5
MR
429 int err;
430 unsigned int cpu, ncores = num_possible_cpus();
08e875c1 431
f6e763b9
MB
432 init_cpu_topology();
433
434 smp_store_cpu_info(smp_processor_id());
435
08e875c1
CM
436 /*
437 * are we trying to boot more cores than exist?
438 */
439 if (max_cpus > ncores)
440 max_cpus = ncores;
441
d329de3f
MZ
442 /* Don't bother if we're effectively UP */
443 if (max_cpus <= 1)
444 return;
445
08e875c1
CM
446 /*
447 * Initialise the present map (which describes the set of CPUs
448 * actually populated at the present time) and release the
449 * secondaries from the bootloader.
d329de3f
MZ
450 *
451 * Make sure we online at most (max_cpus - 1) additional CPUs.
08e875c1 452 */
d329de3f 453 max_cpus--;
08e875c1
CM
454 for_each_possible_cpu(cpu) {
455 if (max_cpus == 0)
456 break;
457
d329de3f
MZ
458 if (cpu == smp_processor_id())
459 continue;
460
cd1aebf5 461 if (!cpu_ops[cpu])
08e875c1
CM
462 continue;
463
cd1aebf5 464 err = cpu_ops[cpu]->cpu_prepare(cpu);
d329de3f
MZ
465 if (err)
466 continue;
08e875c1
CM
467
468 set_cpu_present(cpu, true);
469 max_cpus--;
470 }
08e875c1
CM
471}
472
36310736 473void (*__smp_cross_call)(const struct cpumask *, unsigned int);
08e875c1
CM
474
475void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
476{
45ed695a 477 __smp_cross_call = fn;
08e875c1
CM
478}
479
45ed695a
NP
480static const char *ipi_types[NR_IPI] __tracepoint_string = {
481#define S(x,s) [x] = s
08e875c1
CM
482 S(IPI_RESCHEDULE, "Rescheduling interrupts"),
483 S(IPI_CALL_FUNC, "Function call interrupts"),
484 S(IPI_CALL_FUNC_SINGLE, "Single function call interrupts"),
485 S(IPI_CPU_STOP, "CPU stop interrupts"),
1f85008e 486 S(IPI_TIMER, "Timer broadcast interrupts"),
eb631bb5 487 S(IPI_IRQ_WORK, "IRQ work interrupts"),
08e875c1
CM
488};
489
45ed695a
NP
490static void smp_cross_call(const struct cpumask *target, unsigned int ipinr)
491{
492 trace_ipi_raise(target, ipi_types[ipinr]);
493 __smp_cross_call(target, ipinr);
494}
495
08e875c1
CM
496void show_ipi_list(struct seq_file *p, int prec)
497{
498 unsigned int cpu, i;
499
500 for (i = 0; i < NR_IPI; i++) {
45ed695a 501 seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i,
08e875c1 502 prec >= 4 ? " " : "");
67317c26 503 for_each_online_cpu(cpu)
08e875c1
CM
504 seq_printf(p, "%10u ",
505 __get_irq_stat(cpu, ipi_irqs[i]));
506 seq_printf(p, " %s\n", ipi_types[i]);
507 }
508}
509
510u64 smp_irq_stat_cpu(unsigned int cpu)
511{
512 u64 sum = 0;
513 int i;
514
515 for (i = 0; i < NR_IPI; i++)
516 sum += __get_irq_stat(cpu, ipi_irqs[i]);
517
518 return sum;
519}
520
45ed695a
NP
521void arch_send_call_function_ipi_mask(const struct cpumask *mask)
522{
523 smp_cross_call(mask, IPI_CALL_FUNC);
524}
525
526void arch_send_call_function_single_ipi(int cpu)
527{
528 smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE);
529}
530
531#ifdef CONFIG_IRQ_WORK
532void arch_irq_work_raise(void)
533{
534 if (__smp_cross_call)
535 smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK);
536}
537#endif
538
08e875c1
CM
539static DEFINE_RAW_SPINLOCK(stop_lock);
540
541/*
542 * ipi_cpu_stop - handle IPI from smp_send_stop()
543 */
544static void ipi_cpu_stop(unsigned int cpu)
545{
546 if (system_state == SYSTEM_BOOTING ||
547 system_state == SYSTEM_RUNNING) {
548 raw_spin_lock(&stop_lock);
549 pr_crit("CPU%u: stopping\n", cpu);
550 dump_stack();
551 raw_spin_unlock(&stop_lock);
552 }
553
554 set_cpu_online(cpu, false);
555
08e875c1
CM
556 local_irq_disable();
557
558 while (1)
559 cpu_relax();
560}
561
562/*
563 * Main handler for inter-processor interrupts
564 */
565void handle_IPI(int ipinr, struct pt_regs *regs)
566{
567 unsigned int cpu = smp_processor_id();
568 struct pt_regs *old_regs = set_irq_regs(regs);
569
45ed695a
NP
570 if ((unsigned)ipinr < NR_IPI) {
571 trace_ipi_entry(ipi_types[ipinr]);
572 __inc_irq_stat(cpu, ipi_irqs[ipinr]);
573 }
08e875c1
CM
574
575 switch (ipinr) {
576 case IPI_RESCHEDULE:
577 scheduler_ipi();
578 break;
579
580 case IPI_CALL_FUNC:
581 irq_enter();
582 generic_smp_call_function_interrupt();
583 irq_exit();
584 break;
585
586 case IPI_CALL_FUNC_SINGLE:
587 irq_enter();
588 generic_smp_call_function_single_interrupt();
589 irq_exit();
590 break;
591
592 case IPI_CPU_STOP:
593 irq_enter();
594 ipi_cpu_stop(cpu);
595 irq_exit();
596 break;
597
1f85008e
LP
598#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
599 case IPI_TIMER:
600 irq_enter();
601 tick_receive_broadcast();
602 irq_exit();
603 break;
604#endif
605
eb631bb5
LB
606#ifdef CONFIG_IRQ_WORK
607 case IPI_IRQ_WORK:
608 irq_enter();
609 irq_work_run();
610 irq_exit();
611 break;
612#endif
613
08e875c1
CM
614 default:
615 pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr);
616 break;
617 }
45ed695a
NP
618
619 if ((unsigned)ipinr < NR_IPI)
620 trace_ipi_exit(ipi_types[ipinr]);
08e875c1
CM
621 set_irq_regs(old_regs);
622}
623
624void smp_send_reschedule(int cpu)
625{
626 smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
627}
628
1f85008e
LP
629#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
630void tick_broadcast(const struct cpumask *mask)
631{
632 smp_cross_call(mask, IPI_TIMER);
633}
634#endif
635
08e875c1
CM
636void smp_send_stop(void)
637{
638 unsigned long timeout;
639
640 if (num_online_cpus() > 1) {
641 cpumask_t mask;
642
643 cpumask_copy(&mask, cpu_online_mask);
644 cpu_clear(smp_processor_id(), mask);
645
646 smp_cross_call(&mask, IPI_CPU_STOP);
647 }
648
649 /* Wait up to one second for other CPUs to stop */
650 timeout = USEC_PER_SEC;
651 while (num_online_cpus() > 1 && timeout--)
652 udelay(1);
653
654 if (num_online_cpus() > 1)
655 pr_warning("SMP: failed to stop secondary CPUs\n");
656}
657
658/*
659 * not supported here
660 */
661int setup_profiling_timer(unsigned int multiplier)
662{
663 return -EINVAL;
664}