[mirror_ubuntu-zesty-kernel.git] / arch / arm64 / kvm / hyp / vgic-v3-sr.c

/*
 * Copyright (C) 2012-2015 - ARM Ltd
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/compiler.h>
#include <linux/irqchip/arm-gic-v3.h>
#include <linux/kvm_host.h>

#include <asm/kvm_hyp.h>

#define vtr_to_max_lr_idx(v)		((v) & 0xf)
#define vtr_to_nr_pri_bits(v)		(((u32)(v) >> 29) + 1)

#define read_gicreg(r)							\
	({								\
		u64 reg;						\
		asm volatile("mrs_s %0, " __stringify(r) : "=r" (reg));	\
		reg;							\
	})

#define write_gicreg(v,r)						\
	do {								\
		u64 __val = (v);					\
		asm volatile("msr_s " __stringify(r) ", %0" : : "r" (__val));\
	} while (0)

static u64 __hyp_text __gic_v3_get_lr(unsigned int lr)
{
	switch (lr & 0xf) {
	case 0:
		return read_gicreg(ICH_LR0_EL2);
	case 1:
		return read_gicreg(ICH_LR1_EL2);
	case 2:
		return read_gicreg(ICH_LR2_EL2);
	case 3:
		return read_gicreg(ICH_LR3_EL2);
	case 4:
		return read_gicreg(ICH_LR4_EL2);
	case 5:
		return read_gicreg(ICH_LR5_EL2);
	case 6:
		return read_gicreg(ICH_LR6_EL2);
	case 7:
		return read_gicreg(ICH_LR7_EL2);
	case 8:
		return read_gicreg(ICH_LR8_EL2);
	case 9:
		return read_gicreg(ICH_LR9_EL2);
	case 10:
		return read_gicreg(ICH_LR10_EL2);
	case 11:
		return read_gicreg(ICH_LR11_EL2);
	case 12:
		return read_gicreg(ICH_LR12_EL2);
	case 13:
		return read_gicreg(ICH_LR13_EL2);
	case 14:
		return read_gicreg(ICH_LR14_EL2);
	case 15:
		return read_gicreg(ICH_LR15_EL2);
	}

	unreachable();
}

static void __hyp_text __gic_v3_set_lr(u64 val, int lr)
{
	switch (lr & 0xf) {
	case 0:
		write_gicreg(val, ICH_LR0_EL2);
		break;
	case 1:
		write_gicreg(val, ICH_LR1_EL2);
		break;
	case 2:
		write_gicreg(val, ICH_LR2_EL2);
		break;
	case 3:
		write_gicreg(val, ICH_LR3_EL2);
		break;
	case 4:
		write_gicreg(val, ICH_LR4_EL2);
		break;
	case 5:
		write_gicreg(val, ICH_LR5_EL2);
		break;
	case 6:
		write_gicreg(val, ICH_LR6_EL2);
		break;
	case 7:
		write_gicreg(val, ICH_LR7_EL2);
		break;
	case 8:
		write_gicreg(val, ICH_LR8_EL2);
		break;
	case 9:
		write_gicreg(val, ICH_LR9_EL2);
		break;
	case 10:
		write_gicreg(val, ICH_LR10_EL2);
		break;
	case 11:
		write_gicreg(val, ICH_LR11_EL2);
		break;
	case 12:
		write_gicreg(val, ICH_LR12_EL2);
		break;
	case 13:
		write_gicreg(val, ICH_LR13_EL2);
		break;
	case 14:
		write_gicreg(val, ICH_LR14_EL2);
		break;
	case 15:
		write_gicreg(val, ICH_LR15_EL2);
		break;
	}
}

void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu)
{
	struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
	u64 val;

	/*
	 * Make sure stores to the GIC via the memory mapped interface
	 * are now visible to the system register interface.
	 */
	dsb(st);

	cpu_if->vgic_vmcr  = read_gicreg(ICH_VMCR_EL2);

	if (vcpu->arch.vgic_cpu.live_lrs) {
		int i;
		u32 max_lr_idx, nr_pri_bits;

		cpu_if->vgic_misr  = read_gicreg(ICH_MISR_EL2);
		cpu_if->vgic_eisr  = read_gicreg(ICH_EISR_EL2);
		cpu_if->vgic_elrsr = read_gicreg(ICH_ELSR_EL2);

		write_gicreg(0, ICH_HCR_EL2);
		val = read_gicreg(ICH_VTR_EL2);
		max_lr_idx = vtr_to_max_lr_idx(val);
		nr_pri_bits = vtr_to_nr_pri_bits(val);

		for (i = 0; i <= max_lr_idx; i++) {
			if (vcpu->arch.vgic_cpu.live_lrs & (1UL << i))
				cpu_if->vgic_lr[i] = __gic_v3_get_lr(i);
		}

		switch (nr_pri_bits) {
		case 7:
			cpu_if->vgic_ap0r[3] = read_gicreg(ICH_AP0R3_EL2);
			cpu_if->vgic_ap0r[2] = read_gicreg(ICH_AP0R2_EL2);
		case 6:
			cpu_if->vgic_ap0r[1] = read_gicreg(ICH_AP0R1_EL2);
		default:
			cpu_if->vgic_ap0r[0] = read_gicreg(ICH_AP0R0_EL2);
		}

		switch (nr_pri_bits) {
		case 7:
			cpu_if->vgic_ap1r[3] = read_gicreg(ICH_AP1R3_EL2);
			cpu_if->vgic_ap1r[2] = read_gicreg(ICH_AP1R2_EL2);
		case 6:
			cpu_if->vgic_ap1r[1] = read_gicreg(ICH_AP1R1_EL2);
		default:
			cpu_if->vgic_ap1r[0] = read_gicreg(ICH_AP1R0_EL2);
		}

		vcpu->arch.vgic_cpu.live_lrs = 0;
	} else {
		cpu_if->vgic_misr  = 0;
		cpu_if->vgic_eisr  = 0;
		cpu_if->vgic_elrsr = 0xffff;
		cpu_if->vgic_ap0r[0] = 0;
		cpu_if->vgic_ap0r[1] = 0;
		cpu_if->vgic_ap0r[2] = 0;
		cpu_if->vgic_ap0r[3] = 0;
		cpu_if->vgic_ap1r[0] = 0;
		cpu_if->vgic_ap1r[1] = 0;
		cpu_if->vgic_ap1r[2] = 0;
		cpu_if->vgic_ap1r[3] = 0;
	}

	val = read_gicreg(ICC_SRE_EL2);
	write_gicreg(val | ICC_SRE_EL2_ENABLE, ICC_SRE_EL2);
	isb(); /* Make sure ENABLE is set at EL2 before setting SRE at EL1 */
	write_gicreg(1, ICC_SRE_EL1);
}

void __hyp_text __vgic_v3_restore_state(struct kvm_vcpu *vcpu)
{
	struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
	u64 val;
	u32 max_lr_idx, nr_pri_bits;
	u16 live_lrs = 0;
	int i;

	/*
	 * VFIQEn is RES1 if ICC_SRE_EL1.SRE is 1. This causes a
	 * Group0 interrupt (as generated in GICv2 mode) to be
	 * delivered as a FIQ to the guest, with potentially fatal
	 * consequences. So we must make sure that ICC_SRE_EL1 has
	 * been actually programmed with the value we want before
	 * starting to mess with the rest of the GIC.
	 */
	write_gicreg(cpu_if->vgic_sre, ICC_SRE_EL1);
	isb();

	val = read_gicreg(ICH_VTR_EL2);
	max_lr_idx = vtr_to_max_lr_idx(val);
	nr_pri_bits = vtr_to_nr_pri_bits(val);

	for (i = 0; i <= max_lr_idx; i++) {
		if (cpu_if->vgic_lr[i] & ICH_LR_STATE)
			live_lrs |= (1 << i);
	}

	write_gicreg(cpu_if->vgic_vmcr, ICH_VMCR_EL2);

	if (live_lrs) {
		write_gicreg(cpu_if->vgic_hcr, ICH_HCR_EL2);

		switch (nr_pri_bits) {
		case 7:
			write_gicreg(cpu_if->vgic_ap0r[3], ICH_AP0R3_EL2);
			write_gicreg(cpu_if->vgic_ap0r[2], ICH_AP0R2_EL2);
		case 6:
			write_gicreg(cpu_if->vgic_ap0r[1], ICH_AP0R1_EL2);
		default:
			write_gicreg(cpu_if->vgic_ap0r[0], ICH_AP0R0_EL2);
		}

		switch (nr_pri_bits) {
		case 7:
			write_gicreg(cpu_if->vgic_ap1r[3], ICH_AP1R3_EL2);
			write_gicreg(cpu_if->vgic_ap1r[2], ICH_AP1R2_EL2);
		case 6:
			write_gicreg(cpu_if->vgic_ap1r[1], ICH_AP1R1_EL2);
		default:
			write_gicreg(cpu_if->vgic_ap1r[0], ICH_AP1R0_EL2);
		}

		for (i = 0; i <= max_lr_idx; i++) {
			val = 0;

			if (live_lrs & (1 << i))
				val = cpu_if->vgic_lr[i];

			__gic_v3_set_lr(val, i);
		}
	}

	/*
	 * Ensures that the above will have reached the
	 * (re)distributors. This ensure the guest will read the
	 * correct values from the memory-mapped interface.
	 */
	isb();
	dsb(sy);
	vcpu->arch.vgic_cpu.live_lrs = live_lrs;

	/*
	 * Prevent the guest from touching the GIC system registers if
	 * SRE isn't enabled for GICv3 emulation.
	 */
	if (!cpu_if->vgic_sre) {
		write_gicreg(read_gicreg(ICC_SRE_EL2) & ~ICC_SRE_EL2_ENABLE,
			     ICC_SRE_EL2);
	}
}

static u64 __hyp_text __vgic_v3_read_ich_vtr_el2(void)
{
	return read_gicreg(ICH_VTR_EL2);
}

__alias(__vgic_v3_read_ich_vtr_el2) u64 __vgic_v3_get_ich_vtr_el2(void);
Commit	Line	Data
f68d2b1b MZ	1	/*
	2	* Copyright (C) 2012-2015 - ARM Ltd
	3	* Author: Marc Zyngier <marc.zyngier@arm.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	#include <linux/compiler.h>
	19	#include <linux/irqchip/arm-gic-v3.h>
	20	#include <linux/kvm_host.h>
	21
13720a56	22	#include <asm/kvm_hyp.h>
f68d2b1b MZ	23
	24	#define vtr_to_max_lr_idx(v) ((v) & 0xf)
	25	#define vtr_to_nr_pri_bits(v) (((u32)(v) >> 29) + 1)
	26
	27	#define read_gicreg(r) \
	28	({ \
	29	u64 reg; \
	30	asm volatile("mrs_s %0, " __stringify(r) : "=r" (reg)); \
	31	reg; \
	32	})
	33
	34	#define write_gicreg(v,r) \
	35	do { \
	36	u64 __val = (v); \
	37	asm volatile("msr_s " __stringify(r) ", %0" : : "r" (__val));\
	38	} while (0)
	39
1b8e83c0 MZ	40	static u64 __hyp_text __gic_v3_get_lr(unsigned int lr)
	41	{
	42	switch (lr & 0xf) {
	43	case 0:
	44	return read_gicreg(ICH_LR0_EL2);
	45	case 1:
	46	return read_gicreg(ICH_LR1_EL2);
	47	case 2:
	48	return read_gicreg(ICH_LR2_EL2);
	49	case 3:
	50	return read_gicreg(ICH_LR3_EL2);
	51	case 4:
	52	return read_gicreg(ICH_LR4_EL2);
	53	case 5:
	54	return read_gicreg(ICH_LR5_EL2);
	55	case 6:
	56	return read_gicreg(ICH_LR6_EL2);
	57	case 7:
	58	return read_gicreg(ICH_LR7_EL2);
	59	case 8:
	60	return read_gicreg(ICH_LR8_EL2);
	61	case 9:
	62	return read_gicreg(ICH_LR9_EL2);
	63	case 10:
	64	return read_gicreg(ICH_LR10_EL2);
	65	case 11:
	66	return read_gicreg(ICH_LR11_EL2);
	67	case 12:
	68	return read_gicreg(ICH_LR12_EL2);
	69	case 13:
	70	return read_gicreg(ICH_LR13_EL2);
	71	case 14:
	72	return read_gicreg(ICH_LR14_EL2);
	73	case 15:
	74	return read_gicreg(ICH_LR15_EL2);
	75	}
	76
	77	unreachable();
	78	}
	79
	80	static void __hyp_text __gic_v3_set_lr(u64 val, int lr)
	81	{
	82	switch (lr & 0xf) {
	83	case 0:
	84	write_gicreg(val, ICH_LR0_EL2);
	85	break;
	86	case 1:
	87	write_gicreg(val, ICH_LR1_EL2);
	88	break;
	89	case 2:
	90	write_gicreg(val, ICH_LR2_EL2);
	91	break;
	92	case 3:
	93	write_gicreg(val, ICH_LR3_EL2);
	94	break;
	95	case 4:
	96	write_gicreg(val, ICH_LR4_EL2);
	97	break;
	98	case 5:
	99	write_gicreg(val, ICH_LR5_EL2);
	100	break;
	101	case 6:
	102	write_gicreg(val, ICH_LR6_EL2);
	103	break;
104	case 7:
105	write_gicreg(val, ICH_LR7_EL2);
106	break;
107	case 8:
108	write_gicreg(val, ICH_LR8_EL2);
109	break;
110	case 9:
111	write_gicreg(val, ICH_LR9_EL2);
112	break;
113	case 10:
114	write_gicreg(val, ICH_LR10_EL2);
115	break;
116	case 11:
117	write_gicreg(val, ICH_LR11_EL2);
118	break;
119	case 12:
120	write_gicreg(val, ICH_LR12_EL2);
121	break;
122	case 13:
123	write_gicreg(val, ICH_LR13_EL2);
124	break;
125	case 14:
126	write_gicreg(val, ICH_LR14_EL2);
127	break;
128	case 15:
129	write_gicreg(val, ICH_LR15_EL2);
130	break;
131	}
132	}
133
f68d2b1b MZ	134	void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu)
	135	{
	136	struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
	137	u64 val;
f68d2b1b MZ	138
	139	/*
	140	* Make sure stores to the GIC via the memory mapped interface
	141	* are now visible to the system register interface.
	142	*/
	143	dsb(st);
	144
	145	cpu_if->vgic_vmcr = read_gicreg(ICH_VMCR_EL2);
f68d2b1b	146
1b8e83c0 MZ	147	if (vcpu->arch.vgic_cpu.live_lrs) {
	148	int i;
	149	u32 max_lr_idx, nr_pri_bits;
f68d2b1b	150
1b8e83c0 MZ	151	cpu_if->vgic_misr = read_gicreg(ICH_MISR_EL2);
	152	cpu_if->vgic_eisr = read_gicreg(ICH_EISR_EL2);
	153	cpu_if->vgic_elrsr = read_gicreg(ICH_ELSR_EL2);
f68d2b1b	154
1b8e83c0 MZ	155	write_gicreg(0, ICH_HCR_EL2);
	156	val = read_gicreg(ICH_VTR_EL2);
	157	max_lr_idx = vtr_to_max_lr_idx(val);
	158	nr_pri_bits = vtr_to_nr_pri_bits(val);
f68d2b1b	159
1b8e83c0 MZ	160	for (i = 0; i <= max_lr_idx; i++) {
	161	if (vcpu->arch.vgic_cpu.live_lrs & (1UL << i))
	162	cpu_if->vgic_lr[i] = __gic_v3_get_lr(i);
	163	}
	164
	165	switch (nr_pri_bits) {
	166	case 7:
	167	cpu_if->vgic_ap0r[3] = read_gicreg(ICH_AP0R3_EL2);
	168	cpu_if->vgic_ap0r[2] = read_gicreg(ICH_AP0R2_EL2);
	169	case 6:
	170	cpu_if->vgic_ap0r[1] = read_gicreg(ICH_AP0R1_EL2);
	171	default:
	172	cpu_if->vgic_ap0r[0] = read_gicreg(ICH_AP0R0_EL2);
	173	}
	174
	175	switch (nr_pri_bits) {
	176	case 7:
	177	cpu_if->vgic_ap1r[3] = read_gicreg(ICH_AP1R3_EL2);
	178	cpu_if->vgic_ap1r[2] = read_gicreg(ICH_AP1R2_EL2);
	179	case 6:
	180	cpu_if->vgic_ap1r[1] = read_gicreg(ICH_AP1R1_EL2);
	181	default:
	182	cpu_if->vgic_ap1r[0] = read_gicreg(ICH_AP1R0_EL2);
	183	}
	184
	185	vcpu->arch.vgic_cpu.live_lrs = 0;
	186	} else {
	187	cpu_if->vgic_misr = 0;
	188	cpu_if->vgic_eisr = 0;
	189	cpu_if->vgic_elrsr = 0xffff;
	190	cpu_if->vgic_ap0r[0] = 0;
	191	cpu_if->vgic_ap0r[1] = 0;
	192	cpu_if->vgic_ap0r[2] = 0;
	193	cpu_if->vgic_ap0r[3] = 0;
	194	cpu_if->vgic_ap1r[0] = 0;
	195	cpu_if->vgic_ap1r[1] = 0;
	196	cpu_if->vgic_ap1r[2] = 0;
	197	cpu_if->vgic_ap1r[3] = 0;
f68d2b1b MZ	198	}
	199
	200	val = read_gicreg(ICC_SRE_EL2);
	201	write_gicreg(val \| ICC_SRE_EL2_ENABLE, ICC_SRE_EL2);
	202	isb(); /* Make sure ENABLE is set at EL2 before setting SRE at EL1 */
	203	write_gicreg(1, ICC_SRE_EL1);
	204	}
	205
	206	void __hyp_text __vgic_v3_restore_state(struct kvm_vcpu *vcpu)
	207	{
	208	struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
	209	u64 val;
	210	u32 max_lr_idx, nr_pri_bits;
1b8e83c0 MZ	211	u16 live_lrs = 0;
1b8e83c0 MZ	212	int i;
f68d2b1b MZ	213
	214	/*
	215	* VFIQEn is RES1 if ICC_SRE_EL1.SRE is 1. This causes a
	216	* Group0 interrupt (as generated in GICv2 mode) to be
	217	* delivered as a FIQ to the guest, with potentially fatal
	218	* consequences. So we must make sure that ICC_SRE_EL1 has
	219	* been actually programmed with the value we want before
	220	* starting to mess with the rest of the GIC.
	221	*/
	222	write_gicreg(cpu_if->vgic_sre, ICC_SRE_EL1);
	223	isb();
	224
f68d2b1b MZ	225	val = read_gicreg(ICH_VTR_EL2);
	226	max_lr_idx = vtr_to_max_lr_idx(val);
	227	nr_pri_bits = vtr_to_nr_pri_bits(val);
	228
1b8e83c0 MZ	229	for (i = 0; i <= max_lr_idx; i++) {
	230	if (cpu_if->vgic_lr[i] & ICH_LR_STATE)
	231	live_lrs \|= (1 << i);
f68d2b1b MZ	232	}
f68d2b1b MZ	233
1b8e83c0	234	write_gicreg(cpu_if->vgic_vmcr, ICH_VMCR_EL2);
fd451b90	235
1b8e83c0 MZ	236	if (live_lrs) {
	237	write_gicreg(cpu_if->vgic_hcr, ICH_HCR_EL2);
	238
	239	switch (nr_pri_bits) {
	240	case 7:
	241	write_gicreg(cpu_if->vgic_ap0r[3], ICH_AP0R3_EL2);
	242	write_gicreg(cpu_if->vgic_ap0r[2], ICH_AP0R2_EL2);
	243	case 6:
	244	write_gicreg(cpu_if->vgic_ap0r[1], ICH_AP0R1_EL2);
	245	default:
	246	write_gicreg(cpu_if->vgic_ap0r[0], ICH_AP0R0_EL2);
	247	}
	248
	249	switch (nr_pri_bits) {
	250	case 7:
	251	write_gicreg(cpu_if->vgic_ap1r[3], ICH_AP1R3_EL2);
	252	write_gicreg(cpu_if->vgic_ap1r[2], ICH_AP1R2_EL2);
	253	case 6:
	254	write_gicreg(cpu_if->vgic_ap1r[1], ICH_AP1R1_EL2);
	255	default:
	256	write_gicreg(cpu_if->vgic_ap1r[0], ICH_AP1R0_EL2);
	257	}
	258
	259	for (i = 0; i <= max_lr_idx; i++) {
	260	val = 0;
	261
	262	if (live_lrs & (1 << i))
	263	val = cpu_if->vgic_lr[i];
	264
	265	__gic_v3_set_lr(val, i);
	266	}
f68d2b1b MZ	267	}
	268
	269	/*
	270	* Ensures that the above will have reached the
	271	* (re)distributors. This ensure the guest will read the
	272	* correct values from the memory-mapped interface.
	273	*/
	274	isb();
	275	dsb(sy);
1b8e83c0	276	vcpu->arch.vgic_cpu.live_lrs = live_lrs;
f68d2b1b MZ	277
	278	/*
	279	* Prevent the guest from touching the GIC system registers if
	280	* SRE isn't enabled for GICv3 emulation.
	281	*/
	282	if (!cpu_if->vgic_sre) {
	283	write_gicreg(read_gicreg(ICC_SRE_EL2) & ~ICC_SRE_EL2_ENABLE,
	284	ICC_SRE_EL2);
	285	}
	286	}
	287
3ffa75cd	288	static u64 __hyp_text __vgic_v3_read_ich_vtr_el2(void)
f68d2b1b MZ	289	{
	290	return read_gicreg(ICH_VTR_EL2);
	291	}
044ac37d	292
3ffa75cd	293	__alias(__vgic_v3_read_ich_vtr_el2) u64 __vgic_v3_get_ich_vtr_el2(void);