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arm64: KVM: PMU: Refactor pmu_*_el0_disabled
[mirror_ubuntu-artful-kernel.git] / arch / arm64 / kvm / sys_regs.c
CommitLineData
7c8c5e6a
MZ		 1/*
2 * Copyright (C) 2012,2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * Derived from arch/arm/kvm/coproc.c:
6 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
7 * Authors: Rusty Russell <rusty@rustcorp.com.au>
8 * Christoffer Dall <c.dall@virtualopensystems.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License, version 2, as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
623eefa8 23#include <linux/bsearch.h>
7c8c5e6a 24#include <linux/kvm_host.h>
c6d01a94 25#include <linux/mm.h>
7c8c5e6a 26#include <linux/uaccess.h>
c6d01a94 27
7c8c5e6a
MZ		 28#include <asm/cacheflush.h>
29#include <asm/cputype.h>
0c557ed4 30#include <asm/debug-monitors.h>
c6d01a94
MR		 31#include <asm/esr.h>
32#include <asm/kvm_arm.h>
9d8415d6 33#include <asm/kvm_asm.h>
c6d01a94
MR		 34#include <asm/kvm_coproc.h>
35#include <asm/kvm_emulate.h>
36#include <asm/kvm_host.h>
37#include <asm/kvm_mmu.h>
ab946834 38#include <asm/perf_event.h>
1f3d8699 39#include <asm/sysreg.h>
c6d01a94 40
7c8c5e6a
MZ		 41#include <trace/events/kvm.h>
42
43#include "sys_regs.h"
44
eef8c85a
AB		 45#include "trace.h"
46
7c8c5e6a
MZ		 47/*
48 * All of this file is extremly similar to the ARM coproc.c, but the
49 * types are different. My gut feeling is that it should be pretty
50 * easy to merge, but that would be an ABI breakage -- again. VFP
51 * would also need to be abstracted.
62a89c44
MZ		 52 *
53 * For AArch32, we only take care of what is being trapped. Anything
54 * that has to do with init and userspace access has to go via the
55 * 64bit interface.
7c8c5e6a
MZ		 56 */
57
58/* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
59static u32 cache_levels;
60
61/* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
62#define CSSELR_MAX 12
63
64/* Which cache CCSIDR represents depends on CSSELR value. */
65static u32 get_ccsidr(u32 csselr)
66{
67 u32 ccsidr;
68
69 /* Make sure noone else changes CSSELR during this! */
70 local_irq_disable();
1f3d8699 71 write_sysreg(csselr, csselr_el1);
7c8c5e6a 72 isb();
1f3d8699 73 ccsidr = read_sysreg(ccsidr_el1);
7c8c5e6a
MZ		 74 local_irq_enable();
75
76 return ccsidr;
77}
78
3c1e7165
MZ		 79/*
80 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
81 */
7c8c5e6a 82static bool access_dcsw(struct kvm_vcpu *vcpu,
3fec037d 83 struct sys_reg_params *p,
7c8c5e6a
MZ		 84 const struct sys_reg_desc *r)
85{
7c8c5e6a
MZ		 86 if (!p->is_write)
87 return read_from_write_only(vcpu, p);
88
3c1e7165 89 kvm_set_way_flush(vcpu);
7c8c5e6a
MZ		 90 return true;
91}
92
4d44923b
MZ		 93/*
94 * Generic accessor for VM registers. Only called as long as HCR_TVM
3c1e7165
MZ		 95 * is set. If the guest enables the MMU, we stop trapping the VM
96 * sys_regs and leave it in complete control of the caches.
4d44923b
MZ		 97 */
98static bool access_vm_reg(struct kvm_vcpu *vcpu,
3fec037d 99 struct sys_reg_params *p,
4d44923b
MZ		 100 const struct sys_reg_desc *r)
101{
3c1e7165 102 bool was_enabled = vcpu_has_cache_enabled(vcpu);
4d44923b
MZ		 103
104 BUG_ON(!p->is_write);
105
dedf97e8 106 if (!p->is_aarch32) {
2ec5be3d 107 vcpu_sys_reg(vcpu, r->reg) = p->regval;
dedf97e8
MZ		 108 } else {
109 if (!p->is_32bit)
2ec5be3d
PF		 110 vcpu_cp15_64_high(vcpu, r->reg) = upper_32_bits(p->regval);
111 vcpu_cp15_64_low(vcpu, r->reg) = lower_32_bits(p->regval);
dedf97e8 112 }
f0a3eaff 113
3c1e7165 114 kvm_toggle_cache(vcpu, was_enabled);
4d44923b
MZ		 115 return true;
116}
117
6d52f35a
AP		 118/*
119 * Trap handler for the GICv3 SGI generation system register.
120 * Forward the request to the VGIC emulation.
121 * The cp15_64 code makes sure this automatically works
122 * for both AArch64 and AArch32 accesses.
123 */
124static bool access_gic_sgi(struct kvm_vcpu *vcpu,
3fec037d 125 struct sys_reg_params *p,
6d52f35a
AP		 126 const struct sys_reg_desc *r)
127{
6d52f35a
AP		 128 if (!p->is_write)
129 return read_from_write_only(vcpu, p);
130
2ec5be3d 131 vgic_v3_dispatch_sgi(vcpu, p->regval);
6d52f35a
AP		 132
133 return true;
134}
135
b34f2bcb
MZ		 136static bool access_gic_sre(struct kvm_vcpu *vcpu,
137 struct sys_reg_params *p,
138 const struct sys_reg_desc *r)
139{
140 if (p->is_write)
141 return ignore_write(vcpu, p);
142
143 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
144 return true;
145}
146
7609c125 147static bool trap_raz_wi(struct kvm_vcpu *vcpu,
3fec037d 148 struct sys_reg_params *p,
7609c125 149 const struct sys_reg_desc *r)
7c8c5e6a
MZ		 150{
151 if (p->is_write)
152 return ignore_write(vcpu, p);
153 else
154 return read_zero(vcpu, p);
155}
156
0c557ed4 157static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
3fec037d 158 struct sys_reg_params *p,
0c557ed4
MZ		 159 const struct sys_reg_desc *r)
160{
161 if (p->is_write) {
162 return ignore_write(vcpu, p);
163 } else {
2ec5be3d 164 p->regval = (1 << 3);
0c557ed4
MZ		 165 return true;
166 }
167}
168
169static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
3fec037d 170 struct sys_reg_params *p,
0c557ed4
MZ		 171 const struct sys_reg_desc *r)
172{
173 if (p->is_write) {
174 return ignore_write(vcpu, p);
175 } else {
1f3d8699 176 p->regval = read_sysreg(dbgauthstatus_el1);
0c557ed4
MZ		 177 return true;
178 }
179}
180
181/*
182 * We want to avoid world-switching all the DBG registers all the
183 * time:
184 *
185 * - If we've touched any debug register, it is likely that we're
186 * going to touch more of them. It then makes sense to disable the
187 * traps and start doing the save/restore dance
188 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
189 * then mandatory to save/restore the registers, as the guest
190 * depends on them.
191 *
192 * For this, we use a DIRTY bit, indicating the guest has modified the
193 * debug registers, used as follow:
194 *
195 * On guest entry:
196 * - If the dirty bit is set (because we're coming back from trapping),
197 * disable the traps, save host registers, restore guest registers.
198 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
199 * set the dirty bit, disable the traps, save host registers,
200 * restore guest registers.
201 * - Otherwise, enable the traps
202 *
203 * On guest exit:
204 * - If the dirty bit is set, save guest registers, restore host
205 * registers and clear the dirty bit. This ensure that the host can
206 * now use the debug registers.
207 */
208static bool trap_debug_regs(struct kvm_vcpu *vcpu,
3fec037d 209 struct sys_reg_params *p,
0c557ed4
MZ		 210 const struct sys_reg_desc *r)
211{
212 if (p->is_write) {
2ec5be3d 213 vcpu_sys_reg(vcpu, r->reg) = p->regval;
0c557ed4
MZ		 214 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
215 } else {
2ec5be3d 216 p->regval = vcpu_sys_reg(vcpu, r->reg);
0c557ed4
MZ		 217 }
218
2ec5be3d 219 trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
eef8c85a 220
0c557ed4
MZ		 221 return true;
222}
223
84e690bf
AB		 224/*
225 * reg_to_dbg/dbg_to_reg
226 *
227 * A 32 bit write to a debug register leave top bits alone
228 * A 32 bit read from a debug register only returns the bottom bits
229 *
230 * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the
231 * hyp.S code switches between host and guest values in future.
232 */
281243cb
MZ		 233static void reg_to_dbg(struct kvm_vcpu *vcpu,
234 struct sys_reg_params *p,
235 u64 *dbg_reg)
84e690bf 236{
2ec5be3d 237 u64 val = p->regval;
84e690bf
AB		 238
239 if (p->is_32bit) {
240 val &= 0xffffffffUL;
241 val |= ((*dbg_reg >> 32) << 32);
242 }
243
244 *dbg_reg = val;
245 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
246}
247
281243cb
MZ		 248static void dbg_to_reg(struct kvm_vcpu *vcpu,
249 struct sys_reg_params *p,
250 u64 *dbg_reg)
84e690bf 251{
2ec5be3d 252 p->regval = *dbg_reg;
84e690bf 253 if (p->is_32bit)
2ec5be3d 254 p->regval &= 0xffffffffUL;
84e690bf
AB		 255}
256
281243cb
MZ		 257static bool trap_bvr(struct kvm_vcpu *vcpu,
258 struct sys_reg_params *p,
259 const struct sys_reg_desc *rd)
84e690bf
AB		 260{
261 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
262
263 if (p->is_write)
264 reg_to_dbg(vcpu, p, dbg_reg);
265 else
266 dbg_to_reg(vcpu, p, dbg_reg);
267
eef8c85a
AB		 268 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
269
84e690bf
AB		 270 return true;
271}
272
273static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
274 const struct kvm_one_reg *reg, void __user *uaddr)
275{
276 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
277
1713e5aa 278 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 279 return -EFAULT;
280 return 0;
281}
282
283static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
284 const struct kvm_one_reg *reg, void __user *uaddr)
285{
286 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
287
288 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
289 return -EFAULT;
290 return 0;
291}
292
281243cb
MZ		 293static void reset_bvr(struct kvm_vcpu *vcpu,
294 const struct sys_reg_desc *rd)
84e690bf
AB		 295{
296 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val;
297}
298
281243cb
MZ		 299static bool trap_bcr(struct kvm_vcpu *vcpu,
300 struct sys_reg_params *p,
301 const struct sys_reg_desc *rd)
84e690bf
AB		 302{
303 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
304
305 if (p->is_write)
306 reg_to_dbg(vcpu, p, dbg_reg);
307 else
308 dbg_to_reg(vcpu, p, dbg_reg);
309
eef8c85a
AB		 310 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
311
84e690bf
AB		 312 return true;
313}
314
315static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
316 const struct kvm_one_reg *reg, void __user *uaddr)
317{
318 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
319
1713e5aa 320 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 321 return -EFAULT;
322
323 return 0;
324}
325
326static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
327 const struct kvm_one_reg *reg, void __user *uaddr)
328{
329 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
330
331 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
332 return -EFAULT;
333 return 0;
334}
335
281243cb
MZ		 336static void reset_bcr(struct kvm_vcpu *vcpu,
337 const struct sys_reg_desc *rd)
84e690bf
AB		 338{
339 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val;
340}
341
281243cb
MZ		 342static bool trap_wvr(struct kvm_vcpu *vcpu,
343 struct sys_reg_params *p,
344 const struct sys_reg_desc *rd)
84e690bf
AB		 345{
346 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
347
348 if (p->is_write)
349 reg_to_dbg(vcpu, p, dbg_reg);
350 else
351 dbg_to_reg(vcpu, p, dbg_reg);
352
eef8c85a
AB		 353 trace_trap_reg(__func__, rd->reg, p->is_write,
354 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]);
355
84e690bf
AB		 356 return true;
357}
358
359static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
360 const struct kvm_one_reg *reg, void __user *uaddr)
361{
362 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
363
1713e5aa 364 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 365 return -EFAULT;
366 return 0;
367}
368
369static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
370 const struct kvm_one_reg *reg, void __user *uaddr)
371{
372 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
373
374 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
375 return -EFAULT;
376 return 0;
377}
378
281243cb
MZ		 379static void reset_wvr(struct kvm_vcpu *vcpu,
380 const struct sys_reg_desc *rd)
84e690bf
AB		 381{
382 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val;
383}
384
281243cb
MZ		 385static bool trap_wcr(struct kvm_vcpu *vcpu,
386 struct sys_reg_params *p,
387 const struct sys_reg_desc *rd)
84e690bf
AB		 388{
389 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
390
391 if (p->is_write)
392 reg_to_dbg(vcpu, p, dbg_reg);
393 else
394 dbg_to_reg(vcpu, p, dbg_reg);
395
eef8c85a
AB		 396 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
397
84e690bf
AB		 398 return true;
399}
400
401static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
402 const struct kvm_one_reg *reg, void __user *uaddr)
403{
404 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
405
1713e5aa 406 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 407 return -EFAULT;
408 return 0;
409}
410
411static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
412 const struct kvm_one_reg *reg, void __user *uaddr)
413{
414 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
415
416 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
417 return -EFAULT;
418 return 0;
419}
420
281243cb
MZ		 421static void reset_wcr(struct kvm_vcpu *vcpu,
422 const struct sys_reg_desc *rd)
84e690bf
AB		 423{
424 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val;
425}
426
7c8c5e6a
MZ		 427static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
428{
1f3d8699 429 vcpu_sys_reg(vcpu, AMAIR_EL1) = read_sysreg(amair_el1);
7c8c5e6a
MZ		 430}
431
432static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
433{
4429fc64
AP		 434 u64 mpidr;
435
7c8c5e6a 436 /*
4429fc64
AP		 437 * Map the vcpu_id into the first three affinity level fields of
438 * the MPIDR. We limit the number of VCPUs in level 0 due to a
439 * limitation to 16 CPUs in that level in the ICC_SGIxR registers
440 * of the GICv3 to be able to address each CPU directly when
441 * sending IPIs.
7c8c5e6a 442 */
4429fc64
AP		 443 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
444 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
445 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
446 vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr;
7c8c5e6a
MZ		 447}
448
ab946834
SZ		 449static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
450{
451 u64 pmcr, val;
452
1f3d8699
MR		 453 pmcr = read_sysreg(pmcr_el0);
454 /*
455 * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN
ab946834
SZ		 456 * except PMCR.E resetting to zero.
457 */
458 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
459 | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
460 vcpu_sys_reg(vcpu, PMCR_EL0) = val;
461}
462
6c007036 463static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
d692b8ad
SZ		 464{
465 u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
6c007036 466 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu);
d692b8ad 467
6c007036 468 return !enabled;
d692b8ad
SZ		 469}
470
6c007036 471static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
d692b8ad 472{
6c007036
MZ		 473 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN);
474}
d692b8ad 475
6c007036
MZ		 476static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
477{
478 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN);
d692b8ad
SZ		 479}
480
481static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
482{
6c007036 483 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN);
d692b8ad
SZ		 484}
485
486static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
487{
6c007036 488 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN);
d692b8ad
SZ		 489}
490
ab946834
SZ		 491static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
492 const struct sys_reg_desc *r)
493{
494 u64 val;
495
496 if (!kvm_arm_pmu_v3_ready(vcpu))
497 return trap_raz_wi(vcpu, p, r);
498
d692b8ad
SZ		 499 if (pmu_access_el0_disabled(vcpu))
500 return false;
501
ab946834
SZ		 502 if (p->is_write) {
503 /* Only update writeable bits of PMCR */
504 val = vcpu_sys_reg(vcpu, PMCR_EL0);
505 val &= ~ARMV8_PMU_PMCR_MASK;
506 val |= p->regval & ARMV8_PMU_PMCR_MASK;
507 vcpu_sys_reg(vcpu, PMCR_EL0) = val;
76993739 508 kvm_pmu_handle_pmcr(vcpu, val);
ab946834
SZ		 509 } else {
510 /* PMCR.P & PMCR.C are RAZ */
511 val = vcpu_sys_reg(vcpu, PMCR_EL0)
512 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
513 p->regval = val;
514 }
515
516 return true;
517}
518
3965c3ce
SZ		 519static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
520 const struct sys_reg_desc *r)
521{
522 if (!kvm_arm_pmu_v3_ready(vcpu))
523 return trap_raz_wi(vcpu, p, r);
524
d692b8ad
SZ		 525 if (pmu_access_event_counter_el0_disabled(vcpu))
526 return false;
527
3965c3ce
SZ		 528 if (p->is_write)
529 vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
530 else
531 /* return PMSELR.SEL field */
532 p->regval = vcpu_sys_reg(vcpu, PMSELR_EL0)
533 & ARMV8_PMU_COUNTER_MASK;
534
535 return true;
536}
537
a86b5505
SZ		 538static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
539 const struct sys_reg_desc *r)
540{
541 u64 pmceid;
542
543 if (!kvm_arm_pmu_v3_ready(vcpu))
544 return trap_raz_wi(vcpu, p, r);
545
546 BUG_ON(p->is_write);
547
d692b8ad
SZ		 548 if (pmu_access_el0_disabled(vcpu))
549 return false;
550
a86b5505 551 if (!(p->Op2 & 1))
1f3d8699 552 pmceid = read_sysreg(pmceid0_el0);
a86b5505 553 else
1f3d8699 554 pmceid = read_sysreg(pmceid1_el0);
a86b5505
SZ		 555
556 p->regval = pmceid;
557
558 return true;
559}
560
051ff581
SZ		 561static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
562{
563 u64 pmcr, val;
564
565 pmcr = vcpu_sys_reg(vcpu, PMCR_EL0);
566 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
567 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX)
568 return false;
569
570 return true;
571}
572
573static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
574 struct sys_reg_params *p,
575 const struct sys_reg_desc *r)
576{
577 u64 idx;
578
579 if (!kvm_arm_pmu_v3_ready(vcpu))
580 return trap_raz_wi(vcpu, p, r);
581
582 if (r->CRn == 9 && r->CRm == 13) {
583 if (r->Op2 == 2) {
584 /* PMXEVCNTR_EL0 */
d692b8ad
SZ		 585 if (pmu_access_event_counter_el0_disabled(vcpu))
586 return false;
587
051ff581
SZ		 588 idx = vcpu_sys_reg(vcpu, PMSELR_EL0)
589 & ARMV8_PMU_COUNTER_MASK;
590 } else if (r->Op2 == 0) {
591 /* PMCCNTR_EL0 */
d692b8ad
SZ		 592 if (pmu_access_cycle_counter_el0_disabled(vcpu))
593 return false;
594
051ff581
SZ		 595 idx = ARMV8_PMU_CYCLE_IDX;
596 } else {
9e3f7a29 597 return false;
051ff581 598 }
9e3f7a29
WH		 599 } else if (r->CRn == 0 && r->CRm == 9) {
600 /* PMCCNTR */
601 if (pmu_access_event_counter_el0_disabled(vcpu))
602 return false;
603
604 idx = ARMV8_PMU_CYCLE_IDX;
051ff581
SZ		 605 } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
606 /* PMEVCNTRn_EL0 */
d692b8ad
SZ		 607 if (pmu_access_event_counter_el0_disabled(vcpu))
608 return false;
609
051ff581
SZ		 610 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
611 } else {
9e3f7a29 612 return false;
051ff581
SZ		 613 }
614
615 if (!pmu_counter_idx_valid(vcpu, idx))
616 return false;
617
d692b8ad
SZ		 618 if (p->is_write) {
619 if (pmu_access_el0_disabled(vcpu))
620 return false;
621
051ff581 622 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
d692b8ad 623 } else {
051ff581 624 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
d692b8ad 625 }
051ff581
SZ		 626
627 return true;
628}
629
9feb21ac
SZ		 630static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
631 const struct sys_reg_desc *r)
632{
633 u64 idx, reg;
634
635 if (!kvm_arm_pmu_v3_ready(vcpu))
636 return trap_raz_wi(vcpu, p, r);
637
d692b8ad
SZ		 638 if (pmu_access_el0_disabled(vcpu))
639 return false;
640
9feb21ac
SZ		 641 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
642 /* PMXEVTYPER_EL0 */
643 idx = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
644 reg = PMEVTYPER0_EL0 + idx;
645 } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
646 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
647 if (idx == ARMV8_PMU_CYCLE_IDX)
648 reg = PMCCFILTR_EL0;
649 else
650 /* PMEVTYPERn_EL0 */
651 reg = PMEVTYPER0_EL0 + idx;
652 } else {
653 BUG();
654 }
655
656 if (!pmu_counter_idx_valid(vcpu, idx))
657 return false;
658
659 if (p->is_write) {
660 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
661 vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
662 } else {
663 p->regval = vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
664 }
665
666 return true;
667}
668
96b0eebc
SZ		 669static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
670 const struct sys_reg_desc *r)
671{
672 u64 val, mask;
673
674 if (!kvm_arm_pmu_v3_ready(vcpu))
675 return trap_raz_wi(vcpu, p, r);
676
d692b8ad
SZ		 677 if (pmu_access_el0_disabled(vcpu))
678 return false;
679
96b0eebc
SZ		 680 mask = kvm_pmu_valid_counter_mask(vcpu);
681 if (p->is_write) {
682 val = p->regval & mask;
683 if (r->Op2 & 0x1) {
684 /* accessing PMCNTENSET_EL0 */
685 vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
686 kvm_pmu_enable_counter(vcpu, val);
687 } else {
688 /* accessing PMCNTENCLR_EL0 */
689 vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
690 kvm_pmu_disable_counter(vcpu, val);
691 }
692 } else {
693 p->regval = vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
694 }
695
696 return true;
697}
698
9db52c78
SZ		 699static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
700 const struct sys_reg_desc *r)
701{
702 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
703
704 if (!kvm_arm_pmu_v3_ready(vcpu))
705 return trap_raz_wi(vcpu, p, r);
706
d692b8ad
SZ		 707 if (!vcpu_mode_priv(vcpu))
708 return false;
709
9db52c78
SZ		 710 if (p->is_write) {
711 u64 val = p->regval & mask;
712
713 if (r->Op2 & 0x1)
714 /* accessing PMINTENSET_EL1 */
715 vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
716 else
717 /* accessing PMINTENCLR_EL1 */
718 vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
719 } else {
720 p->regval = vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask;
721 }
722
723 return true;
724}
725
76d883c4
SZ		 726static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
727 const struct sys_reg_desc *r)
728{
729 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
730
731 if (!kvm_arm_pmu_v3_ready(vcpu))
732 return trap_raz_wi(vcpu, p, r);
733
d692b8ad
SZ		 734 if (pmu_access_el0_disabled(vcpu))
735 return false;
736
76d883c4
SZ		 737 if (p->is_write) {
738 if (r->CRm & 0x2)
739 /* accessing PMOVSSET_EL0 */
740 kvm_pmu_overflow_set(vcpu, p->regval & mask);
741 else
742 /* accessing PMOVSCLR_EL0 */
743 vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
744 } else {
745 p->regval = vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask;
746 }
747
748 return true;
749}
750
7a0adc70
SZ		 751static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
752 const struct sys_reg_desc *r)
753{
754 u64 mask;
755
756 if (!kvm_arm_pmu_v3_ready(vcpu))
757 return trap_raz_wi(vcpu, p, r);
758
d692b8ad
SZ		 759 if (pmu_write_swinc_el0_disabled(vcpu))
760 return false;
761
7a0adc70
SZ		 762 if (p->is_write) {
763 mask = kvm_pmu_valid_counter_mask(vcpu);
764 kvm_pmu_software_increment(vcpu, p->regval & mask);
765 return true;
766 }
767
768 return false;
769}
770
d692b8ad
SZ		 771static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
772 const struct sys_reg_desc *r)
773{
774 if (!kvm_arm_pmu_v3_ready(vcpu))
775 return trap_raz_wi(vcpu, p, r);
776
777 if (p->is_write) {
778 if (!vcpu_mode_priv(vcpu))
779 return false;
780
781 vcpu_sys_reg(vcpu, PMUSERENR_EL0) = p->regval
782 & ARMV8_PMU_USERENR_MASK;
783 } else {
784 p->regval = vcpu_sys_reg(vcpu, PMUSERENR_EL0)
785 & ARMV8_PMU_USERENR_MASK;
786 }
787
788 return true;
789}
790
0c557ed4
MZ		 791/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
792#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
793 /* DBGBVRn_EL1 */ \
794 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b100), \
84e690bf 795 trap_bvr, reset_bvr, n, 0, get_bvr, set_bvr }, \
0c557ed4
MZ		 796 /* DBGBCRn_EL1 */ \
797 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b101), \
84e690bf 798 trap_bcr, reset_bcr, n, 0, get_bcr, set_bcr }, \
0c557ed4
MZ		 799 /* DBGWVRn_EL1 */ \
800 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b110), \
84e690bf 801 trap_wvr, reset_wvr, n, 0, get_wvr, set_wvr }, \
0c557ed4
MZ		 802 /* DBGWCRn_EL1 */ \
803 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b111), \
84e690bf 804 trap_wcr, reset_wcr, n, 0, get_wcr, set_wcr }
0c557ed4 805
051ff581
SZ		 806/* Macro to expand the PMEVCNTRn_EL0 register */
807#define PMU_PMEVCNTR_EL0(n) \
808 /* PMEVCNTRn_EL0 */ \
809 { Op0(0b11), Op1(0b011), CRn(0b1110), \
810 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
811 access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), }
812
9feb21ac
SZ		 813/* Macro to expand the PMEVTYPERn_EL0 register */
814#define PMU_PMEVTYPER_EL0(n) \
815 /* PMEVTYPERn_EL0 */ \
816 { Op0(0b11), Op1(0b011), CRn(0b1110), \
817 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
818 access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
819
c9a3c58f
JL		 820static bool access_cntp_tval(struct kvm_vcpu *vcpu,
821 struct sys_reg_params *p,
822 const struct sys_reg_desc *r)
823{
7b6b4631
JL		 824 struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
825 u64 now = kvm_phys_timer_read();
826
827 if (p->is_write)
828 ptimer->cnt_cval = p->regval + now;
829 else
830 p->regval = ptimer->cnt_cval - now;
831
c9a3c58f
JL		 832 return true;
833}
834
835static bool access_cntp_ctl(struct kvm_vcpu *vcpu,
836 struct sys_reg_params *p,
837 const struct sys_reg_desc *r)
838{
7b6b4631
JL		 839 struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
840
841 if (p->is_write) {
842 /* ISTATUS bit is read-only */
843 ptimer->cnt_ctl = p->regval & ~ARCH_TIMER_CTRL_IT_STAT;
844 } else {
845 u64 now = kvm_phys_timer_read();
846
847 p->regval = ptimer->cnt_ctl;
848 /*
849 * Set ISTATUS bit if it's expired.
850 * Note that according to ARMv8 ARM Issue A.k, ISTATUS bit is
851 * UNKNOWN when ENABLE bit is 0, so we chose to set ISTATUS bit
852 * regardless of ENABLE bit for our implementation convenience.
853 */
854 if (ptimer->cnt_cval <= now)
855 p->regval |= ARCH_TIMER_CTRL_IT_STAT;
856 }
857
c9a3c58f
JL		 858 return true;
859}
860
861static bool access_cntp_cval(struct kvm_vcpu *vcpu,
862 struct sys_reg_params *p,
863 const struct sys_reg_desc *r)
864{
7b6b4631
JL		 865 struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
866
867 if (p->is_write)
868 ptimer->cnt_cval = p->regval;
869 else
870 p->regval = ptimer->cnt_cval;
871
c9a3c58f
JL		 872 return true;
873}
874
7c8c5e6a
MZ		 875/*
876 * Architected system registers.
877 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
7609c125 878 *
0c557ed4
MZ		 879 * Debug handling: We do trap most, if not all debug related system
880 * registers. The implementation is good enough to ensure that a guest
881 * can use these with minimal performance degradation. The drawback is
882 * that we don't implement any of the external debug, none of the
883 * OSlock protocol. This should be revisited if we ever encounter a
884 * more demanding guest...
7c8c5e6a
MZ		 885 */
886static const struct sys_reg_desc sys_reg_descs[] = {
887 /* DC ISW */
888 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b0110), Op2(0b010),
889 access_dcsw },
890 /* DC CSW */
891 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1010), Op2(0b010),
892 access_dcsw },
893 /* DC CISW */
894 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b010),
895 access_dcsw },
896
0c557ed4
MZ		 897 DBG_BCR_BVR_WCR_WVR_EL1(0),
898 DBG_BCR_BVR_WCR_WVR_EL1(1),
899 /* MDCCINT_EL1 */
900 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
901 trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
902 /* MDSCR_EL1 */
903 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
904 trap_debug_regs, reset_val, MDSCR_EL1, 0 },
905 DBG_BCR_BVR_WCR_WVR_EL1(2),
906 DBG_BCR_BVR_WCR_WVR_EL1(3),
907 DBG_BCR_BVR_WCR_WVR_EL1(4),
908 DBG_BCR_BVR_WCR_WVR_EL1(5),
909 DBG_BCR_BVR_WCR_WVR_EL1(6),
910 DBG_BCR_BVR_WCR_WVR_EL1(7),
911 DBG_BCR_BVR_WCR_WVR_EL1(8),
912 DBG_BCR_BVR_WCR_WVR_EL1(9),
913 DBG_BCR_BVR_WCR_WVR_EL1(10),
914 DBG_BCR_BVR_WCR_WVR_EL1(11),
915 DBG_BCR_BVR_WCR_WVR_EL1(12),
916 DBG_BCR_BVR_WCR_WVR_EL1(13),
917 DBG_BCR_BVR_WCR_WVR_EL1(14),
918 DBG_BCR_BVR_WCR_WVR_EL1(15),
919
920 /* MDRAR_EL1 */
921 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
922 trap_raz_wi },
923 /* OSLAR_EL1 */
924 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b100),
925 trap_raz_wi },
926 /* OSLSR_EL1 */
927 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0001), Op2(0b100),
928 trap_oslsr_el1 },
929 /* OSDLR_EL1 */
930 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0011), Op2(0b100),
931 trap_raz_wi },
932 /* DBGPRCR_EL1 */
933 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0100), Op2(0b100),
934 trap_raz_wi },
935 /* DBGCLAIMSET_EL1 */
936 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1000), Op2(0b110),
937 trap_raz_wi },
938 /* DBGCLAIMCLR_EL1 */
939 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1001), Op2(0b110),
940 trap_raz_wi },
941 /* DBGAUTHSTATUS_EL1 */
942 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b110),
943 trap_dbgauthstatus_el1 },
944
0c557ed4
MZ		 945 /* MDCCSR_EL1 */
946 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0001), Op2(0b000),
947 trap_raz_wi },
948 /* DBGDTR_EL0 */
949 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0100), Op2(0b000),
950 trap_raz_wi },
951 /* DBGDTR[TR]X_EL0 */
952 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0101), Op2(0b000),
953 trap_raz_wi },
954
62a89c44
MZ		 955 /* DBGVCR32_EL2 */
956 { Op0(0b10), Op1(0b100), CRn(0b0000), CRm(0b0111), Op2(0b000),
957 NULL, reset_val, DBGVCR32_EL2, 0 },
958
7c8c5e6a
MZ		 959 /* MPIDR_EL1 */
960 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b101),
961 NULL, reset_mpidr, MPIDR_EL1 },
962 /* SCTLR_EL1 */
963 { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
3c1e7165 964 access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
7c8c5e6a
MZ		 965 /* CPACR_EL1 */
966 { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010),
967 NULL, reset_val, CPACR_EL1, 0 },
968 /* TTBR0_EL1 */
969 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b000),
4d44923b 970 access_vm_reg, reset_unknown, TTBR0_EL1 },
7c8c5e6a
MZ		 971 /* TTBR1_EL1 */
972 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b001),
4d44923b 973 access_vm_reg, reset_unknown, TTBR1_EL1 },
7c8c5e6a
MZ		 974 /* TCR_EL1 */
975 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b010),
4d44923b 976 access_vm_reg, reset_val, TCR_EL1, 0 },
7c8c5e6a
MZ		 977
978 /* AFSR0_EL1 */
979 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b000),
4d44923b 980 access_vm_reg, reset_unknown, AFSR0_EL1 },
7c8c5e6a
MZ		 981 /* AFSR1_EL1 */
982 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b001),
4d44923b 983 access_vm_reg, reset_unknown, AFSR1_EL1 },
7c8c5e6a
MZ		 984 /* ESR_EL1 */
985 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0010), Op2(0b000),
4d44923b 986 access_vm_reg, reset_unknown, ESR_EL1 },
7c8c5e6a
MZ		 987 /* FAR_EL1 */
988 { Op0(0b11), Op1(0b000), CRn(0b0110), CRm(0b0000), Op2(0b000),
4d44923b 989 access_vm_reg, reset_unknown, FAR_EL1 },
1bbd8054
MZ		 990 /* PAR_EL1 */
991 { Op0(0b11), Op1(0b000), CRn(0b0111), CRm(0b0100), Op2(0b000),
992 NULL, reset_unknown, PAR_EL1 },
7c8c5e6a
MZ		 993
994 /* PMINTENSET_EL1 */
995 { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
9db52c78 996 access_pminten, reset_unknown, PMINTENSET_EL1 },
7c8c5e6a
MZ		 997 /* PMINTENCLR_EL1 */
998 { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),
9db52c78 999 access_pminten, NULL, PMINTENSET_EL1 },
7c8c5e6a
MZ		 1000
1001 /* MAIR_EL1 */
1002 { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
4d44923b 1003 access_vm_reg, reset_unknown, MAIR_EL1 },
7c8c5e6a
MZ		 1004 /* AMAIR_EL1 */
1005 { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0011), Op2(0b000),
4d44923b 1006 access_vm_reg, reset_amair_el1, AMAIR_EL1 },
7c8c5e6a
MZ		 1007
1008 /* VBAR_EL1 */
1009 { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b0000), Op2(0b000),
1010 NULL, reset_val, VBAR_EL1, 0 },
db7dedd0 1011
6d52f35a
AP		 1012 /* ICC_SGI1R_EL1 */
1013 { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1011), Op2(0b101),
1014 access_gic_sgi },
db7dedd0
CD		 1015 /* ICC_SRE_EL1 */
1016 { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1100), Op2(0b101),
b34f2bcb 1017 access_gic_sre },
db7dedd0 1018
7c8c5e6a
MZ		 1019 /* CONTEXTIDR_EL1 */
1020 { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001),
4d44923b 1021 access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
7c8c5e6a
MZ		 1022 /* TPIDR_EL1 */
1023 { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b100),
1024 NULL, reset_unknown, TPIDR_EL1 },
1025
1026 /* CNTKCTL_EL1 */
1027 { Op0(0b11), Op1(0b000), CRn(0b1110), CRm(0b0001), Op2(0b000),
1028 NULL, reset_val, CNTKCTL_EL1, 0},
1029
1030 /* CSSELR_EL1 */
1031 { Op0(0b11), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
1032 NULL, reset_unknown, CSSELR_EL1 },
1033
1034 /* PMCR_EL0 */
1035 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000),
ab946834 1036 access_pmcr, reset_pmcr, },
7c8c5e6a
MZ		 1037 /* PMCNTENSET_EL0 */
1038 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
96b0eebc 1039 access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
7c8c5e6a
MZ		 1040 /* PMCNTENCLR_EL0 */
1041 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
96b0eebc 1042 access_pmcnten, NULL, PMCNTENSET_EL0 },
7c8c5e6a
MZ		 1043 /* PMOVSCLR_EL0 */
1044 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
76d883c4 1045 access_pmovs, NULL, PMOVSSET_EL0 },
7c8c5e6a
MZ		 1046 /* PMSWINC_EL0 */
1047 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
7a0adc70 1048 access_pmswinc, reset_unknown, PMSWINC_EL0 },
7c8c5e6a
MZ		 1049 /* PMSELR_EL0 */
1050 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
3965c3ce 1051 access_pmselr, reset_unknown, PMSELR_EL0 },
7c8c5e6a
MZ		 1052 /* PMCEID0_EL0 */
1053 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
a86b5505 1054 access_pmceid },
7c8c5e6a
MZ		 1055 /* PMCEID1_EL0 */
1056 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
a86b5505 1057 access_pmceid },
7c8c5e6a
MZ		 1058 /* PMCCNTR_EL0 */
1059 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
051ff581 1060 access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 },
7c8c5e6a
MZ		 1061 /* PMXEVTYPER_EL0 */
1062 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
9feb21ac 1063 access_pmu_evtyper },
7c8c5e6a
MZ		 1064 /* PMXEVCNTR_EL0 */
1065 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
051ff581 1066 access_pmu_evcntr },
d692b8ad
SZ		 1067 /* PMUSERENR_EL0
1068 * This register resets as unknown in 64bit mode while it resets as zero
1069 * in 32bit mode. Here we choose to reset it as zero for consistency.
1070 */
7c8c5e6a 1071 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
d692b8ad 1072 access_pmuserenr, reset_val, PMUSERENR_EL0, 0 },
7c8c5e6a
MZ		 1073 /* PMOVSSET_EL0 */
1074 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
76d883c4 1075 access_pmovs, reset_unknown, PMOVSSET_EL0 },
7c8c5e6a
MZ		 1076
1077 /* TPIDR_EL0 */
1078 { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b010),
1079 NULL, reset_unknown, TPIDR_EL0 },
1080 /* TPIDRRO_EL0 */
1081 { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
1082 NULL, reset_unknown, TPIDRRO_EL0 },
62a89c44 1083
c9a3c58f
JL		 1084 /* CNTP_TVAL_EL0 */
1085 { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b0010), Op2(0b000),
1086 access_cntp_tval },
1087 /* CNTP_CTL_EL0 */
1088 { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b0010), Op2(0b001),
1089 access_cntp_ctl },
1090 /* CNTP_CVAL_EL0 */
1091 { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b0010), Op2(0b010),
1092 access_cntp_cval },
1093
051ff581
SZ		 1094 /* PMEVCNTRn_EL0 */
1095 PMU_PMEVCNTR_EL0(0),
1096 PMU_PMEVCNTR_EL0(1),
1097 PMU_PMEVCNTR_EL0(2),
1098 PMU_PMEVCNTR_EL0(3),
1099 PMU_PMEVCNTR_EL0(4),
1100 PMU_PMEVCNTR_EL0(5),
1101 PMU_PMEVCNTR_EL0(6),
1102 PMU_PMEVCNTR_EL0(7),
1103 PMU_PMEVCNTR_EL0(8),
1104 PMU_PMEVCNTR_EL0(9),
1105 PMU_PMEVCNTR_EL0(10),
1106 PMU_PMEVCNTR_EL0(11),
1107 PMU_PMEVCNTR_EL0(12),
1108 PMU_PMEVCNTR_EL0(13),
1109 PMU_PMEVCNTR_EL0(14),
1110 PMU_PMEVCNTR_EL0(15),
1111 PMU_PMEVCNTR_EL0(16),
1112 PMU_PMEVCNTR_EL0(17),
1113 PMU_PMEVCNTR_EL0(18),
1114 PMU_PMEVCNTR_EL0(19),
1115 PMU_PMEVCNTR_EL0(20),
1116 PMU_PMEVCNTR_EL0(21),
1117 PMU_PMEVCNTR_EL0(22),
1118 PMU_PMEVCNTR_EL0(23),
1119 PMU_PMEVCNTR_EL0(24),
1120 PMU_PMEVCNTR_EL0(25),
1121 PMU_PMEVCNTR_EL0(26),
1122 PMU_PMEVCNTR_EL0(27),
1123 PMU_PMEVCNTR_EL0(28),
1124 PMU_PMEVCNTR_EL0(29),
1125 PMU_PMEVCNTR_EL0(30),
9feb21ac
SZ		 1126 /* PMEVTYPERn_EL0 */
1127 PMU_PMEVTYPER_EL0(0),
1128 PMU_PMEVTYPER_EL0(1),
1129 PMU_PMEVTYPER_EL0(2),
1130 PMU_PMEVTYPER_EL0(3),
1131 PMU_PMEVTYPER_EL0(4),
1132 PMU_PMEVTYPER_EL0(5),
1133 PMU_PMEVTYPER_EL0(6),
1134 PMU_PMEVTYPER_EL0(7),
1135 PMU_PMEVTYPER_EL0(8),
1136 PMU_PMEVTYPER_EL0(9),
1137 PMU_PMEVTYPER_EL0(10),
1138 PMU_PMEVTYPER_EL0(11),
1139 PMU_PMEVTYPER_EL0(12),
1140 PMU_PMEVTYPER_EL0(13),
1141 PMU_PMEVTYPER_EL0(14),
1142 PMU_PMEVTYPER_EL0(15),
1143 PMU_PMEVTYPER_EL0(16),
1144 PMU_PMEVTYPER_EL0(17),
1145 PMU_PMEVTYPER_EL0(18),
1146 PMU_PMEVTYPER_EL0(19),
1147 PMU_PMEVTYPER_EL0(20),
1148 PMU_PMEVTYPER_EL0(21),
1149 PMU_PMEVTYPER_EL0(22),
1150 PMU_PMEVTYPER_EL0(23),
1151 PMU_PMEVTYPER_EL0(24),
1152 PMU_PMEVTYPER_EL0(25),
1153 PMU_PMEVTYPER_EL0(26),
1154 PMU_PMEVTYPER_EL0(27),
1155 PMU_PMEVTYPER_EL0(28),
1156 PMU_PMEVTYPER_EL0(29),
1157 PMU_PMEVTYPER_EL0(30),
1158 /* PMCCFILTR_EL0
1159 * This register resets as unknown in 64bit mode while it resets as zero
1160 * in 32bit mode. Here we choose to reset it as zero for consistency.
1161 */
1162 { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b1111), Op2(0b111),
1163 access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 },
051ff581 1164
62a89c44
MZ		 1165 /* DACR32_EL2 */
1166 { Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000),
1167 NULL, reset_unknown, DACR32_EL2 },
1168 /* IFSR32_EL2 */
1169 { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0000), Op2(0b001),
1170 NULL, reset_unknown, IFSR32_EL2 },
1171 /* FPEXC32_EL2 */
1172 { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0011), Op2(0b000),
1173 NULL, reset_val, FPEXC32_EL2, 0x70 },
1174};
1175
bdfb4b38 1176static bool trap_dbgidr(struct kvm_vcpu *vcpu,
3fec037d 1177 struct sys_reg_params *p,
bdfb4b38
MZ		 1178 const struct sys_reg_desc *r)
1179{
1180 if (p->is_write) {
1181 return ignore_write(vcpu, p);
1182 } else {
4db8e5ea
SP		 1183 u64 dfr = read_system_reg(SYS_ID_AA64DFR0_EL1);
1184 u64 pfr = read_system_reg(SYS_ID_AA64PFR0_EL1);
28c5dcb2 1185 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
bdfb4b38 1186
2ec5be3d
PF		 1187 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
1188 (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
1189 (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20)
1190 | (6 << 16) | (el3 << 14) | (el3 << 12));
bdfb4b38
MZ		 1191 return true;
1192 }
1193}
1194
1195static bool trap_debug32(struct kvm_vcpu *vcpu,
3fec037d 1196 struct sys_reg_params *p,
bdfb4b38
MZ		 1197 const struct sys_reg_desc *r)
1198{
1199 if (p->is_write) {
2ec5be3d 1200 vcpu_cp14(vcpu, r->reg) = p->regval;
bdfb4b38
MZ		 1201 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
1202 } else {
2ec5be3d 1203 p->regval = vcpu_cp14(vcpu, r->reg);
bdfb4b38
MZ		 1204 }
1205
1206 return true;
1207}
1208
84e690bf
AB		 1209/* AArch32 debug register mappings
1210 *
1211 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
1212 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
1213 *
1214 * All control registers and watchpoint value registers are mapped to
1215 * the lower 32 bits of their AArch64 equivalents. We share the trap
1216 * handlers with the above AArch64 code which checks what mode the
1217 * system is in.
1218 */
1219
281243cb
MZ		 1220static bool trap_xvr(struct kvm_vcpu *vcpu,
1221 struct sys_reg_params *p,
1222 const struct sys_reg_desc *rd)
84e690bf
AB		 1223{
1224 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
1225
1226 if (p->is_write) {
1227 u64 val = *dbg_reg;
1228
1229 val &= 0xffffffffUL;
2ec5be3d 1230 val |= p->regval << 32;
84e690bf
AB		 1231 *dbg_reg = val;
1232
1233 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
1234 } else {
2ec5be3d 1235 p->regval = *dbg_reg >> 32;
84e690bf
AB		 1236 }
1237
eef8c85a
AB		 1238 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
1239
84e690bf
AB		 1240 return true;
1241}
1242
1243#define DBG_BCR_BVR_WCR_WVR(n) \
1244 /* DBGBVRn */ \
1245 { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
1246 /* DBGBCRn */ \
1247 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
1248 /* DBGWVRn */ \
1249 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
1250 /* DBGWCRn */ \
1251 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1252
1253#define DBGBXVR(n) \
1254 { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n }
bdfb4b38
MZ		 1255
1256/*
1257 * Trapped cp14 registers. We generally ignore most of the external
1258 * debug, on the principle that they don't really make sense to a
84e690bf 1259 * guest. Revisit this one day, would this principle change.
bdfb4b38 1260 */
72564016 1261static const struct sys_reg_desc cp14_regs[] = {
bdfb4b38
MZ		 1262 /* DBGIDR */
1263 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
1264 /* DBGDTRRXext */
1265 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1266
1267 DBG_BCR_BVR_WCR_WVR(0),
1268 /* DBGDSCRint */
1269 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1270 DBG_BCR_BVR_WCR_WVR(1),
1271 /* DBGDCCINT */
1272 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 },
1273 /* DBGDSCRext */
1274 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 },
1275 DBG_BCR_BVR_WCR_WVR(2),
1276 /* DBGDTR[RT]Xint */
1277 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1278 /* DBGDTR[RT]Xext */
1279 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1280 DBG_BCR_BVR_WCR_WVR(3),
1281 DBG_BCR_BVR_WCR_WVR(4),
1282 DBG_BCR_BVR_WCR_WVR(5),
1283 /* DBGWFAR */
1284 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1285 /* DBGOSECCR */
1286 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1287 DBG_BCR_BVR_WCR_WVR(6),
1288 /* DBGVCR */
1289 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 },
1290 DBG_BCR_BVR_WCR_WVR(7),
1291 DBG_BCR_BVR_WCR_WVR(8),
1292 DBG_BCR_BVR_WCR_WVR(9),
1293 DBG_BCR_BVR_WCR_WVR(10),
1294 DBG_BCR_BVR_WCR_WVR(11),
1295 DBG_BCR_BVR_WCR_WVR(12),
1296 DBG_BCR_BVR_WCR_WVR(13),
1297 DBG_BCR_BVR_WCR_WVR(14),
1298 DBG_BCR_BVR_WCR_WVR(15),
1299
1300 /* DBGDRAR (32bit) */
1301 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1302
1303 DBGBXVR(0),
1304 /* DBGOSLAR */
1305 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
1306 DBGBXVR(1),
1307 /* DBGOSLSR */
1308 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
1309 DBGBXVR(2),
1310 DBGBXVR(3),
1311 /* DBGOSDLR */
1312 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1313 DBGBXVR(4),
1314 /* DBGPRCR */
1315 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1316 DBGBXVR(5),
1317 DBGBXVR(6),
1318 DBGBXVR(7),
1319 DBGBXVR(8),
1320 DBGBXVR(9),
1321 DBGBXVR(10),
1322 DBGBXVR(11),
1323 DBGBXVR(12),
1324 DBGBXVR(13),
1325 DBGBXVR(14),
1326 DBGBXVR(15),
1327
1328 /* DBGDSAR (32bit) */
1329 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1330
1331 /* DBGDEVID2 */
1332 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1333 /* DBGDEVID1 */
1334 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1335 /* DBGDEVID */
1336 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1337 /* DBGCLAIMSET */
1338 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1339 /* DBGCLAIMCLR */
1340 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1341 /* DBGAUTHSTATUS */
1342 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
72564016
MZ		 1343};
1344
a9866ba0
MZ		 1345/* Trapped cp14 64bit registers */
1346static const struct sys_reg_desc cp14_64_regs[] = {
bdfb4b38
MZ		 1347 /* DBGDRAR (64bit) */
1348 { Op1( 0), CRm( 1), .access = trap_raz_wi },
1349
1350 /* DBGDSAR (64bit) */
1351 { Op1( 0), CRm( 2), .access = trap_raz_wi },
a9866ba0
MZ		 1352};
1353
051ff581
SZ		 1354/* Macro to expand the PMEVCNTRn register */
1355#define PMU_PMEVCNTR(n) \
1356 /* PMEVCNTRn */ \
1357 { Op1(0), CRn(0b1110), \
1358 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1359 access_pmu_evcntr }
1360
9feb21ac
SZ		 1361/* Macro to expand the PMEVTYPERn register */
1362#define PMU_PMEVTYPER(n) \
1363 /* PMEVTYPERn */ \
1364 { Op1(0), CRn(0b1110), \
1365 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1366 access_pmu_evtyper }
1367
4d44923b
MZ		 1368/*
1369 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
1370 * depending on the way they are accessed (as a 32bit or a 64bit
1371 * register).
1372 */
62a89c44 1373static const struct sys_reg_desc cp15_regs[] = {
6d52f35a
AP		 1374 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
1375
3c1e7165 1376 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
4d44923b
MZ		 1377 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1378 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
1379 { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
1380 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
1381 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
1382 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
1383 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
1384 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
1385 { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
1386 { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
1387
62a89c44
MZ		 1388 /*
1389 * DC{C,I,CI}SW operations:
1390 */
1391 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
1392 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
1393 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
4d44923b 1394
7609c125 1395 /* PMU */
ab946834 1396 { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
96b0eebc
SZ		 1397 { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
1398 { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
76d883c4 1399 { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
7a0adc70 1400 { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
3965c3ce 1401 { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
a86b5505
SZ		 1402 { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
1403 { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
051ff581 1404 { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
9feb21ac 1405 { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
051ff581 1406 { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
d692b8ad 1407 { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr },
9db52c78
SZ		 1408 { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
1409 { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
76d883c4 1410 { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
4d44923b
MZ		 1411
1412 { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
1413 { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
1414 { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
1415 { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
db7dedd0
CD		 1416
1417 /* ICC_SRE */
f7f6f2d9 1418 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
db7dedd0 1419
4d44923b 1420 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
051ff581
SZ		 1421
1422 /* PMEVCNTRn */
1423 PMU_PMEVCNTR(0),
1424 PMU_PMEVCNTR(1),
1425 PMU_PMEVCNTR(2),
1426 PMU_PMEVCNTR(3),
1427 PMU_PMEVCNTR(4),
1428 PMU_PMEVCNTR(5),
1429 PMU_PMEVCNTR(6),
1430 PMU_PMEVCNTR(7),
1431 PMU_PMEVCNTR(8),
1432 PMU_PMEVCNTR(9),
1433 PMU_PMEVCNTR(10),
1434 PMU_PMEVCNTR(11),
1435 PMU_PMEVCNTR(12),
1436 PMU_PMEVCNTR(13),
1437 PMU_PMEVCNTR(14),
1438 PMU_PMEVCNTR(15),
1439 PMU_PMEVCNTR(16),
1440 PMU_PMEVCNTR(17),
1441 PMU_PMEVCNTR(18),
1442 PMU_PMEVCNTR(19),
1443 PMU_PMEVCNTR(20),
1444 PMU_PMEVCNTR(21),
1445 PMU_PMEVCNTR(22),
1446 PMU_PMEVCNTR(23),
1447 PMU_PMEVCNTR(24),
1448 PMU_PMEVCNTR(25),
1449 PMU_PMEVCNTR(26),
1450 PMU_PMEVCNTR(27),
1451 PMU_PMEVCNTR(28),
1452 PMU_PMEVCNTR(29),
1453 PMU_PMEVCNTR(30),
9feb21ac
SZ		 1454 /* PMEVTYPERn */
1455 PMU_PMEVTYPER(0),
1456 PMU_PMEVTYPER(1),
1457 PMU_PMEVTYPER(2),
1458 PMU_PMEVTYPER(3),
1459 PMU_PMEVTYPER(4),
1460 PMU_PMEVTYPER(5),
1461 PMU_PMEVTYPER(6),
1462 PMU_PMEVTYPER(7),
1463 PMU_PMEVTYPER(8),
1464 PMU_PMEVTYPER(9),
1465 PMU_PMEVTYPER(10),
1466 PMU_PMEVTYPER(11),
1467 PMU_PMEVTYPER(12),
1468 PMU_PMEVTYPER(13),
1469 PMU_PMEVTYPER(14),
1470 PMU_PMEVTYPER(15),
1471 PMU_PMEVTYPER(16),
1472 PMU_PMEVTYPER(17),
1473 PMU_PMEVTYPER(18),
1474 PMU_PMEVTYPER(19),
1475 PMU_PMEVTYPER(20),
1476 PMU_PMEVTYPER(21),
1477 PMU_PMEVTYPER(22),
1478 PMU_PMEVTYPER(23),
1479 PMU_PMEVTYPER(24),
1480 PMU_PMEVTYPER(25),
1481 PMU_PMEVTYPER(26),
1482 PMU_PMEVTYPER(27),
1483 PMU_PMEVTYPER(28),
1484 PMU_PMEVTYPER(29),
1485 PMU_PMEVTYPER(30),
1486 /* PMCCFILTR */
1487 { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
a9866ba0
MZ		 1488};
1489
1490static const struct sys_reg_desc cp15_64_regs[] = {
1491 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
051ff581 1492 { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
6d52f35a 1493 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
4d44923b 1494 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
7c8c5e6a
MZ		 1495};
1496
1497/* Target specific emulation tables */
1498static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS];
1499
1500void kvm_register_target_sys_reg_table(unsigned int target,
1501 struct kvm_sys_reg_target_table *table)
1502{
1503 target_tables[target] = table;
1504}
1505
1506/* Get specific register table for this target. */
62a89c44
MZ		 1507static const struct sys_reg_desc *get_target_table(unsigned target,
1508 bool mode_is_64,
1509 size_t *num)
7c8c5e6a
MZ		 1510{
1511 struct kvm_sys_reg_target_table *table;
1512
1513 table = target_tables[target];
62a89c44
MZ		 1514 if (mode_is_64) {
1515 *num = table->table64.num;
1516 return table->table64.table;
1517 } else {
1518 *num = table->table32.num;
1519 return table->table32.table;
1520 }
7c8c5e6a
MZ		 1521}
1522
623eefa8
MZ		 1523#define reg_to_match_value(x) \
1524 ({ \
1525 unsigned long val; \
1526 val = (x)->Op0 << 14; \
1527 val |= (x)->Op1 << 11; \
1528 val |= (x)->CRn << 7; \
1529 val |= (x)->CRm << 3; \
1530 val |= (x)->Op2; \
1531 val; \
1532 })
1533
1534static int match_sys_reg(const void *key, const void *elt)
1535{
1536 const unsigned long pval = (unsigned long)key;
1537 const struct sys_reg_desc *r = elt;
1538
1539 return pval - reg_to_match_value(r);
1540}
1541
7c8c5e6a
MZ		 1542static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
1543 const struct sys_reg_desc table[],
1544 unsigned int num)
1545{
623eefa8
MZ		 1546 unsigned long pval = reg_to_match_value(params);
1547
1548 return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
7c8c5e6a
MZ		 1549}
1550
62a89c44
MZ		 1551int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
1552{
1553 kvm_inject_undefined(vcpu);
1554 return 1;
1555}
1556
72564016
MZ		 1557/*
1558 * emulate_cp -- tries to match a sys_reg access in a handling table, and
1559 * call the corresponding trap handler.
1560 *
1561 * @params: pointer to the descriptor of the access
1562 * @table: array of trap descriptors
1563 * @num: size of the trap descriptor array
1564 *
1565 * Return 0 if the access has been handled, and -1 if not.
1566 */
1567static int emulate_cp(struct kvm_vcpu *vcpu,
3fec037d 1568 struct sys_reg_params *params,
72564016
MZ		 1569 const struct sys_reg_desc *table,
1570 size_t num)
62a89c44 1571{
72564016 1572 const struct sys_reg_desc *r;
62a89c44 1573
72564016
MZ		 1574 if (!table)
1575 return -1; /* Not handled */
62a89c44 1576
62a89c44 1577 r = find_reg(params, table, num);
62a89c44 1578
72564016 1579 if (r) {
62a89c44
MZ		 1580 /*
1581 * Not having an accessor means that we have
1582 * configured a trap that we don't know how to
1583 * handle. This certainly qualifies as a gross bug
1584 * that should be fixed right away.
1585 */
1586 BUG_ON(!r->access);
1587
1588 if (likely(r->access(vcpu, params, r))) {
1589 /* Skip instruction, since it was emulated */
1590 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
6327f35a
SZ		 1591 /* Handled */
1592 return 0;
62a89c44 1593 }
72564016
MZ		 1594 }
1595
1596 /* Not handled */
1597 return -1;
1598}
1599
1600static void unhandled_cp_access(struct kvm_vcpu *vcpu,
1601 struct sys_reg_params *params)
1602{
1603 u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
40c4f8d2 1604 int cp = -1;
72564016
MZ		 1605
1606 switch(hsr_ec) {
c6d01a94
MR		 1607 case ESR_ELx_EC_CP15_32:
1608 case ESR_ELx_EC_CP15_64:
72564016
MZ		 1609 cp = 15;
1610 break;
c6d01a94
MR		 1611 case ESR_ELx_EC_CP14_MR:
1612 case ESR_ELx_EC_CP14_64:
72564016
MZ		 1613 cp = 14;
1614 break;
1615 default:
40c4f8d2 1616 WARN_ON(1);
62a89c44
MZ		 1617 }
1618
72564016
MZ		 1619 kvm_err("Unsupported guest CP%d access at: %08lx\n",
1620 cp, *vcpu_pc(vcpu));
62a89c44
MZ		 1621 print_sys_reg_instr(params);
1622 kvm_inject_undefined(vcpu);
1623}
1624
1625/**
7769db90 1626 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
62a89c44
MZ		 1627 * @vcpu: The VCPU pointer
1628 * @run: The kvm_run struct
1629 */
72564016
MZ		 1630static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
1631 const struct sys_reg_desc *global,
1632 size_t nr_global,
1633 const struct sys_reg_desc *target_specific,
1634 size_t nr_specific)
62a89c44
MZ		 1635{
1636 struct sys_reg_params params;
1637 u32 hsr = kvm_vcpu_get_hsr(vcpu);
2ec5be3d 1638 int Rt = (hsr >> 5) & 0xf;
62a89c44
MZ		 1639 int Rt2 = (hsr >> 10) & 0xf;
1640
2072d29c
MZ		 1641 params.is_aarch32 = true;
1642 params.is_32bit = false;
62a89c44 1643 params.CRm = (hsr >> 1) & 0xf;
62a89c44
MZ		 1644 params.is_write = ((hsr & 1) == 0);
1645
1646 params.Op0 = 0;
1647 params.Op1 = (hsr >> 16) & 0xf;
1648 params.Op2 = 0;
1649 params.CRn = 0;
1650
1651 /*
2ec5be3d 1652 * Make a 64-bit value out of Rt and Rt2. As we use the same trap
62a89c44
MZ		 1653 * backends between AArch32 and AArch64, we get away with it.
1654 */
1655 if (params.is_write) {
2ec5be3d
PF		 1656 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
1657 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
62a89c44
MZ		 1658 }
1659
72564016
MZ		 1660 if (!emulate_cp(vcpu, &params, target_specific, nr_specific))
1661 goto out;
1662 if (!emulate_cp(vcpu, &params, global, nr_global))
1663 goto out;
1664
1665 unhandled_cp_access(vcpu, &params);
62a89c44 1666
72564016 1667out:
2ec5be3d 1668 /* Split up the value between registers for the read side */
62a89c44 1669 if (!params.is_write) {
2ec5be3d
PF		 1670 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
1671 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
62a89c44
MZ		 1672 }
1673
1674 return 1;
1675}
1676
1677/**
7769db90 1678 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
62a89c44
MZ		 1679 * @vcpu: The VCPU pointer
1680 * @run: The kvm_run struct
1681 */
72564016
MZ		 1682static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
1683 const struct sys_reg_desc *global,
1684 size_t nr_global,
1685 const struct sys_reg_desc *target_specific,
1686 size_t nr_specific)
62a89c44
MZ		 1687{
1688 struct sys_reg_params params;
1689 u32 hsr = kvm_vcpu_get_hsr(vcpu);
2ec5be3d 1690 int Rt = (hsr >> 5) & 0xf;
62a89c44 1691
2072d29c
MZ		 1692 params.is_aarch32 = true;
1693 params.is_32bit = true;
62a89c44 1694 params.CRm = (hsr >> 1) & 0xf;
2ec5be3d 1695 params.regval = vcpu_get_reg(vcpu, Rt);
62a89c44
MZ		 1696 params.is_write = ((hsr & 1) == 0);
1697 params.CRn = (hsr >> 10) & 0xf;
1698 params.Op0 = 0;
1699 params.Op1 = (hsr >> 14) & 0x7;
1700 params.Op2 = (hsr >> 17) & 0x7;
1701
2ec5be3d
PF		 1702 if (!emulate_cp(vcpu, &params, target_specific, nr_specific) ||
1703 !emulate_cp(vcpu, &params, global, nr_global)) {
1704 if (!params.is_write)
1705 vcpu_set_reg(vcpu, Rt, params.regval);
72564016 1706 return 1;
2ec5be3d 1707 }
72564016
MZ		 1708
1709 unhandled_cp_access(vcpu, &params);
62a89c44
MZ		 1710 return 1;
1711}
1712
72564016
MZ		 1713int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
1714{
1715 const struct sys_reg_desc *target_specific;
1716 size_t num;
1717
1718 target_specific = get_target_table(vcpu->arch.target, false, &num);
1719 return kvm_handle_cp_64(vcpu,
a9866ba0 1720 cp15_64_regs, ARRAY_SIZE(cp15_64_regs),
72564016
MZ		 1721 target_specific, num);
1722}
1723
1724int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
1725{
1726 const struct sys_reg_desc *target_specific;
1727 size_t num;
1728
1729 target_specific = get_target_table(vcpu->arch.target, false, &num);
1730 return kvm_handle_cp_32(vcpu,
1731 cp15_regs, ARRAY_SIZE(cp15_regs),
1732 target_specific, num);
1733}
1734
1735int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
1736{
1737 return kvm_handle_cp_64(vcpu,
a9866ba0 1738 cp14_64_regs, ARRAY_SIZE(cp14_64_regs),
72564016
MZ		 1739 NULL, 0);
1740}
1741
1742int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
1743{
1744 return kvm_handle_cp_32(vcpu,
1745 cp14_regs, ARRAY_SIZE(cp14_regs),
1746 NULL, 0);
1747}
1748
7c8c5e6a 1749static int emulate_sys_reg(struct kvm_vcpu *vcpu,
3fec037d 1750 struct sys_reg_params *params)
7c8c5e6a
MZ		 1751{
1752 size_t num;
1753 const struct sys_reg_desc *table, *r;
1754
62a89c44 1755 table = get_target_table(vcpu->arch.target, true, &num);
7c8c5e6a
MZ		 1756
1757 /* Search target-specific then generic table. */
1758 r = find_reg(params, table, num);
1759 if (!r)
1760 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1761
1762 if (likely(r)) {
1763 /*
1764 * Not having an accessor means that we have
1765 * configured a trap that we don't know how to
1766 * handle. This certainly qualifies as a gross bug
1767 * that should be fixed right away.
1768 */
1769 BUG_ON(!r->access);
1770
1771 if (likely(r->access(vcpu, params, r))) {
1772 /* Skip instruction, since it was emulated */
1773 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
1774 return 1;
1775 }
1776 /* If access function fails, it should complain. */
1777 } else {
1778 kvm_err("Unsupported guest sys_reg access at: %lx\n",
1779 *vcpu_pc(vcpu));
1780 print_sys_reg_instr(params);
1781 }
1782 kvm_inject_undefined(vcpu);
1783 return 1;
1784}
1785
1786static void reset_sys_reg_descs(struct kvm_vcpu *vcpu,
1787 const struct sys_reg_desc *table, size_t num)
1788{
1789 unsigned long i;
1790
1791 for (i = 0; i < num; i++)
1792 if (table[i].reset)
1793 table[i].reset(vcpu, &table[i]);
1794}
1795
1796/**
1797 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
1798 * @vcpu: The VCPU pointer
1799 * @run: The kvm_run struct
1800 */
1801int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run)
1802{
1803 struct sys_reg_params params;
1804 unsigned long esr = kvm_vcpu_get_hsr(vcpu);
2ec5be3d
PF		 1805 int Rt = (esr >> 5) & 0x1f;
1806 int ret;
7c8c5e6a 1807
eef8c85a
AB		 1808 trace_kvm_handle_sys_reg(esr);
1809
2072d29c
MZ		 1810 params.is_aarch32 = false;
1811 params.is_32bit = false;
7c8c5e6a
MZ		 1812 params.Op0 = (esr >> 20) & 3;
1813 params.Op1 = (esr >> 14) & 0x7;
1814 params.CRn = (esr >> 10) & 0xf;
1815 params.CRm = (esr >> 1) & 0xf;
1816 params.Op2 = (esr >> 17) & 0x7;
2ec5be3d 1817 params.regval = vcpu_get_reg(vcpu, Rt);
7c8c5e6a
MZ		 1818 params.is_write = !(esr & 1);
1819
2ec5be3d
PF		 1820 ret = emulate_sys_reg(vcpu, &params);
1821
1822 if (!params.is_write)
1823 vcpu_set_reg(vcpu, Rt, params.regval);
1824 return ret;
7c8c5e6a
MZ		 1825}
1826
1827/******************************************************************************
1828 * Userspace API
1829 *****************************************************************************/
1830
1831static bool index_to_params(u64 id, struct sys_reg_params *params)
1832{
1833 switch (id & KVM_REG_SIZE_MASK) {
1834 case KVM_REG_SIZE_U64:
1835 /* Any unused index bits means it's not valid. */
1836 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
1837 | KVM_REG_ARM_COPROC_MASK
1838 | KVM_REG_ARM64_SYSREG_OP0_MASK
1839 | KVM_REG_ARM64_SYSREG_OP1_MASK
1840 | KVM_REG_ARM64_SYSREG_CRN_MASK
1841 | KVM_REG_ARM64_SYSREG_CRM_MASK
1842 | KVM_REG_ARM64_SYSREG_OP2_MASK))
1843 return false;
1844 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
1845 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
1846 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
1847 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
1848 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
1849 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
1850 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
1851 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
1852 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
1853 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
1854 return true;
1855 default:
1856 return false;
1857 }
1858}
1859
4b927b94
VK		 1860const struct sys_reg_desc *find_reg_by_id(u64 id,
1861 struct sys_reg_params *params,
1862 const struct sys_reg_desc table[],
1863 unsigned int num)
1864{
1865 if (!index_to_params(id, params))
1866 return NULL;
1867
1868 return find_reg(params, table, num);
1869}
1870
7c8c5e6a
MZ		 1871/* Decode an index value, and find the sys_reg_desc entry. */
1872static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
1873 u64 id)
1874{
1875 size_t num;
1876 const struct sys_reg_desc *table, *r;
1877 struct sys_reg_params params;
1878
1879 /* We only do sys_reg for now. */
1880 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
1881 return NULL;
1882
62a89c44 1883 table = get_target_table(vcpu->arch.target, true, &num);
4b927b94 1884 r = find_reg_by_id(id, &params, table, num);
7c8c5e6a
MZ		 1885 if (!r)
1886 r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1887
1888 /* Not saved in the sys_reg array? */
1889 if (r && !r->reg)
1890 r = NULL;
1891
1892 return r;
1893}
1894
1895/*
1896 * These are the invariant sys_reg registers: we let the guest see the
1897 * host versions of these, so they're part of the guest state.
1898 *
1899 * A future CPU may provide a mechanism to present different values to
1900 * the guest, or a future kvm may trap them.
1901 */
1902
1903#define FUNCTION_INVARIANT(reg) \
1904 static void get_##reg(struct kvm_vcpu *v, \
1905 const struct sys_reg_desc *r) \
1906 { \
1f3d8699 1907 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \
7c8c5e6a
MZ		 1908 }
1909
1910FUNCTION_INVARIANT(midr_el1)
1911FUNCTION_INVARIANT(ctr_el0)
1912FUNCTION_INVARIANT(revidr_el1)
1913FUNCTION_INVARIANT(id_pfr0_el1)
1914FUNCTION_INVARIANT(id_pfr1_el1)
1915FUNCTION_INVARIANT(id_dfr0_el1)
1916FUNCTION_INVARIANT(id_afr0_el1)
1917FUNCTION_INVARIANT(id_mmfr0_el1)
1918FUNCTION_INVARIANT(id_mmfr1_el1)
1919FUNCTION_INVARIANT(id_mmfr2_el1)
1920FUNCTION_INVARIANT(id_mmfr3_el1)
1921FUNCTION_INVARIANT(id_isar0_el1)
1922FUNCTION_INVARIANT(id_isar1_el1)
1923FUNCTION_INVARIANT(id_isar2_el1)
1924FUNCTION_INVARIANT(id_isar3_el1)
1925FUNCTION_INVARIANT(id_isar4_el1)
1926FUNCTION_INVARIANT(id_isar5_el1)
1927FUNCTION_INVARIANT(clidr_el1)
1928FUNCTION_INVARIANT(aidr_el1)
1929
1930/* ->val is filled in by kvm_sys_reg_table_init() */
1931static struct sys_reg_desc invariant_sys_regs[] = {
1932 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b000),
1933 NULL, get_midr_el1 },
1934 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b110),
1935 NULL, get_revidr_el1 },
1936 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b000),
1937 NULL, get_id_pfr0_el1 },
1938 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b001),
1939 NULL, get_id_pfr1_el1 },
1940 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b010),
1941 NULL, get_id_dfr0_el1 },
1942 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b011),
1943 NULL, get_id_afr0_el1 },
1944 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b100),
1945 NULL, get_id_mmfr0_el1 },
1946 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b101),
1947 NULL, get_id_mmfr1_el1 },
1948 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b110),
1949 NULL, get_id_mmfr2_el1 },
1950 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b111),
1951 NULL, get_id_mmfr3_el1 },
1952 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
1953 NULL, get_id_isar0_el1 },
1954 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b001),
1955 NULL, get_id_isar1_el1 },
1956 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
1957 NULL, get_id_isar2_el1 },
1958 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b011),
1959 NULL, get_id_isar3_el1 },
1960 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b100),
1961 NULL, get_id_isar4_el1 },
1962 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b101),
1963 NULL, get_id_isar5_el1 },
1964 { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b001),
1965 NULL, get_clidr_el1 },
1966 { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b111),
1967 NULL, get_aidr_el1 },
1968 { Op0(0b11), Op1(0b011), CRn(0b0000), CRm(0b0000), Op2(0b001),
1969 NULL, get_ctr_el0 },
1970};
1971
26c99af1 1972static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
7c8c5e6a 1973{
7c8c5e6a
MZ		 1974 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
1975 return -EFAULT;
1976 return 0;
1977}
1978
26c99af1 1979static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
7c8c5e6a 1980{
7c8c5e6a
MZ		 1981 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
1982 return -EFAULT;
1983 return 0;
1984}
1985
1986static int get_invariant_sys_reg(u64 id, void __user *uaddr)
1987{
1988 struct sys_reg_params params;
1989 const struct sys_reg_desc *r;
1990
4b927b94
VK		 1991 r = find_reg_by_id(id, &params, invariant_sys_regs,
1992 ARRAY_SIZE(invariant_sys_regs));
7c8c5e6a
MZ		 1993 if (!r)
1994 return -ENOENT;
1995
1996 return reg_to_user(uaddr, &r->val, id);
1997}
1998
1999static int set_invariant_sys_reg(u64 id, void __user *uaddr)
2000{
2001 struct sys_reg_params params;
2002 const struct sys_reg_desc *r;
2003 int err;
2004 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
2005
4b927b94
VK		 2006 r = find_reg_by_id(id, &params, invariant_sys_regs,
2007 ARRAY_SIZE(invariant_sys_regs));
7c8c5e6a
MZ		 2008 if (!r)
2009 return -ENOENT;
2010
2011 err = reg_from_user(&val, uaddr, id);
2012 if (err)
2013 return err;
2014
2015 /* This is what we mean by invariant: you can't change it. */
2016 if (r->val != val)
2017 return -EINVAL;
2018
2019 return 0;
2020}
2021
2022static bool is_valid_cache(u32 val)
2023{
2024 u32 level, ctype;
2025
2026 if (val >= CSSELR_MAX)
18d45766 2027 return false;
7c8c5e6a
MZ		 2028
2029 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
2030 level = (val >> 1);
2031 ctype = (cache_levels >> (level * 3)) & 7;
2032
2033 switch (ctype) {
2034 case 0: /* No cache */
2035 return false;
2036 case 1: /* Instruction cache only */
2037 return (val & 1);
2038 case 2: /* Data cache only */
2039 case 4: /* Unified cache */
2040 return !(val & 1);
2041 case 3: /* Separate instruction and data caches */
2042 return true;
2043 default: /* Reserved: we can't know instruction or data. */
2044 return false;
2045 }
2046}
2047
2048static int demux_c15_get(u64 id, void __user *uaddr)
2049{
2050 u32 val;
2051 u32 __user *uval = uaddr;
2052
2053 /* Fail if we have unknown bits set. */
2054 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2055 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2056 return -ENOENT;
2057
2058 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2059 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2060 if (KVM_REG_SIZE(id) != 4)
2061 return -ENOENT;
2062 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2063 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2064 if (!is_valid_cache(val))
2065 return -ENOENT;
2066
2067 return put_user(get_ccsidr(val), uval);
2068 default:
2069 return -ENOENT;
2070 }
2071}
2072
2073static int demux_c15_set(u64 id, void __user *uaddr)
2074{
2075 u32 val, newval;
2076 u32 __user *uval = uaddr;
2077
2078 /* Fail if we have unknown bits set. */
2079 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2080 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2081 return -ENOENT;
2082
2083 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2084 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2085 if (KVM_REG_SIZE(id) != 4)
2086 return -ENOENT;
2087 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2088 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2089 if (!is_valid_cache(val))
2090 return -ENOENT;
2091
2092 if (get_user(newval, uval))
2093 return -EFAULT;
2094
2095 /* This is also invariant: you can't change it. */
2096 if (newval != get_ccsidr(val))
2097 return -EINVAL;
2098 return 0;
2099 default:
2100 return -ENOENT;
2101 }
2102}
2103
2104int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2105{
2106 const struct sys_reg_desc *r;
2107 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2108
2109 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2110 return demux_c15_get(reg->id, uaddr);
2111
2112 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2113 return -ENOENT;
2114
2115 r = index_to_sys_reg_desc(vcpu, reg->id);
2116 if (!r)
2117 return get_invariant_sys_reg(reg->id, uaddr);
2118
84e690bf
AB		 2119 if (r->get_user)
2120 return (r->get_user)(vcpu, r, reg, uaddr);
2121
7c8c5e6a
MZ		 2122 return reg_to_user(uaddr, &vcpu_sys_reg(vcpu, r->reg), reg->id);
2123}
2124
2125int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2126{
2127 const struct sys_reg_desc *r;
2128 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2129
2130 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2131 return demux_c15_set(reg->id, uaddr);
2132
2133 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2134 return -ENOENT;
2135
2136 r = index_to_sys_reg_desc(vcpu, reg->id);
2137 if (!r)
2138 return set_invariant_sys_reg(reg->id, uaddr);
2139
84e690bf
AB		 2140 if (r->set_user)
2141 return (r->set_user)(vcpu, r, reg, uaddr);
2142
7c8c5e6a
MZ		 2143 return reg_from_user(&vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
2144}
2145
2146static unsigned int num_demux_regs(void)
2147{
2148 unsigned int i, count = 0;
2149
2150 for (i = 0; i < CSSELR_MAX; i++)
2151 if (is_valid_cache(i))
2152 count++;
2153
2154 return count;
2155}
2156
2157static int write_demux_regids(u64 __user *uindices)
2158{
efd48cea 2159 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
7c8c5e6a
MZ		 2160 unsigned int i;
2161
2162 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
2163 for (i = 0; i < CSSELR_MAX; i++) {
2164 if (!is_valid_cache(i))
2165 continue;
2166 if (put_user(val | i, uindices))
2167 return -EFAULT;
2168 uindices++;
2169 }
2170 return 0;
2171}
2172
2173static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
2174{
2175 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
2176 KVM_REG_ARM64_SYSREG |
2177 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
2178 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
2179 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
2180 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
2181 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
2182}
2183
2184static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
2185{
2186 if (!*uind)
2187 return true;
2188
2189 if (put_user(sys_reg_to_index(reg), *uind))
2190 return false;
2191
2192 (*uind)++;
2193 return true;
2194}
2195
2196/* Assumed ordered tables, see kvm_sys_reg_table_init. */
2197static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
2198{
2199 const struct sys_reg_desc *i1, *i2, *end1, *end2;
2200 unsigned int total = 0;
2201 size_t num;
2202
2203 /* We check for duplicates here, to allow arch-specific overrides. */
62a89c44 2204 i1 = get_target_table(vcpu->arch.target, true, &num);
7c8c5e6a
MZ		 2205 end1 = i1 + num;
2206 i2 = sys_reg_descs;
2207 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
2208
2209 BUG_ON(i1 == end1 || i2 == end2);
2210
2211 /* Walk carefully, as both tables may refer to the same register. */
2212 while (i1 || i2) {
2213 int cmp = cmp_sys_reg(i1, i2);
2214 /* target-specific overrides generic entry. */
2215 if (cmp <= 0) {
2216 /* Ignore registers we trap but don't save. */
2217 if (i1->reg) {
2218 if (!copy_reg_to_user(i1, &uind))
2219 return -EFAULT;
2220 total++;
2221 }
2222 } else {
2223 /* Ignore registers we trap but don't save. */
2224 if (i2->reg) {
2225 if (!copy_reg_to_user(i2, &uind))
2226 return -EFAULT;
2227 total++;
2228 }
2229 }
2230
2231 if (cmp <= 0 && ++i1 == end1)
2232 i1 = NULL;
2233 if (cmp >= 0 && ++i2 == end2)
2234 i2 = NULL;
2235 }
2236 return total;
2237}
2238
2239unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
2240{
2241 return ARRAY_SIZE(invariant_sys_regs)
2242 + num_demux_regs()
2243 + walk_sys_regs(vcpu, (u64 __user *)NULL);
2244}
2245
2246int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
2247{
2248 unsigned int i;
2249 int err;
2250
2251 /* Then give them all the invariant registers' indices. */
2252 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
2253 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
2254 return -EFAULT;
2255 uindices++;
2256 }
2257
2258 err = walk_sys_regs(vcpu, uindices);
2259 if (err < 0)
2260 return err;
2261 uindices += err;
2262
2263 return write_demux_regids(uindices);
2264}
2265
e6a95517
MZ		 2266static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n)
2267{
2268 unsigned int i;
2269
2270 for (i = 1; i < n; i++) {
2271 if (cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2272 kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
2273 return 1;
2274 }
2275 }
2276
2277 return 0;
2278}
2279
7c8c5e6a
MZ		 2280void kvm_sys_reg_table_init(void)
2281{
2282 unsigned int i;
2283 struct sys_reg_desc clidr;
2284
2285 /* Make sure tables are unique and in order. */
e6a95517
MZ		 2286 BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs)));
2287 BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs)));
2288 BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs)));
2289 BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs)));
2290 BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs)));
2291 BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs)));
7c8c5e6a
MZ		 2292
2293 /* We abuse the reset function to overwrite the table itself. */
2294 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
2295 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
2296
2297 /*
2298 * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
2299 *
2300 * If software reads the Cache Type fields from Ctype1
2301 * upwards, once it has seen a value of 0b000, no caches
2302 * exist at further-out levels of the hierarchy. So, for
2303 * example, if Ctype3 is the first Cache Type field with a
2304 * value of 0b000, the values of Ctype4 to Ctype7 must be
2305 * ignored.
2306 */
2307 get_clidr_el1(NULL, &clidr); /* Ugly... */
2308 cache_levels = clidr.val;
2309 for (i = 0; i < 7; i++)
2310 if (((cache_levels >> (i*3)) & 7) == 0)
2311 break;
2312 /* Clear all higher bits. */
2313 cache_levels &= (1 << (i*3))-1;
2314}
2315
2316/**
2317 * kvm_reset_sys_regs - sets system registers to reset value
2318 * @vcpu: The VCPU pointer
2319 *
2320 * This function finds the right table above and sets the registers on the
2321 * virtual CPU struct to their architecturally defined reset values.
2322 */
2323void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
2324{
2325 size_t num;
2326 const struct sys_reg_desc *table;
2327
2328 /* Catch someone adding a register without putting in reset entry. */
2329 memset(&vcpu->arch.ctxt.sys_regs, 0x42, sizeof(vcpu->arch.ctxt.sys_regs));
2330
2331 /* Generic chip reset first (so target could override). */
2332 reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2333
62a89c44 2334 table = get_target_table(vcpu->arch.target, true, &num);
7c8c5e6a
MZ		 2335 reset_sys_reg_descs(vcpu, table, num);
2336
2337 for (num = 1; num < NR_SYS_REGS; num++)
2338 if (vcpu_sys_reg(vcpu, num) == 0x4242424242424242)
2339 panic("Didn't reset vcpu_sys_reg(%zi)", num);
2340}
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