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KVM: arm/arm64: vgic: Improve sync_hwstate performance
[mirror_ubuntu-artful-kernel.git] / arch / arm64 / kvm / sys_regs.c
CommitLineData
7c8c5e6a
MZ		 1/*
2 * Copyright (C) 2012,2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * Derived from arch/arm/kvm/coproc.c:
6 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
7 * Authors: Rusty Russell <rusty@rustcorp.com.au>
8 * Christoffer Dall <c.dall@virtualopensystems.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License, version 2, as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
623eefa8 23#include <linux/bsearch.h>
7c8c5e6a 24#include <linux/kvm_host.h>
c6d01a94 25#include <linux/mm.h>
7c8c5e6a 26#include <linux/uaccess.h>
c6d01a94 27
7c8c5e6a
MZ		 28#include <asm/cacheflush.h>
29#include <asm/cputype.h>
0c557ed4 30#include <asm/debug-monitors.h>
c6d01a94
MR		 31#include <asm/esr.h>
32#include <asm/kvm_arm.h>
9d8415d6 33#include <asm/kvm_asm.h>
c6d01a94
MR		 34#include <asm/kvm_coproc.h>
35#include <asm/kvm_emulate.h>
36#include <asm/kvm_host.h>
37#include <asm/kvm_mmu.h>
ab946834 38#include <asm/perf_event.h>
1f3d8699 39#include <asm/sysreg.h>
c6d01a94 40
7c8c5e6a
MZ		 41#include <trace/events/kvm.h>
42
43#include "sys_regs.h"
44
eef8c85a
AB		 45#include "trace.h"
46
7c8c5e6a
MZ		 47/*
48 * All of this file is extremly similar to the ARM coproc.c, but the
49 * types are different. My gut feeling is that it should be pretty
50 * easy to merge, but that would be an ABI breakage -- again. VFP
51 * would also need to be abstracted.
62a89c44
MZ		 52 *
53 * For AArch32, we only take care of what is being trapped. Anything
54 * that has to do with init and userspace access has to go via the
55 * 64bit interface.
7c8c5e6a
MZ		 56 */
57
58/* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
59static u32 cache_levels;
60
61/* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
62#define CSSELR_MAX 12
63
64/* Which cache CCSIDR represents depends on CSSELR value. */
65static u32 get_ccsidr(u32 csselr)
66{
67 u32 ccsidr;
68
69 /* Make sure noone else changes CSSELR during this! */
70 local_irq_disable();
1f3d8699 71 write_sysreg(csselr, csselr_el1);
7c8c5e6a 72 isb();
1f3d8699 73 ccsidr = read_sysreg(ccsidr_el1);
7c8c5e6a
MZ		 74 local_irq_enable();
75
76 return ccsidr;
77}
78
3c1e7165
MZ		 79/*
80 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
81 */
7c8c5e6a 82static bool access_dcsw(struct kvm_vcpu *vcpu,
3fec037d 83 struct sys_reg_params *p,
7c8c5e6a
MZ		 84 const struct sys_reg_desc *r)
85{
7c8c5e6a
MZ		 86 if (!p->is_write)
87 return read_from_write_only(vcpu, p);
88
3c1e7165 89 kvm_set_way_flush(vcpu);
7c8c5e6a
MZ		 90 return true;
91}
92
4d44923b
MZ		 93/*
94 * Generic accessor for VM registers. Only called as long as HCR_TVM
3c1e7165
MZ		 95 * is set. If the guest enables the MMU, we stop trapping the VM
96 * sys_regs and leave it in complete control of the caches.
4d44923b
MZ		 97 */
98static bool access_vm_reg(struct kvm_vcpu *vcpu,
3fec037d 99 struct sys_reg_params *p,
4d44923b
MZ		 100 const struct sys_reg_desc *r)
101{
3c1e7165 102 bool was_enabled = vcpu_has_cache_enabled(vcpu);
4d44923b
MZ		 103
104 BUG_ON(!p->is_write);
105
dedf97e8 106 if (!p->is_aarch32) {
2ec5be3d 107 vcpu_sys_reg(vcpu, r->reg) = p->regval;
dedf97e8
MZ		 108 } else {
109 if (!p->is_32bit)
2ec5be3d
PF		 110 vcpu_cp15_64_high(vcpu, r->reg) = upper_32_bits(p->regval);
111 vcpu_cp15_64_low(vcpu, r->reg) = lower_32_bits(p->regval);
dedf97e8 112 }
f0a3eaff 113
3c1e7165 114 kvm_toggle_cache(vcpu, was_enabled);
4d44923b
MZ		 115 return true;
116}
117
6d52f35a
AP		 118/*
119 * Trap handler for the GICv3 SGI generation system register.
120 * Forward the request to the VGIC emulation.
121 * The cp15_64 code makes sure this automatically works
122 * for both AArch64 and AArch32 accesses.
123 */
124static bool access_gic_sgi(struct kvm_vcpu *vcpu,
3fec037d 125 struct sys_reg_params *p,
6d52f35a
AP		 126 const struct sys_reg_desc *r)
127{
6d52f35a
AP		 128 if (!p->is_write)
129 return read_from_write_only(vcpu, p);
130
2ec5be3d 131 vgic_v3_dispatch_sgi(vcpu, p->regval);
6d52f35a
AP		 132
133 return true;
134}
135
b34f2bcb
MZ		 136static bool access_gic_sre(struct kvm_vcpu *vcpu,
137 struct sys_reg_params *p,
138 const struct sys_reg_desc *r)
139{
140 if (p->is_write)
141 return ignore_write(vcpu, p);
142
143 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
144 return true;
145}
146
7609c125 147static bool trap_raz_wi(struct kvm_vcpu *vcpu,
3fec037d 148 struct sys_reg_params *p,
7609c125 149 const struct sys_reg_desc *r)
7c8c5e6a
MZ		 150{
151 if (p->is_write)
152 return ignore_write(vcpu, p);
153 else
154 return read_zero(vcpu, p);
155}
156
0c557ed4 157static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
3fec037d 158 struct sys_reg_params *p,
0c557ed4
MZ		 159 const struct sys_reg_desc *r)
160{
161 if (p->is_write) {
162 return ignore_write(vcpu, p);
163 } else {
2ec5be3d 164 p->regval = (1 << 3);
0c557ed4
MZ		 165 return true;
166 }
167}
168
169static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
3fec037d 170 struct sys_reg_params *p,
0c557ed4
MZ		 171 const struct sys_reg_desc *r)
172{
173 if (p->is_write) {
174 return ignore_write(vcpu, p);
175 } else {
1f3d8699 176 p->regval = read_sysreg(dbgauthstatus_el1);
0c557ed4
MZ		 177 return true;
178 }
179}
180
181/*
182 * We want to avoid world-switching all the DBG registers all the
183 * time:
184 *
185 * - If we've touched any debug register, it is likely that we're
186 * going to touch more of them. It then makes sense to disable the
187 * traps and start doing the save/restore dance
188 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
189 * then mandatory to save/restore the registers, as the guest
190 * depends on them.
191 *
192 * For this, we use a DIRTY bit, indicating the guest has modified the
193 * debug registers, used as follow:
194 *
195 * On guest entry:
196 * - If the dirty bit is set (because we're coming back from trapping),
197 * disable the traps, save host registers, restore guest registers.
198 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
199 * set the dirty bit, disable the traps, save host registers,
200 * restore guest registers.
201 * - Otherwise, enable the traps
202 *
203 * On guest exit:
204 * - If the dirty bit is set, save guest registers, restore host
205 * registers and clear the dirty bit. This ensure that the host can
206 * now use the debug registers.
207 */
208static bool trap_debug_regs(struct kvm_vcpu *vcpu,
3fec037d 209 struct sys_reg_params *p,
0c557ed4
MZ		 210 const struct sys_reg_desc *r)
211{
212 if (p->is_write) {
2ec5be3d 213 vcpu_sys_reg(vcpu, r->reg) = p->regval;
0c557ed4
MZ		 214 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
215 } else {
2ec5be3d 216 p->regval = vcpu_sys_reg(vcpu, r->reg);
0c557ed4
MZ		 217 }
218
2ec5be3d 219 trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
eef8c85a 220
0c557ed4
MZ		 221 return true;
222}
223
84e690bf
AB		 224/*
225 * reg_to_dbg/dbg_to_reg
226 *
227 * A 32 bit write to a debug register leave top bits alone
228 * A 32 bit read from a debug register only returns the bottom bits
229 *
230 * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the
231 * hyp.S code switches between host and guest values in future.
232 */
281243cb
MZ		 233static void reg_to_dbg(struct kvm_vcpu *vcpu,
234 struct sys_reg_params *p,
235 u64 *dbg_reg)
84e690bf 236{
2ec5be3d 237 u64 val = p->regval;
84e690bf
AB		 238
239 if (p->is_32bit) {
240 val &= 0xffffffffUL;
241 val |= ((*dbg_reg >> 32) << 32);
242 }
243
244 *dbg_reg = val;
245 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
246}
247
281243cb
MZ		 248static void dbg_to_reg(struct kvm_vcpu *vcpu,
249 struct sys_reg_params *p,
250 u64 *dbg_reg)
84e690bf 251{
2ec5be3d 252 p->regval = *dbg_reg;
84e690bf 253 if (p->is_32bit)
2ec5be3d 254 p->regval &= 0xffffffffUL;
84e690bf
AB		 255}
256
281243cb
MZ		 257static bool trap_bvr(struct kvm_vcpu *vcpu,
258 struct sys_reg_params *p,
259 const struct sys_reg_desc *rd)
84e690bf
AB		 260{
261 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
262
263 if (p->is_write)
264 reg_to_dbg(vcpu, p, dbg_reg);
265 else
266 dbg_to_reg(vcpu, p, dbg_reg);
267
eef8c85a
AB		 268 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
269
84e690bf
AB		 270 return true;
271}
272
273static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
274 const struct kvm_one_reg *reg, void __user *uaddr)
275{
276 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
277
1713e5aa 278 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 279 return -EFAULT;
280 return 0;
281}
282
283static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
284 const struct kvm_one_reg *reg, void __user *uaddr)
285{
286 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
287
288 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
289 return -EFAULT;
290 return 0;
291}
292
281243cb
MZ		 293static void reset_bvr(struct kvm_vcpu *vcpu,
294 const struct sys_reg_desc *rd)
84e690bf
AB		 295{
296 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val;
297}
298
281243cb
MZ		 299static bool trap_bcr(struct kvm_vcpu *vcpu,
300 struct sys_reg_params *p,
301 const struct sys_reg_desc *rd)
84e690bf
AB		 302{
303 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
304
305 if (p->is_write)
306 reg_to_dbg(vcpu, p, dbg_reg);
307 else
308 dbg_to_reg(vcpu, p, dbg_reg);
309
eef8c85a
AB		 310 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
311
84e690bf
AB		 312 return true;
313}
314
315static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
316 const struct kvm_one_reg *reg, void __user *uaddr)
317{
318 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
319
1713e5aa 320 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 321 return -EFAULT;
322
323 return 0;
324}
325
326static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
327 const struct kvm_one_reg *reg, void __user *uaddr)
328{
329 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
330
331 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
332 return -EFAULT;
333 return 0;
334}
335
281243cb
MZ		 336static void reset_bcr(struct kvm_vcpu *vcpu,
337 const struct sys_reg_desc *rd)
84e690bf
AB		 338{
339 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val;
340}
341
281243cb
MZ		 342static bool trap_wvr(struct kvm_vcpu *vcpu,
343 struct sys_reg_params *p,
344 const struct sys_reg_desc *rd)
84e690bf
AB		 345{
346 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
347
348 if (p->is_write)
349 reg_to_dbg(vcpu, p, dbg_reg);
350 else
351 dbg_to_reg(vcpu, p, dbg_reg);
352
eef8c85a
AB		 353 trace_trap_reg(__func__, rd->reg, p->is_write,
354 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]);
355
84e690bf
AB		 356 return true;
357}
358
359static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
360 const struct kvm_one_reg *reg, void __user *uaddr)
361{
362 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
363
1713e5aa 364 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 365 return -EFAULT;
366 return 0;
367}
368
369static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
370 const struct kvm_one_reg *reg, void __user *uaddr)
371{
372 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
373
374 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
375 return -EFAULT;
376 return 0;
377}
378
281243cb
MZ		 379static void reset_wvr(struct kvm_vcpu *vcpu,
380 const struct sys_reg_desc *rd)
84e690bf
AB		 381{
382 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val;
383}
384
281243cb
MZ		 385static bool trap_wcr(struct kvm_vcpu *vcpu,
386 struct sys_reg_params *p,
387 const struct sys_reg_desc *rd)
84e690bf
AB		 388{
389 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
390
391 if (p->is_write)
392 reg_to_dbg(vcpu, p, dbg_reg);
393 else
394 dbg_to_reg(vcpu, p, dbg_reg);
395
eef8c85a
AB		 396 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
397
84e690bf
AB		 398 return true;
399}
400
401static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
402 const struct kvm_one_reg *reg, void __user *uaddr)
403{
404 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
405
1713e5aa 406 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 407 return -EFAULT;
408 return 0;
409}
410
411static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
412 const struct kvm_one_reg *reg, void __user *uaddr)
413{
414 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
415
416 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
417 return -EFAULT;
418 return 0;
419}
420
281243cb
MZ		 421static void reset_wcr(struct kvm_vcpu *vcpu,
422 const struct sys_reg_desc *rd)
84e690bf
AB		 423{
424 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val;
425}
426
7c8c5e6a
MZ		 427static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
428{
1f3d8699 429 vcpu_sys_reg(vcpu, AMAIR_EL1) = read_sysreg(amair_el1);
7c8c5e6a
MZ		 430}
431
432static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
433{
4429fc64
AP		 434 u64 mpidr;
435
7c8c5e6a 436 /*
4429fc64
AP		 437 * Map the vcpu_id into the first three affinity level fields of
438 * the MPIDR. We limit the number of VCPUs in level 0 due to a
439 * limitation to 16 CPUs in that level in the ICC_SGIxR registers
440 * of the GICv3 to be able to address each CPU directly when
441 * sending IPIs.
7c8c5e6a 442 */
4429fc64
AP		 443 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
444 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
445 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
446 vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr;
7c8c5e6a
MZ		 447}
448
ab946834
SZ		 449static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
450{
451 u64 pmcr, val;
452
1f3d8699
MR		 453 pmcr = read_sysreg(pmcr_el0);
454 /*
455 * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN
ab946834
SZ		 456 * except PMCR.E resetting to zero.
457 */
458 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
459 | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
460 vcpu_sys_reg(vcpu, PMCR_EL0) = val;
461}
462
d692b8ad
SZ		 463static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
464{
465 u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
466
467 return !((reg & ARMV8_PMU_USERENR_EN) || vcpu_mode_priv(vcpu));
468}
469
470static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
471{
472 u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
473
474 return !((reg & (ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN))
475 || vcpu_mode_priv(vcpu));
476}
477
478static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
479{
480 u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
481
482 return !((reg & (ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN))
483 || vcpu_mode_priv(vcpu));
484}
485
486static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
487{
488 u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
489
490 return !((reg & (ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN))
491 || vcpu_mode_priv(vcpu));
492}
493
ab946834
SZ		 494static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
495 const struct sys_reg_desc *r)
496{
497 u64 val;
498
499 if (!kvm_arm_pmu_v3_ready(vcpu))
500 return trap_raz_wi(vcpu, p, r);
501
d692b8ad
SZ		 502 if (pmu_access_el0_disabled(vcpu))
503 return false;
504
ab946834
SZ		 505 if (p->is_write) {
506 /* Only update writeable bits of PMCR */
507 val = vcpu_sys_reg(vcpu, PMCR_EL0);
508 val &= ~ARMV8_PMU_PMCR_MASK;
509 val |= p->regval & ARMV8_PMU_PMCR_MASK;
510 vcpu_sys_reg(vcpu, PMCR_EL0) = val;
76993739 511 kvm_pmu_handle_pmcr(vcpu, val);
ab946834
SZ		 512 } else {
513 /* PMCR.P & PMCR.C are RAZ */
514 val = vcpu_sys_reg(vcpu, PMCR_EL0)
515 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
516 p->regval = val;
517 }
518
519 return true;
520}
521
3965c3ce
SZ		 522static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
523 const struct sys_reg_desc *r)
524{
525 if (!kvm_arm_pmu_v3_ready(vcpu))
526 return trap_raz_wi(vcpu, p, r);
527
d692b8ad
SZ		 528 if (pmu_access_event_counter_el0_disabled(vcpu))
529 return false;
530
3965c3ce
SZ		 531 if (p->is_write)
532 vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
533 else
534 /* return PMSELR.SEL field */
535 p->regval = vcpu_sys_reg(vcpu, PMSELR_EL0)
536 & ARMV8_PMU_COUNTER_MASK;
537
538 return true;
539}
540
a86b5505
SZ		 541static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
542 const struct sys_reg_desc *r)
543{
544 u64 pmceid;
545
546 if (!kvm_arm_pmu_v3_ready(vcpu))
547 return trap_raz_wi(vcpu, p, r);
548
549 BUG_ON(p->is_write);
550
d692b8ad
SZ		 551 if (pmu_access_el0_disabled(vcpu))
552 return false;
553
a86b5505 554 if (!(p->Op2 & 1))
1f3d8699 555 pmceid = read_sysreg(pmceid0_el0);
a86b5505 556 else
1f3d8699 557 pmceid = read_sysreg(pmceid1_el0);
a86b5505
SZ		 558
559 p->regval = pmceid;
560
561 return true;
562}
563
051ff581
SZ		 564static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
565{
566 u64 pmcr, val;
567
568 pmcr = vcpu_sys_reg(vcpu, PMCR_EL0);
569 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
570 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX)
571 return false;
572
573 return true;
574}
575
576static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
577 struct sys_reg_params *p,
578 const struct sys_reg_desc *r)
579{
580 u64 idx;
581
582 if (!kvm_arm_pmu_v3_ready(vcpu))
583 return trap_raz_wi(vcpu, p, r);
584
585 if (r->CRn == 9 && r->CRm == 13) {
586 if (r->Op2 == 2) {
587 /* PMXEVCNTR_EL0 */
d692b8ad
SZ		 588 if (pmu_access_event_counter_el0_disabled(vcpu))
589 return false;
590
051ff581
SZ		 591 idx = vcpu_sys_reg(vcpu, PMSELR_EL0)
592 & ARMV8_PMU_COUNTER_MASK;
593 } else if (r->Op2 == 0) {
594 /* PMCCNTR_EL0 */
d692b8ad
SZ		 595 if (pmu_access_cycle_counter_el0_disabled(vcpu))
596 return false;
597
051ff581
SZ		 598 idx = ARMV8_PMU_CYCLE_IDX;
599 } else {
9e3f7a29 600 return false;
051ff581 601 }
9e3f7a29
WH		 602 } else if (r->CRn == 0 && r->CRm == 9) {
603 /* PMCCNTR */
604 if (pmu_access_event_counter_el0_disabled(vcpu))
605 return false;
606
607 idx = ARMV8_PMU_CYCLE_IDX;
051ff581
SZ		 608 } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
609 /* PMEVCNTRn_EL0 */
d692b8ad
SZ		 610 if (pmu_access_event_counter_el0_disabled(vcpu))
611 return false;
612
051ff581
SZ		 613 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
614 } else {
9e3f7a29 615 return false;
051ff581
SZ		 616 }
617
618 if (!pmu_counter_idx_valid(vcpu, idx))
619 return false;
620
d692b8ad
SZ		 621 if (p->is_write) {
622 if (pmu_access_el0_disabled(vcpu))
623 return false;
624
051ff581 625 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
d692b8ad 626 } else {
051ff581 627 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
d692b8ad 628 }
051ff581
SZ		 629
630 return true;
631}
632
9feb21ac
SZ		 633static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
634 const struct sys_reg_desc *r)
635{
636 u64 idx, reg;
637
638 if (!kvm_arm_pmu_v3_ready(vcpu))
639 return trap_raz_wi(vcpu, p, r);
640
d692b8ad
SZ		 641 if (pmu_access_el0_disabled(vcpu))
642 return false;
643
9feb21ac
SZ		 644 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
645 /* PMXEVTYPER_EL0 */
646 idx = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
647 reg = PMEVTYPER0_EL0 + idx;
648 } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
649 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
650 if (idx == ARMV8_PMU_CYCLE_IDX)
651 reg = PMCCFILTR_EL0;
652 else
653 /* PMEVTYPERn_EL0 */
654 reg = PMEVTYPER0_EL0 + idx;
655 } else {
656 BUG();
657 }
658
659 if (!pmu_counter_idx_valid(vcpu, idx))
660 return false;
661
662 if (p->is_write) {
663 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
664 vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
665 } else {
666 p->regval = vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
667 }
668
669 return true;
670}
671
96b0eebc
SZ		 672static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
673 const struct sys_reg_desc *r)
674{
675 u64 val, mask;
676
677 if (!kvm_arm_pmu_v3_ready(vcpu))
678 return trap_raz_wi(vcpu, p, r);
679
d692b8ad
SZ		 680 if (pmu_access_el0_disabled(vcpu))
681 return false;
682
96b0eebc
SZ		 683 mask = kvm_pmu_valid_counter_mask(vcpu);
684 if (p->is_write) {
685 val = p->regval & mask;
686 if (r->Op2 & 0x1) {
687 /* accessing PMCNTENSET_EL0 */
688 vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
689 kvm_pmu_enable_counter(vcpu, val);
690 } else {
691 /* accessing PMCNTENCLR_EL0 */
692 vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
693 kvm_pmu_disable_counter(vcpu, val);
694 }
695 } else {
696 p->regval = vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
697 }
698
699 return true;
700}
701
9db52c78
SZ		 702static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
703 const struct sys_reg_desc *r)
704{
705 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
706
707 if (!kvm_arm_pmu_v3_ready(vcpu))
708 return trap_raz_wi(vcpu, p, r);
709
d692b8ad
SZ		 710 if (!vcpu_mode_priv(vcpu))
711 return false;
712
9db52c78
SZ		 713 if (p->is_write) {
714 u64 val = p->regval & mask;
715
716 if (r->Op2 & 0x1)
717 /* accessing PMINTENSET_EL1 */
718 vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
719 else
720 /* accessing PMINTENCLR_EL1 */
721 vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
722 } else {
723 p->regval = vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask;
724 }
725
726 return true;
727}
728
76d883c4
SZ		 729static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
730 const struct sys_reg_desc *r)
731{
732 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
733
734 if (!kvm_arm_pmu_v3_ready(vcpu))
735 return trap_raz_wi(vcpu, p, r);
736
d692b8ad
SZ		 737 if (pmu_access_el0_disabled(vcpu))
738 return false;
739
76d883c4
SZ		 740 if (p->is_write) {
741 if (r->CRm & 0x2)
742 /* accessing PMOVSSET_EL0 */
743 kvm_pmu_overflow_set(vcpu, p->regval & mask);
744 else
745 /* accessing PMOVSCLR_EL0 */
746 vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
747 } else {
748 p->regval = vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask;
749 }
750
751 return true;
752}
753
7a0adc70
SZ		 754static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
755 const struct sys_reg_desc *r)
756{
757 u64 mask;
758
759 if (!kvm_arm_pmu_v3_ready(vcpu))
760 return trap_raz_wi(vcpu, p, r);
761
d692b8ad
SZ		 762 if (pmu_write_swinc_el0_disabled(vcpu))
763 return false;
764
7a0adc70
SZ		 765 if (p->is_write) {
766 mask = kvm_pmu_valid_counter_mask(vcpu);
767 kvm_pmu_software_increment(vcpu, p->regval & mask);
768 return true;
769 }
770
771 return false;
772}
773
d692b8ad
SZ		 774static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
775 const struct sys_reg_desc *r)
776{
777 if (!kvm_arm_pmu_v3_ready(vcpu))
778 return trap_raz_wi(vcpu, p, r);
779
780 if (p->is_write) {
781 if (!vcpu_mode_priv(vcpu))
782 return false;
783
784 vcpu_sys_reg(vcpu, PMUSERENR_EL0) = p->regval
785 & ARMV8_PMU_USERENR_MASK;
786 } else {
787 p->regval = vcpu_sys_reg(vcpu, PMUSERENR_EL0)
788 & ARMV8_PMU_USERENR_MASK;
789 }
790
791 return true;
792}
793
0c557ed4
MZ		 794/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
795#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
796 /* DBGBVRn_EL1 */ \
797 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b100), \
84e690bf 798 trap_bvr, reset_bvr, n, 0, get_bvr, set_bvr }, \
0c557ed4
MZ		 799 /* DBGBCRn_EL1 */ \
800 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b101), \
84e690bf 801 trap_bcr, reset_bcr, n, 0, get_bcr, set_bcr }, \
0c557ed4
MZ		 802 /* DBGWVRn_EL1 */ \
803 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b110), \
84e690bf 804 trap_wvr, reset_wvr, n, 0, get_wvr, set_wvr }, \
0c557ed4
MZ		 805 /* DBGWCRn_EL1 */ \
806 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b111), \
84e690bf 807 trap_wcr, reset_wcr, n, 0, get_wcr, set_wcr }
0c557ed4 808
051ff581
SZ		 809/* Macro to expand the PMEVCNTRn_EL0 register */
810#define PMU_PMEVCNTR_EL0(n) \
811 /* PMEVCNTRn_EL0 */ \
812 { Op0(0b11), Op1(0b011), CRn(0b1110), \
813 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
814 access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), }
815
9feb21ac
SZ		 816/* Macro to expand the PMEVTYPERn_EL0 register */
817#define PMU_PMEVTYPER_EL0(n) \
818 /* PMEVTYPERn_EL0 */ \
819 { Op0(0b11), Op1(0b011), CRn(0b1110), \
820 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
821 access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
822
c9a3c58f
JL		 823static bool access_cntp_tval(struct kvm_vcpu *vcpu,
824 struct sys_reg_params *p,
825 const struct sys_reg_desc *r)
826{
7b6b4631
JL		 827 struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
828 u64 now = kvm_phys_timer_read();
829
830 if (p->is_write)
831 ptimer->cnt_cval = p->regval + now;
832 else
833 p->regval = ptimer->cnt_cval - now;
834
c9a3c58f
JL		 835 return true;
836}
837
838static bool access_cntp_ctl(struct kvm_vcpu *vcpu,
839 struct sys_reg_params *p,
840 const struct sys_reg_desc *r)
841{
7b6b4631
JL		 842 struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
843
844 if (p->is_write) {
845 /* ISTATUS bit is read-only */
846 ptimer->cnt_ctl = p->regval & ~ARCH_TIMER_CTRL_IT_STAT;
847 } else {
848 u64 now = kvm_phys_timer_read();
849
850 p->regval = ptimer->cnt_ctl;
851 /*
852 * Set ISTATUS bit if it's expired.
853 * Note that according to ARMv8 ARM Issue A.k, ISTATUS bit is
854 * UNKNOWN when ENABLE bit is 0, so we chose to set ISTATUS bit
855 * regardless of ENABLE bit for our implementation convenience.
856 */
857 if (ptimer->cnt_cval <= now)
858 p->regval |= ARCH_TIMER_CTRL_IT_STAT;
859 }
860
c9a3c58f
JL		 861 return true;
862}
863
864static bool access_cntp_cval(struct kvm_vcpu *vcpu,
865 struct sys_reg_params *p,
866 const struct sys_reg_desc *r)
867{
7b6b4631
JL		 868 struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
869
870 if (p->is_write)
871 ptimer->cnt_cval = p->regval;
872 else
873 p->regval = ptimer->cnt_cval;
874
c9a3c58f
JL		 875 return true;
876}
877
7c8c5e6a
MZ		 878/*
879 * Architected system registers.
880 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
7609c125 881 *
0c557ed4
MZ		 882 * Debug handling: We do trap most, if not all debug related system
883 * registers. The implementation is good enough to ensure that a guest
884 * can use these with minimal performance degradation. The drawback is
885 * that we don't implement any of the external debug, none of the
886 * OSlock protocol. This should be revisited if we ever encounter a
887 * more demanding guest...
7c8c5e6a
MZ		 888 */
889static const struct sys_reg_desc sys_reg_descs[] = {
890 /* DC ISW */
891 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b0110), Op2(0b010),
892 access_dcsw },
893 /* DC CSW */
894 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1010), Op2(0b010),
895 access_dcsw },
896 /* DC CISW */
897 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b010),
898 access_dcsw },
899
0c557ed4
MZ		 900 DBG_BCR_BVR_WCR_WVR_EL1(0),
901 DBG_BCR_BVR_WCR_WVR_EL1(1),
902 /* MDCCINT_EL1 */
903 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
904 trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
905 /* MDSCR_EL1 */
906 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
907 trap_debug_regs, reset_val, MDSCR_EL1, 0 },
908 DBG_BCR_BVR_WCR_WVR_EL1(2),
909 DBG_BCR_BVR_WCR_WVR_EL1(3),
910 DBG_BCR_BVR_WCR_WVR_EL1(4),
911 DBG_BCR_BVR_WCR_WVR_EL1(5),
912 DBG_BCR_BVR_WCR_WVR_EL1(6),
913 DBG_BCR_BVR_WCR_WVR_EL1(7),
914 DBG_BCR_BVR_WCR_WVR_EL1(8),
915 DBG_BCR_BVR_WCR_WVR_EL1(9),
916 DBG_BCR_BVR_WCR_WVR_EL1(10),
917 DBG_BCR_BVR_WCR_WVR_EL1(11),
918 DBG_BCR_BVR_WCR_WVR_EL1(12),
919 DBG_BCR_BVR_WCR_WVR_EL1(13),
920 DBG_BCR_BVR_WCR_WVR_EL1(14),
921 DBG_BCR_BVR_WCR_WVR_EL1(15),
922
923 /* MDRAR_EL1 */
924 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
925 trap_raz_wi },
926 /* OSLAR_EL1 */
927 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b100),
928 trap_raz_wi },
929 /* OSLSR_EL1 */
930 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0001), Op2(0b100),
931 trap_oslsr_el1 },
932 /* OSDLR_EL1 */
933 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0011), Op2(0b100),
934 trap_raz_wi },
935 /* DBGPRCR_EL1 */
936 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0100), Op2(0b100),
937 trap_raz_wi },
938 /* DBGCLAIMSET_EL1 */
939 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1000), Op2(0b110),
940 trap_raz_wi },
941 /* DBGCLAIMCLR_EL1 */
942 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1001), Op2(0b110),
943 trap_raz_wi },
944 /* DBGAUTHSTATUS_EL1 */
945 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b110),
946 trap_dbgauthstatus_el1 },
947
0c557ed4
MZ		 948 /* MDCCSR_EL1 */
949 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0001), Op2(0b000),
950 trap_raz_wi },
951 /* DBGDTR_EL0 */
952 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0100), Op2(0b000),
953 trap_raz_wi },
954 /* DBGDTR[TR]X_EL0 */
955 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0101), Op2(0b000),
956 trap_raz_wi },
957
62a89c44
MZ		 958 /* DBGVCR32_EL2 */
959 { Op0(0b10), Op1(0b100), CRn(0b0000), CRm(0b0111), Op2(0b000),
960 NULL, reset_val, DBGVCR32_EL2, 0 },
961
7c8c5e6a
MZ		 962 /* MPIDR_EL1 */
963 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b101),
964 NULL, reset_mpidr, MPIDR_EL1 },
965 /* SCTLR_EL1 */
966 { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
3c1e7165 967 access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
7c8c5e6a
MZ		 968 /* CPACR_EL1 */
969 { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010),
970 NULL, reset_val, CPACR_EL1, 0 },
971 /* TTBR0_EL1 */
972 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b000),
4d44923b 973 access_vm_reg, reset_unknown, TTBR0_EL1 },
7c8c5e6a
MZ		 974 /* TTBR1_EL1 */
975 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b001),
4d44923b 976 access_vm_reg, reset_unknown, TTBR1_EL1 },
7c8c5e6a
MZ		 977 /* TCR_EL1 */
978 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b010),
4d44923b 979 access_vm_reg, reset_val, TCR_EL1, 0 },
7c8c5e6a
MZ		 980
981 /* AFSR0_EL1 */
982 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b000),
4d44923b 983 access_vm_reg, reset_unknown, AFSR0_EL1 },
7c8c5e6a
MZ		 984 /* AFSR1_EL1 */
985 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b001),
4d44923b 986 access_vm_reg, reset_unknown, AFSR1_EL1 },
7c8c5e6a
MZ		 987 /* ESR_EL1 */
988 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0010), Op2(0b000),
4d44923b 989 access_vm_reg, reset_unknown, ESR_EL1 },
7c8c5e6a
MZ		 990 /* FAR_EL1 */
991 { Op0(0b11), Op1(0b000), CRn(0b0110), CRm(0b0000), Op2(0b000),
4d44923b 992 access_vm_reg, reset_unknown, FAR_EL1 },
1bbd8054
MZ		 993 /* PAR_EL1 */
994 { Op0(0b11), Op1(0b000), CRn(0b0111), CRm(0b0100), Op2(0b000),
995 NULL, reset_unknown, PAR_EL1 },
7c8c5e6a
MZ		 996
997 /* PMINTENSET_EL1 */
998 { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
9db52c78 999 access_pminten, reset_unknown, PMINTENSET_EL1 },
7c8c5e6a
MZ		 1000 /* PMINTENCLR_EL1 */
1001 { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),
9db52c78 1002 access_pminten, NULL, PMINTENSET_EL1 },
7c8c5e6a
MZ		 1003
1004 /* MAIR_EL1 */
1005 { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
4d44923b 1006 access_vm_reg, reset_unknown, MAIR_EL1 },
7c8c5e6a
MZ		 1007 /* AMAIR_EL1 */
1008 { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0011), Op2(0b000),
4d44923b 1009 access_vm_reg, reset_amair_el1, AMAIR_EL1 },
7c8c5e6a
MZ		 1010
1011 /* VBAR_EL1 */
1012 { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b0000), Op2(0b000),
1013 NULL, reset_val, VBAR_EL1, 0 },
db7dedd0 1014
6d52f35a
AP		 1015 /* ICC_SGI1R_EL1 */
1016 { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1011), Op2(0b101),
1017 access_gic_sgi },
db7dedd0
CD		 1018 /* ICC_SRE_EL1 */
1019 { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1100), Op2(0b101),
b34f2bcb 1020 access_gic_sre },
db7dedd0 1021
7c8c5e6a
MZ		 1022 /* CONTEXTIDR_EL1 */
1023 { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001),
4d44923b 1024 access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
7c8c5e6a
MZ		 1025 /* TPIDR_EL1 */
1026 { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b100),
1027 NULL, reset_unknown, TPIDR_EL1 },
1028
1029 /* CNTKCTL_EL1 */
1030 { Op0(0b11), Op1(0b000), CRn(0b1110), CRm(0b0001), Op2(0b000),
1031 NULL, reset_val, CNTKCTL_EL1, 0},
1032
1033 /* CSSELR_EL1 */
1034 { Op0(0b11), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
1035 NULL, reset_unknown, CSSELR_EL1 },
1036
1037 /* PMCR_EL0 */
1038 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000),
ab946834 1039 access_pmcr, reset_pmcr, },
7c8c5e6a
MZ		 1040 /* PMCNTENSET_EL0 */
1041 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
96b0eebc 1042 access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
7c8c5e6a
MZ		 1043 /* PMCNTENCLR_EL0 */
1044 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
96b0eebc 1045 access_pmcnten, NULL, PMCNTENSET_EL0 },
7c8c5e6a
MZ		 1046 /* PMOVSCLR_EL0 */
1047 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
76d883c4 1048 access_pmovs, NULL, PMOVSSET_EL0 },
7c8c5e6a
MZ		 1049 /* PMSWINC_EL0 */
1050 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
7a0adc70 1051 access_pmswinc, reset_unknown, PMSWINC_EL0 },
7c8c5e6a
MZ		 1052 /* PMSELR_EL0 */
1053 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
3965c3ce 1054 access_pmselr, reset_unknown, PMSELR_EL0 },
7c8c5e6a
MZ		 1055 /* PMCEID0_EL0 */
1056 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
a86b5505 1057 access_pmceid },
7c8c5e6a
MZ		 1058 /* PMCEID1_EL0 */
1059 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
a86b5505 1060 access_pmceid },
7c8c5e6a
MZ		 1061 /* PMCCNTR_EL0 */
1062 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
051ff581 1063 access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 },
7c8c5e6a
MZ		 1064 /* PMXEVTYPER_EL0 */
1065 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
9feb21ac 1066 access_pmu_evtyper },
7c8c5e6a
MZ		 1067 /* PMXEVCNTR_EL0 */
1068 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
051ff581 1069 access_pmu_evcntr },
d692b8ad
SZ		 1070 /* PMUSERENR_EL0
1071 * This register resets as unknown in 64bit mode while it resets as zero
1072 * in 32bit mode. Here we choose to reset it as zero for consistency.
1073 */
7c8c5e6a 1074 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
d692b8ad 1075 access_pmuserenr, reset_val, PMUSERENR_EL0, 0 },
7c8c5e6a
MZ		 1076 /* PMOVSSET_EL0 */
1077 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
76d883c4 1078 access_pmovs, reset_unknown, PMOVSSET_EL0 },
7c8c5e6a
MZ		 1079
1080 /* TPIDR_EL0 */
1081 { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b010),
1082 NULL, reset_unknown, TPIDR_EL0 },
1083 /* TPIDRRO_EL0 */
1084 { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
1085 NULL, reset_unknown, TPIDRRO_EL0 },
62a89c44 1086
c9a3c58f
JL		 1087 /* CNTP_TVAL_EL0 */
1088 { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b0010), Op2(0b000),
1089 access_cntp_tval },
1090 /* CNTP_CTL_EL0 */
1091 { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b0010), Op2(0b001),
1092 access_cntp_ctl },
1093 /* CNTP_CVAL_EL0 */
1094 { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b0010), Op2(0b010),
1095 access_cntp_cval },
1096
051ff581
SZ		 1097 /* PMEVCNTRn_EL0 */
1098 PMU_PMEVCNTR_EL0(0),
1099 PMU_PMEVCNTR_EL0(1),
1100 PMU_PMEVCNTR_EL0(2),
1101 PMU_PMEVCNTR_EL0(3),
1102 PMU_PMEVCNTR_EL0(4),
1103 PMU_PMEVCNTR_EL0(5),
1104 PMU_PMEVCNTR_EL0(6),
1105 PMU_PMEVCNTR_EL0(7),
1106 PMU_PMEVCNTR_EL0(8),
1107 PMU_PMEVCNTR_EL0(9),
1108 PMU_PMEVCNTR_EL0(10),
1109 PMU_PMEVCNTR_EL0(11),
1110 PMU_PMEVCNTR_EL0(12),
1111 PMU_PMEVCNTR_EL0(13),
1112 PMU_PMEVCNTR_EL0(14),
1113 PMU_PMEVCNTR_EL0(15),
1114 PMU_PMEVCNTR_EL0(16),
1115 PMU_PMEVCNTR_EL0(17),
1116 PMU_PMEVCNTR_EL0(18),
1117 PMU_PMEVCNTR_EL0(19),
1118 PMU_PMEVCNTR_EL0(20),
1119 PMU_PMEVCNTR_EL0(21),
1120 PMU_PMEVCNTR_EL0(22),
1121 PMU_PMEVCNTR_EL0(23),
1122 PMU_PMEVCNTR_EL0(24),
1123 PMU_PMEVCNTR_EL0(25),
1124 PMU_PMEVCNTR_EL0(26),
1125 PMU_PMEVCNTR_EL0(27),
1126 PMU_PMEVCNTR_EL0(28),
1127 PMU_PMEVCNTR_EL0(29),
1128 PMU_PMEVCNTR_EL0(30),
9feb21ac
SZ		 1129 /* PMEVTYPERn_EL0 */
1130 PMU_PMEVTYPER_EL0(0),
1131 PMU_PMEVTYPER_EL0(1),
1132 PMU_PMEVTYPER_EL0(2),
1133 PMU_PMEVTYPER_EL0(3),
1134 PMU_PMEVTYPER_EL0(4),
1135 PMU_PMEVTYPER_EL0(5),
1136 PMU_PMEVTYPER_EL0(6),
1137 PMU_PMEVTYPER_EL0(7),
1138 PMU_PMEVTYPER_EL0(8),
1139 PMU_PMEVTYPER_EL0(9),
1140 PMU_PMEVTYPER_EL0(10),
1141 PMU_PMEVTYPER_EL0(11),
1142 PMU_PMEVTYPER_EL0(12),
1143 PMU_PMEVTYPER_EL0(13),
1144 PMU_PMEVTYPER_EL0(14),
1145 PMU_PMEVTYPER_EL0(15),
1146 PMU_PMEVTYPER_EL0(16),
1147 PMU_PMEVTYPER_EL0(17),
1148 PMU_PMEVTYPER_EL0(18),
1149 PMU_PMEVTYPER_EL0(19),
1150 PMU_PMEVTYPER_EL0(20),
1151 PMU_PMEVTYPER_EL0(21),
1152 PMU_PMEVTYPER_EL0(22),
1153 PMU_PMEVTYPER_EL0(23),
1154 PMU_PMEVTYPER_EL0(24),
1155 PMU_PMEVTYPER_EL0(25),
1156 PMU_PMEVTYPER_EL0(26),
1157 PMU_PMEVTYPER_EL0(27),
1158 PMU_PMEVTYPER_EL0(28),
1159 PMU_PMEVTYPER_EL0(29),
1160 PMU_PMEVTYPER_EL0(30),
1161 /* PMCCFILTR_EL0
1162 * This register resets as unknown in 64bit mode while it resets as zero
1163 * in 32bit mode. Here we choose to reset it as zero for consistency.
1164 */
1165 { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b1111), Op2(0b111),
1166 access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 },
051ff581 1167
62a89c44
MZ		 1168 /* DACR32_EL2 */
1169 { Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000),
1170 NULL, reset_unknown, DACR32_EL2 },
1171 /* IFSR32_EL2 */
1172 { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0000), Op2(0b001),
1173 NULL, reset_unknown, IFSR32_EL2 },
1174 /* FPEXC32_EL2 */
1175 { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0011), Op2(0b000),
1176 NULL, reset_val, FPEXC32_EL2, 0x70 },
1177};
1178
bdfb4b38 1179static bool trap_dbgidr(struct kvm_vcpu *vcpu,
3fec037d 1180 struct sys_reg_params *p,
bdfb4b38
MZ		 1181 const struct sys_reg_desc *r)
1182{
1183 if (p->is_write) {
1184 return ignore_write(vcpu, p);
1185 } else {
4db8e5ea
SP		 1186 u64 dfr = read_system_reg(SYS_ID_AA64DFR0_EL1);
1187 u64 pfr = read_system_reg(SYS_ID_AA64PFR0_EL1);
28c5dcb2 1188 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
bdfb4b38 1189
2ec5be3d
PF		 1190 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
1191 (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
1192 (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20)
1193 | (6 << 16) | (el3 << 14) | (el3 << 12));
bdfb4b38
MZ		 1194 return true;
1195 }
1196}
1197
1198static bool trap_debug32(struct kvm_vcpu *vcpu,
3fec037d 1199 struct sys_reg_params *p,
bdfb4b38
MZ		 1200 const struct sys_reg_desc *r)
1201{
1202 if (p->is_write) {
2ec5be3d 1203 vcpu_cp14(vcpu, r->reg) = p->regval;
bdfb4b38
MZ		 1204 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
1205 } else {
2ec5be3d 1206 p->regval = vcpu_cp14(vcpu, r->reg);
bdfb4b38
MZ		 1207 }
1208
1209 return true;
1210}
1211
84e690bf
AB		 1212/* AArch32 debug register mappings
1213 *
1214 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
1215 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
1216 *
1217 * All control registers and watchpoint value registers are mapped to
1218 * the lower 32 bits of their AArch64 equivalents. We share the trap
1219 * handlers with the above AArch64 code which checks what mode the
1220 * system is in.
1221 */
1222
281243cb
MZ		 1223static bool trap_xvr(struct kvm_vcpu *vcpu,
1224 struct sys_reg_params *p,
1225 const struct sys_reg_desc *rd)
84e690bf
AB		 1226{
1227 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
1228
1229 if (p->is_write) {
1230 u64 val = *dbg_reg;
1231
1232 val &= 0xffffffffUL;
2ec5be3d 1233 val |= p->regval << 32;
84e690bf
AB		 1234 *dbg_reg = val;
1235
1236 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
1237 } else {
2ec5be3d 1238 p->regval = *dbg_reg >> 32;
84e690bf
AB		 1239 }
1240
eef8c85a
AB		 1241 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
1242
84e690bf
AB		 1243 return true;
1244}
1245
1246#define DBG_BCR_BVR_WCR_WVR(n) \
1247 /* DBGBVRn */ \
1248 { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
1249 /* DBGBCRn */ \
1250 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
1251 /* DBGWVRn */ \
1252 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
1253 /* DBGWCRn */ \
1254 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1255
1256#define DBGBXVR(n) \
1257 { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n }
bdfb4b38
MZ		 1258
1259/*
1260 * Trapped cp14 registers. We generally ignore most of the external
1261 * debug, on the principle that they don't really make sense to a
84e690bf 1262 * guest. Revisit this one day, would this principle change.
bdfb4b38 1263 */
72564016 1264static const struct sys_reg_desc cp14_regs[] = {
bdfb4b38
MZ		 1265 /* DBGIDR */
1266 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
1267 /* DBGDTRRXext */
1268 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1269
1270 DBG_BCR_BVR_WCR_WVR(0),
1271 /* DBGDSCRint */
1272 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1273 DBG_BCR_BVR_WCR_WVR(1),
1274 /* DBGDCCINT */
1275 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 },
1276 /* DBGDSCRext */
1277 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 },
1278 DBG_BCR_BVR_WCR_WVR(2),
1279 /* DBGDTR[RT]Xint */
1280 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1281 /* DBGDTR[RT]Xext */
1282 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1283 DBG_BCR_BVR_WCR_WVR(3),
1284 DBG_BCR_BVR_WCR_WVR(4),
1285 DBG_BCR_BVR_WCR_WVR(5),
1286 /* DBGWFAR */
1287 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1288 /* DBGOSECCR */
1289 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1290 DBG_BCR_BVR_WCR_WVR(6),
1291 /* DBGVCR */
1292 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 },
1293 DBG_BCR_BVR_WCR_WVR(7),
1294 DBG_BCR_BVR_WCR_WVR(8),
1295 DBG_BCR_BVR_WCR_WVR(9),
1296 DBG_BCR_BVR_WCR_WVR(10),
1297 DBG_BCR_BVR_WCR_WVR(11),
1298 DBG_BCR_BVR_WCR_WVR(12),
1299 DBG_BCR_BVR_WCR_WVR(13),
1300 DBG_BCR_BVR_WCR_WVR(14),
1301 DBG_BCR_BVR_WCR_WVR(15),
1302
1303 /* DBGDRAR (32bit) */
1304 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1305
1306 DBGBXVR(0),
1307 /* DBGOSLAR */
1308 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
1309 DBGBXVR(1),
1310 /* DBGOSLSR */
1311 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
1312 DBGBXVR(2),
1313 DBGBXVR(3),
1314 /* DBGOSDLR */
1315 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1316 DBGBXVR(4),
1317 /* DBGPRCR */
1318 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1319 DBGBXVR(5),
1320 DBGBXVR(6),
1321 DBGBXVR(7),
1322 DBGBXVR(8),
1323 DBGBXVR(9),
1324 DBGBXVR(10),
1325 DBGBXVR(11),
1326 DBGBXVR(12),
1327 DBGBXVR(13),
1328 DBGBXVR(14),
1329 DBGBXVR(15),
1330
1331 /* DBGDSAR (32bit) */
1332 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1333
1334 /* DBGDEVID2 */
1335 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1336 /* DBGDEVID1 */
1337 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1338 /* DBGDEVID */
1339 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1340 /* DBGCLAIMSET */
1341 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1342 /* DBGCLAIMCLR */
1343 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1344 /* DBGAUTHSTATUS */
1345 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
72564016
MZ		 1346};
1347
a9866ba0
MZ		 1348/* Trapped cp14 64bit registers */
1349static const struct sys_reg_desc cp14_64_regs[] = {
bdfb4b38
MZ		 1350 /* DBGDRAR (64bit) */
1351 { Op1( 0), CRm( 1), .access = trap_raz_wi },
1352
1353 /* DBGDSAR (64bit) */
1354 { Op1( 0), CRm( 2), .access = trap_raz_wi },
a9866ba0
MZ		 1355};
1356
051ff581
SZ		 1357/* Macro to expand the PMEVCNTRn register */
1358#define PMU_PMEVCNTR(n) \
1359 /* PMEVCNTRn */ \
1360 { Op1(0), CRn(0b1110), \
1361 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1362 access_pmu_evcntr }
1363
9feb21ac
SZ		 1364/* Macro to expand the PMEVTYPERn register */
1365#define PMU_PMEVTYPER(n) \
1366 /* PMEVTYPERn */ \
1367 { Op1(0), CRn(0b1110), \
1368 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1369 access_pmu_evtyper }
1370
4d44923b
MZ		 1371/*
1372 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
1373 * depending on the way they are accessed (as a 32bit or a 64bit
1374 * register).
1375 */
62a89c44 1376static const struct sys_reg_desc cp15_regs[] = {
6d52f35a
AP		 1377 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
1378
3c1e7165 1379 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
4d44923b
MZ		 1380 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1381 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
1382 { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
1383 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
1384 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
1385 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
1386 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
1387 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
1388 { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
1389 { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
1390
62a89c44
MZ		 1391 /*
1392 * DC{C,I,CI}SW operations:
1393 */
1394 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
1395 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
1396 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
4d44923b 1397
7609c125 1398 /* PMU */
ab946834 1399 { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
96b0eebc
SZ		 1400 { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
1401 { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
76d883c4 1402 { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
7a0adc70 1403 { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
3965c3ce 1404 { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
a86b5505
SZ		 1405 { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
1406 { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
051ff581 1407 { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
9feb21ac 1408 { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
051ff581 1409 { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
d692b8ad 1410 { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr },
9db52c78
SZ		 1411 { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
1412 { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
76d883c4 1413 { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
4d44923b
MZ		 1414
1415 { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
1416 { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
1417 { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
1418 { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
db7dedd0
CD		 1419
1420 /* ICC_SRE */
f7f6f2d9 1421 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
db7dedd0 1422
4d44923b 1423 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
051ff581
SZ		 1424
1425 /* PMEVCNTRn */
1426 PMU_PMEVCNTR(0),
1427 PMU_PMEVCNTR(1),
1428 PMU_PMEVCNTR(2),
1429 PMU_PMEVCNTR(3),
1430 PMU_PMEVCNTR(4),
1431 PMU_PMEVCNTR(5),
1432 PMU_PMEVCNTR(6),
1433 PMU_PMEVCNTR(7),
1434 PMU_PMEVCNTR(8),
1435 PMU_PMEVCNTR(9),
1436 PMU_PMEVCNTR(10),
1437 PMU_PMEVCNTR(11),
1438 PMU_PMEVCNTR(12),
1439 PMU_PMEVCNTR(13),
1440 PMU_PMEVCNTR(14),
1441 PMU_PMEVCNTR(15),
1442 PMU_PMEVCNTR(16),
1443 PMU_PMEVCNTR(17),
1444 PMU_PMEVCNTR(18),
1445 PMU_PMEVCNTR(19),
1446 PMU_PMEVCNTR(20),
1447 PMU_PMEVCNTR(21),
1448 PMU_PMEVCNTR(22),
1449 PMU_PMEVCNTR(23),
1450 PMU_PMEVCNTR(24),
1451 PMU_PMEVCNTR(25),
1452 PMU_PMEVCNTR(26),
1453 PMU_PMEVCNTR(27),
1454 PMU_PMEVCNTR(28),
1455 PMU_PMEVCNTR(29),
1456 PMU_PMEVCNTR(30),
9feb21ac
SZ		 1457 /* PMEVTYPERn */
1458 PMU_PMEVTYPER(0),
1459 PMU_PMEVTYPER(1),
1460 PMU_PMEVTYPER(2),
1461 PMU_PMEVTYPER(3),
1462 PMU_PMEVTYPER(4),
1463 PMU_PMEVTYPER(5),
1464 PMU_PMEVTYPER(6),
1465 PMU_PMEVTYPER(7),
1466 PMU_PMEVTYPER(8),
1467 PMU_PMEVTYPER(9),
1468 PMU_PMEVTYPER(10),
1469 PMU_PMEVTYPER(11),
1470 PMU_PMEVTYPER(12),
1471 PMU_PMEVTYPER(13),
1472 PMU_PMEVTYPER(14),
1473 PMU_PMEVTYPER(15),
1474 PMU_PMEVTYPER(16),
1475 PMU_PMEVTYPER(17),
1476 PMU_PMEVTYPER(18),
1477 PMU_PMEVTYPER(19),
1478 PMU_PMEVTYPER(20),
1479 PMU_PMEVTYPER(21),
1480 PMU_PMEVTYPER(22),
1481 PMU_PMEVTYPER(23),
1482 PMU_PMEVTYPER(24),
1483 PMU_PMEVTYPER(25),
1484 PMU_PMEVTYPER(26),
1485 PMU_PMEVTYPER(27),
1486 PMU_PMEVTYPER(28),
1487 PMU_PMEVTYPER(29),
1488 PMU_PMEVTYPER(30),
1489 /* PMCCFILTR */
1490 { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
a9866ba0
MZ		 1491};
1492
1493static const struct sys_reg_desc cp15_64_regs[] = {
1494 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
051ff581 1495 { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
6d52f35a 1496 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
4d44923b 1497 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
7c8c5e6a
MZ		 1498};
1499
1500/* Target specific emulation tables */
1501static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS];
1502
1503void kvm_register_target_sys_reg_table(unsigned int target,
1504 struct kvm_sys_reg_target_table *table)
1505{
1506 target_tables[target] = table;
1507}
1508
1509/* Get specific register table for this target. */
62a89c44
MZ		 1510static const struct sys_reg_desc *get_target_table(unsigned target,
1511 bool mode_is_64,
1512 size_t *num)
7c8c5e6a
MZ		 1513{
1514 struct kvm_sys_reg_target_table *table;
1515
1516 table = target_tables[target];
62a89c44
MZ		 1517 if (mode_is_64) {
1518 *num = table->table64.num;
1519 return table->table64.table;
1520 } else {
1521 *num = table->table32.num;
1522 return table->table32.table;
1523 }
7c8c5e6a
MZ		 1524}
1525
623eefa8
MZ		 1526#define reg_to_match_value(x) \
1527 ({ \
1528 unsigned long val; \
1529 val = (x)->Op0 << 14; \
1530 val |= (x)->Op1 << 11; \
1531 val |= (x)->CRn << 7; \
1532 val |= (x)->CRm << 3; \
1533 val |= (x)->Op2; \
1534 val; \
1535 })
1536
1537static int match_sys_reg(const void *key, const void *elt)
1538{
1539 const unsigned long pval = (unsigned long)key;
1540 const struct sys_reg_desc *r = elt;
1541
1542 return pval - reg_to_match_value(r);
1543}
1544
7c8c5e6a
MZ		 1545static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
1546 const struct sys_reg_desc table[],
1547 unsigned int num)
1548{
623eefa8
MZ		 1549 unsigned long pval = reg_to_match_value(params);
1550
1551 return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
7c8c5e6a
MZ		 1552}
1553
62a89c44
MZ		 1554int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
1555{
1556 kvm_inject_undefined(vcpu);
1557 return 1;
1558}
1559
72564016
MZ		 1560/*
1561 * emulate_cp -- tries to match a sys_reg access in a handling table, and
1562 * call the corresponding trap handler.
1563 *
1564 * @params: pointer to the descriptor of the access
1565 * @table: array of trap descriptors
1566 * @num: size of the trap descriptor array
1567 *
1568 * Return 0 if the access has been handled, and -1 if not.
1569 */
1570static int emulate_cp(struct kvm_vcpu *vcpu,
3fec037d 1571 struct sys_reg_params *params,
72564016
MZ		 1572 const struct sys_reg_desc *table,
1573 size_t num)
62a89c44 1574{
72564016 1575 const struct sys_reg_desc *r;
62a89c44 1576
72564016
MZ		 1577 if (!table)
1578 return -1; /* Not handled */
62a89c44 1579
62a89c44 1580 r = find_reg(params, table, num);
62a89c44 1581
72564016 1582 if (r) {
62a89c44
MZ		 1583 /*
1584 * Not having an accessor means that we have
1585 * configured a trap that we don't know how to
1586 * handle. This certainly qualifies as a gross bug
1587 * that should be fixed right away.
1588 */
1589 BUG_ON(!r->access);
1590
1591 if (likely(r->access(vcpu, params, r))) {
1592 /* Skip instruction, since it was emulated */
1593 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
6327f35a
SZ		 1594 /* Handled */
1595 return 0;
62a89c44 1596 }
72564016
MZ		 1597 }
1598
1599 /* Not handled */
1600 return -1;
1601}
1602
1603static void unhandled_cp_access(struct kvm_vcpu *vcpu,
1604 struct sys_reg_params *params)
1605{
1606 u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
40c4f8d2 1607 int cp = -1;
72564016
MZ		 1608
1609 switch(hsr_ec) {
c6d01a94
MR		 1610 case ESR_ELx_EC_CP15_32:
1611 case ESR_ELx_EC_CP15_64:
72564016
MZ		 1612 cp = 15;
1613 break;
c6d01a94
MR		 1614 case ESR_ELx_EC_CP14_MR:
1615 case ESR_ELx_EC_CP14_64:
72564016
MZ		 1616 cp = 14;
1617 break;
1618 default:
40c4f8d2 1619 WARN_ON(1);
62a89c44
MZ		 1620 }
1621
72564016
MZ		 1622 kvm_err("Unsupported guest CP%d access at: %08lx\n",
1623 cp, *vcpu_pc(vcpu));
62a89c44
MZ		 1624 print_sys_reg_instr(params);
1625 kvm_inject_undefined(vcpu);
1626}
1627
1628/**
7769db90 1629 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
62a89c44
MZ		 1630 * @vcpu: The VCPU pointer
1631 * @run: The kvm_run struct
1632 */
72564016
MZ		 1633static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
1634 const struct sys_reg_desc *global,
1635 size_t nr_global,
1636 const struct sys_reg_desc *target_specific,
1637 size_t nr_specific)
62a89c44
MZ		 1638{
1639 struct sys_reg_params params;
1640 u32 hsr = kvm_vcpu_get_hsr(vcpu);
2ec5be3d 1641 int Rt = (hsr >> 5) & 0xf;
62a89c44
MZ		 1642 int Rt2 = (hsr >> 10) & 0xf;
1643
2072d29c
MZ		 1644 params.is_aarch32 = true;
1645 params.is_32bit = false;
62a89c44 1646 params.CRm = (hsr >> 1) & 0xf;
62a89c44
MZ		 1647 params.is_write = ((hsr & 1) == 0);
1648
1649 params.Op0 = 0;
1650 params.Op1 = (hsr >> 16) & 0xf;
1651 params.Op2 = 0;
1652 params.CRn = 0;
1653
1654 /*
2ec5be3d 1655 * Make a 64-bit value out of Rt and Rt2. As we use the same trap
62a89c44
MZ		 1656 * backends between AArch32 and AArch64, we get away with it.
1657 */
1658 if (params.is_write) {
2ec5be3d
PF		 1659 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
1660 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
62a89c44
MZ		 1661 }
1662
72564016
MZ		 1663 if (!emulate_cp(vcpu, &params, target_specific, nr_specific))
1664 goto out;
1665 if (!emulate_cp(vcpu, &params, global, nr_global))
1666 goto out;
1667
1668 unhandled_cp_access(vcpu, &params);
62a89c44 1669
72564016 1670out:
2ec5be3d 1671 /* Split up the value between registers for the read side */
62a89c44 1672 if (!params.is_write) {
2ec5be3d
PF		 1673 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
1674 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
62a89c44
MZ		 1675 }
1676
1677 return 1;
1678}
1679
1680/**
7769db90 1681 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
62a89c44
MZ		 1682 * @vcpu: The VCPU pointer
1683 * @run: The kvm_run struct
1684 */
72564016
MZ		 1685static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
1686 const struct sys_reg_desc *global,
1687 size_t nr_global,
1688 const struct sys_reg_desc *target_specific,
1689 size_t nr_specific)
62a89c44
MZ		 1690{
1691 struct sys_reg_params params;
1692 u32 hsr = kvm_vcpu_get_hsr(vcpu);
2ec5be3d 1693 int Rt = (hsr >> 5) & 0xf;
62a89c44 1694
2072d29c
MZ		 1695 params.is_aarch32 = true;
1696 params.is_32bit = true;
62a89c44 1697 params.CRm = (hsr >> 1) & 0xf;
2ec5be3d 1698 params.regval = vcpu_get_reg(vcpu, Rt);
62a89c44
MZ		 1699 params.is_write = ((hsr & 1) == 0);
1700 params.CRn = (hsr >> 10) & 0xf;
1701 params.Op0 = 0;
1702 params.Op1 = (hsr >> 14) & 0x7;
1703 params.Op2 = (hsr >> 17) & 0x7;
1704
2ec5be3d
PF		 1705 if (!emulate_cp(vcpu, &params, target_specific, nr_specific) ||
1706 !emulate_cp(vcpu, &params, global, nr_global)) {
1707 if (!params.is_write)
1708 vcpu_set_reg(vcpu, Rt, params.regval);
72564016 1709 return 1;
2ec5be3d 1710 }
72564016
MZ		 1711
1712 unhandled_cp_access(vcpu, &params);
62a89c44
MZ		 1713 return 1;
1714}
1715
72564016
MZ		 1716int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
1717{
1718 const struct sys_reg_desc *target_specific;
1719 size_t num;
1720
1721 target_specific = get_target_table(vcpu->arch.target, false, &num);
1722 return kvm_handle_cp_64(vcpu,
a9866ba0 1723 cp15_64_regs, ARRAY_SIZE(cp15_64_regs),
72564016
MZ		 1724 target_specific, num);
1725}
1726
1727int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
1728{
1729 const struct sys_reg_desc *target_specific;
1730 size_t num;
1731
1732 target_specific = get_target_table(vcpu->arch.target, false, &num);
1733 return kvm_handle_cp_32(vcpu,
1734 cp15_regs, ARRAY_SIZE(cp15_regs),
1735 target_specific, num);
1736}
1737
1738int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
1739{
1740 return kvm_handle_cp_64(vcpu,
a9866ba0 1741 cp14_64_regs, ARRAY_SIZE(cp14_64_regs),
72564016
MZ		 1742 NULL, 0);
1743}
1744
1745int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
1746{
1747 return kvm_handle_cp_32(vcpu,
1748 cp14_regs, ARRAY_SIZE(cp14_regs),
1749 NULL, 0);
1750}
1751
7c8c5e6a 1752static int emulate_sys_reg(struct kvm_vcpu *vcpu,
3fec037d 1753 struct sys_reg_params *params)
7c8c5e6a
MZ		 1754{
1755 size_t num;
1756 const struct sys_reg_desc *table, *r;
1757
62a89c44 1758 table = get_target_table(vcpu->arch.target, true, &num);
7c8c5e6a
MZ		 1759
1760 /* Search target-specific then generic table. */
1761 r = find_reg(params, table, num);
1762 if (!r)
1763 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1764
1765 if (likely(r)) {
1766 /*
1767 * Not having an accessor means that we have
1768 * configured a trap that we don't know how to
1769 * handle. This certainly qualifies as a gross bug
1770 * that should be fixed right away.
1771 */
1772 BUG_ON(!r->access);
1773
1774 if (likely(r->access(vcpu, params, r))) {
1775 /* Skip instruction, since it was emulated */
1776 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
1777 return 1;
1778 }
1779 /* If access function fails, it should complain. */
1780 } else {
1781 kvm_err("Unsupported guest sys_reg access at: %lx\n",
1782 *vcpu_pc(vcpu));
1783 print_sys_reg_instr(params);
1784 }
1785 kvm_inject_undefined(vcpu);
1786 return 1;
1787}
1788
1789static void reset_sys_reg_descs(struct kvm_vcpu *vcpu,
1790 const struct sys_reg_desc *table, size_t num)
1791{
1792 unsigned long i;
1793
1794 for (i = 0; i < num; i++)
1795 if (table[i].reset)
1796 table[i].reset(vcpu, &table[i]);
1797}
1798
1799/**
1800 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
1801 * @vcpu: The VCPU pointer
1802 * @run: The kvm_run struct
1803 */
1804int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run)
1805{
1806 struct sys_reg_params params;
1807 unsigned long esr = kvm_vcpu_get_hsr(vcpu);
2ec5be3d
PF		 1808 int Rt = (esr >> 5) & 0x1f;
1809 int ret;
7c8c5e6a 1810
eef8c85a
AB		 1811 trace_kvm_handle_sys_reg(esr);
1812
2072d29c
MZ		 1813 params.is_aarch32 = false;
1814 params.is_32bit = false;
7c8c5e6a
MZ		 1815 params.Op0 = (esr >> 20) & 3;
1816 params.Op1 = (esr >> 14) & 0x7;
1817 params.CRn = (esr >> 10) & 0xf;
1818 params.CRm = (esr >> 1) & 0xf;
1819 params.Op2 = (esr >> 17) & 0x7;
2ec5be3d 1820 params.regval = vcpu_get_reg(vcpu, Rt);
7c8c5e6a
MZ		 1821 params.is_write = !(esr & 1);
1822
2ec5be3d
PF		 1823 ret = emulate_sys_reg(vcpu, &params);
1824
1825 if (!params.is_write)
1826 vcpu_set_reg(vcpu, Rt, params.regval);
1827 return ret;
7c8c5e6a
MZ		 1828}
1829
1830/******************************************************************************
1831 * Userspace API
1832 *****************************************************************************/
1833
1834static bool index_to_params(u64 id, struct sys_reg_params *params)
1835{
1836 switch (id & KVM_REG_SIZE_MASK) {
1837 case KVM_REG_SIZE_U64:
1838 /* Any unused index bits means it's not valid. */
1839 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
1840 | KVM_REG_ARM_COPROC_MASK
1841 | KVM_REG_ARM64_SYSREG_OP0_MASK
1842 | KVM_REG_ARM64_SYSREG_OP1_MASK
1843 | KVM_REG_ARM64_SYSREG_CRN_MASK
1844 | KVM_REG_ARM64_SYSREG_CRM_MASK
1845 | KVM_REG_ARM64_SYSREG_OP2_MASK))
1846 return false;
1847 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
1848 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
1849 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
1850 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
1851 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
1852 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
1853 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
1854 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
1855 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
1856 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
1857 return true;
1858 default:
1859 return false;
1860 }
1861}
1862
4b927b94
VK		 1863const struct sys_reg_desc *find_reg_by_id(u64 id,
1864 struct sys_reg_params *params,
1865 const struct sys_reg_desc table[],
1866 unsigned int num)
1867{
1868 if (!index_to_params(id, params))
1869 return NULL;
1870
1871 return find_reg(params, table, num);
1872}
1873
7c8c5e6a
MZ		 1874/* Decode an index value, and find the sys_reg_desc entry. */
1875static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
1876 u64 id)
1877{
1878 size_t num;
1879 const struct sys_reg_desc *table, *r;
1880 struct sys_reg_params params;
1881
1882 /* We only do sys_reg for now. */
1883 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
1884 return NULL;
1885
62a89c44 1886 table = get_target_table(vcpu->arch.target, true, &num);
4b927b94 1887 r = find_reg_by_id(id, &params, table, num);
7c8c5e6a
MZ		 1888 if (!r)
1889 r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1890
1891 /* Not saved in the sys_reg array? */
1892 if (r && !r->reg)
1893 r = NULL;
1894
1895 return r;
1896}
1897
1898/*
1899 * These are the invariant sys_reg registers: we let the guest see the
1900 * host versions of these, so they're part of the guest state.
1901 *
1902 * A future CPU may provide a mechanism to present different values to
1903 * the guest, or a future kvm may trap them.
1904 */
1905
1906#define FUNCTION_INVARIANT(reg) \
1907 static void get_##reg(struct kvm_vcpu *v, \
1908 const struct sys_reg_desc *r) \
1909 { \
1f3d8699 1910 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \
7c8c5e6a
MZ		 1911 }
1912
1913FUNCTION_INVARIANT(midr_el1)
1914FUNCTION_INVARIANT(ctr_el0)
1915FUNCTION_INVARIANT(revidr_el1)
1916FUNCTION_INVARIANT(id_pfr0_el1)
1917FUNCTION_INVARIANT(id_pfr1_el1)
1918FUNCTION_INVARIANT(id_dfr0_el1)
1919FUNCTION_INVARIANT(id_afr0_el1)
1920FUNCTION_INVARIANT(id_mmfr0_el1)
1921FUNCTION_INVARIANT(id_mmfr1_el1)
1922FUNCTION_INVARIANT(id_mmfr2_el1)
1923FUNCTION_INVARIANT(id_mmfr3_el1)
1924FUNCTION_INVARIANT(id_isar0_el1)
1925FUNCTION_INVARIANT(id_isar1_el1)
1926FUNCTION_INVARIANT(id_isar2_el1)
1927FUNCTION_INVARIANT(id_isar3_el1)
1928FUNCTION_INVARIANT(id_isar4_el1)
1929FUNCTION_INVARIANT(id_isar5_el1)
1930FUNCTION_INVARIANT(clidr_el1)
1931FUNCTION_INVARIANT(aidr_el1)
1932
1933/* ->val is filled in by kvm_sys_reg_table_init() */
1934static struct sys_reg_desc invariant_sys_regs[] = {
1935 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b000),
1936 NULL, get_midr_el1 },
1937 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b110),
1938 NULL, get_revidr_el1 },
1939 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b000),
1940 NULL, get_id_pfr0_el1 },
1941 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b001),
1942 NULL, get_id_pfr1_el1 },
1943 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b010),
1944 NULL, get_id_dfr0_el1 },
1945 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b011),
1946 NULL, get_id_afr0_el1 },
1947 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b100),
1948 NULL, get_id_mmfr0_el1 },
1949 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b101),
1950 NULL, get_id_mmfr1_el1 },
1951 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b110),
1952 NULL, get_id_mmfr2_el1 },
1953 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b111),
1954 NULL, get_id_mmfr3_el1 },
1955 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
1956 NULL, get_id_isar0_el1 },
1957 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b001),
1958 NULL, get_id_isar1_el1 },
1959 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
1960 NULL, get_id_isar2_el1 },
1961 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b011),
1962 NULL, get_id_isar3_el1 },
1963 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b100),
1964 NULL, get_id_isar4_el1 },
1965 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b101),
1966 NULL, get_id_isar5_el1 },
1967 { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b001),
1968 NULL, get_clidr_el1 },
1969 { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b111),
1970 NULL, get_aidr_el1 },
1971 { Op0(0b11), Op1(0b011), CRn(0b0000), CRm(0b0000), Op2(0b001),
1972 NULL, get_ctr_el0 },
1973};
1974
26c99af1 1975static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
7c8c5e6a 1976{
7c8c5e6a
MZ		 1977 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
1978 return -EFAULT;
1979 return 0;
1980}
1981
26c99af1 1982static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
7c8c5e6a 1983{
7c8c5e6a
MZ		 1984 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
1985 return -EFAULT;
1986 return 0;
1987}
1988
1989static int get_invariant_sys_reg(u64 id, void __user *uaddr)
1990{
1991 struct sys_reg_params params;
1992 const struct sys_reg_desc *r;
1993
4b927b94
VK		 1994 r = find_reg_by_id(id, &params, invariant_sys_regs,
1995 ARRAY_SIZE(invariant_sys_regs));
7c8c5e6a
MZ		 1996 if (!r)
1997 return -ENOENT;
1998
1999 return reg_to_user(uaddr, &r->val, id);
2000}
2001
2002static int set_invariant_sys_reg(u64 id, void __user *uaddr)
2003{
2004 struct sys_reg_params params;
2005 const struct sys_reg_desc *r;
2006 int err;
2007 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
2008
4b927b94
VK		 2009 r = find_reg_by_id(id, &params, invariant_sys_regs,
2010 ARRAY_SIZE(invariant_sys_regs));
7c8c5e6a
MZ		 2011 if (!r)
2012 return -ENOENT;
2013
2014 err = reg_from_user(&val, uaddr, id);
2015 if (err)
2016 return err;
2017
2018 /* This is what we mean by invariant: you can't change it. */
2019 if (r->val != val)
2020 return -EINVAL;
2021
2022 return 0;
2023}
2024
2025static bool is_valid_cache(u32 val)
2026{
2027 u32 level, ctype;
2028
2029 if (val >= CSSELR_MAX)
18d45766 2030 return false;
7c8c5e6a
MZ		 2031
2032 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
2033 level = (val >> 1);
2034 ctype = (cache_levels >> (level * 3)) & 7;
2035
2036 switch (ctype) {
2037 case 0: /* No cache */
2038 return false;
2039 case 1: /* Instruction cache only */
2040 return (val & 1);
2041 case 2: /* Data cache only */
2042 case 4: /* Unified cache */
2043 return !(val & 1);
2044 case 3: /* Separate instruction and data caches */
2045 return true;
2046 default: /* Reserved: we can't know instruction or data. */
2047 return false;
2048 }
2049}
2050
2051static int demux_c15_get(u64 id, void __user *uaddr)
2052{
2053 u32 val;
2054 u32 __user *uval = uaddr;
2055
2056 /* Fail if we have unknown bits set. */
2057 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2058 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2059 return -ENOENT;
2060
2061 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2062 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2063 if (KVM_REG_SIZE(id) != 4)
2064 return -ENOENT;
2065 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2066 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2067 if (!is_valid_cache(val))
2068 return -ENOENT;
2069
2070 return put_user(get_ccsidr(val), uval);
2071 default:
2072 return -ENOENT;
2073 }
2074}
2075
2076static int demux_c15_set(u64 id, void __user *uaddr)
2077{
2078 u32 val, newval;
2079 u32 __user *uval = uaddr;
2080
2081 /* Fail if we have unknown bits set. */
2082 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2083 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2084 return -ENOENT;
2085
2086 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2087 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2088 if (KVM_REG_SIZE(id) != 4)
2089 return -ENOENT;
2090 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2091 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2092 if (!is_valid_cache(val))
2093 return -ENOENT;
2094
2095 if (get_user(newval, uval))
2096 return -EFAULT;
2097
2098 /* This is also invariant: you can't change it. */
2099 if (newval != get_ccsidr(val))
2100 return -EINVAL;
2101 return 0;
2102 default:
2103 return -ENOENT;
2104 }
2105}
2106
2107int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2108{
2109 const struct sys_reg_desc *r;
2110 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2111
2112 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2113 return demux_c15_get(reg->id, uaddr);
2114
2115 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2116 return -ENOENT;
2117
2118 r = index_to_sys_reg_desc(vcpu, reg->id);
2119 if (!r)
2120 return get_invariant_sys_reg(reg->id, uaddr);
2121
84e690bf
AB		 2122 if (r->get_user)
2123 return (r->get_user)(vcpu, r, reg, uaddr);
2124
7c8c5e6a
MZ		 2125 return reg_to_user(uaddr, &vcpu_sys_reg(vcpu, r->reg), reg->id);
2126}
2127
2128int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2129{
2130 const struct sys_reg_desc *r;
2131 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2132
2133 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2134 return demux_c15_set(reg->id, uaddr);
2135
2136 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2137 return -ENOENT;
2138
2139 r = index_to_sys_reg_desc(vcpu, reg->id);
2140 if (!r)
2141 return set_invariant_sys_reg(reg->id, uaddr);
2142
84e690bf
AB		 2143 if (r->set_user)
2144 return (r->set_user)(vcpu, r, reg, uaddr);
2145
7c8c5e6a
MZ		 2146 return reg_from_user(&vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
2147}
2148
2149static unsigned int num_demux_regs(void)
2150{
2151 unsigned int i, count = 0;
2152
2153 for (i = 0; i < CSSELR_MAX; i++)
2154 if (is_valid_cache(i))
2155 count++;
2156
2157 return count;
2158}
2159
2160static int write_demux_regids(u64 __user *uindices)
2161{
efd48cea 2162 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
7c8c5e6a
MZ		 2163 unsigned int i;
2164
2165 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
2166 for (i = 0; i < CSSELR_MAX; i++) {
2167 if (!is_valid_cache(i))
2168 continue;
2169 if (put_user(val | i, uindices))
2170 return -EFAULT;
2171 uindices++;
2172 }
2173 return 0;
2174}
2175
2176static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
2177{
2178 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
2179 KVM_REG_ARM64_SYSREG |
2180 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
2181 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
2182 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
2183 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
2184 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
2185}
2186
2187static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
2188{
2189 if (!*uind)
2190 return true;
2191
2192 if (put_user(sys_reg_to_index(reg), *uind))
2193 return false;
2194
2195 (*uind)++;
2196 return true;
2197}
2198
2199/* Assumed ordered tables, see kvm_sys_reg_table_init. */
2200static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
2201{
2202 const struct sys_reg_desc *i1, *i2, *end1, *end2;
2203 unsigned int total = 0;
2204 size_t num;
2205
2206 /* We check for duplicates here, to allow arch-specific overrides. */
62a89c44 2207 i1 = get_target_table(vcpu->arch.target, true, &num);
7c8c5e6a
MZ		 2208 end1 = i1 + num;
2209 i2 = sys_reg_descs;
2210 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
2211
2212 BUG_ON(i1 == end1 || i2 == end2);
2213
2214 /* Walk carefully, as both tables may refer to the same register. */
2215 while (i1 || i2) {
2216 int cmp = cmp_sys_reg(i1, i2);
2217 /* target-specific overrides generic entry. */
2218 if (cmp <= 0) {
2219 /* Ignore registers we trap but don't save. */
2220 if (i1->reg) {
2221 if (!copy_reg_to_user(i1, &uind))
2222 return -EFAULT;
2223 total++;
2224 }
2225 } else {
2226 /* Ignore registers we trap but don't save. */
2227 if (i2->reg) {
2228 if (!copy_reg_to_user(i2, &uind))
2229 return -EFAULT;
2230 total++;
2231 }
2232 }
2233
2234 if (cmp <= 0 && ++i1 == end1)
2235 i1 = NULL;
2236 if (cmp >= 0 && ++i2 == end2)
2237 i2 = NULL;
2238 }
2239 return total;
2240}
2241
2242unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
2243{
2244 return ARRAY_SIZE(invariant_sys_regs)
2245 + num_demux_regs()
2246 + walk_sys_regs(vcpu, (u64 __user *)NULL);
2247}
2248
2249int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
2250{
2251 unsigned int i;
2252 int err;
2253
2254 /* Then give them all the invariant registers' indices. */
2255 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
2256 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
2257 return -EFAULT;
2258 uindices++;
2259 }
2260
2261 err = walk_sys_regs(vcpu, uindices);
2262 if (err < 0)
2263 return err;
2264 uindices += err;
2265
2266 return write_demux_regids(uindices);
2267}
2268
e6a95517
MZ		 2269static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n)
2270{
2271 unsigned int i;
2272
2273 for (i = 1; i < n; i++) {
2274 if (cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2275 kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
2276 return 1;
2277 }
2278 }
2279
2280 return 0;
2281}
2282
7c8c5e6a
MZ		 2283void kvm_sys_reg_table_init(void)
2284{
2285 unsigned int i;
2286 struct sys_reg_desc clidr;
2287
2288 /* Make sure tables are unique and in order. */
e6a95517
MZ		 2289 BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs)));
2290 BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs)));
2291 BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs)));
2292 BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs)));
2293 BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs)));
2294 BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs)));
7c8c5e6a
MZ		 2295
2296 /* We abuse the reset function to overwrite the table itself. */
2297 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
2298 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
2299
2300 /*
2301 * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
2302 *
2303 * If software reads the Cache Type fields from Ctype1
2304 * upwards, once it has seen a value of 0b000, no caches
2305 * exist at further-out levels of the hierarchy. So, for
2306 * example, if Ctype3 is the first Cache Type field with a
2307 * value of 0b000, the values of Ctype4 to Ctype7 must be
2308 * ignored.
2309 */
2310 get_clidr_el1(NULL, &clidr); /* Ugly... */
2311 cache_levels = clidr.val;
2312 for (i = 0; i < 7; i++)
2313 if (((cache_levels >> (i*3)) & 7) == 0)
2314 break;
2315 /* Clear all higher bits. */
2316 cache_levels &= (1 << (i*3))-1;
2317}
2318
2319/**
2320 * kvm_reset_sys_regs - sets system registers to reset value
2321 * @vcpu: The VCPU pointer
2322 *
2323 * This function finds the right table above and sets the registers on the
2324 * virtual CPU struct to their architecturally defined reset values.
2325 */
2326void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
2327{
2328 size_t num;
2329 const struct sys_reg_desc *table;
2330
2331 /* Catch someone adding a register without putting in reset entry. */
2332 memset(&vcpu->arch.ctxt.sys_regs, 0x42, sizeof(vcpu->arch.ctxt.sys_regs));
2333
2334 /* Generic chip reset first (so target could override). */
2335 reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2336
62a89c44 2337 table = get_target_table(vcpu->arch.target, true, &num);
7c8c5e6a
MZ		 2338 reset_sys_reg_descs(vcpu, table, num);
2339
2340 for (num = 1; num < NR_SYS_REGS; num++)
2341 if (vcpu_sys_reg(vcpu, num) == 0x4242424242424242)
2342 panic("Didn't reset vcpu_sys_reg(%zi)", num);
2343}
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