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arm64: KVM: PMU: Inject UNDEF on non-privileged accesses
[mirror_ubuntu-artful-kernel.git] / arch / arm64 / kvm / sys_regs.c
CommitLineData
7c8c5e6a
MZ		 1/*
2 * Copyright (C) 2012,2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * Derived from arch/arm/kvm/coproc.c:
6 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
7 * Authors: Rusty Russell <rusty@rustcorp.com.au>
8 * Christoffer Dall <c.dall@virtualopensystems.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License, version 2, as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
623eefa8 23#include <linux/bsearch.h>
7c8c5e6a 24#include <linux/kvm_host.h>
c6d01a94 25#include <linux/mm.h>
7c8c5e6a 26#include <linux/uaccess.h>
c6d01a94 27
7c8c5e6a
MZ		 28#include <asm/cacheflush.h>
29#include <asm/cputype.h>
0c557ed4 30#include <asm/debug-monitors.h>
c6d01a94
MR		 31#include <asm/esr.h>
32#include <asm/kvm_arm.h>
9d8415d6 33#include <asm/kvm_asm.h>
c6d01a94
MR		 34#include <asm/kvm_coproc.h>
35#include <asm/kvm_emulate.h>
36#include <asm/kvm_host.h>
37#include <asm/kvm_mmu.h>
ab946834 38#include <asm/perf_event.h>
1f3d8699 39#include <asm/sysreg.h>
c6d01a94 40
7c8c5e6a
MZ		 41#include <trace/events/kvm.h>
42
43#include "sys_regs.h"
44
eef8c85a
AB		 45#include "trace.h"
46
7c8c5e6a
MZ		 47/*
48 * All of this file is extremly similar to the ARM coproc.c, but the
49 * types are different. My gut feeling is that it should be pretty
50 * easy to merge, but that would be an ABI breakage -- again. VFP
51 * would also need to be abstracted.
62a89c44
MZ		 52 *
53 * For AArch32, we only take care of what is being trapped. Anything
54 * that has to do with init and userspace access has to go via the
55 * 64bit interface.
7c8c5e6a
MZ		 56 */
57
58/* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
59static u32 cache_levels;
60
61/* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
62#define CSSELR_MAX 12
63
64/* Which cache CCSIDR represents depends on CSSELR value. */
65static u32 get_ccsidr(u32 csselr)
66{
67 u32 ccsidr;
68
69 /* Make sure noone else changes CSSELR during this! */
70 local_irq_disable();
1f3d8699 71 write_sysreg(csselr, csselr_el1);
7c8c5e6a 72 isb();
1f3d8699 73 ccsidr = read_sysreg(ccsidr_el1);
7c8c5e6a
MZ		 74 local_irq_enable();
75
76 return ccsidr;
77}
78
3c1e7165
MZ		 79/*
80 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
81 */
7c8c5e6a 82static bool access_dcsw(struct kvm_vcpu *vcpu,
3fec037d 83 struct sys_reg_params *p,
7c8c5e6a
MZ		 84 const struct sys_reg_desc *r)
85{
7c8c5e6a
MZ		 86 if (!p->is_write)
87 return read_from_write_only(vcpu, p);
88
3c1e7165 89 kvm_set_way_flush(vcpu);
7c8c5e6a
MZ		 90 return true;
91}
92
4d44923b
MZ		 93/*
94 * Generic accessor for VM registers. Only called as long as HCR_TVM
3c1e7165
MZ		 95 * is set. If the guest enables the MMU, we stop trapping the VM
96 * sys_regs and leave it in complete control of the caches.
4d44923b
MZ		 97 */
98static bool access_vm_reg(struct kvm_vcpu *vcpu,
3fec037d 99 struct sys_reg_params *p,
4d44923b
MZ		 100 const struct sys_reg_desc *r)
101{
3c1e7165 102 bool was_enabled = vcpu_has_cache_enabled(vcpu);
4d44923b
MZ		 103
104 BUG_ON(!p->is_write);
105
dedf97e8 106 if (!p->is_aarch32) {
2ec5be3d 107 vcpu_sys_reg(vcpu, r->reg) = p->regval;
dedf97e8
MZ		 108 } else {
109 if (!p->is_32bit)
2ec5be3d
PF		 110 vcpu_cp15_64_high(vcpu, r->reg) = upper_32_bits(p->regval);
111 vcpu_cp15_64_low(vcpu, r->reg) = lower_32_bits(p->regval);
dedf97e8 112 }
f0a3eaff 113
3c1e7165 114 kvm_toggle_cache(vcpu, was_enabled);
4d44923b
MZ		 115 return true;
116}
117
6d52f35a
AP		 118/*
119 * Trap handler for the GICv3 SGI generation system register.
120 * Forward the request to the VGIC emulation.
121 * The cp15_64 code makes sure this automatically works
122 * for both AArch64 and AArch32 accesses.
123 */
124static bool access_gic_sgi(struct kvm_vcpu *vcpu,
3fec037d 125 struct sys_reg_params *p,
6d52f35a
AP		 126 const struct sys_reg_desc *r)
127{
6d52f35a
AP		 128 if (!p->is_write)
129 return read_from_write_only(vcpu, p);
130
2ec5be3d 131 vgic_v3_dispatch_sgi(vcpu, p->regval);
6d52f35a
AP		 132
133 return true;
134}
135
b34f2bcb
MZ		 136static bool access_gic_sre(struct kvm_vcpu *vcpu,
137 struct sys_reg_params *p,
138 const struct sys_reg_desc *r)
139{
140 if (p->is_write)
141 return ignore_write(vcpu, p);
142
143 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
144 return true;
145}
146
7609c125 147static bool trap_raz_wi(struct kvm_vcpu *vcpu,
3fec037d 148 struct sys_reg_params *p,
7609c125 149 const struct sys_reg_desc *r)
7c8c5e6a
MZ		 150{
151 if (p->is_write)
152 return ignore_write(vcpu, p);
153 else
154 return read_zero(vcpu, p);
155}
156
0c557ed4 157static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
3fec037d 158 struct sys_reg_params *p,
0c557ed4
MZ		 159 const struct sys_reg_desc *r)
160{
161 if (p->is_write) {
162 return ignore_write(vcpu, p);
163 } else {
2ec5be3d 164 p->regval = (1 << 3);
0c557ed4
MZ		 165 return true;
166 }
167}
168
169static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
3fec037d 170 struct sys_reg_params *p,
0c557ed4
MZ		 171 const struct sys_reg_desc *r)
172{
173 if (p->is_write) {
174 return ignore_write(vcpu, p);
175 } else {
1f3d8699 176 p->regval = read_sysreg(dbgauthstatus_el1);
0c557ed4
MZ		 177 return true;
178 }
179}
180
181/*
182 * We want to avoid world-switching all the DBG registers all the
183 * time:
184 *
185 * - If we've touched any debug register, it is likely that we're
186 * going to touch more of them. It then makes sense to disable the
187 * traps and start doing the save/restore dance
188 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
189 * then mandatory to save/restore the registers, as the guest
190 * depends on them.
191 *
192 * For this, we use a DIRTY bit, indicating the guest has modified the
193 * debug registers, used as follow:
194 *
195 * On guest entry:
196 * - If the dirty bit is set (because we're coming back from trapping),
197 * disable the traps, save host registers, restore guest registers.
198 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
199 * set the dirty bit, disable the traps, save host registers,
200 * restore guest registers.
201 * - Otherwise, enable the traps
202 *
203 * On guest exit:
204 * - If the dirty bit is set, save guest registers, restore host
205 * registers and clear the dirty bit. This ensure that the host can
206 * now use the debug registers.
207 */
208static bool trap_debug_regs(struct kvm_vcpu *vcpu,
3fec037d 209 struct sys_reg_params *p,
0c557ed4
MZ		 210 const struct sys_reg_desc *r)
211{
212 if (p->is_write) {
2ec5be3d 213 vcpu_sys_reg(vcpu, r->reg) = p->regval;
0c557ed4
MZ		 214 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
215 } else {
2ec5be3d 216 p->regval = vcpu_sys_reg(vcpu, r->reg);
0c557ed4
MZ		 217 }
218
2ec5be3d 219 trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
eef8c85a 220
0c557ed4
MZ		 221 return true;
222}
223
84e690bf
AB		 224/*
225 * reg_to_dbg/dbg_to_reg
226 *
227 * A 32 bit write to a debug register leave top bits alone
228 * A 32 bit read from a debug register only returns the bottom bits
229 *
230 * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the
231 * hyp.S code switches between host and guest values in future.
232 */
281243cb
MZ		 233static void reg_to_dbg(struct kvm_vcpu *vcpu,
234 struct sys_reg_params *p,
235 u64 *dbg_reg)
84e690bf 236{
2ec5be3d 237 u64 val = p->regval;
84e690bf
AB		 238
239 if (p->is_32bit) {
240 val &= 0xffffffffUL;
241 val |= ((*dbg_reg >> 32) << 32);
242 }
243
244 *dbg_reg = val;
245 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
246}
247
281243cb
MZ		 248static void dbg_to_reg(struct kvm_vcpu *vcpu,
249 struct sys_reg_params *p,
250 u64 *dbg_reg)
84e690bf 251{
2ec5be3d 252 p->regval = *dbg_reg;
84e690bf 253 if (p->is_32bit)
2ec5be3d 254 p->regval &= 0xffffffffUL;
84e690bf
AB		 255}
256
281243cb
MZ		 257static bool trap_bvr(struct kvm_vcpu *vcpu,
258 struct sys_reg_params *p,
259 const struct sys_reg_desc *rd)
84e690bf
AB		 260{
261 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
262
263 if (p->is_write)
264 reg_to_dbg(vcpu, p, dbg_reg);
265 else
266 dbg_to_reg(vcpu, p, dbg_reg);
267
eef8c85a
AB		 268 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
269
84e690bf
AB		 270 return true;
271}
272
273static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
274 const struct kvm_one_reg *reg, void __user *uaddr)
275{
276 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
277
1713e5aa 278 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 279 return -EFAULT;
280 return 0;
281}
282
283static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
284 const struct kvm_one_reg *reg, void __user *uaddr)
285{
286 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
287
288 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
289 return -EFAULT;
290 return 0;
291}
292
281243cb
MZ		 293static void reset_bvr(struct kvm_vcpu *vcpu,
294 const struct sys_reg_desc *rd)
84e690bf
AB		 295{
296 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val;
297}
298
281243cb
MZ		 299static bool trap_bcr(struct kvm_vcpu *vcpu,
300 struct sys_reg_params *p,
301 const struct sys_reg_desc *rd)
84e690bf
AB		 302{
303 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
304
305 if (p->is_write)
306 reg_to_dbg(vcpu, p, dbg_reg);
307 else
308 dbg_to_reg(vcpu, p, dbg_reg);
309
eef8c85a
AB		 310 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
311
84e690bf
AB		 312 return true;
313}
314
315static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
316 const struct kvm_one_reg *reg, void __user *uaddr)
317{
318 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
319
1713e5aa 320 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 321 return -EFAULT;
322
323 return 0;
324}
325
326static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
327 const struct kvm_one_reg *reg, void __user *uaddr)
328{
329 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
330
331 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
332 return -EFAULT;
333 return 0;
334}
335
281243cb
MZ		 336static void reset_bcr(struct kvm_vcpu *vcpu,
337 const struct sys_reg_desc *rd)
84e690bf
AB		 338{
339 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val;
340}
341
281243cb
MZ		 342static bool trap_wvr(struct kvm_vcpu *vcpu,
343 struct sys_reg_params *p,
344 const struct sys_reg_desc *rd)
84e690bf
AB		 345{
346 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
347
348 if (p->is_write)
349 reg_to_dbg(vcpu, p, dbg_reg);
350 else
351 dbg_to_reg(vcpu, p, dbg_reg);
352
eef8c85a
AB		 353 trace_trap_reg(__func__, rd->reg, p->is_write,
354 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]);
355
84e690bf
AB		 356 return true;
357}
358
359static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
360 const struct kvm_one_reg *reg, void __user *uaddr)
361{
362 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
363
1713e5aa 364 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 365 return -EFAULT;
366 return 0;
367}
368
369static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
370 const struct kvm_one_reg *reg, void __user *uaddr)
371{
372 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
373
374 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
375 return -EFAULT;
376 return 0;
377}
378
281243cb
MZ		 379static void reset_wvr(struct kvm_vcpu *vcpu,
380 const struct sys_reg_desc *rd)
84e690bf
AB		 381{
382 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val;
383}
384
281243cb
MZ		 385static bool trap_wcr(struct kvm_vcpu *vcpu,
386 struct sys_reg_params *p,
387 const struct sys_reg_desc *rd)
84e690bf
AB		 388{
389 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
390
391 if (p->is_write)
392 reg_to_dbg(vcpu, p, dbg_reg);
393 else
394 dbg_to_reg(vcpu, p, dbg_reg);
395
eef8c85a
AB		 396 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
397
84e690bf
AB		 398 return true;
399}
400
401static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
402 const struct kvm_one_reg *reg, void __user *uaddr)
403{
404 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
405
1713e5aa 406 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 407 return -EFAULT;
408 return 0;
409}
410
411static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
412 const struct kvm_one_reg *reg, void __user *uaddr)
413{
414 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
415
416 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
417 return -EFAULT;
418 return 0;
419}
420
281243cb
MZ		 421static void reset_wcr(struct kvm_vcpu *vcpu,
422 const struct sys_reg_desc *rd)
84e690bf
AB		 423{
424 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val;
425}
426
7c8c5e6a
MZ		 427static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
428{
1f3d8699 429 vcpu_sys_reg(vcpu, AMAIR_EL1) = read_sysreg(amair_el1);
7c8c5e6a
MZ		 430}
431
432static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
433{
4429fc64
AP		 434 u64 mpidr;
435
7c8c5e6a 436 /*
4429fc64
AP		 437 * Map the vcpu_id into the first three affinity level fields of
438 * the MPIDR. We limit the number of VCPUs in level 0 due to a
439 * limitation to 16 CPUs in that level in the ICC_SGIxR registers
440 * of the GICv3 to be able to address each CPU directly when
441 * sending IPIs.
7c8c5e6a 442 */
4429fc64
AP		 443 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
444 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
445 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
446 vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr;
7c8c5e6a
MZ		 447}
448
ab946834
SZ		 449static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
450{
451 u64 pmcr, val;
452
1f3d8699
MR		 453 pmcr = read_sysreg(pmcr_el0);
454 /*
455 * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN
ab946834
SZ		 456 * except PMCR.E resetting to zero.
457 */
458 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
459 | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
460 vcpu_sys_reg(vcpu, PMCR_EL0) = val;
461}
462
6c007036 463static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
d692b8ad
SZ		 464{
465 u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
6c007036 466 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu);
d692b8ad 467
24d5950f
MZ		 468 if (!enabled)
469 kvm_inject_undefined(vcpu);
470
6c007036 471 return !enabled;
d692b8ad
SZ		 472}
473
6c007036 474static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
d692b8ad 475{
6c007036
MZ		 476 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN);
477}
d692b8ad 478
6c007036
MZ		 479static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
480{
481 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN);
d692b8ad
SZ		 482}
483
484static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
485{
6c007036 486 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN);
d692b8ad
SZ		 487}
488
489static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
490{
6c007036 491 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN);
d692b8ad
SZ		 492}
493
ab946834
SZ		 494static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
495 const struct sys_reg_desc *r)
496{
497 u64 val;
498
499 if (!kvm_arm_pmu_v3_ready(vcpu))
500 return trap_raz_wi(vcpu, p, r);
501
d692b8ad
SZ		 502 if (pmu_access_el0_disabled(vcpu))
503 return false;
504
ab946834
SZ		 505 if (p->is_write) {
506 /* Only update writeable bits of PMCR */
507 val = vcpu_sys_reg(vcpu, PMCR_EL0);
508 val &= ~ARMV8_PMU_PMCR_MASK;
509 val |= p->regval & ARMV8_PMU_PMCR_MASK;
510 vcpu_sys_reg(vcpu, PMCR_EL0) = val;
76993739 511 kvm_pmu_handle_pmcr(vcpu, val);
ab946834
SZ		 512 } else {
513 /* PMCR.P & PMCR.C are RAZ */
514 val = vcpu_sys_reg(vcpu, PMCR_EL0)
515 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
516 p->regval = val;
517 }
518
519 return true;
520}
521
3965c3ce
SZ		 522static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
523 const struct sys_reg_desc *r)
524{
525 if (!kvm_arm_pmu_v3_ready(vcpu))
526 return trap_raz_wi(vcpu, p, r);
527
d692b8ad
SZ		 528 if (pmu_access_event_counter_el0_disabled(vcpu))
529 return false;
530
3965c3ce
SZ		 531 if (p->is_write)
532 vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
533 else
534 /* return PMSELR.SEL field */
535 p->regval = vcpu_sys_reg(vcpu, PMSELR_EL0)
536 & ARMV8_PMU_COUNTER_MASK;
537
538 return true;
539}
540
a86b5505
SZ		 541static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
542 const struct sys_reg_desc *r)
543{
544 u64 pmceid;
545
546 if (!kvm_arm_pmu_v3_ready(vcpu))
547 return trap_raz_wi(vcpu, p, r);
548
549 BUG_ON(p->is_write);
550
d692b8ad
SZ		 551 if (pmu_access_el0_disabled(vcpu))
552 return false;
553
a86b5505 554 if (!(p->Op2 & 1))
1f3d8699 555 pmceid = read_sysreg(pmceid0_el0);
a86b5505 556 else
1f3d8699 557 pmceid = read_sysreg(pmceid1_el0);
a86b5505
SZ		 558
559 p->regval = pmceid;
560
561 return true;
562}
563
051ff581
SZ		 564static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
565{
566 u64 pmcr, val;
567
568 pmcr = vcpu_sys_reg(vcpu, PMCR_EL0);
569 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
24d5950f
MZ		 570 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) {
571 kvm_inject_undefined(vcpu);
051ff581 572 return false;
24d5950f 573 }
051ff581
SZ		 574
575 return true;
576}
577
578static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
579 struct sys_reg_params *p,
580 const struct sys_reg_desc *r)
581{
582 u64 idx;
583
584 if (!kvm_arm_pmu_v3_ready(vcpu))
585 return trap_raz_wi(vcpu, p, r);
586
587 if (r->CRn == 9 && r->CRm == 13) {
588 if (r->Op2 == 2) {
589 /* PMXEVCNTR_EL0 */
d692b8ad
SZ		 590 if (pmu_access_event_counter_el0_disabled(vcpu))
591 return false;
592
051ff581
SZ		 593 idx = vcpu_sys_reg(vcpu, PMSELR_EL0)
594 & ARMV8_PMU_COUNTER_MASK;
595 } else if (r->Op2 == 0) {
596 /* PMCCNTR_EL0 */
d692b8ad
SZ		 597 if (pmu_access_cycle_counter_el0_disabled(vcpu))
598 return false;
599
051ff581
SZ		 600 idx = ARMV8_PMU_CYCLE_IDX;
601 } else {
9e3f7a29 602 return false;
051ff581 603 }
9e3f7a29
WH		 604 } else if (r->CRn == 0 && r->CRm == 9) {
605 /* PMCCNTR */
606 if (pmu_access_event_counter_el0_disabled(vcpu))
607 return false;
608
609 idx = ARMV8_PMU_CYCLE_IDX;
051ff581
SZ		 610 } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
611 /* PMEVCNTRn_EL0 */
d692b8ad
SZ		 612 if (pmu_access_event_counter_el0_disabled(vcpu))
613 return false;
614
051ff581
SZ		 615 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
616 } else {
9e3f7a29 617 return false;
051ff581
SZ		 618 }
619
620 if (!pmu_counter_idx_valid(vcpu, idx))
621 return false;
622
d692b8ad
SZ		 623 if (p->is_write) {
624 if (pmu_access_el0_disabled(vcpu))
625 return false;
626
051ff581 627 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
d692b8ad 628 } else {
051ff581 629 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
d692b8ad 630 }
051ff581
SZ		 631
632 return true;
633}
634
9feb21ac
SZ		 635static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
636 const struct sys_reg_desc *r)
637{
638 u64 idx, reg;
639
640 if (!kvm_arm_pmu_v3_ready(vcpu))
641 return trap_raz_wi(vcpu, p, r);
642
d692b8ad
SZ		 643 if (pmu_access_el0_disabled(vcpu))
644 return false;
645
9feb21ac
SZ		 646 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
647 /* PMXEVTYPER_EL0 */
648 idx = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
649 reg = PMEVTYPER0_EL0 + idx;
650 } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
651 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
652 if (idx == ARMV8_PMU_CYCLE_IDX)
653 reg = PMCCFILTR_EL0;
654 else
655 /* PMEVTYPERn_EL0 */
656 reg = PMEVTYPER0_EL0 + idx;
657 } else {
658 BUG();
659 }
660
661 if (!pmu_counter_idx_valid(vcpu, idx))
662 return false;
663
664 if (p->is_write) {
665 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
666 vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
667 } else {
668 p->regval = vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
669 }
670
671 return true;
672}
673
96b0eebc
SZ		 674static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
675 const struct sys_reg_desc *r)
676{
677 u64 val, mask;
678
679 if (!kvm_arm_pmu_v3_ready(vcpu))
680 return trap_raz_wi(vcpu, p, r);
681
d692b8ad
SZ		 682 if (pmu_access_el0_disabled(vcpu))
683 return false;
684
96b0eebc
SZ		 685 mask = kvm_pmu_valid_counter_mask(vcpu);
686 if (p->is_write) {
687 val = p->regval & mask;
688 if (r->Op2 & 0x1) {
689 /* accessing PMCNTENSET_EL0 */
690 vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
691 kvm_pmu_enable_counter(vcpu, val);
692 } else {
693 /* accessing PMCNTENCLR_EL0 */
694 vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
695 kvm_pmu_disable_counter(vcpu, val);
696 }
697 } else {
698 p->regval = vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
699 }
700
701 return true;
702}
703
9db52c78
SZ		 704static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
705 const struct sys_reg_desc *r)
706{
707 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
708
709 if (!kvm_arm_pmu_v3_ready(vcpu))
710 return trap_raz_wi(vcpu, p, r);
711
9008c235
MZ		 712 if (!vcpu_mode_priv(vcpu)) {
713 kvm_inject_undefined(vcpu);
d692b8ad 714 return false;
9008c235 715 }
d692b8ad 716
9db52c78
SZ		 717 if (p->is_write) {
718 u64 val = p->regval & mask;
719
720 if (r->Op2 & 0x1)
721 /* accessing PMINTENSET_EL1 */
722 vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
723 else
724 /* accessing PMINTENCLR_EL1 */
725 vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
726 } else {
727 p->regval = vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask;
728 }
729
730 return true;
731}
732
76d883c4
SZ		 733static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
734 const struct sys_reg_desc *r)
735{
736 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
737
738 if (!kvm_arm_pmu_v3_ready(vcpu))
739 return trap_raz_wi(vcpu, p, r);
740
d692b8ad
SZ		 741 if (pmu_access_el0_disabled(vcpu))
742 return false;
743
76d883c4
SZ		 744 if (p->is_write) {
745 if (r->CRm & 0x2)
746 /* accessing PMOVSSET_EL0 */
747 kvm_pmu_overflow_set(vcpu, p->regval & mask);
748 else
749 /* accessing PMOVSCLR_EL0 */
750 vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
751 } else {
752 p->regval = vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask;
753 }
754
755 return true;
756}
757
7a0adc70
SZ		 758static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
759 const struct sys_reg_desc *r)
760{
761 u64 mask;
762
763 if (!kvm_arm_pmu_v3_ready(vcpu))
764 return trap_raz_wi(vcpu, p, r);
765
d692b8ad
SZ		 766 if (pmu_write_swinc_el0_disabled(vcpu))
767 return false;
768
7a0adc70
SZ		 769 if (p->is_write) {
770 mask = kvm_pmu_valid_counter_mask(vcpu);
771 kvm_pmu_software_increment(vcpu, p->regval & mask);
772 return true;
773 }
774
775 return false;
776}
777
d692b8ad
SZ		 778static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
779 const struct sys_reg_desc *r)
780{
781 if (!kvm_arm_pmu_v3_ready(vcpu))
782 return trap_raz_wi(vcpu, p, r);
783
784 if (p->is_write) {
9008c235
MZ		 785 if (!vcpu_mode_priv(vcpu)) {
786 kvm_inject_undefined(vcpu);
d692b8ad 787 return false;
9008c235 788 }
d692b8ad
SZ		 789
790 vcpu_sys_reg(vcpu, PMUSERENR_EL0) = p->regval
791 & ARMV8_PMU_USERENR_MASK;
792 } else {
793 p->regval = vcpu_sys_reg(vcpu, PMUSERENR_EL0)
794 & ARMV8_PMU_USERENR_MASK;
795 }
796
797 return true;
798}
799
0c557ed4
MZ		 800/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
801#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
802 /* DBGBVRn_EL1 */ \
803 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b100), \
84e690bf 804 trap_bvr, reset_bvr, n, 0, get_bvr, set_bvr }, \
0c557ed4
MZ		 805 /* DBGBCRn_EL1 */ \
806 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b101), \
84e690bf 807 trap_bcr, reset_bcr, n, 0, get_bcr, set_bcr }, \
0c557ed4
MZ		 808 /* DBGWVRn_EL1 */ \
809 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b110), \
84e690bf 810 trap_wvr, reset_wvr, n, 0, get_wvr, set_wvr }, \
0c557ed4
MZ		 811 /* DBGWCRn_EL1 */ \
812 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b111), \
84e690bf 813 trap_wcr, reset_wcr, n, 0, get_wcr, set_wcr }
0c557ed4 814
051ff581
SZ		 815/* Macro to expand the PMEVCNTRn_EL0 register */
816#define PMU_PMEVCNTR_EL0(n) \
817 /* PMEVCNTRn_EL0 */ \
818 { Op0(0b11), Op1(0b011), CRn(0b1110), \
819 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
820 access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), }
821
9feb21ac
SZ		 822/* Macro to expand the PMEVTYPERn_EL0 register */
823#define PMU_PMEVTYPER_EL0(n) \
824 /* PMEVTYPERn_EL0 */ \
825 { Op0(0b11), Op1(0b011), CRn(0b1110), \
826 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
827 access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
828
c9a3c58f
JL		 829static bool access_cntp_tval(struct kvm_vcpu *vcpu,
830 struct sys_reg_params *p,
831 const struct sys_reg_desc *r)
832{
7b6b4631
JL		 833 struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
834 u64 now = kvm_phys_timer_read();
835
836 if (p->is_write)
837 ptimer->cnt_cval = p->regval + now;
838 else
839 p->regval = ptimer->cnt_cval - now;
840
c9a3c58f
JL		 841 return true;
842}
843
844static bool access_cntp_ctl(struct kvm_vcpu *vcpu,
845 struct sys_reg_params *p,
846 const struct sys_reg_desc *r)
847{
7b6b4631
JL		 848 struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
849
850 if (p->is_write) {
851 /* ISTATUS bit is read-only */
852 ptimer->cnt_ctl = p->regval & ~ARCH_TIMER_CTRL_IT_STAT;
853 } else {
854 u64 now = kvm_phys_timer_read();
855
856 p->regval = ptimer->cnt_ctl;
857 /*
858 * Set ISTATUS bit if it's expired.
859 * Note that according to ARMv8 ARM Issue A.k, ISTATUS bit is
860 * UNKNOWN when ENABLE bit is 0, so we chose to set ISTATUS bit
861 * regardless of ENABLE bit for our implementation convenience.
862 */
863 if (ptimer->cnt_cval <= now)
864 p->regval |= ARCH_TIMER_CTRL_IT_STAT;
865 }
866
c9a3c58f
JL		 867 return true;
868}
869
870static bool access_cntp_cval(struct kvm_vcpu *vcpu,
871 struct sys_reg_params *p,
872 const struct sys_reg_desc *r)
873{
7b6b4631
JL		 874 struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
875
876 if (p->is_write)
877 ptimer->cnt_cval = p->regval;
878 else
879 p->regval = ptimer->cnt_cval;
880
c9a3c58f
JL		 881 return true;
882}
883
7c8c5e6a
MZ		 884/*
885 * Architected system registers.
886 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
7609c125 887 *
0c557ed4
MZ		 888 * Debug handling: We do trap most, if not all debug related system
889 * registers. The implementation is good enough to ensure that a guest
890 * can use these with minimal performance degradation. The drawback is
891 * that we don't implement any of the external debug, none of the
892 * OSlock protocol. This should be revisited if we ever encounter a
893 * more demanding guest...
7c8c5e6a
MZ		 894 */
895static const struct sys_reg_desc sys_reg_descs[] = {
896 /* DC ISW */
897 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b0110), Op2(0b010),
898 access_dcsw },
899 /* DC CSW */
900 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1010), Op2(0b010),
901 access_dcsw },
902 /* DC CISW */
903 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b010),
904 access_dcsw },
905
0c557ed4
MZ		 906 DBG_BCR_BVR_WCR_WVR_EL1(0),
907 DBG_BCR_BVR_WCR_WVR_EL1(1),
908 /* MDCCINT_EL1 */
909 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
910 trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
911 /* MDSCR_EL1 */
912 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
913 trap_debug_regs, reset_val, MDSCR_EL1, 0 },
914 DBG_BCR_BVR_WCR_WVR_EL1(2),
915 DBG_BCR_BVR_WCR_WVR_EL1(3),
916 DBG_BCR_BVR_WCR_WVR_EL1(4),
917 DBG_BCR_BVR_WCR_WVR_EL1(5),
918 DBG_BCR_BVR_WCR_WVR_EL1(6),
919 DBG_BCR_BVR_WCR_WVR_EL1(7),
920 DBG_BCR_BVR_WCR_WVR_EL1(8),
921 DBG_BCR_BVR_WCR_WVR_EL1(9),
922 DBG_BCR_BVR_WCR_WVR_EL1(10),
923 DBG_BCR_BVR_WCR_WVR_EL1(11),
924 DBG_BCR_BVR_WCR_WVR_EL1(12),
925 DBG_BCR_BVR_WCR_WVR_EL1(13),
926 DBG_BCR_BVR_WCR_WVR_EL1(14),
927 DBG_BCR_BVR_WCR_WVR_EL1(15),
928
929 /* MDRAR_EL1 */
930 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
931 trap_raz_wi },
932 /* OSLAR_EL1 */
933 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b100),
934 trap_raz_wi },
935 /* OSLSR_EL1 */
936 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0001), Op2(0b100),
937 trap_oslsr_el1 },
938 /* OSDLR_EL1 */
939 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0011), Op2(0b100),
940 trap_raz_wi },
941 /* DBGPRCR_EL1 */
942 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0100), Op2(0b100),
943 trap_raz_wi },
944 /* DBGCLAIMSET_EL1 */
945 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1000), Op2(0b110),
946 trap_raz_wi },
947 /* DBGCLAIMCLR_EL1 */
948 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1001), Op2(0b110),
949 trap_raz_wi },
950 /* DBGAUTHSTATUS_EL1 */
951 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b110),
952 trap_dbgauthstatus_el1 },
953
0c557ed4
MZ		 954 /* MDCCSR_EL1 */
955 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0001), Op2(0b000),
956 trap_raz_wi },
957 /* DBGDTR_EL0 */
958 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0100), Op2(0b000),
959 trap_raz_wi },
960 /* DBGDTR[TR]X_EL0 */
961 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0101), Op2(0b000),
962 trap_raz_wi },
963
62a89c44
MZ		 964 /* DBGVCR32_EL2 */
965 { Op0(0b10), Op1(0b100), CRn(0b0000), CRm(0b0111), Op2(0b000),
966 NULL, reset_val, DBGVCR32_EL2, 0 },
967
7c8c5e6a
MZ		 968 /* MPIDR_EL1 */
969 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b101),
970 NULL, reset_mpidr, MPIDR_EL1 },
971 /* SCTLR_EL1 */
972 { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
3c1e7165 973 access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
7c8c5e6a
MZ		 974 /* CPACR_EL1 */
975 { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010),
976 NULL, reset_val, CPACR_EL1, 0 },
977 /* TTBR0_EL1 */
978 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b000),
4d44923b 979 access_vm_reg, reset_unknown, TTBR0_EL1 },
7c8c5e6a
MZ		 980 /* TTBR1_EL1 */
981 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b001),
4d44923b 982 access_vm_reg, reset_unknown, TTBR1_EL1 },
7c8c5e6a
MZ		 983 /* TCR_EL1 */
984 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b010),
4d44923b 985 access_vm_reg, reset_val, TCR_EL1, 0 },
7c8c5e6a
MZ		 986
987 /* AFSR0_EL1 */
988 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b000),
4d44923b 989 access_vm_reg, reset_unknown, AFSR0_EL1 },
7c8c5e6a
MZ		 990 /* AFSR1_EL1 */
991 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b001),
4d44923b 992 access_vm_reg, reset_unknown, AFSR1_EL1 },
7c8c5e6a
MZ		 993 /* ESR_EL1 */
994 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0010), Op2(0b000),
4d44923b 995 access_vm_reg, reset_unknown, ESR_EL1 },
7c8c5e6a
MZ		 996 /* FAR_EL1 */
997 { Op0(0b11), Op1(0b000), CRn(0b0110), CRm(0b0000), Op2(0b000),
4d44923b 998 access_vm_reg, reset_unknown, FAR_EL1 },
1bbd8054
MZ		 999 /* PAR_EL1 */
1000 { Op0(0b11), Op1(0b000), CRn(0b0111), CRm(0b0100), Op2(0b000),
1001 NULL, reset_unknown, PAR_EL1 },
7c8c5e6a
MZ		 1002
1003 /* PMINTENSET_EL1 */
1004 { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
9db52c78 1005 access_pminten, reset_unknown, PMINTENSET_EL1 },
7c8c5e6a
MZ		 1006 /* PMINTENCLR_EL1 */
1007 { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),
9db52c78 1008 access_pminten, NULL, PMINTENSET_EL1 },
7c8c5e6a
MZ		 1009
1010 /* MAIR_EL1 */
1011 { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
4d44923b 1012 access_vm_reg, reset_unknown, MAIR_EL1 },
7c8c5e6a
MZ		 1013 /* AMAIR_EL1 */
1014 { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0011), Op2(0b000),
4d44923b 1015 access_vm_reg, reset_amair_el1, AMAIR_EL1 },
7c8c5e6a
MZ		 1016
1017 /* VBAR_EL1 */
1018 { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b0000), Op2(0b000),
1019 NULL, reset_val, VBAR_EL1, 0 },
db7dedd0 1020
6d52f35a
AP		 1021 /* ICC_SGI1R_EL1 */
1022 { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1011), Op2(0b101),
1023 access_gic_sgi },
db7dedd0
CD		 1024 /* ICC_SRE_EL1 */
1025 { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1100), Op2(0b101),
b34f2bcb 1026 access_gic_sre },
db7dedd0 1027
7c8c5e6a
MZ		 1028 /* CONTEXTIDR_EL1 */
1029 { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001),
4d44923b 1030 access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
7c8c5e6a
MZ		 1031 /* TPIDR_EL1 */
1032 { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b100),
1033 NULL, reset_unknown, TPIDR_EL1 },
1034
1035 /* CNTKCTL_EL1 */
1036 { Op0(0b11), Op1(0b000), CRn(0b1110), CRm(0b0001), Op2(0b000),
1037 NULL, reset_val, CNTKCTL_EL1, 0},
1038
1039 /* CSSELR_EL1 */
1040 { Op0(0b11), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
1041 NULL, reset_unknown, CSSELR_EL1 },
1042
1043 /* PMCR_EL0 */
1044 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000),
ab946834 1045 access_pmcr, reset_pmcr, },
7c8c5e6a
MZ		 1046 /* PMCNTENSET_EL0 */
1047 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
96b0eebc 1048 access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
7c8c5e6a
MZ		 1049 /* PMCNTENCLR_EL0 */
1050 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
96b0eebc 1051 access_pmcnten, NULL, PMCNTENSET_EL0 },
7c8c5e6a
MZ		 1052 /* PMOVSCLR_EL0 */
1053 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
76d883c4 1054 access_pmovs, NULL, PMOVSSET_EL0 },
7c8c5e6a
MZ		 1055 /* PMSWINC_EL0 */
1056 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
7a0adc70 1057 access_pmswinc, reset_unknown, PMSWINC_EL0 },
7c8c5e6a
MZ		 1058 /* PMSELR_EL0 */
1059 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
3965c3ce 1060 access_pmselr, reset_unknown, PMSELR_EL0 },
7c8c5e6a
MZ		 1061 /* PMCEID0_EL0 */
1062 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
a86b5505 1063 access_pmceid },
7c8c5e6a
MZ		 1064 /* PMCEID1_EL0 */
1065 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
a86b5505 1066 access_pmceid },
7c8c5e6a
MZ		 1067 /* PMCCNTR_EL0 */
1068 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
051ff581 1069 access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 },
7c8c5e6a
MZ		 1070 /* PMXEVTYPER_EL0 */
1071 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
9feb21ac 1072 access_pmu_evtyper },
7c8c5e6a
MZ		 1073 /* PMXEVCNTR_EL0 */
1074 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
051ff581 1075 access_pmu_evcntr },
d692b8ad
SZ		 1076 /* PMUSERENR_EL0
1077 * This register resets as unknown in 64bit mode while it resets as zero
1078 * in 32bit mode. Here we choose to reset it as zero for consistency.
1079 */
7c8c5e6a 1080 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
d692b8ad 1081 access_pmuserenr, reset_val, PMUSERENR_EL0, 0 },
7c8c5e6a
MZ		 1082 /* PMOVSSET_EL0 */
1083 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
76d883c4 1084 access_pmovs, reset_unknown, PMOVSSET_EL0 },
7c8c5e6a
MZ		 1085
1086 /* TPIDR_EL0 */
1087 { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b010),
1088 NULL, reset_unknown, TPIDR_EL0 },
1089 /* TPIDRRO_EL0 */
1090 { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
1091 NULL, reset_unknown, TPIDRRO_EL0 },
62a89c44 1092
c9a3c58f
JL		 1093 /* CNTP_TVAL_EL0 */
1094 { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b0010), Op2(0b000),
1095 access_cntp_tval },
1096 /* CNTP_CTL_EL0 */
1097 { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b0010), Op2(0b001),
1098 access_cntp_ctl },
1099 /* CNTP_CVAL_EL0 */
1100 { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b0010), Op2(0b010),
1101 access_cntp_cval },
1102
051ff581
SZ		 1103 /* PMEVCNTRn_EL0 */
1104 PMU_PMEVCNTR_EL0(0),
1105 PMU_PMEVCNTR_EL0(1),
1106 PMU_PMEVCNTR_EL0(2),
1107 PMU_PMEVCNTR_EL0(3),
1108 PMU_PMEVCNTR_EL0(4),
1109 PMU_PMEVCNTR_EL0(5),
1110 PMU_PMEVCNTR_EL0(6),
1111 PMU_PMEVCNTR_EL0(7),
1112 PMU_PMEVCNTR_EL0(8),
1113 PMU_PMEVCNTR_EL0(9),
1114 PMU_PMEVCNTR_EL0(10),
1115 PMU_PMEVCNTR_EL0(11),
1116 PMU_PMEVCNTR_EL0(12),
1117 PMU_PMEVCNTR_EL0(13),
1118 PMU_PMEVCNTR_EL0(14),
1119 PMU_PMEVCNTR_EL0(15),
1120 PMU_PMEVCNTR_EL0(16),
1121 PMU_PMEVCNTR_EL0(17),
1122 PMU_PMEVCNTR_EL0(18),
1123 PMU_PMEVCNTR_EL0(19),
1124 PMU_PMEVCNTR_EL0(20),
1125 PMU_PMEVCNTR_EL0(21),
1126 PMU_PMEVCNTR_EL0(22),
1127 PMU_PMEVCNTR_EL0(23),
1128 PMU_PMEVCNTR_EL0(24),
1129 PMU_PMEVCNTR_EL0(25),
1130 PMU_PMEVCNTR_EL0(26),
1131 PMU_PMEVCNTR_EL0(27),
1132 PMU_PMEVCNTR_EL0(28),
1133 PMU_PMEVCNTR_EL0(29),
1134 PMU_PMEVCNTR_EL0(30),
9feb21ac
SZ		 1135 /* PMEVTYPERn_EL0 */
1136 PMU_PMEVTYPER_EL0(0),
1137 PMU_PMEVTYPER_EL0(1),
1138 PMU_PMEVTYPER_EL0(2),
1139 PMU_PMEVTYPER_EL0(3),
1140 PMU_PMEVTYPER_EL0(4),
1141 PMU_PMEVTYPER_EL0(5),
1142 PMU_PMEVTYPER_EL0(6),
1143 PMU_PMEVTYPER_EL0(7),
1144 PMU_PMEVTYPER_EL0(8),
1145 PMU_PMEVTYPER_EL0(9),
1146 PMU_PMEVTYPER_EL0(10),
1147 PMU_PMEVTYPER_EL0(11),
1148 PMU_PMEVTYPER_EL0(12),
1149 PMU_PMEVTYPER_EL0(13),
1150 PMU_PMEVTYPER_EL0(14),
1151 PMU_PMEVTYPER_EL0(15),
1152 PMU_PMEVTYPER_EL0(16),
1153 PMU_PMEVTYPER_EL0(17),
1154 PMU_PMEVTYPER_EL0(18),
1155 PMU_PMEVTYPER_EL0(19),
1156 PMU_PMEVTYPER_EL0(20),
1157 PMU_PMEVTYPER_EL0(21),
1158 PMU_PMEVTYPER_EL0(22),
1159 PMU_PMEVTYPER_EL0(23),
1160 PMU_PMEVTYPER_EL0(24),
1161 PMU_PMEVTYPER_EL0(25),
1162 PMU_PMEVTYPER_EL0(26),
1163 PMU_PMEVTYPER_EL0(27),
1164 PMU_PMEVTYPER_EL0(28),
1165 PMU_PMEVTYPER_EL0(29),
1166 PMU_PMEVTYPER_EL0(30),
1167 /* PMCCFILTR_EL0
1168 * This register resets as unknown in 64bit mode while it resets as zero
1169 * in 32bit mode. Here we choose to reset it as zero for consistency.
1170 */
1171 { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b1111), Op2(0b111),
1172 access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 },
051ff581 1173
62a89c44
MZ		 1174 /* DACR32_EL2 */
1175 { Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000),
1176 NULL, reset_unknown, DACR32_EL2 },
1177 /* IFSR32_EL2 */
1178 { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0000), Op2(0b001),
1179 NULL, reset_unknown, IFSR32_EL2 },
1180 /* FPEXC32_EL2 */
1181 { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0011), Op2(0b000),
1182 NULL, reset_val, FPEXC32_EL2, 0x70 },
1183};
1184
bdfb4b38 1185static bool trap_dbgidr(struct kvm_vcpu *vcpu,
3fec037d 1186 struct sys_reg_params *p,
bdfb4b38
MZ		 1187 const struct sys_reg_desc *r)
1188{
1189 if (p->is_write) {
1190 return ignore_write(vcpu, p);
1191 } else {
4db8e5ea
SP		 1192 u64 dfr = read_system_reg(SYS_ID_AA64DFR0_EL1);
1193 u64 pfr = read_system_reg(SYS_ID_AA64PFR0_EL1);
28c5dcb2 1194 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
bdfb4b38 1195
2ec5be3d
PF		 1196 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
1197 (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
1198 (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20)
1199 | (6 << 16) | (el3 << 14) | (el3 << 12));
bdfb4b38
MZ		 1200 return true;
1201 }
1202}
1203
1204static bool trap_debug32(struct kvm_vcpu *vcpu,
3fec037d 1205 struct sys_reg_params *p,
bdfb4b38
MZ		 1206 const struct sys_reg_desc *r)
1207{
1208 if (p->is_write) {
2ec5be3d 1209 vcpu_cp14(vcpu, r->reg) = p->regval;
bdfb4b38
MZ		 1210 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
1211 } else {
2ec5be3d 1212 p->regval = vcpu_cp14(vcpu, r->reg);
bdfb4b38
MZ		 1213 }
1214
1215 return true;
1216}
1217
84e690bf
AB		 1218/* AArch32 debug register mappings
1219 *
1220 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
1221 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
1222 *
1223 * All control registers and watchpoint value registers are mapped to
1224 * the lower 32 bits of their AArch64 equivalents. We share the trap
1225 * handlers with the above AArch64 code which checks what mode the
1226 * system is in.
1227 */
1228
281243cb
MZ		 1229static bool trap_xvr(struct kvm_vcpu *vcpu,
1230 struct sys_reg_params *p,
1231 const struct sys_reg_desc *rd)
84e690bf
AB		 1232{
1233 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
1234
1235 if (p->is_write) {
1236 u64 val = *dbg_reg;
1237
1238 val &= 0xffffffffUL;
2ec5be3d 1239 val |= p->regval << 32;
84e690bf
AB		 1240 *dbg_reg = val;
1241
1242 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
1243 } else {
2ec5be3d 1244 p->regval = *dbg_reg >> 32;
84e690bf
AB		 1245 }
1246
eef8c85a
AB		 1247 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
1248
84e690bf
AB		 1249 return true;
1250}
1251
1252#define DBG_BCR_BVR_WCR_WVR(n) \
1253 /* DBGBVRn */ \
1254 { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
1255 /* DBGBCRn */ \
1256 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
1257 /* DBGWVRn */ \
1258 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
1259 /* DBGWCRn */ \
1260 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1261
1262#define DBGBXVR(n) \
1263 { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n }
bdfb4b38
MZ		 1264
1265/*
1266 * Trapped cp14 registers. We generally ignore most of the external
1267 * debug, on the principle that they don't really make sense to a
84e690bf 1268 * guest. Revisit this one day, would this principle change.
bdfb4b38 1269 */
72564016 1270static const struct sys_reg_desc cp14_regs[] = {
bdfb4b38
MZ		 1271 /* DBGIDR */
1272 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
1273 /* DBGDTRRXext */
1274 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1275
1276 DBG_BCR_BVR_WCR_WVR(0),
1277 /* DBGDSCRint */
1278 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1279 DBG_BCR_BVR_WCR_WVR(1),
1280 /* DBGDCCINT */
1281 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 },
1282 /* DBGDSCRext */
1283 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 },
1284 DBG_BCR_BVR_WCR_WVR(2),
1285 /* DBGDTR[RT]Xint */
1286 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1287 /* DBGDTR[RT]Xext */
1288 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1289 DBG_BCR_BVR_WCR_WVR(3),
1290 DBG_BCR_BVR_WCR_WVR(4),
1291 DBG_BCR_BVR_WCR_WVR(5),
1292 /* DBGWFAR */
1293 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1294 /* DBGOSECCR */
1295 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1296 DBG_BCR_BVR_WCR_WVR(6),
1297 /* DBGVCR */
1298 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 },
1299 DBG_BCR_BVR_WCR_WVR(7),
1300 DBG_BCR_BVR_WCR_WVR(8),
1301 DBG_BCR_BVR_WCR_WVR(9),
1302 DBG_BCR_BVR_WCR_WVR(10),
1303 DBG_BCR_BVR_WCR_WVR(11),
1304 DBG_BCR_BVR_WCR_WVR(12),
1305 DBG_BCR_BVR_WCR_WVR(13),
1306 DBG_BCR_BVR_WCR_WVR(14),
1307 DBG_BCR_BVR_WCR_WVR(15),
1308
1309 /* DBGDRAR (32bit) */
1310 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1311
1312 DBGBXVR(0),
1313 /* DBGOSLAR */
1314 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
1315 DBGBXVR(1),
1316 /* DBGOSLSR */
1317 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
1318 DBGBXVR(2),
1319 DBGBXVR(3),
1320 /* DBGOSDLR */
1321 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1322 DBGBXVR(4),
1323 /* DBGPRCR */
1324 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1325 DBGBXVR(5),
1326 DBGBXVR(6),
1327 DBGBXVR(7),
1328 DBGBXVR(8),
1329 DBGBXVR(9),
1330 DBGBXVR(10),
1331 DBGBXVR(11),
1332 DBGBXVR(12),
1333 DBGBXVR(13),
1334 DBGBXVR(14),
1335 DBGBXVR(15),
1336
1337 /* DBGDSAR (32bit) */
1338 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1339
1340 /* DBGDEVID2 */
1341 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1342 /* DBGDEVID1 */
1343 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1344 /* DBGDEVID */
1345 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1346 /* DBGCLAIMSET */
1347 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1348 /* DBGCLAIMCLR */
1349 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1350 /* DBGAUTHSTATUS */
1351 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
72564016
MZ		 1352};
1353
a9866ba0
MZ		 1354/* Trapped cp14 64bit registers */
1355static const struct sys_reg_desc cp14_64_regs[] = {
bdfb4b38
MZ		 1356 /* DBGDRAR (64bit) */
1357 { Op1( 0), CRm( 1), .access = trap_raz_wi },
1358
1359 /* DBGDSAR (64bit) */
1360 { Op1( 0), CRm( 2), .access = trap_raz_wi },
a9866ba0
MZ		 1361};
1362
051ff581
SZ		 1363/* Macro to expand the PMEVCNTRn register */
1364#define PMU_PMEVCNTR(n) \
1365 /* PMEVCNTRn */ \
1366 { Op1(0), CRn(0b1110), \
1367 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1368 access_pmu_evcntr }
1369
9feb21ac
SZ		 1370/* Macro to expand the PMEVTYPERn register */
1371#define PMU_PMEVTYPER(n) \
1372 /* PMEVTYPERn */ \
1373 { Op1(0), CRn(0b1110), \
1374 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1375 access_pmu_evtyper }
1376
4d44923b
MZ		 1377/*
1378 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
1379 * depending on the way they are accessed (as a 32bit or a 64bit
1380 * register).
1381 */
62a89c44 1382static const struct sys_reg_desc cp15_regs[] = {
6d52f35a
AP		 1383 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
1384
3c1e7165 1385 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
4d44923b
MZ		 1386 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1387 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
1388 { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
1389 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
1390 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
1391 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
1392 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
1393 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
1394 { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
1395 { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
1396
62a89c44
MZ		 1397 /*
1398 * DC{C,I,CI}SW operations:
1399 */
1400 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
1401 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
1402 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
4d44923b 1403
7609c125 1404 /* PMU */
ab946834 1405 { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
96b0eebc
SZ		 1406 { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
1407 { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
76d883c4 1408 { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
7a0adc70 1409 { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
3965c3ce 1410 { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
a86b5505
SZ		 1411 { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
1412 { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
051ff581 1413 { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
9feb21ac 1414 { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
051ff581 1415 { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
d692b8ad 1416 { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr },
9db52c78
SZ		 1417 { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
1418 { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
76d883c4 1419 { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
4d44923b
MZ		 1420
1421 { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
1422 { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
1423 { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
1424 { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
db7dedd0
CD		 1425
1426 /* ICC_SRE */
f7f6f2d9 1427 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
db7dedd0 1428
4d44923b 1429 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
051ff581
SZ		 1430
1431 /* PMEVCNTRn */
1432 PMU_PMEVCNTR(0),
1433 PMU_PMEVCNTR(1),
1434 PMU_PMEVCNTR(2),
1435 PMU_PMEVCNTR(3),
1436 PMU_PMEVCNTR(4),
1437 PMU_PMEVCNTR(5),
1438 PMU_PMEVCNTR(6),
1439 PMU_PMEVCNTR(7),
1440 PMU_PMEVCNTR(8),
1441 PMU_PMEVCNTR(9),
1442 PMU_PMEVCNTR(10),
1443 PMU_PMEVCNTR(11),
1444 PMU_PMEVCNTR(12),
1445 PMU_PMEVCNTR(13),
1446 PMU_PMEVCNTR(14),
1447 PMU_PMEVCNTR(15),
1448 PMU_PMEVCNTR(16),
1449 PMU_PMEVCNTR(17),
1450 PMU_PMEVCNTR(18),
1451 PMU_PMEVCNTR(19),
1452 PMU_PMEVCNTR(20),
1453 PMU_PMEVCNTR(21),
1454 PMU_PMEVCNTR(22),
1455 PMU_PMEVCNTR(23),
1456 PMU_PMEVCNTR(24),
1457 PMU_PMEVCNTR(25),
1458 PMU_PMEVCNTR(26),
1459 PMU_PMEVCNTR(27),
1460 PMU_PMEVCNTR(28),
1461 PMU_PMEVCNTR(29),
1462 PMU_PMEVCNTR(30),
9feb21ac
SZ		 1463 /* PMEVTYPERn */
1464 PMU_PMEVTYPER(0),
1465 PMU_PMEVTYPER(1),
1466 PMU_PMEVTYPER(2),
1467 PMU_PMEVTYPER(3),
1468 PMU_PMEVTYPER(4),
1469 PMU_PMEVTYPER(5),
1470 PMU_PMEVTYPER(6),
1471 PMU_PMEVTYPER(7),
1472 PMU_PMEVTYPER(8),
1473 PMU_PMEVTYPER(9),
1474 PMU_PMEVTYPER(10),
1475 PMU_PMEVTYPER(11),
1476 PMU_PMEVTYPER(12),
1477 PMU_PMEVTYPER(13),
1478 PMU_PMEVTYPER(14),
1479 PMU_PMEVTYPER(15),
1480 PMU_PMEVTYPER(16),
1481 PMU_PMEVTYPER(17),
1482 PMU_PMEVTYPER(18),
1483 PMU_PMEVTYPER(19),
1484 PMU_PMEVTYPER(20),
1485 PMU_PMEVTYPER(21),
1486 PMU_PMEVTYPER(22),
1487 PMU_PMEVTYPER(23),
1488 PMU_PMEVTYPER(24),
1489 PMU_PMEVTYPER(25),
1490 PMU_PMEVTYPER(26),
1491 PMU_PMEVTYPER(27),
1492 PMU_PMEVTYPER(28),
1493 PMU_PMEVTYPER(29),
1494 PMU_PMEVTYPER(30),
1495 /* PMCCFILTR */
1496 { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
a9866ba0
MZ		 1497};
1498
1499static const struct sys_reg_desc cp15_64_regs[] = {
1500 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
051ff581 1501 { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
6d52f35a 1502 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
4d44923b 1503 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
7c8c5e6a
MZ		 1504};
1505
1506/* Target specific emulation tables */
1507static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS];
1508
1509void kvm_register_target_sys_reg_table(unsigned int target,
1510 struct kvm_sys_reg_target_table *table)
1511{
1512 target_tables[target] = table;
1513}
1514
1515/* Get specific register table for this target. */
62a89c44
MZ		 1516static const struct sys_reg_desc *get_target_table(unsigned target,
1517 bool mode_is_64,
1518 size_t *num)
7c8c5e6a
MZ		 1519{
1520 struct kvm_sys_reg_target_table *table;
1521
1522 table = target_tables[target];
62a89c44
MZ		 1523 if (mode_is_64) {
1524 *num = table->table64.num;
1525 return table->table64.table;
1526 } else {
1527 *num = table->table32.num;
1528 return table->table32.table;
1529 }
7c8c5e6a
MZ		 1530}
1531
623eefa8
MZ		 1532#define reg_to_match_value(x) \
1533 ({ \
1534 unsigned long val; \
1535 val = (x)->Op0 << 14; \
1536 val |= (x)->Op1 << 11; \
1537 val |= (x)->CRn << 7; \
1538 val |= (x)->CRm << 3; \
1539 val |= (x)->Op2; \
1540 val; \
1541 })
1542
1543static int match_sys_reg(const void *key, const void *elt)
1544{
1545 const unsigned long pval = (unsigned long)key;
1546 const struct sys_reg_desc *r = elt;
1547
1548 return pval - reg_to_match_value(r);
1549}
1550
7c8c5e6a
MZ		 1551static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
1552 const struct sys_reg_desc table[],
1553 unsigned int num)
1554{
623eefa8
MZ		 1555 unsigned long pval = reg_to_match_value(params);
1556
1557 return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
7c8c5e6a
MZ		 1558}
1559
62a89c44
MZ		 1560int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
1561{
1562 kvm_inject_undefined(vcpu);
1563 return 1;
1564}
1565
72564016
MZ		 1566/*
1567 * emulate_cp -- tries to match a sys_reg access in a handling table, and
1568 * call the corresponding trap handler.
1569 *
1570 * @params: pointer to the descriptor of the access
1571 * @table: array of trap descriptors
1572 * @num: size of the trap descriptor array
1573 *
1574 * Return 0 if the access has been handled, and -1 if not.
1575 */
1576static int emulate_cp(struct kvm_vcpu *vcpu,
3fec037d 1577 struct sys_reg_params *params,
72564016
MZ		 1578 const struct sys_reg_desc *table,
1579 size_t num)
62a89c44 1580{
72564016 1581 const struct sys_reg_desc *r;
62a89c44 1582
72564016
MZ		 1583 if (!table)
1584 return -1; /* Not handled */
62a89c44 1585
62a89c44 1586 r = find_reg(params, table, num);
62a89c44 1587
72564016 1588 if (r) {
62a89c44
MZ		 1589 /*
1590 * Not having an accessor means that we have
1591 * configured a trap that we don't know how to
1592 * handle. This certainly qualifies as a gross bug
1593 * that should be fixed right away.
1594 */
1595 BUG_ON(!r->access);
1596
1597 if (likely(r->access(vcpu, params, r))) {
1598 /* Skip instruction, since it was emulated */
1599 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
6327f35a
SZ		 1600 /* Handled */
1601 return 0;
62a89c44 1602 }
72564016
MZ		 1603 }
1604
1605 /* Not handled */
1606 return -1;
1607}
1608
1609static void unhandled_cp_access(struct kvm_vcpu *vcpu,
1610 struct sys_reg_params *params)
1611{
1612 u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
40c4f8d2 1613 int cp = -1;
72564016
MZ		 1614
1615 switch(hsr_ec) {
c6d01a94
MR		 1616 case ESR_ELx_EC_CP15_32:
1617 case ESR_ELx_EC_CP15_64:
72564016
MZ		 1618 cp = 15;
1619 break;
c6d01a94
MR		 1620 case ESR_ELx_EC_CP14_MR:
1621 case ESR_ELx_EC_CP14_64:
72564016
MZ		 1622 cp = 14;
1623 break;
1624 default:
40c4f8d2 1625 WARN_ON(1);
62a89c44
MZ		 1626 }
1627
72564016
MZ		 1628 kvm_err("Unsupported guest CP%d access at: %08lx\n",
1629 cp, *vcpu_pc(vcpu));
62a89c44
MZ		 1630 print_sys_reg_instr(params);
1631 kvm_inject_undefined(vcpu);
1632}
1633
1634/**
7769db90 1635 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
62a89c44
MZ		 1636 * @vcpu: The VCPU pointer
1637 * @run: The kvm_run struct
1638 */
72564016
MZ		 1639static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
1640 const struct sys_reg_desc *global,
1641 size_t nr_global,
1642 const struct sys_reg_desc *target_specific,
1643 size_t nr_specific)
62a89c44
MZ		 1644{
1645 struct sys_reg_params params;
1646 u32 hsr = kvm_vcpu_get_hsr(vcpu);
2ec5be3d 1647 int Rt = (hsr >> 5) & 0xf;
62a89c44
MZ		 1648 int Rt2 = (hsr >> 10) & 0xf;
1649
2072d29c
MZ		 1650 params.is_aarch32 = true;
1651 params.is_32bit = false;
62a89c44 1652 params.CRm = (hsr >> 1) & 0xf;
62a89c44
MZ		 1653 params.is_write = ((hsr & 1) == 0);
1654
1655 params.Op0 = 0;
1656 params.Op1 = (hsr >> 16) & 0xf;
1657 params.Op2 = 0;
1658 params.CRn = 0;
1659
1660 /*
2ec5be3d 1661 * Make a 64-bit value out of Rt and Rt2. As we use the same trap
62a89c44
MZ		 1662 * backends between AArch32 and AArch64, we get away with it.
1663 */
1664 if (params.is_write) {
2ec5be3d
PF		 1665 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
1666 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
62a89c44
MZ		 1667 }
1668
72564016
MZ		 1669 if (!emulate_cp(vcpu, &params, target_specific, nr_specific))
1670 goto out;
1671 if (!emulate_cp(vcpu, &params, global, nr_global))
1672 goto out;
1673
1674 unhandled_cp_access(vcpu, &params);
62a89c44 1675
72564016 1676out:
2ec5be3d 1677 /* Split up the value between registers for the read side */
62a89c44 1678 if (!params.is_write) {
2ec5be3d
PF		 1679 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
1680 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
62a89c44
MZ		 1681 }
1682
1683 return 1;
1684}
1685
1686/**
7769db90 1687 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
62a89c44
MZ		 1688 * @vcpu: The VCPU pointer
1689 * @run: The kvm_run struct
1690 */
72564016
MZ		 1691static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
1692 const struct sys_reg_desc *global,
1693 size_t nr_global,
1694 const struct sys_reg_desc *target_specific,
1695 size_t nr_specific)
62a89c44
MZ		 1696{
1697 struct sys_reg_params params;
1698 u32 hsr = kvm_vcpu_get_hsr(vcpu);
2ec5be3d 1699 int Rt = (hsr >> 5) & 0xf;
62a89c44 1700
2072d29c
MZ		 1701 params.is_aarch32 = true;
1702 params.is_32bit = true;
62a89c44 1703 params.CRm = (hsr >> 1) & 0xf;
2ec5be3d 1704 params.regval = vcpu_get_reg(vcpu, Rt);
62a89c44
MZ		 1705 params.is_write = ((hsr & 1) == 0);
1706 params.CRn = (hsr >> 10) & 0xf;
1707 params.Op0 = 0;
1708 params.Op1 = (hsr >> 14) & 0x7;
1709 params.Op2 = (hsr >> 17) & 0x7;
1710
2ec5be3d
PF		 1711 if (!emulate_cp(vcpu, &params, target_specific, nr_specific) ||
1712 !emulate_cp(vcpu, &params, global, nr_global)) {
1713 if (!params.is_write)
1714 vcpu_set_reg(vcpu, Rt, params.regval);
72564016 1715 return 1;
2ec5be3d 1716 }
72564016
MZ		 1717
1718 unhandled_cp_access(vcpu, &params);
62a89c44
MZ		 1719 return 1;
1720}
1721
72564016
MZ		 1722int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
1723{
1724 const struct sys_reg_desc *target_specific;
1725 size_t num;
1726
1727 target_specific = get_target_table(vcpu->arch.target, false, &num);
1728 return kvm_handle_cp_64(vcpu,
a9866ba0 1729 cp15_64_regs, ARRAY_SIZE(cp15_64_regs),
72564016
MZ		 1730 target_specific, num);
1731}
1732
1733int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
1734{
1735 const struct sys_reg_desc *target_specific;
1736 size_t num;
1737
1738 target_specific = get_target_table(vcpu->arch.target, false, &num);
1739 return kvm_handle_cp_32(vcpu,
1740 cp15_regs, ARRAY_SIZE(cp15_regs),
1741 target_specific, num);
1742}
1743
1744int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
1745{
1746 return kvm_handle_cp_64(vcpu,
a9866ba0 1747 cp14_64_regs, ARRAY_SIZE(cp14_64_regs),
72564016
MZ		 1748 NULL, 0);
1749}
1750
1751int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
1752{
1753 return kvm_handle_cp_32(vcpu,
1754 cp14_regs, ARRAY_SIZE(cp14_regs),
1755 NULL, 0);
1756}
1757
7c8c5e6a 1758static int emulate_sys_reg(struct kvm_vcpu *vcpu,
3fec037d 1759 struct sys_reg_params *params)
7c8c5e6a
MZ		 1760{
1761 size_t num;
1762 const struct sys_reg_desc *table, *r;
1763
62a89c44 1764 table = get_target_table(vcpu->arch.target, true, &num);
7c8c5e6a
MZ		 1765
1766 /* Search target-specific then generic table. */
1767 r = find_reg(params, table, num);
1768 if (!r)
1769 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1770
1771 if (likely(r)) {
1772 /*
1773 * Not having an accessor means that we have
1774 * configured a trap that we don't know how to
1775 * handle. This certainly qualifies as a gross bug
1776 * that should be fixed right away.
1777 */
1778 BUG_ON(!r->access);
1779
1780 if (likely(r->access(vcpu, params, r))) {
1781 /* Skip instruction, since it was emulated */
1782 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
1783 return 1;
1784 }
1785 /* If access function fails, it should complain. */
1786 } else {
1787 kvm_err("Unsupported guest sys_reg access at: %lx\n",
1788 *vcpu_pc(vcpu));
1789 print_sys_reg_instr(params);
1790 }
1791 kvm_inject_undefined(vcpu);
1792 return 1;
1793}
1794
1795static void reset_sys_reg_descs(struct kvm_vcpu *vcpu,
1796 const struct sys_reg_desc *table, size_t num)
1797{
1798 unsigned long i;
1799
1800 for (i = 0; i < num; i++)
1801 if (table[i].reset)
1802 table[i].reset(vcpu, &table[i]);
1803}
1804
1805/**
1806 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
1807 * @vcpu: The VCPU pointer
1808 * @run: The kvm_run struct
1809 */
1810int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run)
1811{
1812 struct sys_reg_params params;
1813 unsigned long esr = kvm_vcpu_get_hsr(vcpu);
2ec5be3d
PF		 1814 int Rt = (esr >> 5) & 0x1f;
1815 int ret;
7c8c5e6a 1816
eef8c85a
AB		 1817 trace_kvm_handle_sys_reg(esr);
1818
2072d29c
MZ		 1819 params.is_aarch32 = false;
1820 params.is_32bit = false;
7c8c5e6a
MZ		 1821 params.Op0 = (esr >> 20) & 3;
1822 params.Op1 = (esr >> 14) & 0x7;
1823 params.CRn = (esr >> 10) & 0xf;
1824 params.CRm = (esr >> 1) & 0xf;
1825 params.Op2 = (esr >> 17) & 0x7;
2ec5be3d 1826 params.regval = vcpu_get_reg(vcpu, Rt);
7c8c5e6a
MZ		 1827 params.is_write = !(esr & 1);
1828
2ec5be3d
PF		 1829 ret = emulate_sys_reg(vcpu, &params);
1830
1831 if (!params.is_write)
1832 vcpu_set_reg(vcpu, Rt, params.regval);
1833 return ret;
7c8c5e6a
MZ		 1834}
1835
1836/******************************************************************************
1837 * Userspace API
1838 *****************************************************************************/
1839
1840static bool index_to_params(u64 id, struct sys_reg_params *params)
1841{
1842 switch (id & KVM_REG_SIZE_MASK) {
1843 case KVM_REG_SIZE_U64:
1844 /* Any unused index bits means it's not valid. */
1845 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
1846 | KVM_REG_ARM_COPROC_MASK
1847 | KVM_REG_ARM64_SYSREG_OP0_MASK
1848 | KVM_REG_ARM64_SYSREG_OP1_MASK
1849 | KVM_REG_ARM64_SYSREG_CRN_MASK
1850 | KVM_REG_ARM64_SYSREG_CRM_MASK
1851 | KVM_REG_ARM64_SYSREG_OP2_MASK))
1852 return false;
1853 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
1854 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
1855 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
1856 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
1857 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
1858 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
1859 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
1860 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
1861 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
1862 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
1863 return true;
1864 default:
1865 return false;
1866 }
1867}
1868
4b927b94
VK		 1869const struct sys_reg_desc *find_reg_by_id(u64 id,
1870 struct sys_reg_params *params,
1871 const struct sys_reg_desc table[],
1872 unsigned int num)
1873{
1874 if (!index_to_params(id, params))
1875 return NULL;
1876
1877 return find_reg(params, table, num);
1878}
1879
7c8c5e6a
MZ		 1880/* Decode an index value, and find the sys_reg_desc entry. */
1881static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
1882 u64 id)
1883{
1884 size_t num;
1885 const struct sys_reg_desc *table, *r;
1886 struct sys_reg_params params;
1887
1888 /* We only do sys_reg for now. */
1889 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
1890 return NULL;
1891
62a89c44 1892 table = get_target_table(vcpu->arch.target, true, &num);
4b927b94 1893 r = find_reg_by_id(id, &params, table, num);
7c8c5e6a
MZ		 1894 if (!r)
1895 r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1896
1897 /* Not saved in the sys_reg array? */
1898 if (r && !r->reg)
1899 r = NULL;
1900
1901 return r;
1902}
1903
1904/*
1905 * These are the invariant sys_reg registers: we let the guest see the
1906 * host versions of these, so they're part of the guest state.
1907 *
1908 * A future CPU may provide a mechanism to present different values to
1909 * the guest, or a future kvm may trap them.
1910 */
1911
1912#define FUNCTION_INVARIANT(reg) \
1913 static void get_##reg(struct kvm_vcpu *v, \
1914 const struct sys_reg_desc *r) \
1915 { \
1f3d8699 1916 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \
7c8c5e6a
MZ		 1917 }
1918
1919FUNCTION_INVARIANT(midr_el1)
1920FUNCTION_INVARIANT(ctr_el0)
1921FUNCTION_INVARIANT(revidr_el1)
1922FUNCTION_INVARIANT(id_pfr0_el1)
1923FUNCTION_INVARIANT(id_pfr1_el1)
1924FUNCTION_INVARIANT(id_dfr0_el1)
1925FUNCTION_INVARIANT(id_afr0_el1)
1926FUNCTION_INVARIANT(id_mmfr0_el1)
1927FUNCTION_INVARIANT(id_mmfr1_el1)
1928FUNCTION_INVARIANT(id_mmfr2_el1)
1929FUNCTION_INVARIANT(id_mmfr3_el1)
1930FUNCTION_INVARIANT(id_isar0_el1)
1931FUNCTION_INVARIANT(id_isar1_el1)
1932FUNCTION_INVARIANT(id_isar2_el1)
1933FUNCTION_INVARIANT(id_isar3_el1)
1934FUNCTION_INVARIANT(id_isar4_el1)
1935FUNCTION_INVARIANT(id_isar5_el1)
1936FUNCTION_INVARIANT(clidr_el1)
1937FUNCTION_INVARIANT(aidr_el1)
1938
1939/* ->val is filled in by kvm_sys_reg_table_init() */
1940static struct sys_reg_desc invariant_sys_regs[] = {
1941 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b000),
1942 NULL, get_midr_el1 },
1943 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b110),
1944 NULL, get_revidr_el1 },
1945 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b000),
1946 NULL, get_id_pfr0_el1 },
1947 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b001),
1948 NULL, get_id_pfr1_el1 },
1949 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b010),
1950 NULL, get_id_dfr0_el1 },
1951 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b011),
1952 NULL, get_id_afr0_el1 },
1953 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b100),
1954 NULL, get_id_mmfr0_el1 },
1955 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b101),
1956 NULL, get_id_mmfr1_el1 },
1957 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b110),
1958 NULL, get_id_mmfr2_el1 },
1959 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b111),
1960 NULL, get_id_mmfr3_el1 },
1961 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
1962 NULL, get_id_isar0_el1 },
1963 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b001),
1964 NULL, get_id_isar1_el1 },
1965 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
1966 NULL, get_id_isar2_el1 },
1967 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b011),
1968 NULL, get_id_isar3_el1 },
1969 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b100),
1970 NULL, get_id_isar4_el1 },
1971 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b101),
1972 NULL, get_id_isar5_el1 },
1973 { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b001),
1974 NULL, get_clidr_el1 },
1975 { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b111),
1976 NULL, get_aidr_el1 },
1977 { Op0(0b11), Op1(0b011), CRn(0b0000), CRm(0b0000), Op2(0b001),
1978 NULL, get_ctr_el0 },
1979};
1980
26c99af1 1981static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
7c8c5e6a 1982{
7c8c5e6a
MZ		 1983 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
1984 return -EFAULT;
1985 return 0;
1986}
1987
26c99af1 1988static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
7c8c5e6a 1989{
7c8c5e6a
MZ		 1990 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
1991 return -EFAULT;
1992 return 0;
1993}
1994
1995static int get_invariant_sys_reg(u64 id, void __user *uaddr)
1996{
1997 struct sys_reg_params params;
1998 const struct sys_reg_desc *r;
1999
4b927b94
VK		 2000 r = find_reg_by_id(id, &params, invariant_sys_regs,
2001 ARRAY_SIZE(invariant_sys_regs));
7c8c5e6a
MZ		 2002 if (!r)
2003 return -ENOENT;
2004
2005 return reg_to_user(uaddr, &r->val, id);
2006}
2007
2008static int set_invariant_sys_reg(u64 id, void __user *uaddr)
2009{
2010 struct sys_reg_params params;
2011 const struct sys_reg_desc *r;
2012 int err;
2013 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
2014
4b927b94
VK		 2015 r = find_reg_by_id(id, &params, invariant_sys_regs,
2016 ARRAY_SIZE(invariant_sys_regs));
7c8c5e6a
MZ		 2017 if (!r)
2018 return -ENOENT;
2019
2020 err = reg_from_user(&val, uaddr, id);
2021 if (err)
2022 return err;
2023
2024 /* This is what we mean by invariant: you can't change it. */
2025 if (r->val != val)
2026 return -EINVAL;
2027
2028 return 0;
2029}
2030
2031static bool is_valid_cache(u32 val)
2032{
2033 u32 level, ctype;
2034
2035 if (val >= CSSELR_MAX)
18d45766 2036 return false;
7c8c5e6a
MZ		 2037
2038 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
2039 level = (val >> 1);
2040 ctype = (cache_levels >> (level * 3)) & 7;
2041
2042 switch (ctype) {
2043 case 0: /* No cache */
2044 return false;
2045 case 1: /* Instruction cache only */
2046 return (val & 1);
2047 case 2: /* Data cache only */
2048 case 4: /* Unified cache */
2049 return !(val & 1);
2050 case 3: /* Separate instruction and data caches */
2051 return true;
2052 default: /* Reserved: we can't know instruction or data. */
2053 return false;
2054 }
2055}
2056
2057static int demux_c15_get(u64 id, void __user *uaddr)
2058{
2059 u32 val;
2060 u32 __user *uval = uaddr;
2061
2062 /* Fail if we have unknown bits set. */
2063 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2064 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2065 return -ENOENT;
2066
2067 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2068 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2069 if (KVM_REG_SIZE(id) != 4)
2070 return -ENOENT;
2071 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2072 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2073 if (!is_valid_cache(val))
2074 return -ENOENT;
2075
2076 return put_user(get_ccsidr(val), uval);
2077 default:
2078 return -ENOENT;
2079 }
2080}
2081
2082static int demux_c15_set(u64 id, void __user *uaddr)
2083{
2084 u32 val, newval;
2085 u32 __user *uval = uaddr;
2086
2087 /* Fail if we have unknown bits set. */
2088 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2089 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2090 return -ENOENT;
2091
2092 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2093 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2094 if (KVM_REG_SIZE(id) != 4)
2095 return -ENOENT;
2096 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2097 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2098 if (!is_valid_cache(val))
2099 return -ENOENT;
2100
2101 if (get_user(newval, uval))
2102 return -EFAULT;
2103
2104 /* This is also invariant: you can't change it. */
2105 if (newval != get_ccsidr(val))
2106 return -EINVAL;
2107 return 0;
2108 default:
2109 return -ENOENT;
2110 }
2111}
2112
2113int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2114{
2115 const struct sys_reg_desc *r;
2116 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2117
2118 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2119 return demux_c15_get(reg->id, uaddr);
2120
2121 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2122 return -ENOENT;
2123
2124 r = index_to_sys_reg_desc(vcpu, reg->id);
2125 if (!r)
2126 return get_invariant_sys_reg(reg->id, uaddr);
2127
84e690bf
AB		 2128 if (r->get_user)
2129 return (r->get_user)(vcpu, r, reg, uaddr);
2130
7c8c5e6a
MZ		 2131 return reg_to_user(uaddr, &vcpu_sys_reg(vcpu, r->reg), reg->id);
2132}
2133
2134int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2135{
2136 const struct sys_reg_desc *r;
2137 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2138
2139 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2140 return demux_c15_set(reg->id, uaddr);
2141
2142 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2143 return -ENOENT;
2144
2145 r = index_to_sys_reg_desc(vcpu, reg->id);
2146 if (!r)
2147 return set_invariant_sys_reg(reg->id, uaddr);
2148
84e690bf
AB		 2149 if (r->set_user)
2150 return (r->set_user)(vcpu, r, reg, uaddr);
2151
7c8c5e6a
MZ		 2152 return reg_from_user(&vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
2153}
2154
2155static unsigned int num_demux_regs(void)
2156{
2157 unsigned int i, count = 0;
2158
2159 for (i = 0; i < CSSELR_MAX; i++)
2160 if (is_valid_cache(i))
2161 count++;
2162
2163 return count;
2164}
2165
2166static int write_demux_regids(u64 __user *uindices)
2167{
efd48cea 2168 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
7c8c5e6a
MZ		 2169 unsigned int i;
2170
2171 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
2172 for (i = 0; i < CSSELR_MAX; i++) {
2173 if (!is_valid_cache(i))
2174 continue;
2175 if (put_user(val | i, uindices))
2176 return -EFAULT;
2177 uindices++;
2178 }
2179 return 0;
2180}
2181
2182static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
2183{
2184 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
2185 KVM_REG_ARM64_SYSREG |
2186 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
2187 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
2188 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
2189 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
2190 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
2191}
2192
2193static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
2194{
2195 if (!*uind)
2196 return true;
2197
2198 if (put_user(sys_reg_to_index(reg), *uind))
2199 return false;
2200
2201 (*uind)++;
2202 return true;
2203}
2204
2205/* Assumed ordered tables, see kvm_sys_reg_table_init. */
2206static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
2207{
2208 const struct sys_reg_desc *i1, *i2, *end1, *end2;
2209 unsigned int total = 0;
2210 size_t num;
2211
2212 /* We check for duplicates here, to allow arch-specific overrides. */
62a89c44 2213 i1 = get_target_table(vcpu->arch.target, true, &num);
7c8c5e6a
MZ		 2214 end1 = i1 + num;
2215 i2 = sys_reg_descs;
2216 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
2217
2218 BUG_ON(i1 == end1 || i2 == end2);
2219
2220 /* Walk carefully, as both tables may refer to the same register. */
2221 while (i1 || i2) {
2222 int cmp = cmp_sys_reg(i1, i2);
2223 /* target-specific overrides generic entry. */
2224 if (cmp <= 0) {
2225 /* Ignore registers we trap but don't save. */
2226 if (i1->reg) {
2227 if (!copy_reg_to_user(i1, &uind))
2228 return -EFAULT;
2229 total++;
2230 }
2231 } else {
2232 /* Ignore registers we trap but don't save. */
2233 if (i2->reg) {
2234 if (!copy_reg_to_user(i2, &uind))
2235 return -EFAULT;
2236 total++;
2237 }
2238 }
2239
2240 if (cmp <= 0 && ++i1 == end1)
2241 i1 = NULL;
2242 if (cmp >= 0 && ++i2 == end2)
2243 i2 = NULL;
2244 }
2245 return total;
2246}
2247
2248unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
2249{
2250 return ARRAY_SIZE(invariant_sys_regs)
2251 + num_demux_regs()
2252 + walk_sys_regs(vcpu, (u64 __user *)NULL);
2253}
2254
2255int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
2256{
2257 unsigned int i;
2258 int err;
2259
2260 /* Then give them all the invariant registers' indices. */
2261 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
2262 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
2263 return -EFAULT;
2264 uindices++;
2265 }
2266
2267 err = walk_sys_regs(vcpu, uindices);
2268 if (err < 0)
2269 return err;
2270 uindices += err;
2271
2272 return write_demux_regids(uindices);
2273}
2274
e6a95517
MZ		 2275static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n)
2276{
2277 unsigned int i;
2278
2279 for (i = 1; i < n; i++) {
2280 if (cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2281 kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
2282 return 1;
2283 }
2284 }
2285
2286 return 0;
2287}
2288
7c8c5e6a
MZ		 2289void kvm_sys_reg_table_init(void)
2290{
2291 unsigned int i;
2292 struct sys_reg_desc clidr;
2293
2294 /* Make sure tables are unique and in order. */
e6a95517
MZ		 2295 BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs)));
2296 BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs)));
2297 BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs)));
2298 BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs)));
2299 BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs)));
2300 BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs)));
7c8c5e6a
MZ		 2301
2302 /* We abuse the reset function to overwrite the table itself. */
2303 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
2304 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
2305
2306 /*
2307 * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
2308 *
2309 * If software reads the Cache Type fields from Ctype1
2310 * upwards, once it has seen a value of 0b000, no caches
2311 * exist at further-out levels of the hierarchy. So, for
2312 * example, if Ctype3 is the first Cache Type field with a
2313 * value of 0b000, the values of Ctype4 to Ctype7 must be
2314 * ignored.
2315 */
2316 get_clidr_el1(NULL, &clidr); /* Ugly... */
2317 cache_levels = clidr.val;
2318 for (i = 0; i < 7; i++)
2319 if (((cache_levels >> (i*3)) & 7) == 0)
2320 break;
2321 /* Clear all higher bits. */
2322 cache_levels &= (1 << (i*3))-1;
2323}
2324
2325/**
2326 * kvm_reset_sys_regs - sets system registers to reset value
2327 * @vcpu: The VCPU pointer
2328 *
2329 * This function finds the right table above and sets the registers on the
2330 * virtual CPU struct to their architecturally defined reset values.
2331 */
2332void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
2333{
2334 size_t num;
2335 const struct sys_reg_desc *table;
2336
2337 /* Catch someone adding a register without putting in reset entry. */
2338 memset(&vcpu->arch.ctxt.sys_regs, 0x42, sizeof(vcpu->arch.ctxt.sys_regs));
2339
2340 /* Generic chip reset first (so target could override). */
2341 reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2342
62a89c44 2343 table = get_target_table(vcpu->arch.target, true, &num);
7c8c5e6a
MZ		 2344 reset_sys_reg_descs(vcpu, table, num);
2345
2346 for (num = 1; num < NR_SYS_REGS; num++)
2347 if (vcpu_sys_reg(vcpu, num) == 0x4242424242424242)
2348 panic("Didn't reset vcpu_sys_reg(%zi)", num);
2349}
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