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KVM: arm/arm64: vgic: Add distributor and redistributor access
[mirror_ubuntu-artful-kernel.git] / arch / arm64 / kvm / sys_regs.c
CommitLineData
7c8c5e6a
MZ		 1/*
2 * Copyright (C) 2012,2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * Derived from arch/arm/kvm/coproc.c:
6 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
7 * Authors: Rusty Russell <rusty@rustcorp.com.au>
8 * Christoffer Dall <c.dall@virtualopensystems.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License, version 2, as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
623eefa8 23#include <linux/bsearch.h>
7c8c5e6a 24#include <linux/kvm_host.h>
c6d01a94 25#include <linux/mm.h>
7c8c5e6a 26#include <linux/uaccess.h>
c6d01a94 27
7c8c5e6a
MZ		 28#include <asm/cacheflush.h>
29#include <asm/cputype.h>
0c557ed4 30#include <asm/debug-monitors.h>
c6d01a94
MR		 31#include <asm/esr.h>
32#include <asm/kvm_arm.h>
9d8415d6 33#include <asm/kvm_asm.h>
c6d01a94
MR		 34#include <asm/kvm_coproc.h>
35#include <asm/kvm_emulate.h>
36#include <asm/kvm_host.h>
37#include <asm/kvm_mmu.h>
ab946834 38#include <asm/perf_event.h>
1f3d8699 39#include <asm/sysreg.h>
c6d01a94 40
7c8c5e6a
MZ		 41#include <trace/events/kvm.h>
42
43#include "sys_regs.h"
44
eef8c85a
AB		 45#include "trace.h"
46
7c8c5e6a
MZ		 47/*
48 * All of this file is extremly similar to the ARM coproc.c, but the
49 * types are different. My gut feeling is that it should be pretty
50 * easy to merge, but that would be an ABI breakage -- again. VFP
51 * would also need to be abstracted.
62a89c44
MZ		 52 *
53 * For AArch32, we only take care of what is being trapped. Anything
54 * that has to do with init and userspace access has to go via the
55 * 64bit interface.
7c8c5e6a
MZ		 56 */
57
58/* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
59static u32 cache_levels;
60
61/* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
62#define CSSELR_MAX 12
63
64/* Which cache CCSIDR represents depends on CSSELR value. */
65static u32 get_ccsidr(u32 csselr)
66{
67 u32 ccsidr;
68
69 /* Make sure noone else changes CSSELR during this! */
70 local_irq_disable();
1f3d8699 71 write_sysreg(csselr, csselr_el1);
7c8c5e6a 72 isb();
1f3d8699 73 ccsidr = read_sysreg(ccsidr_el1);
7c8c5e6a
MZ		 74 local_irq_enable();
75
76 return ccsidr;
77}
78
3c1e7165
MZ		 79/*
80 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
81 */
7c8c5e6a 82static bool access_dcsw(struct kvm_vcpu *vcpu,
3fec037d 83 struct sys_reg_params *p,
7c8c5e6a
MZ		 84 const struct sys_reg_desc *r)
85{
7c8c5e6a
MZ		 86 if (!p->is_write)
87 return read_from_write_only(vcpu, p);
88
3c1e7165 89 kvm_set_way_flush(vcpu);
7c8c5e6a
MZ		 90 return true;
91}
92
4d44923b
MZ		 93/*
94 * Generic accessor for VM registers. Only called as long as HCR_TVM
3c1e7165
MZ		 95 * is set. If the guest enables the MMU, we stop trapping the VM
96 * sys_regs and leave it in complete control of the caches.
4d44923b
MZ		 97 */
98static bool access_vm_reg(struct kvm_vcpu *vcpu,
3fec037d 99 struct sys_reg_params *p,
4d44923b
MZ		 100 const struct sys_reg_desc *r)
101{
3c1e7165 102 bool was_enabled = vcpu_has_cache_enabled(vcpu);
4d44923b
MZ		 103
104 BUG_ON(!p->is_write);
105
dedf97e8 106 if (!p->is_aarch32) {
2ec5be3d 107 vcpu_sys_reg(vcpu, r->reg) = p->regval;
dedf97e8
MZ		 108 } else {
109 if (!p->is_32bit)
2ec5be3d
PF		 110 vcpu_cp15_64_high(vcpu, r->reg) = upper_32_bits(p->regval);
111 vcpu_cp15_64_low(vcpu, r->reg) = lower_32_bits(p->regval);
dedf97e8 112 }
f0a3eaff 113
3c1e7165 114 kvm_toggle_cache(vcpu, was_enabled);
4d44923b
MZ		 115 return true;
116}
117
6d52f35a
AP		 118/*
119 * Trap handler for the GICv3 SGI generation system register.
120 * Forward the request to the VGIC emulation.
121 * The cp15_64 code makes sure this automatically works
122 * for both AArch64 and AArch32 accesses.
123 */
124static bool access_gic_sgi(struct kvm_vcpu *vcpu,
3fec037d 125 struct sys_reg_params *p,
6d52f35a
AP		 126 const struct sys_reg_desc *r)
127{
6d52f35a
AP		 128 if (!p->is_write)
129 return read_from_write_only(vcpu, p);
130
2ec5be3d 131 vgic_v3_dispatch_sgi(vcpu, p->regval);
6d52f35a
AP		 132
133 return true;
134}
135
b34f2bcb
MZ		 136static bool access_gic_sre(struct kvm_vcpu *vcpu,
137 struct sys_reg_params *p,
138 const struct sys_reg_desc *r)
139{
140 if (p->is_write)
141 return ignore_write(vcpu, p);
142
143 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
144 return true;
145}
146
7609c125 147static bool trap_raz_wi(struct kvm_vcpu *vcpu,
3fec037d 148 struct sys_reg_params *p,
7609c125 149 const struct sys_reg_desc *r)
7c8c5e6a
MZ		 150{
151 if (p->is_write)
152 return ignore_write(vcpu, p);
153 else
154 return read_zero(vcpu, p);
155}
156
0c557ed4 157static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
3fec037d 158 struct sys_reg_params *p,
0c557ed4
MZ		 159 const struct sys_reg_desc *r)
160{
161 if (p->is_write) {
162 return ignore_write(vcpu, p);
163 } else {
2ec5be3d 164 p->regval = (1 << 3);
0c557ed4
MZ		 165 return true;
166 }
167}
168
169static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
3fec037d 170 struct sys_reg_params *p,
0c557ed4
MZ		 171 const struct sys_reg_desc *r)
172{
173 if (p->is_write) {
174 return ignore_write(vcpu, p);
175 } else {
1f3d8699 176 p->regval = read_sysreg(dbgauthstatus_el1);
0c557ed4
MZ		 177 return true;
178 }
179}
180
181/*
182 * We want to avoid world-switching all the DBG registers all the
183 * time:
184 *
185 * - If we've touched any debug register, it is likely that we're
186 * going to touch more of them. It then makes sense to disable the
187 * traps and start doing the save/restore dance
188 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
189 * then mandatory to save/restore the registers, as the guest
190 * depends on them.
191 *
192 * For this, we use a DIRTY bit, indicating the guest has modified the
193 * debug registers, used as follow:
194 *
195 * On guest entry:
196 * - If the dirty bit is set (because we're coming back from trapping),
197 * disable the traps, save host registers, restore guest registers.
198 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
199 * set the dirty bit, disable the traps, save host registers,
200 * restore guest registers.
201 * - Otherwise, enable the traps
202 *
203 * On guest exit:
204 * - If the dirty bit is set, save guest registers, restore host
205 * registers and clear the dirty bit. This ensure that the host can
206 * now use the debug registers.
207 */
208static bool trap_debug_regs(struct kvm_vcpu *vcpu,
3fec037d 209 struct sys_reg_params *p,
0c557ed4
MZ		 210 const struct sys_reg_desc *r)
211{
212 if (p->is_write) {
2ec5be3d 213 vcpu_sys_reg(vcpu, r->reg) = p->regval;
0c557ed4
MZ		 214 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
215 } else {
2ec5be3d 216 p->regval = vcpu_sys_reg(vcpu, r->reg);
0c557ed4
MZ		 217 }
218
2ec5be3d 219 trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
eef8c85a 220
0c557ed4
MZ		 221 return true;
222}
223
84e690bf
AB		 224/*
225 * reg_to_dbg/dbg_to_reg
226 *
227 * A 32 bit write to a debug register leave top bits alone
228 * A 32 bit read from a debug register only returns the bottom bits
229 *
230 * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the
231 * hyp.S code switches between host and guest values in future.
232 */
281243cb
MZ		 233static void reg_to_dbg(struct kvm_vcpu *vcpu,
234 struct sys_reg_params *p,
235 u64 *dbg_reg)
84e690bf 236{
2ec5be3d 237 u64 val = p->regval;
84e690bf
AB		 238
239 if (p->is_32bit) {
240 val &= 0xffffffffUL;
241 val |= ((*dbg_reg >> 32) << 32);
242 }
243
244 *dbg_reg = val;
245 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
246}
247
281243cb
MZ		 248static void dbg_to_reg(struct kvm_vcpu *vcpu,
249 struct sys_reg_params *p,
250 u64 *dbg_reg)
84e690bf 251{
2ec5be3d 252 p->regval = *dbg_reg;
84e690bf 253 if (p->is_32bit)
2ec5be3d 254 p->regval &= 0xffffffffUL;
84e690bf
AB		 255}
256
281243cb
MZ		 257static bool trap_bvr(struct kvm_vcpu *vcpu,
258 struct sys_reg_params *p,
259 const struct sys_reg_desc *rd)
84e690bf
AB		 260{
261 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
262
263 if (p->is_write)
264 reg_to_dbg(vcpu, p, dbg_reg);
265 else
266 dbg_to_reg(vcpu, p, dbg_reg);
267
eef8c85a
AB		 268 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
269
84e690bf
AB		 270 return true;
271}
272
273static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
274 const struct kvm_one_reg *reg, void __user *uaddr)
275{
276 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
277
1713e5aa 278 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 279 return -EFAULT;
280 return 0;
281}
282
283static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
284 const struct kvm_one_reg *reg, void __user *uaddr)
285{
286 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
287
288 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
289 return -EFAULT;
290 return 0;
291}
292
281243cb
MZ		 293static void reset_bvr(struct kvm_vcpu *vcpu,
294 const struct sys_reg_desc *rd)
84e690bf
AB		 295{
296 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val;
297}
298
281243cb
MZ		 299static bool trap_bcr(struct kvm_vcpu *vcpu,
300 struct sys_reg_params *p,
301 const struct sys_reg_desc *rd)
84e690bf
AB		 302{
303 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
304
305 if (p->is_write)
306 reg_to_dbg(vcpu, p, dbg_reg);
307 else
308 dbg_to_reg(vcpu, p, dbg_reg);
309
eef8c85a
AB		 310 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
311
84e690bf
AB		 312 return true;
313}
314
315static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
316 const struct kvm_one_reg *reg, void __user *uaddr)
317{
318 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
319
1713e5aa 320 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 321 return -EFAULT;
322
323 return 0;
324}
325
326static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
327 const struct kvm_one_reg *reg, void __user *uaddr)
328{
329 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
330
331 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
332 return -EFAULT;
333 return 0;
334}
335
281243cb
MZ		 336static void reset_bcr(struct kvm_vcpu *vcpu,
337 const struct sys_reg_desc *rd)
84e690bf
AB		 338{
339 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val;
340}
341
281243cb
MZ		 342static bool trap_wvr(struct kvm_vcpu *vcpu,
343 struct sys_reg_params *p,
344 const struct sys_reg_desc *rd)
84e690bf
AB		 345{
346 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
347
348 if (p->is_write)
349 reg_to_dbg(vcpu, p, dbg_reg);
350 else
351 dbg_to_reg(vcpu, p, dbg_reg);
352
eef8c85a
AB		 353 trace_trap_reg(__func__, rd->reg, p->is_write,
354 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]);
355
84e690bf
AB		 356 return true;
357}
358
359static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
360 const struct kvm_one_reg *reg, void __user *uaddr)
361{
362 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
363
1713e5aa 364 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 365 return -EFAULT;
366 return 0;
367}
368
369static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
370 const struct kvm_one_reg *reg, void __user *uaddr)
371{
372 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
373
374 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
375 return -EFAULT;
376 return 0;
377}
378
281243cb
MZ		 379static void reset_wvr(struct kvm_vcpu *vcpu,
380 const struct sys_reg_desc *rd)
84e690bf
AB		 381{
382 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val;
383}
384
281243cb
MZ		 385static bool trap_wcr(struct kvm_vcpu *vcpu,
386 struct sys_reg_params *p,
387 const struct sys_reg_desc *rd)
84e690bf
AB		 388{
389 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
390
391 if (p->is_write)
392 reg_to_dbg(vcpu, p, dbg_reg);
393 else
394 dbg_to_reg(vcpu, p, dbg_reg);
395
eef8c85a
AB		 396 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
397
84e690bf
AB		 398 return true;
399}
400
401static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
402 const struct kvm_one_reg *reg, void __user *uaddr)
403{
404 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
405
1713e5aa 406 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 407 return -EFAULT;
408 return 0;
409}
410
411static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
412 const struct kvm_one_reg *reg, void __user *uaddr)
413{
414 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
415
416 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
417 return -EFAULT;
418 return 0;
419}
420
281243cb
MZ		 421static void reset_wcr(struct kvm_vcpu *vcpu,
422 const struct sys_reg_desc *rd)
84e690bf
AB		 423{
424 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val;
425}
426
7c8c5e6a
MZ		 427static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
428{
1f3d8699 429 vcpu_sys_reg(vcpu, AMAIR_EL1) = read_sysreg(amair_el1);
7c8c5e6a
MZ		 430}
431
432static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
433{
4429fc64
AP		 434 u64 mpidr;
435
7c8c5e6a 436 /*
4429fc64
AP		 437 * Map the vcpu_id into the first three affinity level fields of
438 * the MPIDR. We limit the number of VCPUs in level 0 due to a
439 * limitation to 16 CPUs in that level in the ICC_SGIxR registers
440 * of the GICv3 to be able to address each CPU directly when
441 * sending IPIs.
7c8c5e6a 442 */
4429fc64
AP		 443 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
444 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
445 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
446 vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr;
7c8c5e6a
MZ		 447}
448
ab946834
SZ		 449static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
450{
451 u64 pmcr, val;
452
1f3d8699
MR		 453 pmcr = read_sysreg(pmcr_el0);
454 /*
455 * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN
ab946834
SZ		 456 * except PMCR.E resetting to zero.
457 */
458 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
459 | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
460 vcpu_sys_reg(vcpu, PMCR_EL0) = val;
461}
462
d692b8ad
SZ		 463static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
464{
465 u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
466
467 return !((reg & ARMV8_PMU_USERENR_EN) || vcpu_mode_priv(vcpu));
468}
469
470static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
471{
472 u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
473
474 return !((reg & (ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN))
475 || vcpu_mode_priv(vcpu));
476}
477
478static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
479{
480 u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
481
482 return !((reg & (ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN))
483 || vcpu_mode_priv(vcpu));
484}
485
486static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
487{
488 u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
489
490 return !((reg & (ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN))
491 || vcpu_mode_priv(vcpu));
492}
493
ab946834
SZ		 494static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
495 const struct sys_reg_desc *r)
496{
497 u64 val;
498
499 if (!kvm_arm_pmu_v3_ready(vcpu))
500 return trap_raz_wi(vcpu, p, r);
501
d692b8ad
SZ		 502 if (pmu_access_el0_disabled(vcpu))
503 return false;
504
ab946834
SZ		 505 if (p->is_write) {
506 /* Only update writeable bits of PMCR */
507 val = vcpu_sys_reg(vcpu, PMCR_EL0);
508 val &= ~ARMV8_PMU_PMCR_MASK;
509 val |= p->regval & ARMV8_PMU_PMCR_MASK;
510 vcpu_sys_reg(vcpu, PMCR_EL0) = val;
76993739 511 kvm_pmu_handle_pmcr(vcpu, val);
ab946834
SZ		 512 } else {
513 /* PMCR.P & PMCR.C are RAZ */
514 val = vcpu_sys_reg(vcpu, PMCR_EL0)
515 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
516 p->regval = val;
517 }
518
519 return true;
520}
521
3965c3ce
SZ		 522static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
523 const struct sys_reg_desc *r)
524{
525 if (!kvm_arm_pmu_v3_ready(vcpu))
526 return trap_raz_wi(vcpu, p, r);
527
d692b8ad
SZ		 528 if (pmu_access_event_counter_el0_disabled(vcpu))
529 return false;
530
3965c3ce
SZ		 531 if (p->is_write)
532 vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
533 else
534 /* return PMSELR.SEL field */
535 p->regval = vcpu_sys_reg(vcpu, PMSELR_EL0)
536 & ARMV8_PMU_COUNTER_MASK;
537
538 return true;
539}
540
a86b5505
SZ		 541static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
542 const struct sys_reg_desc *r)
543{
544 u64 pmceid;
545
546 if (!kvm_arm_pmu_v3_ready(vcpu))
547 return trap_raz_wi(vcpu, p, r);
548
549 BUG_ON(p->is_write);
550
d692b8ad
SZ		 551 if (pmu_access_el0_disabled(vcpu))
552 return false;
553
a86b5505 554 if (!(p->Op2 & 1))
1f3d8699 555 pmceid = read_sysreg(pmceid0_el0);
a86b5505 556 else
1f3d8699 557 pmceid = read_sysreg(pmceid1_el0);
a86b5505
SZ		 558
559 p->regval = pmceid;
560
561 return true;
562}
563
051ff581
SZ		 564static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
565{
566 u64 pmcr, val;
567
568 pmcr = vcpu_sys_reg(vcpu, PMCR_EL0);
569 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
570 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX)
571 return false;
572
573 return true;
574}
575
576static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
577 struct sys_reg_params *p,
578 const struct sys_reg_desc *r)
579{
580 u64 idx;
581
582 if (!kvm_arm_pmu_v3_ready(vcpu))
583 return trap_raz_wi(vcpu, p, r);
584
585 if (r->CRn == 9 && r->CRm == 13) {
586 if (r->Op2 == 2) {
587 /* PMXEVCNTR_EL0 */
d692b8ad
SZ		 588 if (pmu_access_event_counter_el0_disabled(vcpu))
589 return false;
590
051ff581
SZ		 591 idx = vcpu_sys_reg(vcpu, PMSELR_EL0)
592 & ARMV8_PMU_COUNTER_MASK;
593 } else if (r->Op2 == 0) {
594 /* PMCCNTR_EL0 */
d692b8ad
SZ		 595 if (pmu_access_cycle_counter_el0_disabled(vcpu))
596 return false;
597
051ff581
SZ		 598 idx = ARMV8_PMU_CYCLE_IDX;
599 } else {
9e3f7a29 600 return false;
051ff581 601 }
9e3f7a29
WH		 602 } else if (r->CRn == 0 && r->CRm == 9) {
603 /* PMCCNTR */
604 if (pmu_access_event_counter_el0_disabled(vcpu))
605 return false;
606
607 idx = ARMV8_PMU_CYCLE_IDX;
051ff581
SZ		 608 } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
609 /* PMEVCNTRn_EL0 */
d692b8ad
SZ		 610 if (pmu_access_event_counter_el0_disabled(vcpu))
611 return false;
612
051ff581
SZ		 613 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
614 } else {
9e3f7a29 615 return false;
051ff581
SZ		 616 }
617
618 if (!pmu_counter_idx_valid(vcpu, idx))
619 return false;
620
d692b8ad
SZ		 621 if (p->is_write) {
622 if (pmu_access_el0_disabled(vcpu))
623 return false;
624
051ff581 625 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
d692b8ad 626 } else {
051ff581 627 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
d692b8ad 628 }
051ff581
SZ		 629
630 return true;
631}
632
9feb21ac
SZ		 633static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
634 const struct sys_reg_desc *r)
635{
636 u64 idx, reg;
637
638 if (!kvm_arm_pmu_v3_ready(vcpu))
639 return trap_raz_wi(vcpu, p, r);
640
d692b8ad
SZ		 641 if (pmu_access_el0_disabled(vcpu))
642 return false;
643
9feb21ac
SZ		 644 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
645 /* PMXEVTYPER_EL0 */
646 idx = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
647 reg = PMEVTYPER0_EL0 + idx;
648 } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
649 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
650 if (idx == ARMV8_PMU_CYCLE_IDX)
651 reg = PMCCFILTR_EL0;
652 else
653 /* PMEVTYPERn_EL0 */
654 reg = PMEVTYPER0_EL0 + idx;
655 } else {
656 BUG();
657 }
658
659 if (!pmu_counter_idx_valid(vcpu, idx))
660 return false;
661
662 if (p->is_write) {
663 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
664 vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
665 } else {
666 p->regval = vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
667 }
668
669 return true;
670}
671
96b0eebc
SZ		 672static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
673 const struct sys_reg_desc *r)
674{
675 u64 val, mask;
676
677 if (!kvm_arm_pmu_v3_ready(vcpu))
678 return trap_raz_wi(vcpu, p, r);
679
d692b8ad
SZ		 680 if (pmu_access_el0_disabled(vcpu))
681 return false;
682
96b0eebc
SZ		 683 mask = kvm_pmu_valid_counter_mask(vcpu);
684 if (p->is_write) {
685 val = p->regval & mask;
686 if (r->Op2 & 0x1) {
687 /* accessing PMCNTENSET_EL0 */
688 vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
689 kvm_pmu_enable_counter(vcpu, val);
690 } else {
691 /* accessing PMCNTENCLR_EL0 */
692 vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
693 kvm_pmu_disable_counter(vcpu, val);
694 }
695 } else {
696 p->regval = vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
697 }
698
699 return true;
700}
701
9db52c78
SZ		 702static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
703 const struct sys_reg_desc *r)
704{
705 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
706
707 if (!kvm_arm_pmu_v3_ready(vcpu))
708 return trap_raz_wi(vcpu, p, r);
709
d692b8ad
SZ		 710 if (!vcpu_mode_priv(vcpu))
711 return false;
712
9db52c78
SZ		 713 if (p->is_write) {
714 u64 val = p->regval & mask;
715
716 if (r->Op2 & 0x1)
717 /* accessing PMINTENSET_EL1 */
718 vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
719 else
720 /* accessing PMINTENCLR_EL1 */
721 vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
722 } else {
723 p->regval = vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask;
724 }
725
726 return true;
727}
728
76d883c4
SZ		 729static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
730 const struct sys_reg_desc *r)
731{
732 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
733
734 if (!kvm_arm_pmu_v3_ready(vcpu))
735 return trap_raz_wi(vcpu, p, r);
736
d692b8ad
SZ		 737 if (pmu_access_el0_disabled(vcpu))
738 return false;
739
76d883c4
SZ		 740 if (p->is_write) {
741 if (r->CRm & 0x2)
742 /* accessing PMOVSSET_EL0 */
743 kvm_pmu_overflow_set(vcpu, p->regval & mask);
744 else
745 /* accessing PMOVSCLR_EL0 */
746 vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
747 } else {
748 p->regval = vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask;
749 }
750
751 return true;
752}
753
7a0adc70
SZ		 754static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
755 const struct sys_reg_desc *r)
756{
757 u64 mask;
758
759 if (!kvm_arm_pmu_v3_ready(vcpu))
760 return trap_raz_wi(vcpu, p, r);
761
d692b8ad
SZ		 762 if (pmu_write_swinc_el0_disabled(vcpu))
763 return false;
764
7a0adc70
SZ		 765 if (p->is_write) {
766 mask = kvm_pmu_valid_counter_mask(vcpu);
767 kvm_pmu_software_increment(vcpu, p->regval & mask);
768 return true;
769 }
770
771 return false;
772}
773
d692b8ad
SZ		 774static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
775 const struct sys_reg_desc *r)
776{
777 if (!kvm_arm_pmu_v3_ready(vcpu))
778 return trap_raz_wi(vcpu, p, r);
779
780 if (p->is_write) {
781 if (!vcpu_mode_priv(vcpu))
782 return false;
783
784 vcpu_sys_reg(vcpu, PMUSERENR_EL0) = p->regval
785 & ARMV8_PMU_USERENR_MASK;
786 } else {
787 p->regval = vcpu_sys_reg(vcpu, PMUSERENR_EL0)
788 & ARMV8_PMU_USERENR_MASK;
789 }
790
791 return true;
792}
793
0c557ed4
MZ		 794/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
795#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
796 /* DBGBVRn_EL1 */ \
797 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b100), \
84e690bf 798 trap_bvr, reset_bvr, n, 0, get_bvr, set_bvr }, \
0c557ed4
MZ		 799 /* DBGBCRn_EL1 */ \
800 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b101), \
84e690bf 801 trap_bcr, reset_bcr, n, 0, get_bcr, set_bcr }, \
0c557ed4
MZ		 802 /* DBGWVRn_EL1 */ \
803 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b110), \
84e690bf 804 trap_wvr, reset_wvr, n, 0, get_wvr, set_wvr }, \
0c557ed4
MZ		 805 /* DBGWCRn_EL1 */ \
806 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b111), \
84e690bf 807 trap_wcr, reset_wcr, n, 0, get_wcr, set_wcr }
0c557ed4 808
051ff581
SZ		 809/* Macro to expand the PMEVCNTRn_EL0 register */
810#define PMU_PMEVCNTR_EL0(n) \
811 /* PMEVCNTRn_EL0 */ \
812 { Op0(0b11), Op1(0b011), CRn(0b1110), \
813 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
814 access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), }
815
9feb21ac
SZ		 816/* Macro to expand the PMEVTYPERn_EL0 register */
817#define PMU_PMEVTYPER_EL0(n) \
818 /* PMEVTYPERn_EL0 */ \
819 { Op0(0b11), Op1(0b011), CRn(0b1110), \
820 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
821 access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
822
7c8c5e6a
MZ		 823/*
824 * Architected system registers.
825 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
7609c125 826 *
0c557ed4
MZ		 827 * Debug handling: We do trap most, if not all debug related system
828 * registers. The implementation is good enough to ensure that a guest
829 * can use these with minimal performance degradation. The drawback is
830 * that we don't implement any of the external debug, none of the
831 * OSlock protocol. This should be revisited if we ever encounter a
832 * more demanding guest...
7c8c5e6a
MZ		 833 */
834static const struct sys_reg_desc sys_reg_descs[] = {
835 /* DC ISW */
836 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b0110), Op2(0b010),
837 access_dcsw },
838 /* DC CSW */
839 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1010), Op2(0b010),
840 access_dcsw },
841 /* DC CISW */
842 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b010),
843 access_dcsw },
844
0c557ed4
MZ		 845 DBG_BCR_BVR_WCR_WVR_EL1(0),
846 DBG_BCR_BVR_WCR_WVR_EL1(1),
847 /* MDCCINT_EL1 */
848 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
849 trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
850 /* MDSCR_EL1 */
851 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
852 trap_debug_regs, reset_val, MDSCR_EL1, 0 },
853 DBG_BCR_BVR_WCR_WVR_EL1(2),
854 DBG_BCR_BVR_WCR_WVR_EL1(3),
855 DBG_BCR_BVR_WCR_WVR_EL1(4),
856 DBG_BCR_BVR_WCR_WVR_EL1(5),
857 DBG_BCR_BVR_WCR_WVR_EL1(6),
858 DBG_BCR_BVR_WCR_WVR_EL1(7),
859 DBG_BCR_BVR_WCR_WVR_EL1(8),
860 DBG_BCR_BVR_WCR_WVR_EL1(9),
861 DBG_BCR_BVR_WCR_WVR_EL1(10),
862 DBG_BCR_BVR_WCR_WVR_EL1(11),
863 DBG_BCR_BVR_WCR_WVR_EL1(12),
864 DBG_BCR_BVR_WCR_WVR_EL1(13),
865 DBG_BCR_BVR_WCR_WVR_EL1(14),
866 DBG_BCR_BVR_WCR_WVR_EL1(15),
867
868 /* MDRAR_EL1 */
869 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
870 trap_raz_wi },
871 /* OSLAR_EL1 */
872 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b100),
873 trap_raz_wi },
874 /* OSLSR_EL1 */
875 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0001), Op2(0b100),
876 trap_oslsr_el1 },
877 /* OSDLR_EL1 */
878 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0011), Op2(0b100),
879 trap_raz_wi },
880 /* DBGPRCR_EL1 */
881 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0100), Op2(0b100),
882 trap_raz_wi },
883 /* DBGCLAIMSET_EL1 */
884 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1000), Op2(0b110),
885 trap_raz_wi },
886 /* DBGCLAIMCLR_EL1 */
887 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1001), Op2(0b110),
888 trap_raz_wi },
889 /* DBGAUTHSTATUS_EL1 */
890 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b110),
891 trap_dbgauthstatus_el1 },
892
0c557ed4
MZ		 893 /* MDCCSR_EL1 */
894 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0001), Op2(0b000),
895 trap_raz_wi },
896 /* DBGDTR_EL0 */
897 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0100), Op2(0b000),
898 trap_raz_wi },
899 /* DBGDTR[TR]X_EL0 */
900 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0101), Op2(0b000),
901 trap_raz_wi },
902
62a89c44
MZ		 903 /* DBGVCR32_EL2 */
904 { Op0(0b10), Op1(0b100), CRn(0b0000), CRm(0b0111), Op2(0b000),
905 NULL, reset_val, DBGVCR32_EL2, 0 },
906
7c8c5e6a
MZ		 907 /* MPIDR_EL1 */
908 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b101),
909 NULL, reset_mpidr, MPIDR_EL1 },
910 /* SCTLR_EL1 */
911 { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
3c1e7165 912 access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
7c8c5e6a
MZ		 913 /* CPACR_EL1 */
914 { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010),
915 NULL, reset_val, CPACR_EL1, 0 },
916 /* TTBR0_EL1 */
917 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b000),
4d44923b 918 access_vm_reg, reset_unknown, TTBR0_EL1 },
7c8c5e6a
MZ		 919 /* TTBR1_EL1 */
920 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b001),
4d44923b 921 access_vm_reg, reset_unknown, TTBR1_EL1 },
7c8c5e6a
MZ		 922 /* TCR_EL1 */
923 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b010),
4d44923b 924 access_vm_reg, reset_val, TCR_EL1, 0 },
7c8c5e6a
MZ		 925
926 /* AFSR0_EL1 */
927 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b000),
4d44923b 928 access_vm_reg, reset_unknown, AFSR0_EL1 },
7c8c5e6a
MZ		 929 /* AFSR1_EL1 */
930 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b001),
4d44923b 931 access_vm_reg, reset_unknown, AFSR1_EL1 },
7c8c5e6a
MZ		 932 /* ESR_EL1 */
933 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0010), Op2(0b000),
4d44923b 934 access_vm_reg, reset_unknown, ESR_EL1 },
7c8c5e6a
MZ		 935 /* FAR_EL1 */
936 { Op0(0b11), Op1(0b000), CRn(0b0110), CRm(0b0000), Op2(0b000),
4d44923b 937 access_vm_reg, reset_unknown, FAR_EL1 },
1bbd8054
MZ		 938 /* PAR_EL1 */
939 { Op0(0b11), Op1(0b000), CRn(0b0111), CRm(0b0100), Op2(0b000),
940 NULL, reset_unknown, PAR_EL1 },
7c8c5e6a
MZ		 941
942 /* PMINTENSET_EL1 */
943 { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
9db52c78 944 access_pminten, reset_unknown, PMINTENSET_EL1 },
7c8c5e6a
MZ		 945 /* PMINTENCLR_EL1 */
946 { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),
9db52c78 947 access_pminten, NULL, PMINTENSET_EL1 },
7c8c5e6a
MZ		 948
949 /* MAIR_EL1 */
950 { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
4d44923b 951 access_vm_reg, reset_unknown, MAIR_EL1 },
7c8c5e6a
MZ		 952 /* AMAIR_EL1 */
953 { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0011), Op2(0b000),
4d44923b 954 access_vm_reg, reset_amair_el1, AMAIR_EL1 },
7c8c5e6a
MZ		 955
956 /* VBAR_EL1 */
957 { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b0000), Op2(0b000),
958 NULL, reset_val, VBAR_EL1, 0 },
db7dedd0 959
6d52f35a
AP		 960 /* ICC_SGI1R_EL1 */
961 { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1011), Op2(0b101),
962 access_gic_sgi },
db7dedd0
CD		 963 /* ICC_SRE_EL1 */
964 { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1100), Op2(0b101),
b34f2bcb 965 access_gic_sre },
db7dedd0 966
7c8c5e6a
MZ		 967 /* CONTEXTIDR_EL1 */
968 { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001),
4d44923b 969 access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
7c8c5e6a
MZ		 970 /* TPIDR_EL1 */
971 { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b100),
972 NULL, reset_unknown, TPIDR_EL1 },
973
974 /* CNTKCTL_EL1 */
975 { Op0(0b11), Op1(0b000), CRn(0b1110), CRm(0b0001), Op2(0b000),
976 NULL, reset_val, CNTKCTL_EL1, 0},
977
978 /* CSSELR_EL1 */
979 { Op0(0b11), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
980 NULL, reset_unknown, CSSELR_EL1 },
981
982 /* PMCR_EL0 */
983 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000),
ab946834 984 access_pmcr, reset_pmcr, },
7c8c5e6a
MZ		 985 /* PMCNTENSET_EL0 */
986 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
96b0eebc 987 access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
7c8c5e6a
MZ		 988 /* PMCNTENCLR_EL0 */
989 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
96b0eebc 990 access_pmcnten, NULL, PMCNTENSET_EL0 },
7c8c5e6a
MZ		 991 /* PMOVSCLR_EL0 */
992 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
76d883c4 993 access_pmovs, NULL, PMOVSSET_EL0 },
7c8c5e6a
MZ		 994 /* PMSWINC_EL0 */
995 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
7a0adc70 996 access_pmswinc, reset_unknown, PMSWINC_EL0 },
7c8c5e6a
MZ		 997 /* PMSELR_EL0 */
998 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
3965c3ce 999 access_pmselr, reset_unknown, PMSELR_EL0 },
7c8c5e6a
MZ		 1000 /* PMCEID0_EL0 */
1001 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
a86b5505 1002 access_pmceid },
7c8c5e6a
MZ		 1003 /* PMCEID1_EL0 */
1004 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
a86b5505 1005 access_pmceid },
7c8c5e6a
MZ		 1006 /* PMCCNTR_EL0 */
1007 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
051ff581 1008 access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 },
7c8c5e6a
MZ		 1009 /* PMXEVTYPER_EL0 */
1010 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
9feb21ac 1011 access_pmu_evtyper },
7c8c5e6a
MZ		 1012 /* PMXEVCNTR_EL0 */
1013 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
051ff581 1014 access_pmu_evcntr },
d692b8ad
SZ		 1015 /* PMUSERENR_EL0
1016 * This register resets as unknown in 64bit mode while it resets as zero
1017 * in 32bit mode. Here we choose to reset it as zero for consistency.
1018 */
7c8c5e6a 1019 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
d692b8ad 1020 access_pmuserenr, reset_val, PMUSERENR_EL0, 0 },
7c8c5e6a
MZ		 1021 /* PMOVSSET_EL0 */
1022 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
76d883c4 1023 access_pmovs, reset_unknown, PMOVSSET_EL0 },
7c8c5e6a
MZ		 1024
1025 /* TPIDR_EL0 */
1026 { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b010),
1027 NULL, reset_unknown, TPIDR_EL0 },
1028 /* TPIDRRO_EL0 */
1029 { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
1030 NULL, reset_unknown, TPIDRRO_EL0 },
62a89c44 1031
051ff581
SZ		 1032 /* PMEVCNTRn_EL0 */
1033 PMU_PMEVCNTR_EL0(0),
1034 PMU_PMEVCNTR_EL0(1),
1035 PMU_PMEVCNTR_EL0(2),
1036 PMU_PMEVCNTR_EL0(3),
1037 PMU_PMEVCNTR_EL0(4),
1038 PMU_PMEVCNTR_EL0(5),
1039 PMU_PMEVCNTR_EL0(6),
1040 PMU_PMEVCNTR_EL0(7),
1041 PMU_PMEVCNTR_EL0(8),
1042 PMU_PMEVCNTR_EL0(9),
1043 PMU_PMEVCNTR_EL0(10),
1044 PMU_PMEVCNTR_EL0(11),
1045 PMU_PMEVCNTR_EL0(12),
1046 PMU_PMEVCNTR_EL0(13),
1047 PMU_PMEVCNTR_EL0(14),
1048 PMU_PMEVCNTR_EL0(15),
1049 PMU_PMEVCNTR_EL0(16),
1050 PMU_PMEVCNTR_EL0(17),
1051 PMU_PMEVCNTR_EL0(18),
1052 PMU_PMEVCNTR_EL0(19),
1053 PMU_PMEVCNTR_EL0(20),
1054 PMU_PMEVCNTR_EL0(21),
1055 PMU_PMEVCNTR_EL0(22),
1056 PMU_PMEVCNTR_EL0(23),
1057 PMU_PMEVCNTR_EL0(24),
1058 PMU_PMEVCNTR_EL0(25),
1059 PMU_PMEVCNTR_EL0(26),
1060 PMU_PMEVCNTR_EL0(27),
1061 PMU_PMEVCNTR_EL0(28),
1062 PMU_PMEVCNTR_EL0(29),
1063 PMU_PMEVCNTR_EL0(30),
9feb21ac
SZ		 1064 /* PMEVTYPERn_EL0 */
1065 PMU_PMEVTYPER_EL0(0),
1066 PMU_PMEVTYPER_EL0(1),
1067 PMU_PMEVTYPER_EL0(2),
1068 PMU_PMEVTYPER_EL0(3),
1069 PMU_PMEVTYPER_EL0(4),
1070 PMU_PMEVTYPER_EL0(5),
1071 PMU_PMEVTYPER_EL0(6),
1072 PMU_PMEVTYPER_EL0(7),
1073 PMU_PMEVTYPER_EL0(8),
1074 PMU_PMEVTYPER_EL0(9),
1075 PMU_PMEVTYPER_EL0(10),
1076 PMU_PMEVTYPER_EL0(11),
1077 PMU_PMEVTYPER_EL0(12),
1078 PMU_PMEVTYPER_EL0(13),
1079 PMU_PMEVTYPER_EL0(14),
1080 PMU_PMEVTYPER_EL0(15),
1081 PMU_PMEVTYPER_EL0(16),
1082 PMU_PMEVTYPER_EL0(17),
1083 PMU_PMEVTYPER_EL0(18),
1084 PMU_PMEVTYPER_EL0(19),
1085 PMU_PMEVTYPER_EL0(20),
1086 PMU_PMEVTYPER_EL0(21),
1087 PMU_PMEVTYPER_EL0(22),
1088 PMU_PMEVTYPER_EL0(23),
1089 PMU_PMEVTYPER_EL0(24),
1090 PMU_PMEVTYPER_EL0(25),
1091 PMU_PMEVTYPER_EL0(26),
1092 PMU_PMEVTYPER_EL0(27),
1093 PMU_PMEVTYPER_EL0(28),
1094 PMU_PMEVTYPER_EL0(29),
1095 PMU_PMEVTYPER_EL0(30),
1096 /* PMCCFILTR_EL0
1097 * This register resets as unknown in 64bit mode while it resets as zero
1098 * in 32bit mode. Here we choose to reset it as zero for consistency.
1099 */
1100 { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b1111), Op2(0b111),
1101 access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 },
051ff581 1102
62a89c44
MZ		 1103 /* DACR32_EL2 */
1104 { Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000),
1105 NULL, reset_unknown, DACR32_EL2 },
1106 /* IFSR32_EL2 */
1107 { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0000), Op2(0b001),
1108 NULL, reset_unknown, IFSR32_EL2 },
1109 /* FPEXC32_EL2 */
1110 { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0011), Op2(0b000),
1111 NULL, reset_val, FPEXC32_EL2, 0x70 },
1112};
1113
bdfb4b38 1114static bool trap_dbgidr(struct kvm_vcpu *vcpu,
3fec037d 1115 struct sys_reg_params *p,
bdfb4b38
MZ		 1116 const struct sys_reg_desc *r)
1117{
1118 if (p->is_write) {
1119 return ignore_write(vcpu, p);
1120 } else {
4db8e5ea
SP		 1121 u64 dfr = read_system_reg(SYS_ID_AA64DFR0_EL1);
1122 u64 pfr = read_system_reg(SYS_ID_AA64PFR0_EL1);
28c5dcb2 1123 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
bdfb4b38 1124
2ec5be3d
PF		 1125 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
1126 (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
1127 (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20)
1128 | (6 << 16) | (el3 << 14) | (el3 << 12));
bdfb4b38
MZ		 1129 return true;
1130 }
1131}
1132
1133static bool trap_debug32(struct kvm_vcpu *vcpu,
3fec037d 1134 struct sys_reg_params *p,
bdfb4b38
MZ		 1135 const struct sys_reg_desc *r)
1136{
1137 if (p->is_write) {
2ec5be3d 1138 vcpu_cp14(vcpu, r->reg) = p->regval;
bdfb4b38
MZ		 1139 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
1140 } else {
2ec5be3d 1141 p->regval = vcpu_cp14(vcpu, r->reg);
bdfb4b38
MZ		 1142 }
1143
1144 return true;
1145}
1146
84e690bf
AB		 1147/* AArch32 debug register mappings
1148 *
1149 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
1150 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
1151 *
1152 * All control registers and watchpoint value registers are mapped to
1153 * the lower 32 bits of their AArch64 equivalents. We share the trap
1154 * handlers with the above AArch64 code which checks what mode the
1155 * system is in.
1156 */
1157
281243cb
MZ		 1158static bool trap_xvr(struct kvm_vcpu *vcpu,
1159 struct sys_reg_params *p,
1160 const struct sys_reg_desc *rd)
84e690bf
AB		 1161{
1162 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
1163
1164 if (p->is_write) {
1165 u64 val = *dbg_reg;
1166
1167 val &= 0xffffffffUL;
2ec5be3d 1168 val |= p->regval << 32;
84e690bf
AB		 1169 *dbg_reg = val;
1170
1171 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
1172 } else {
2ec5be3d 1173 p->regval = *dbg_reg >> 32;
84e690bf
AB		 1174 }
1175
eef8c85a
AB		 1176 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
1177
84e690bf
AB		 1178 return true;
1179}
1180
1181#define DBG_BCR_BVR_WCR_WVR(n) \
1182 /* DBGBVRn */ \
1183 { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
1184 /* DBGBCRn */ \
1185 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
1186 /* DBGWVRn */ \
1187 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
1188 /* DBGWCRn */ \
1189 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1190
1191#define DBGBXVR(n) \
1192 { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n }
bdfb4b38
MZ		 1193
1194/*
1195 * Trapped cp14 registers. We generally ignore most of the external
1196 * debug, on the principle that they don't really make sense to a
84e690bf 1197 * guest. Revisit this one day, would this principle change.
bdfb4b38 1198 */
72564016 1199static const struct sys_reg_desc cp14_regs[] = {
bdfb4b38
MZ		 1200 /* DBGIDR */
1201 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
1202 /* DBGDTRRXext */
1203 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1204
1205 DBG_BCR_BVR_WCR_WVR(0),
1206 /* DBGDSCRint */
1207 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1208 DBG_BCR_BVR_WCR_WVR(1),
1209 /* DBGDCCINT */
1210 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 },
1211 /* DBGDSCRext */
1212 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 },
1213 DBG_BCR_BVR_WCR_WVR(2),
1214 /* DBGDTR[RT]Xint */
1215 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1216 /* DBGDTR[RT]Xext */
1217 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1218 DBG_BCR_BVR_WCR_WVR(3),
1219 DBG_BCR_BVR_WCR_WVR(4),
1220 DBG_BCR_BVR_WCR_WVR(5),
1221 /* DBGWFAR */
1222 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1223 /* DBGOSECCR */
1224 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1225 DBG_BCR_BVR_WCR_WVR(6),
1226 /* DBGVCR */
1227 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 },
1228 DBG_BCR_BVR_WCR_WVR(7),
1229 DBG_BCR_BVR_WCR_WVR(8),
1230 DBG_BCR_BVR_WCR_WVR(9),
1231 DBG_BCR_BVR_WCR_WVR(10),
1232 DBG_BCR_BVR_WCR_WVR(11),
1233 DBG_BCR_BVR_WCR_WVR(12),
1234 DBG_BCR_BVR_WCR_WVR(13),
1235 DBG_BCR_BVR_WCR_WVR(14),
1236 DBG_BCR_BVR_WCR_WVR(15),
1237
1238 /* DBGDRAR (32bit) */
1239 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1240
1241 DBGBXVR(0),
1242 /* DBGOSLAR */
1243 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
1244 DBGBXVR(1),
1245 /* DBGOSLSR */
1246 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
1247 DBGBXVR(2),
1248 DBGBXVR(3),
1249 /* DBGOSDLR */
1250 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1251 DBGBXVR(4),
1252 /* DBGPRCR */
1253 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1254 DBGBXVR(5),
1255 DBGBXVR(6),
1256 DBGBXVR(7),
1257 DBGBXVR(8),
1258 DBGBXVR(9),
1259 DBGBXVR(10),
1260 DBGBXVR(11),
1261 DBGBXVR(12),
1262 DBGBXVR(13),
1263 DBGBXVR(14),
1264 DBGBXVR(15),
1265
1266 /* DBGDSAR (32bit) */
1267 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1268
1269 /* DBGDEVID2 */
1270 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1271 /* DBGDEVID1 */
1272 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1273 /* DBGDEVID */
1274 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1275 /* DBGCLAIMSET */
1276 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1277 /* DBGCLAIMCLR */
1278 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1279 /* DBGAUTHSTATUS */
1280 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
72564016
MZ		 1281};
1282
a9866ba0
MZ		 1283/* Trapped cp14 64bit registers */
1284static const struct sys_reg_desc cp14_64_regs[] = {
bdfb4b38
MZ		 1285 /* DBGDRAR (64bit) */
1286 { Op1( 0), CRm( 1), .access = trap_raz_wi },
1287
1288 /* DBGDSAR (64bit) */
1289 { Op1( 0), CRm( 2), .access = trap_raz_wi },
a9866ba0
MZ		 1290};
1291
051ff581
SZ		 1292/* Macro to expand the PMEVCNTRn register */
1293#define PMU_PMEVCNTR(n) \
1294 /* PMEVCNTRn */ \
1295 { Op1(0), CRn(0b1110), \
1296 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1297 access_pmu_evcntr }
1298
9feb21ac
SZ		 1299/* Macro to expand the PMEVTYPERn register */
1300#define PMU_PMEVTYPER(n) \
1301 /* PMEVTYPERn */ \
1302 { Op1(0), CRn(0b1110), \
1303 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1304 access_pmu_evtyper }
1305
4d44923b
MZ		 1306/*
1307 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
1308 * depending on the way they are accessed (as a 32bit or a 64bit
1309 * register).
1310 */
62a89c44 1311static const struct sys_reg_desc cp15_regs[] = {
6d52f35a
AP		 1312 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
1313
3c1e7165 1314 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
4d44923b
MZ		 1315 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1316 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
1317 { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
1318 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
1319 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
1320 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
1321 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
1322 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
1323 { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
1324 { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
1325
62a89c44
MZ		 1326 /*
1327 * DC{C,I,CI}SW operations:
1328 */
1329 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
1330 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
1331 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
4d44923b 1332
7609c125 1333 /* PMU */
ab946834 1334 { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
96b0eebc
SZ		 1335 { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
1336 { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
76d883c4 1337 { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
7a0adc70 1338 { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
3965c3ce 1339 { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
a86b5505
SZ		 1340 { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
1341 { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
051ff581 1342 { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
9feb21ac 1343 { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
051ff581 1344 { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
d692b8ad 1345 { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr },
9db52c78
SZ		 1346 { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
1347 { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
76d883c4 1348 { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
4d44923b
MZ		 1349
1350 { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
1351 { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
1352 { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
1353 { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
db7dedd0
CD		 1354
1355 /* ICC_SRE */
f7f6f2d9 1356 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
db7dedd0 1357
4d44923b 1358 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
051ff581
SZ		 1359
1360 /* PMEVCNTRn */
1361 PMU_PMEVCNTR(0),
1362 PMU_PMEVCNTR(1),
1363 PMU_PMEVCNTR(2),
1364 PMU_PMEVCNTR(3),
1365 PMU_PMEVCNTR(4),
1366 PMU_PMEVCNTR(5),
1367 PMU_PMEVCNTR(6),
1368 PMU_PMEVCNTR(7),
1369 PMU_PMEVCNTR(8),
1370 PMU_PMEVCNTR(9),
1371 PMU_PMEVCNTR(10),
1372 PMU_PMEVCNTR(11),
1373 PMU_PMEVCNTR(12),
1374 PMU_PMEVCNTR(13),
1375 PMU_PMEVCNTR(14),
1376 PMU_PMEVCNTR(15),
1377 PMU_PMEVCNTR(16),
1378 PMU_PMEVCNTR(17),
1379 PMU_PMEVCNTR(18),
1380 PMU_PMEVCNTR(19),
1381 PMU_PMEVCNTR(20),
1382 PMU_PMEVCNTR(21),
1383 PMU_PMEVCNTR(22),
1384 PMU_PMEVCNTR(23),
1385 PMU_PMEVCNTR(24),
1386 PMU_PMEVCNTR(25),
1387 PMU_PMEVCNTR(26),
1388 PMU_PMEVCNTR(27),
1389 PMU_PMEVCNTR(28),
1390 PMU_PMEVCNTR(29),
1391 PMU_PMEVCNTR(30),
9feb21ac
SZ		 1392 /* PMEVTYPERn */
1393 PMU_PMEVTYPER(0),
1394 PMU_PMEVTYPER(1),
1395 PMU_PMEVTYPER(2),
1396 PMU_PMEVTYPER(3),
1397 PMU_PMEVTYPER(4),
1398 PMU_PMEVTYPER(5),
1399 PMU_PMEVTYPER(6),
1400 PMU_PMEVTYPER(7),
1401 PMU_PMEVTYPER(8),
1402 PMU_PMEVTYPER(9),
1403 PMU_PMEVTYPER(10),
1404 PMU_PMEVTYPER(11),
1405 PMU_PMEVTYPER(12),
1406 PMU_PMEVTYPER(13),
1407 PMU_PMEVTYPER(14),
1408 PMU_PMEVTYPER(15),
1409 PMU_PMEVTYPER(16),
1410 PMU_PMEVTYPER(17),
1411 PMU_PMEVTYPER(18),
1412 PMU_PMEVTYPER(19),
1413 PMU_PMEVTYPER(20),
1414 PMU_PMEVTYPER(21),
1415 PMU_PMEVTYPER(22),
1416 PMU_PMEVTYPER(23),
1417 PMU_PMEVTYPER(24),
1418 PMU_PMEVTYPER(25),
1419 PMU_PMEVTYPER(26),
1420 PMU_PMEVTYPER(27),
1421 PMU_PMEVTYPER(28),
1422 PMU_PMEVTYPER(29),
1423 PMU_PMEVTYPER(30),
1424 /* PMCCFILTR */
1425 { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
a9866ba0
MZ		 1426};
1427
1428static const struct sys_reg_desc cp15_64_regs[] = {
1429 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
051ff581 1430 { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
6d52f35a 1431 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
4d44923b 1432 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
7c8c5e6a
MZ		 1433};
1434
1435/* Target specific emulation tables */
1436static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS];
1437
1438void kvm_register_target_sys_reg_table(unsigned int target,
1439 struct kvm_sys_reg_target_table *table)
1440{
1441 target_tables[target] = table;
1442}
1443
1444/* Get specific register table for this target. */
62a89c44
MZ		 1445static const struct sys_reg_desc *get_target_table(unsigned target,
1446 bool mode_is_64,
1447 size_t *num)
7c8c5e6a
MZ		 1448{
1449 struct kvm_sys_reg_target_table *table;
1450
1451 table = target_tables[target];
62a89c44
MZ		 1452 if (mode_is_64) {
1453 *num = table->table64.num;
1454 return table->table64.table;
1455 } else {
1456 *num = table->table32.num;
1457 return table->table32.table;
1458 }
7c8c5e6a
MZ		 1459}
1460
623eefa8
MZ		 1461#define reg_to_match_value(x) \
1462 ({ \
1463 unsigned long val; \
1464 val = (x)->Op0 << 14; \
1465 val |= (x)->Op1 << 11; \
1466 val |= (x)->CRn << 7; \
1467 val |= (x)->CRm << 3; \
1468 val |= (x)->Op2; \
1469 val; \
1470 })
1471
1472static int match_sys_reg(const void *key, const void *elt)
1473{
1474 const unsigned long pval = (unsigned long)key;
1475 const struct sys_reg_desc *r = elt;
1476
1477 return pval - reg_to_match_value(r);
1478}
1479
7c8c5e6a
MZ		 1480static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
1481 const struct sys_reg_desc table[],
1482 unsigned int num)
1483{
623eefa8
MZ		 1484 unsigned long pval = reg_to_match_value(params);
1485
1486 return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
7c8c5e6a
MZ		 1487}
1488
62a89c44
MZ		 1489int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
1490{
1491 kvm_inject_undefined(vcpu);
1492 return 1;
1493}
1494
72564016
MZ		 1495/*
1496 * emulate_cp -- tries to match a sys_reg access in a handling table, and
1497 * call the corresponding trap handler.
1498 *
1499 * @params: pointer to the descriptor of the access
1500 * @table: array of trap descriptors
1501 * @num: size of the trap descriptor array
1502 *
1503 * Return 0 if the access has been handled, and -1 if not.
1504 */
1505static int emulate_cp(struct kvm_vcpu *vcpu,
3fec037d 1506 struct sys_reg_params *params,
72564016
MZ		 1507 const struct sys_reg_desc *table,
1508 size_t num)
62a89c44 1509{
72564016 1510 const struct sys_reg_desc *r;
62a89c44 1511
72564016
MZ		 1512 if (!table)
1513 return -1; /* Not handled */
62a89c44 1514
62a89c44 1515 r = find_reg(params, table, num);
62a89c44 1516
72564016 1517 if (r) {
62a89c44
MZ		 1518 /*
1519 * Not having an accessor means that we have
1520 * configured a trap that we don't know how to
1521 * handle. This certainly qualifies as a gross bug
1522 * that should be fixed right away.
1523 */
1524 BUG_ON(!r->access);
1525
1526 if (likely(r->access(vcpu, params, r))) {
1527 /* Skip instruction, since it was emulated */
1528 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
6327f35a
SZ		 1529 /* Handled */
1530 return 0;
62a89c44 1531 }
72564016
MZ		 1532 }
1533
1534 /* Not handled */
1535 return -1;
1536}
1537
1538static void unhandled_cp_access(struct kvm_vcpu *vcpu,
1539 struct sys_reg_params *params)
1540{
1541 u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
40c4f8d2 1542 int cp = -1;
72564016
MZ		 1543
1544 switch(hsr_ec) {
c6d01a94
MR		 1545 case ESR_ELx_EC_CP15_32:
1546 case ESR_ELx_EC_CP15_64:
72564016
MZ		 1547 cp = 15;
1548 break;
c6d01a94
MR		 1549 case ESR_ELx_EC_CP14_MR:
1550 case ESR_ELx_EC_CP14_64:
72564016
MZ		 1551 cp = 14;
1552 break;
1553 default:
40c4f8d2 1554 WARN_ON(1);
62a89c44
MZ		 1555 }
1556
72564016
MZ		 1557 kvm_err("Unsupported guest CP%d access at: %08lx\n",
1558 cp, *vcpu_pc(vcpu));
62a89c44
MZ		 1559 print_sys_reg_instr(params);
1560 kvm_inject_undefined(vcpu);
1561}
1562
1563/**
7769db90 1564 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
62a89c44
MZ		 1565 * @vcpu: The VCPU pointer
1566 * @run: The kvm_run struct
1567 */
72564016
MZ		 1568static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
1569 const struct sys_reg_desc *global,
1570 size_t nr_global,
1571 const struct sys_reg_desc *target_specific,
1572 size_t nr_specific)
62a89c44
MZ		 1573{
1574 struct sys_reg_params params;
1575 u32 hsr = kvm_vcpu_get_hsr(vcpu);
2ec5be3d 1576 int Rt = (hsr >> 5) & 0xf;
62a89c44
MZ		 1577 int Rt2 = (hsr >> 10) & 0xf;
1578
2072d29c
MZ		 1579 params.is_aarch32 = true;
1580 params.is_32bit = false;
62a89c44 1581 params.CRm = (hsr >> 1) & 0xf;
62a89c44
MZ		 1582 params.is_write = ((hsr & 1) == 0);
1583
1584 params.Op0 = 0;
1585 params.Op1 = (hsr >> 16) & 0xf;
1586 params.Op2 = 0;
1587 params.CRn = 0;
1588
1589 /*
2ec5be3d 1590 * Make a 64-bit value out of Rt and Rt2. As we use the same trap
62a89c44
MZ		 1591 * backends between AArch32 and AArch64, we get away with it.
1592 */
1593 if (params.is_write) {
2ec5be3d
PF		 1594 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
1595 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
62a89c44
MZ		 1596 }
1597
72564016
MZ		 1598 if (!emulate_cp(vcpu, &params, target_specific, nr_specific))
1599 goto out;
1600 if (!emulate_cp(vcpu, &params, global, nr_global))
1601 goto out;
1602
1603 unhandled_cp_access(vcpu, &params);
62a89c44 1604
72564016 1605out:
2ec5be3d 1606 /* Split up the value between registers for the read side */
62a89c44 1607 if (!params.is_write) {
2ec5be3d
PF		 1608 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
1609 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
62a89c44
MZ		 1610 }
1611
1612 return 1;
1613}
1614
1615/**
7769db90 1616 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
62a89c44
MZ		 1617 * @vcpu: The VCPU pointer
1618 * @run: The kvm_run struct
1619 */
72564016
MZ		 1620static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
1621 const struct sys_reg_desc *global,
1622 size_t nr_global,
1623 const struct sys_reg_desc *target_specific,
1624 size_t nr_specific)
62a89c44
MZ		 1625{
1626 struct sys_reg_params params;
1627 u32 hsr = kvm_vcpu_get_hsr(vcpu);
2ec5be3d 1628 int Rt = (hsr >> 5) & 0xf;
62a89c44 1629
2072d29c
MZ		 1630 params.is_aarch32 = true;
1631 params.is_32bit = true;
62a89c44 1632 params.CRm = (hsr >> 1) & 0xf;
2ec5be3d 1633 params.regval = vcpu_get_reg(vcpu, Rt);
62a89c44
MZ		 1634 params.is_write = ((hsr & 1) == 0);
1635 params.CRn = (hsr >> 10) & 0xf;
1636 params.Op0 = 0;
1637 params.Op1 = (hsr >> 14) & 0x7;
1638 params.Op2 = (hsr >> 17) & 0x7;
1639
2ec5be3d
PF		 1640 if (!emulate_cp(vcpu, &params, target_specific, nr_specific) ||
1641 !emulate_cp(vcpu, &params, global, nr_global)) {
1642 if (!params.is_write)
1643 vcpu_set_reg(vcpu, Rt, params.regval);
72564016 1644 return 1;
2ec5be3d 1645 }
72564016
MZ		 1646
1647 unhandled_cp_access(vcpu, &params);
62a89c44
MZ		 1648 return 1;
1649}
1650
72564016
MZ		 1651int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
1652{
1653 const struct sys_reg_desc *target_specific;
1654 size_t num;
1655
1656 target_specific = get_target_table(vcpu->arch.target, false, &num);
1657 return kvm_handle_cp_64(vcpu,
a9866ba0 1658 cp15_64_regs, ARRAY_SIZE(cp15_64_regs),
72564016
MZ		 1659 target_specific, num);
1660}
1661
1662int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
1663{
1664 const struct sys_reg_desc *target_specific;
1665 size_t num;
1666
1667 target_specific = get_target_table(vcpu->arch.target, false, &num);
1668 return kvm_handle_cp_32(vcpu,
1669 cp15_regs, ARRAY_SIZE(cp15_regs),
1670 target_specific, num);
1671}
1672
1673int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
1674{
1675 return kvm_handle_cp_64(vcpu,
a9866ba0 1676 cp14_64_regs, ARRAY_SIZE(cp14_64_regs),
72564016
MZ		 1677 NULL, 0);
1678}
1679
1680int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
1681{
1682 return kvm_handle_cp_32(vcpu,
1683 cp14_regs, ARRAY_SIZE(cp14_regs),
1684 NULL, 0);
1685}
1686
7c8c5e6a 1687static int emulate_sys_reg(struct kvm_vcpu *vcpu,
3fec037d 1688 struct sys_reg_params *params)
7c8c5e6a
MZ		 1689{
1690 size_t num;
1691 const struct sys_reg_desc *table, *r;
1692
62a89c44 1693 table = get_target_table(vcpu->arch.target, true, &num);
7c8c5e6a
MZ		 1694
1695 /* Search target-specific then generic table. */
1696 r = find_reg(params, table, num);
1697 if (!r)
1698 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1699
1700 if (likely(r)) {
1701 /*
1702 * Not having an accessor means that we have
1703 * configured a trap that we don't know how to
1704 * handle. This certainly qualifies as a gross bug
1705 * that should be fixed right away.
1706 */
1707 BUG_ON(!r->access);
1708
1709 if (likely(r->access(vcpu, params, r))) {
1710 /* Skip instruction, since it was emulated */
1711 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
1712 return 1;
1713 }
1714 /* If access function fails, it should complain. */
1715 } else {
1716 kvm_err("Unsupported guest sys_reg access at: %lx\n",
1717 *vcpu_pc(vcpu));
1718 print_sys_reg_instr(params);
1719 }
1720 kvm_inject_undefined(vcpu);
1721 return 1;
1722}
1723
1724static void reset_sys_reg_descs(struct kvm_vcpu *vcpu,
1725 const struct sys_reg_desc *table, size_t num)
1726{
1727 unsigned long i;
1728
1729 for (i = 0; i < num; i++)
1730 if (table[i].reset)
1731 table[i].reset(vcpu, &table[i]);
1732}
1733
1734/**
1735 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
1736 * @vcpu: The VCPU pointer
1737 * @run: The kvm_run struct
1738 */
1739int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run)
1740{
1741 struct sys_reg_params params;
1742 unsigned long esr = kvm_vcpu_get_hsr(vcpu);
2ec5be3d
PF		 1743 int Rt = (esr >> 5) & 0x1f;
1744 int ret;
7c8c5e6a 1745
eef8c85a
AB		 1746 trace_kvm_handle_sys_reg(esr);
1747
2072d29c
MZ		 1748 params.is_aarch32 = false;
1749 params.is_32bit = false;
7c8c5e6a
MZ		 1750 params.Op0 = (esr >> 20) & 3;
1751 params.Op1 = (esr >> 14) & 0x7;
1752 params.CRn = (esr >> 10) & 0xf;
1753 params.CRm = (esr >> 1) & 0xf;
1754 params.Op2 = (esr >> 17) & 0x7;
2ec5be3d 1755 params.regval = vcpu_get_reg(vcpu, Rt);
7c8c5e6a
MZ		 1756 params.is_write = !(esr & 1);
1757
2ec5be3d
PF		 1758 ret = emulate_sys_reg(vcpu, &params);
1759
1760 if (!params.is_write)
1761 vcpu_set_reg(vcpu, Rt, params.regval);
1762 return ret;
7c8c5e6a
MZ		 1763}
1764
1765/******************************************************************************
1766 * Userspace API
1767 *****************************************************************************/
1768
1769static bool index_to_params(u64 id, struct sys_reg_params *params)
1770{
1771 switch (id & KVM_REG_SIZE_MASK) {
1772 case KVM_REG_SIZE_U64:
1773 /* Any unused index bits means it's not valid. */
1774 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
1775 | KVM_REG_ARM_COPROC_MASK
1776 | KVM_REG_ARM64_SYSREG_OP0_MASK
1777 | KVM_REG_ARM64_SYSREG_OP1_MASK
1778 | KVM_REG_ARM64_SYSREG_CRN_MASK
1779 | KVM_REG_ARM64_SYSREG_CRM_MASK
1780 | KVM_REG_ARM64_SYSREG_OP2_MASK))
1781 return false;
1782 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
1783 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
1784 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
1785 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
1786 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
1787 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
1788 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
1789 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
1790 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
1791 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
1792 return true;
1793 default:
1794 return false;
1795 }
1796}
1797
1798/* Decode an index value, and find the sys_reg_desc entry. */
1799static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
1800 u64 id)
1801{
1802 size_t num;
1803 const struct sys_reg_desc *table, *r;
1804 struct sys_reg_params params;
1805
1806 /* We only do sys_reg for now. */
1807 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
1808 return NULL;
1809
1810 if (!index_to_params(id, &params))
1811 return NULL;
1812
62a89c44 1813 table = get_target_table(vcpu->arch.target, true, &num);
7c8c5e6a
MZ		 1814 r = find_reg(&params, table, num);
1815 if (!r)
1816 r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1817
1818 /* Not saved in the sys_reg array? */
1819 if (r && !r->reg)
1820 r = NULL;
1821
1822 return r;
1823}
1824
1825/*
1826 * These are the invariant sys_reg registers: we let the guest see the
1827 * host versions of these, so they're part of the guest state.
1828 *
1829 * A future CPU may provide a mechanism to present different values to
1830 * the guest, or a future kvm may trap them.
1831 */
1832
1833#define FUNCTION_INVARIANT(reg) \
1834 static void get_##reg(struct kvm_vcpu *v, \
1835 const struct sys_reg_desc *r) \
1836 { \
1f3d8699 1837 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \
7c8c5e6a
MZ		 1838 }
1839
1840FUNCTION_INVARIANT(midr_el1)
1841FUNCTION_INVARIANT(ctr_el0)
1842FUNCTION_INVARIANT(revidr_el1)
1843FUNCTION_INVARIANT(id_pfr0_el1)
1844FUNCTION_INVARIANT(id_pfr1_el1)
1845FUNCTION_INVARIANT(id_dfr0_el1)
1846FUNCTION_INVARIANT(id_afr0_el1)
1847FUNCTION_INVARIANT(id_mmfr0_el1)
1848FUNCTION_INVARIANT(id_mmfr1_el1)
1849FUNCTION_INVARIANT(id_mmfr2_el1)
1850FUNCTION_INVARIANT(id_mmfr3_el1)
1851FUNCTION_INVARIANT(id_isar0_el1)
1852FUNCTION_INVARIANT(id_isar1_el1)
1853FUNCTION_INVARIANT(id_isar2_el1)
1854FUNCTION_INVARIANT(id_isar3_el1)
1855FUNCTION_INVARIANT(id_isar4_el1)
1856FUNCTION_INVARIANT(id_isar5_el1)
1857FUNCTION_INVARIANT(clidr_el1)
1858FUNCTION_INVARIANT(aidr_el1)
1859
1860/* ->val is filled in by kvm_sys_reg_table_init() */
1861static struct sys_reg_desc invariant_sys_regs[] = {
1862 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b000),
1863 NULL, get_midr_el1 },
1864 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b110),
1865 NULL, get_revidr_el1 },
1866 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b000),
1867 NULL, get_id_pfr0_el1 },
1868 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b001),
1869 NULL, get_id_pfr1_el1 },
1870 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b010),
1871 NULL, get_id_dfr0_el1 },
1872 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b011),
1873 NULL, get_id_afr0_el1 },
1874 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b100),
1875 NULL, get_id_mmfr0_el1 },
1876 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b101),
1877 NULL, get_id_mmfr1_el1 },
1878 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b110),
1879 NULL, get_id_mmfr2_el1 },
1880 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b111),
1881 NULL, get_id_mmfr3_el1 },
1882 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
1883 NULL, get_id_isar0_el1 },
1884 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b001),
1885 NULL, get_id_isar1_el1 },
1886 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
1887 NULL, get_id_isar2_el1 },
1888 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b011),
1889 NULL, get_id_isar3_el1 },
1890 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b100),
1891 NULL, get_id_isar4_el1 },
1892 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b101),
1893 NULL, get_id_isar5_el1 },
1894 { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b001),
1895 NULL, get_clidr_el1 },
1896 { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b111),
1897 NULL, get_aidr_el1 },
1898 { Op0(0b11), Op1(0b011), CRn(0b0000), CRm(0b0000), Op2(0b001),
1899 NULL, get_ctr_el0 },
1900};
1901
26c99af1 1902static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
7c8c5e6a 1903{
7c8c5e6a
MZ		 1904 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
1905 return -EFAULT;
1906 return 0;
1907}
1908
26c99af1 1909static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
7c8c5e6a 1910{
7c8c5e6a
MZ		 1911 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
1912 return -EFAULT;
1913 return 0;
1914}
1915
1916static int get_invariant_sys_reg(u64 id, void __user *uaddr)
1917{
1918 struct sys_reg_params params;
1919 const struct sys_reg_desc *r;
1920
1921 if (!index_to_params(id, &params))
1922 return -ENOENT;
1923
1924 r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
1925 if (!r)
1926 return -ENOENT;
1927
1928 return reg_to_user(uaddr, &r->val, id);
1929}
1930
1931static int set_invariant_sys_reg(u64 id, void __user *uaddr)
1932{
1933 struct sys_reg_params params;
1934 const struct sys_reg_desc *r;
1935 int err;
1936 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
1937
1938 if (!index_to_params(id, &params))
1939 return -ENOENT;
1940 r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
1941 if (!r)
1942 return -ENOENT;
1943
1944 err = reg_from_user(&val, uaddr, id);
1945 if (err)
1946 return err;
1947
1948 /* This is what we mean by invariant: you can't change it. */
1949 if (r->val != val)
1950 return -EINVAL;
1951
1952 return 0;
1953}
1954
1955static bool is_valid_cache(u32 val)
1956{
1957 u32 level, ctype;
1958
1959 if (val >= CSSELR_MAX)
18d45766 1960 return false;
7c8c5e6a
MZ		 1961
1962 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
1963 level = (val >> 1);
1964 ctype = (cache_levels >> (level * 3)) & 7;
1965
1966 switch (ctype) {
1967 case 0: /* No cache */
1968 return false;
1969 case 1: /* Instruction cache only */
1970 return (val & 1);
1971 case 2: /* Data cache only */
1972 case 4: /* Unified cache */
1973 return !(val & 1);
1974 case 3: /* Separate instruction and data caches */
1975 return true;
1976 default: /* Reserved: we can't know instruction or data. */
1977 return false;
1978 }
1979}
1980
1981static int demux_c15_get(u64 id, void __user *uaddr)
1982{
1983 u32 val;
1984 u32 __user *uval = uaddr;
1985
1986 /* Fail if we have unknown bits set. */
1987 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
1988 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
1989 return -ENOENT;
1990
1991 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
1992 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
1993 if (KVM_REG_SIZE(id) != 4)
1994 return -ENOENT;
1995 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
1996 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
1997 if (!is_valid_cache(val))
1998 return -ENOENT;
1999
2000 return put_user(get_ccsidr(val), uval);
2001 default:
2002 return -ENOENT;
2003 }
2004}
2005
2006static int demux_c15_set(u64 id, void __user *uaddr)
2007{
2008 u32 val, newval;
2009 u32 __user *uval = uaddr;
2010
2011 /* Fail if we have unknown bits set. */
2012 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2013 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2014 return -ENOENT;
2015
2016 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2017 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2018 if (KVM_REG_SIZE(id) != 4)
2019 return -ENOENT;
2020 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2021 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2022 if (!is_valid_cache(val))
2023 return -ENOENT;
2024
2025 if (get_user(newval, uval))
2026 return -EFAULT;
2027
2028 /* This is also invariant: you can't change it. */
2029 if (newval != get_ccsidr(val))
2030 return -EINVAL;
2031 return 0;
2032 default:
2033 return -ENOENT;
2034 }
2035}
2036
2037int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2038{
2039 const struct sys_reg_desc *r;
2040 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2041
2042 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2043 return demux_c15_get(reg->id, uaddr);
2044
2045 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2046 return -ENOENT;
2047
2048 r = index_to_sys_reg_desc(vcpu, reg->id);
2049 if (!r)
2050 return get_invariant_sys_reg(reg->id, uaddr);
2051
84e690bf
AB		 2052 if (r->get_user)
2053 return (r->get_user)(vcpu, r, reg, uaddr);
2054
7c8c5e6a
MZ		 2055 return reg_to_user(uaddr, &vcpu_sys_reg(vcpu, r->reg), reg->id);
2056}
2057
2058int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2059{
2060 const struct sys_reg_desc *r;
2061 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2062
2063 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2064 return demux_c15_set(reg->id, uaddr);
2065
2066 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2067 return -ENOENT;
2068
2069 r = index_to_sys_reg_desc(vcpu, reg->id);
2070 if (!r)
2071 return set_invariant_sys_reg(reg->id, uaddr);
2072
84e690bf
AB		 2073 if (r->set_user)
2074 return (r->set_user)(vcpu, r, reg, uaddr);
2075
7c8c5e6a
MZ		 2076 return reg_from_user(&vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
2077}
2078
2079static unsigned int num_demux_regs(void)
2080{
2081 unsigned int i, count = 0;
2082
2083 for (i = 0; i < CSSELR_MAX; i++)
2084 if (is_valid_cache(i))
2085 count++;
2086
2087 return count;
2088}
2089
2090static int write_demux_regids(u64 __user *uindices)
2091{
efd48cea 2092 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
7c8c5e6a
MZ		 2093 unsigned int i;
2094
2095 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
2096 for (i = 0; i < CSSELR_MAX; i++) {
2097 if (!is_valid_cache(i))
2098 continue;
2099 if (put_user(val | i, uindices))
2100 return -EFAULT;
2101 uindices++;
2102 }
2103 return 0;
2104}
2105
2106static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
2107{
2108 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
2109 KVM_REG_ARM64_SYSREG |
2110 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
2111 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
2112 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
2113 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
2114 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
2115}
2116
2117static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
2118{
2119 if (!*uind)
2120 return true;
2121
2122 if (put_user(sys_reg_to_index(reg), *uind))
2123 return false;
2124
2125 (*uind)++;
2126 return true;
2127}
2128
2129/* Assumed ordered tables, see kvm_sys_reg_table_init. */
2130static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
2131{
2132 const struct sys_reg_desc *i1, *i2, *end1, *end2;
2133 unsigned int total = 0;
2134 size_t num;
2135
2136 /* We check for duplicates here, to allow arch-specific overrides. */
62a89c44 2137 i1 = get_target_table(vcpu->arch.target, true, &num);
7c8c5e6a
MZ		 2138 end1 = i1 + num;
2139 i2 = sys_reg_descs;
2140 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
2141
2142 BUG_ON(i1 == end1 || i2 == end2);
2143
2144 /* Walk carefully, as both tables may refer to the same register. */
2145 while (i1 || i2) {
2146 int cmp = cmp_sys_reg(i1, i2);
2147 /* target-specific overrides generic entry. */
2148 if (cmp <= 0) {
2149 /* Ignore registers we trap but don't save. */
2150 if (i1->reg) {
2151 if (!copy_reg_to_user(i1, &uind))
2152 return -EFAULT;
2153 total++;
2154 }
2155 } else {
2156 /* Ignore registers we trap but don't save. */
2157 if (i2->reg) {
2158 if (!copy_reg_to_user(i2, &uind))
2159 return -EFAULT;
2160 total++;
2161 }
2162 }
2163
2164 if (cmp <= 0 && ++i1 == end1)
2165 i1 = NULL;
2166 if (cmp >= 0 && ++i2 == end2)
2167 i2 = NULL;
2168 }
2169 return total;
2170}
2171
2172unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
2173{
2174 return ARRAY_SIZE(invariant_sys_regs)
2175 + num_demux_regs()
2176 + walk_sys_regs(vcpu, (u64 __user *)NULL);
2177}
2178
2179int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
2180{
2181 unsigned int i;
2182 int err;
2183
2184 /* Then give them all the invariant registers' indices. */
2185 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
2186 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
2187 return -EFAULT;
2188 uindices++;
2189 }
2190
2191 err = walk_sys_regs(vcpu, uindices);
2192 if (err < 0)
2193 return err;
2194 uindices += err;
2195
2196 return write_demux_regids(uindices);
2197}
2198
e6a95517
MZ		 2199static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n)
2200{
2201 unsigned int i;
2202
2203 for (i = 1; i < n; i++) {
2204 if (cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2205 kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
2206 return 1;
2207 }
2208 }
2209
2210 return 0;
2211}
2212
7c8c5e6a
MZ		 2213void kvm_sys_reg_table_init(void)
2214{
2215 unsigned int i;
2216 struct sys_reg_desc clidr;
2217
2218 /* Make sure tables are unique and in order. */
e6a95517
MZ		 2219 BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs)));
2220 BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs)));
2221 BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs)));
2222 BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs)));
2223 BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs)));
2224 BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs)));
7c8c5e6a
MZ		 2225
2226 /* We abuse the reset function to overwrite the table itself. */
2227 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
2228 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
2229
2230 /*
2231 * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
2232 *
2233 * If software reads the Cache Type fields from Ctype1
2234 * upwards, once it has seen a value of 0b000, no caches
2235 * exist at further-out levels of the hierarchy. So, for
2236 * example, if Ctype3 is the first Cache Type field with a
2237 * value of 0b000, the values of Ctype4 to Ctype7 must be
2238 * ignored.
2239 */
2240 get_clidr_el1(NULL, &clidr); /* Ugly... */
2241 cache_levels = clidr.val;
2242 for (i = 0; i < 7; i++)
2243 if (((cache_levels >> (i*3)) & 7) == 0)
2244 break;
2245 /* Clear all higher bits. */
2246 cache_levels &= (1 << (i*3))-1;
2247}
2248
2249/**
2250 * kvm_reset_sys_regs - sets system registers to reset value
2251 * @vcpu: The VCPU pointer
2252 *
2253 * This function finds the right table above and sets the registers on the
2254 * virtual CPU struct to their architecturally defined reset values.
2255 */
2256void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
2257{
2258 size_t num;
2259 const struct sys_reg_desc *table;
2260
2261 /* Catch someone adding a register without putting in reset entry. */
2262 memset(&vcpu->arch.ctxt.sys_regs, 0x42, sizeof(vcpu->arch.ctxt.sys_regs));
2263
2264 /* Generic chip reset first (so target could override). */
2265 reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2266
62a89c44 2267 table = get_target_table(vcpu->arch.target, true, &num);
7c8c5e6a
MZ		 2268 reset_sys_reg_descs(vcpu, table, num);
2269
2270 for (num = 1; num < NR_SYS_REGS; num++)
2271 if (vcpu_sys_reg(vcpu, num) == 0x4242424242424242)
2272 panic("Didn't reset vcpu_sys_reg(%zi)", num);
2273}
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