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KVM: arm64: Set CSV2 for guests on hardware unaffected by Spectre-v2
[mirror_ubuntu-jammy-kernel.git] / arch / arm64 / kvm / sys_regs.c
CommitLineData
caab277b 1// SPDX-License-Identifier: GPL-2.0-only
7c8c5e6a
MZ		 2/*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/kvm/coproc.c:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Authors: Rusty Russell <rusty@rustcorp.com.au>
9 * Christoffer Dall <c.dall@virtualopensystems.com>
7c8c5e6a
MZ		 10 */
11
623eefa8 12#include <linux/bsearch.h>
7c8c5e6a 13#include <linux/kvm_host.h>
c6d01a94 14#include <linux/mm.h>
07d79fe7 15#include <linux/printk.h>
7c8c5e6a 16#include <linux/uaccess.h>
c6d01a94 17
7c8c5e6a
MZ		 18#include <asm/cacheflush.h>
19#include <asm/cputype.h>
0c557ed4 20#include <asm/debug-monitors.h>
c6d01a94
MR		 21#include <asm/esr.h>
22#include <asm/kvm_arm.h>
23#include <asm/kvm_coproc.h>
24#include <asm/kvm_emulate.h>
d47533da 25#include <asm/kvm_hyp.h>
c6d01a94 26#include <asm/kvm_mmu.h>
ab946834 27#include <asm/perf_event.h>
1f3d8699 28#include <asm/sysreg.h>
c6d01a94 29
7c8c5e6a
MZ		 30#include <trace/events/kvm.h>
31
32#include "sys_regs.h"
33
eef8c85a
AB		 34#include "trace.h"
35
7c8c5e6a 36/*
656012c7 37 * All of this file is extremely similar to the ARM coproc.c, but the
7c8c5e6a
MZ		 38 * types are different. My gut feeling is that it should be pretty
39 * easy to merge, but that would be an ABI breakage -- again. VFP
40 * would also need to be abstracted.
62a89c44
MZ		 41 *
42 * For AArch32, we only take care of what is being trapped. Anything
43 * that has to do with init and userspace access has to go via the
44 * 64bit interface.
7c8c5e6a
MZ		 45 */
46
7b5b4df1 47static bool read_from_write_only(struct kvm_vcpu *vcpu,
e7f1d1ee
MZ		 48 struct sys_reg_params *params,
49 const struct sys_reg_desc *r)
7b5b4df1
MZ		 50{
51 WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n");
52 print_sys_reg_instr(params);
53 kvm_inject_undefined(vcpu);
54 return false;
55}
56
7b1dba1f
MZ		 57static bool write_to_read_only(struct kvm_vcpu *vcpu,
58 struct sys_reg_params *params,
59 const struct sys_reg_desc *r)
60{
61 WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n");
62 print_sys_reg_instr(params);
63 kvm_inject_undefined(vcpu);
64 return false;
65}
66
7ea90bdd 67static bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val)
d47533da 68{
d47533da
CD		 69 /*
70 * System registers listed in the switch are not saved on every
71 * exit from the guest but are only saved on vcpu_put.
fc7563b3
CD		 72 *
73 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
74 * should never be listed below, because the guest cannot modify its
75 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's
76 * thread when emulating cross-VCPU communication.
d47533da
CD		 77 */
78 switch (reg) {
7ea90bdd
MZ		 79 case CSSELR_EL1: *val = read_sysreg_s(SYS_CSSELR_EL1); break;
80 case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break;
7ea90bdd
MZ		 81 case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break;
82 case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break;
83 case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break;
84 case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break;
85 case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break;
86 case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break;
87 case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break;
88 case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break;
89 case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break;
90 case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break;
91 case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break;
92 case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break;
93 case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break;
94 case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break;
95 case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break;
96 case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break;
98909e6d 97 case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break;
7ea90bdd
MZ		 98 case PAR_EL1: *val = read_sysreg_s(SYS_PAR_EL1); break;
99 case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break;
100 case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break;
101 case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break;
102 default: return false;
d47533da
CD		 103 }
104
7ea90bdd 105 return true;
d47533da
CD		 106}
107
7ea90bdd 108static bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg)
d47533da 109{
d47533da
CD		 110 /*
111 * System registers listed in the switch are not restored on every
112 * entry to the guest but are only restored on vcpu_load.
fc7563b3
CD		 113 *
114 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
656012c7
FT		 115 * should never be listed below, because the MPIDR should only be set
116 * once, before running the VCPU, and never changed later.
d47533da
CD		 117 */
118 switch (reg) {
7ea90bdd
MZ		 119 case CSSELR_EL1: write_sysreg_s(val, SYS_CSSELR_EL1); break;
120 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break;
7ea90bdd
MZ		 121 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break;
122 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break;
123 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break;
124 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break;
125 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break;
126 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break;
127 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break;
128 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break;
129 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break;
130 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break;
131 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break;
132 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break;
133 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break;
134 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break;
135 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break;
136 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break;
98909e6d 137 case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break;
7ea90bdd
MZ		 138 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break;
139 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break;
140 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break;
141 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break;
142 default: return false;
d47533da
CD		 143 }
144
7ea90bdd
MZ		 145 return true;
146}
147
148u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
149{
150 u64 val = 0x8badf00d8badf00d;
151
152 if (vcpu->arch.sysregs_loaded_on_cpu &&
153 __vcpu_read_sys_reg_from_cpu(reg, &val))
154 return val;
155
156 return __vcpu_sys_reg(vcpu, reg);
157}
158
159void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
160{
161 if (vcpu->arch.sysregs_loaded_on_cpu &&
162 __vcpu_write_sys_reg_to_cpu(val, reg))
163 return;
164
d47533da
CD		 165 __vcpu_sys_reg(vcpu, reg) = val;
166}
167
7c8c5e6a
MZ		 168/* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
169static u32 cache_levels;
170
171/* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
172#define CSSELR_MAX 12
173
174/* Which cache CCSIDR represents depends on CSSELR value. */
175static u32 get_ccsidr(u32 csselr)
176{
177 u32 ccsidr;
178
179 /* Make sure noone else changes CSSELR during this! */
180 local_irq_disable();
1f3d8699 181 write_sysreg(csselr, csselr_el1);
7c8c5e6a 182 isb();
1f3d8699 183 ccsidr = read_sysreg(ccsidr_el1);
7c8c5e6a
MZ		 184 local_irq_enable();
185
186 return ccsidr;
187}
188
3c1e7165
MZ		 189/*
190 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
191 */
7c8c5e6a 192static bool access_dcsw(struct kvm_vcpu *vcpu,
3fec037d 193 struct sys_reg_params *p,
7c8c5e6a
MZ		 194 const struct sys_reg_desc *r)
195{
7c8c5e6a 196 if (!p->is_write)
e7f1d1ee 197 return read_from_write_only(vcpu, p, r);
7c8c5e6a 198
09605e94
MZ		 199 /*
200 * Only track S/W ops if we don't have FWB. It still indicates
201 * that the guest is a bit broken (S/W operations should only
202 * be done by firmware, knowing that there is only a single
203 * CPU left in the system, and certainly not from non-secure
204 * software).
205 */
206 if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
207 kvm_set_way_flush(vcpu);
208
7c8c5e6a
MZ		 209 return true;
210}
211
4d44923b
MZ		 212/*
213 * Generic accessor for VM registers. Only called as long as HCR_TVM
3c1e7165
MZ		 214 * is set. If the guest enables the MMU, we stop trapping the VM
215 * sys_regs and leave it in complete control of the caches.
4d44923b
MZ		 216 */
217static bool access_vm_reg(struct kvm_vcpu *vcpu,
3fec037d 218 struct sys_reg_params *p,
4d44923b
MZ		 219 const struct sys_reg_desc *r)
220{
3c1e7165 221 bool was_enabled = vcpu_has_cache_enabled(vcpu);
52f6c4f0
CD		 222 u64 val;
223 int reg = r->reg;
4d44923b
MZ		 224
225 BUG_ON(!p->is_write);
226
52f6c4f0
CD		 227 /* See the 32bit mapping in kvm_host.h */
228 if (p->is_aarch32)
229 reg = r->reg / 2;
230
231 if (!p->is_aarch32 || !p->is_32bit) {
232 val = p->regval;
dedf97e8 233 } else {
8d404c4c 234 val = vcpu_read_sys_reg(vcpu, reg);
52f6c4f0
CD		 235 if (r->reg % 2)
236 val = (p->regval << 32) | (u64)lower_32_bits(val);
237 else
238 val = ((u64)upper_32_bits(val) << 32) |
239 lower_32_bits(p->regval);
dedf97e8 240 }
8d404c4c 241 vcpu_write_sys_reg(vcpu, val, reg);
f0a3eaff 242
3c1e7165 243 kvm_toggle_cache(vcpu, was_enabled);
4d44923b
MZ		 244 return true;
245}
246
af473829
JM		 247static bool access_actlr(struct kvm_vcpu *vcpu,
248 struct sys_reg_params *p,
249 const struct sys_reg_desc *r)
250{
251 if (p->is_write)
252 return ignore_write(vcpu, p);
253
254 p->regval = vcpu_read_sys_reg(vcpu, ACTLR_EL1);
255
256 if (p->is_aarch32) {
257 if (r->Op2 & 2)
258 p->regval = upper_32_bits(p->regval);
259 else
260 p->regval = lower_32_bits(p->regval);
261 }
262
263 return true;
264}
265
6d52f35a
AP		 266/*
267 * Trap handler for the GICv3 SGI generation system register.
268 * Forward the request to the VGIC emulation.
269 * The cp15_64 code makes sure this automatically works
270 * for both AArch64 and AArch32 accesses.
271 */
272static bool access_gic_sgi(struct kvm_vcpu *vcpu,
3fec037d 273 struct sys_reg_params *p,
6d52f35a
AP		 274 const struct sys_reg_desc *r)
275{
03bd646d
MZ		 276 bool g1;
277
6d52f35a 278 if (!p->is_write)
e7f1d1ee 279 return read_from_write_only(vcpu, p, r);
6d52f35a 280
03bd646d
MZ		 281 /*
282 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates
283 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group,
284 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively
285 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure
286 * group.
287 */
288 if (p->is_aarch32) {
289 switch (p->Op1) {
290 default: /* Keep GCC quiet */
291 case 0: /* ICC_SGI1R */
292 g1 = true;
293 break;
294 case 1: /* ICC_ASGI1R */
295 case 2: /* ICC_SGI0R */
296 g1 = false;
297 break;
298 }
299 } else {
300 switch (p->Op2) {
301 default: /* Keep GCC quiet */
302 case 5: /* ICC_SGI1R_EL1 */
303 g1 = true;
304 break;
305 case 6: /* ICC_ASGI1R_EL1 */
306 case 7: /* ICC_SGI0R_EL1 */
307 g1 = false;
308 break;
309 }
310 }
311
312 vgic_v3_dispatch_sgi(vcpu, p->regval, g1);
6d52f35a
AP		 313
314 return true;
315}
316
b34f2bcb
MZ		 317static bool access_gic_sre(struct kvm_vcpu *vcpu,
318 struct sys_reg_params *p,
319 const struct sys_reg_desc *r)
320{
321 if (p->is_write)
322 return ignore_write(vcpu, p);
323
324 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
325 return true;
326}
327
7609c125 328static bool trap_raz_wi(struct kvm_vcpu *vcpu,
3fec037d 329 struct sys_reg_params *p,
7609c125 330 const struct sys_reg_desc *r)
7c8c5e6a
MZ		 331{
332 if (p->is_write)
333 return ignore_write(vcpu, p);
334 else
335 return read_zero(vcpu, p);
336}
337
22925521
MZ		 338/*
339 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the
340 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0
341 * system, these registers should UNDEF. LORID_EL1 being a RO register, we
342 * treat it separately.
343 */
344static bool trap_loregion(struct kvm_vcpu *vcpu,
345 struct sys_reg_params *p,
346 const struct sys_reg_desc *r)
cc33c4e2 347{
22925521
MZ		 348 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
349 u32 sr = sys_reg((u32)r->Op0, (u32)r->Op1,
350 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
351
352 if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) {
353 kvm_inject_undefined(vcpu);
354 return false;
355 }
356
357 if (p->is_write && sr == SYS_LORID_EL1)
358 return write_to_read_only(vcpu, p, r);
359
360 return trap_raz_wi(vcpu, p, r);
cc33c4e2
MR		 361}
362
0c557ed4 363static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
3fec037d 364 struct sys_reg_params *p,
0c557ed4
MZ		 365 const struct sys_reg_desc *r)
366{
367 if (p->is_write) {
368 return ignore_write(vcpu, p);
369 } else {
2ec5be3d 370 p->regval = (1 << 3);
0c557ed4
MZ		 371 return true;
372 }
373}
374
375static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
3fec037d 376 struct sys_reg_params *p,
0c557ed4
MZ		 377 const struct sys_reg_desc *r)
378{
379 if (p->is_write) {
380 return ignore_write(vcpu, p);
381 } else {
1f3d8699 382 p->regval = read_sysreg(dbgauthstatus_el1);
0c557ed4
MZ		 383 return true;
384 }
385}
386
387/*
388 * We want to avoid world-switching all the DBG registers all the
389 * time:
390 *
391 * - If we've touched any debug register, it is likely that we're
392 * going to touch more of them. It then makes sense to disable the
393 * traps and start doing the save/restore dance
394 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
395 * then mandatory to save/restore the registers, as the guest
396 * depends on them.
397 *
398 * For this, we use a DIRTY bit, indicating the guest has modified the
399 * debug registers, used as follow:
400 *
401 * On guest entry:
402 * - If the dirty bit is set (because we're coming back from trapping),
403 * disable the traps, save host registers, restore guest registers.
404 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
405 * set the dirty bit, disable the traps, save host registers,
406 * restore guest registers.
407 * - Otherwise, enable the traps
408 *
409 * On guest exit:
410 * - If the dirty bit is set, save guest registers, restore host
411 * registers and clear the dirty bit. This ensure that the host can
412 * now use the debug registers.
413 */
414static bool trap_debug_regs(struct kvm_vcpu *vcpu,
3fec037d 415 struct sys_reg_params *p,
0c557ed4
MZ		 416 const struct sys_reg_desc *r)
417{
418 if (p->is_write) {
8d404c4c 419 vcpu_write_sys_reg(vcpu, p->regval, r->reg);
fa89d31c 420 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
0c557ed4 421 } else {
8d404c4c 422 p->regval = vcpu_read_sys_reg(vcpu, r->reg);
0c557ed4
MZ		 423 }
424
2ec5be3d 425 trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
eef8c85a 426
0c557ed4
MZ		 427 return true;
428}
429
84e690bf
AB		 430/*
431 * reg_to_dbg/dbg_to_reg
432 *
433 * A 32 bit write to a debug register leave top bits alone
434 * A 32 bit read from a debug register only returns the bottom bits
435 *
436 * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the
437 * hyp.S code switches between host and guest values in future.
438 */
281243cb
MZ		 439static void reg_to_dbg(struct kvm_vcpu *vcpu,
440 struct sys_reg_params *p,
441 u64 *dbg_reg)
84e690bf 442{
2ec5be3d 443 u64 val = p->regval;
84e690bf
AB		 444
445 if (p->is_32bit) {
446 val &= 0xffffffffUL;
447 val |= ((*dbg_reg >> 32) << 32);
448 }
449
450 *dbg_reg = val;
fa89d31c 451 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
84e690bf
AB		 452}
453
281243cb
MZ		 454static void dbg_to_reg(struct kvm_vcpu *vcpu,
455 struct sys_reg_params *p,
456 u64 *dbg_reg)
84e690bf 457{
2ec5be3d 458 p->regval = *dbg_reg;
84e690bf 459 if (p->is_32bit)
2ec5be3d 460 p->regval &= 0xffffffffUL;
84e690bf
AB		 461}
462
281243cb
MZ		 463static bool trap_bvr(struct kvm_vcpu *vcpu,
464 struct sys_reg_params *p,
465 const struct sys_reg_desc *rd)
84e690bf
AB		 466{
467 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
468
469 if (p->is_write)
470 reg_to_dbg(vcpu, p, dbg_reg);
471 else
472 dbg_to_reg(vcpu, p, dbg_reg);
473
eef8c85a
AB		 474 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
475
84e690bf
AB		 476 return true;
477}
478
479static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
480 const struct kvm_one_reg *reg, void __user *uaddr)
481{
482 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
483
1713e5aa 484 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 485 return -EFAULT;
486 return 0;
487}
488
489static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
490 const struct kvm_one_reg *reg, void __user *uaddr)
491{
492 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
493
494 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
495 return -EFAULT;
496 return 0;
497}
498
281243cb
MZ		 499static void reset_bvr(struct kvm_vcpu *vcpu,
500 const struct sys_reg_desc *rd)
84e690bf
AB		 501{
502 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val;
503}
504
281243cb
MZ		 505static bool trap_bcr(struct kvm_vcpu *vcpu,
506 struct sys_reg_params *p,
507 const struct sys_reg_desc *rd)
84e690bf
AB		 508{
509 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
510
511 if (p->is_write)
512 reg_to_dbg(vcpu, p, dbg_reg);
513 else
514 dbg_to_reg(vcpu, p, dbg_reg);
515
eef8c85a
AB		 516 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
517
84e690bf
AB		 518 return true;
519}
520
521static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
522 const struct kvm_one_reg *reg, void __user *uaddr)
523{
524 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
525
1713e5aa 526 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 527 return -EFAULT;
528
529 return 0;
530}
531
532static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
533 const struct kvm_one_reg *reg, void __user *uaddr)
534{
535 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
536
537 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
538 return -EFAULT;
539 return 0;
540}
541
281243cb
MZ		 542static void reset_bcr(struct kvm_vcpu *vcpu,
543 const struct sys_reg_desc *rd)
84e690bf
AB		 544{
545 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val;
546}
547
281243cb
MZ		 548static bool trap_wvr(struct kvm_vcpu *vcpu,
549 struct sys_reg_params *p,
550 const struct sys_reg_desc *rd)
84e690bf
AB		 551{
552 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
553
554 if (p->is_write)
555 reg_to_dbg(vcpu, p, dbg_reg);
556 else
557 dbg_to_reg(vcpu, p, dbg_reg);
558
eef8c85a
AB		 559 trace_trap_reg(__func__, rd->reg, p->is_write,
560 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]);
561
84e690bf
AB		 562 return true;
563}
564
565static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
566 const struct kvm_one_reg *reg, void __user *uaddr)
567{
568 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
569
1713e5aa 570 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 571 return -EFAULT;
572 return 0;
573}
574
575static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
576 const struct kvm_one_reg *reg, void __user *uaddr)
577{
578 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
579
580 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
581 return -EFAULT;
582 return 0;
583}
584
281243cb
MZ		 585static void reset_wvr(struct kvm_vcpu *vcpu,
586 const struct sys_reg_desc *rd)
84e690bf
AB		 587{
588 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val;
589}
590
281243cb
MZ		 591static bool trap_wcr(struct kvm_vcpu *vcpu,
592 struct sys_reg_params *p,
593 const struct sys_reg_desc *rd)
84e690bf
AB		 594{
595 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
596
597 if (p->is_write)
598 reg_to_dbg(vcpu, p, dbg_reg);
599 else
600 dbg_to_reg(vcpu, p, dbg_reg);
601
eef8c85a
AB		 602 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
603
84e690bf
AB		 604 return true;
605}
606
607static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
608 const struct kvm_one_reg *reg, void __user *uaddr)
609{
610 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
611
1713e5aa 612 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 613 return -EFAULT;
614 return 0;
615}
616
617static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
618 const struct kvm_one_reg *reg, void __user *uaddr)
619{
620 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
621
622 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
623 return -EFAULT;
624 return 0;
625}
626
281243cb
MZ		 627static void reset_wcr(struct kvm_vcpu *vcpu,
628 const struct sys_reg_desc *rd)
84e690bf
AB		 629{
630 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val;
631}
632
7c8c5e6a
MZ		 633static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
634{
8d404c4c
CD		 635 u64 amair = read_sysreg(amair_el1);
636 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1);
7c8c5e6a
MZ		 637}
638
af473829
JM		 639static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
640{
641 u64 actlr = read_sysreg(actlr_el1);
642 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1);
643}
644
7c8c5e6a
MZ		 645static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
646{
4429fc64
AP		 647 u64 mpidr;
648
7c8c5e6a 649 /*
4429fc64
AP		 650 * Map the vcpu_id into the first three affinity level fields of
651 * the MPIDR. We limit the number of VCPUs in level 0 due to a
652 * limitation to 16 CPUs in that level in the ICC_SGIxR registers
653 * of the GICv3 to be able to address each CPU directly when
654 * sending IPIs.
7c8c5e6a 655 */
4429fc64
AP		 656 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
657 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
658 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
8d404c4c 659 vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1);
7c8c5e6a
MZ		 660}
661
ab946834
SZ		 662static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
663{
664 u64 pmcr, val;
665
1f3d8699
MR		 666 pmcr = read_sysreg(pmcr_el0);
667 /*
668 * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN
ab946834
SZ		 669 * except PMCR.E resetting to zero.
670 */
671 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
672 | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
6f163714
MZ		 673 if (!system_supports_32bit_el0())
674 val |= ARMV8_PMU_PMCR_LC;
03fdfb26 675 __vcpu_sys_reg(vcpu, r->reg) = val;
ab946834
SZ		 676}
677
6c007036 678static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
d692b8ad 679{
8d404c4c 680 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0);
6c007036 681 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu);
d692b8ad 682
24d5950f
MZ		 683 if (!enabled)
684 kvm_inject_undefined(vcpu);
d692b8ad 685
6c007036 686 return !enabled;
d692b8ad
SZ		 687}
688
6c007036 689static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
d692b8ad 690{
6c007036
MZ		 691 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN);
692}
d692b8ad 693
6c007036
MZ		 694static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
695{
696 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN);
d692b8ad
SZ		 697}
698
699static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
700{
6c007036 701 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN);
d692b8ad
SZ		 702}
703
704static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
705{
6c007036 706 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN);
d692b8ad
SZ		 707}
708
ab946834
SZ		 709static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
710 const struct sys_reg_desc *r)
711{
712 u64 val;
713
714 if (!kvm_arm_pmu_v3_ready(vcpu))
715 return trap_raz_wi(vcpu, p, r);
716
d692b8ad
SZ		 717 if (pmu_access_el0_disabled(vcpu))
718 return false;
719
ab946834
SZ		 720 if (p->is_write) {
721 /* Only update writeable bits of PMCR */
8d404c4c 722 val = __vcpu_sys_reg(vcpu, PMCR_EL0);
ab946834
SZ		 723 val &= ~ARMV8_PMU_PMCR_MASK;
724 val |= p->regval & ARMV8_PMU_PMCR_MASK;
6f163714
MZ		 725 if (!system_supports_32bit_el0())
726 val |= ARMV8_PMU_PMCR_LC;
8d404c4c 727 __vcpu_sys_reg(vcpu, PMCR_EL0) = val;
76993739 728 kvm_pmu_handle_pmcr(vcpu, val);
435e53fb 729 kvm_vcpu_pmu_restore_guest(vcpu);
ab946834
SZ		 730 } else {
731 /* PMCR.P & PMCR.C are RAZ */
8d404c4c 732 val = __vcpu_sys_reg(vcpu, PMCR_EL0)
ab946834
SZ		 733 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
734 p->regval = val;
735 }
736
737 return true;
738}
739
3965c3ce
SZ		 740static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
741 const struct sys_reg_desc *r)
742{
743 if (!kvm_arm_pmu_v3_ready(vcpu))
744 return trap_raz_wi(vcpu, p, r);
745
d692b8ad
SZ		 746 if (pmu_access_event_counter_el0_disabled(vcpu))
747 return false;
748
3965c3ce 749 if (p->is_write)
8d404c4c 750 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
3965c3ce
SZ		 751 else
752 /* return PMSELR.SEL field */
8d404c4c 753 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
3965c3ce
SZ		 754 & ARMV8_PMU_COUNTER_MASK;
755
756 return true;
757}
758
a86b5505
SZ		 759static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
760 const struct sys_reg_desc *r)
761{
762 u64 pmceid;
763
764 if (!kvm_arm_pmu_v3_ready(vcpu))
765 return trap_raz_wi(vcpu, p, r);
766
767 BUG_ON(p->is_write);
768
d692b8ad
SZ		 769 if (pmu_access_el0_disabled(vcpu))
770 return false;
771
a86b5505 772 if (!(p->Op2 & 1))
1f3d8699 773 pmceid = read_sysreg(pmceid0_el0);
a86b5505 774 else
1f3d8699 775 pmceid = read_sysreg(pmceid1_el0);
a86b5505
SZ		 776
777 p->regval = pmceid;
778
779 return true;
780}
781
051ff581
SZ		 782static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
783{
784 u64 pmcr, val;
785
8d404c4c 786 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0);
051ff581 787 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
24d5950f
MZ		 788 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) {
789 kvm_inject_undefined(vcpu);
051ff581 790 return false;
24d5950f 791 }
051ff581
SZ		 792
793 return true;
794}
795
796static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
797 struct sys_reg_params *p,
798 const struct sys_reg_desc *r)
799{
800 u64 idx;
801
802 if (!kvm_arm_pmu_v3_ready(vcpu))
803 return trap_raz_wi(vcpu, p, r);
804
805 if (r->CRn == 9 && r->CRm == 13) {
806 if (r->Op2 == 2) {
807 /* PMXEVCNTR_EL0 */
d692b8ad
SZ		 808 if (pmu_access_event_counter_el0_disabled(vcpu))
809 return false;
810
8d404c4c 811 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0)
051ff581
SZ		 812 & ARMV8_PMU_COUNTER_MASK;
813 } else if (r->Op2 == 0) {
814 /* PMCCNTR_EL0 */
d692b8ad
SZ		 815 if (pmu_access_cycle_counter_el0_disabled(vcpu))
816 return false;
817
051ff581
SZ		 818 idx = ARMV8_PMU_CYCLE_IDX;
819 } else {
9e3f7a29 820 return false;
051ff581 821 }
9e3f7a29
WH		 822 } else if (r->CRn == 0 && r->CRm == 9) {
823 /* PMCCNTR */
824 if (pmu_access_event_counter_el0_disabled(vcpu))
825 return false;
826
827 idx = ARMV8_PMU_CYCLE_IDX;
051ff581
SZ		 828 } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
829 /* PMEVCNTRn_EL0 */
d692b8ad
SZ		 830 if (pmu_access_event_counter_el0_disabled(vcpu))
831 return false;
832
051ff581
SZ		 833 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
834 } else {
9e3f7a29 835 return false;
051ff581
SZ		 836 }
837
838 if (!pmu_counter_idx_valid(vcpu, idx))
839 return false;
840
d692b8ad
SZ		 841 if (p->is_write) {
842 if (pmu_access_el0_disabled(vcpu))
843 return false;
844
051ff581 845 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
d692b8ad 846 } else {
051ff581 847 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
d692b8ad 848 }
051ff581
SZ		 849
850 return true;
851}
852
9feb21ac
SZ		 853static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
854 const struct sys_reg_desc *r)
855{
856 u64 idx, reg;
857
858 if (!kvm_arm_pmu_v3_ready(vcpu))
859 return trap_raz_wi(vcpu, p, r);
860
d692b8ad
SZ		 861 if (pmu_access_el0_disabled(vcpu))
862 return false;
863
9feb21ac
SZ		 864 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
865 /* PMXEVTYPER_EL0 */
8d404c4c 866 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
9feb21ac
SZ		 867 reg = PMEVTYPER0_EL0 + idx;
868 } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
869 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
870 if (idx == ARMV8_PMU_CYCLE_IDX)
871 reg = PMCCFILTR_EL0;
872 else
873 /* PMEVTYPERn_EL0 */
874 reg = PMEVTYPER0_EL0 + idx;
875 } else {
876 BUG();
877 }
878
879 if (!pmu_counter_idx_valid(vcpu, idx))
880 return false;
881
882 if (p->is_write) {
883 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
8d404c4c 884 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
435e53fb 885 kvm_vcpu_pmu_restore_guest(vcpu);
9feb21ac 886 } else {
8d404c4c 887 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
9feb21ac
SZ		 888 }
889
890 return true;
891}
892
96b0eebc
SZ		 893static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
894 const struct sys_reg_desc *r)
895{
896 u64 val, mask;
897
898 if (!kvm_arm_pmu_v3_ready(vcpu))
899 return trap_raz_wi(vcpu, p, r);
900
d692b8ad
SZ		 901 if (pmu_access_el0_disabled(vcpu))
902 return false;
903
96b0eebc
SZ		 904 mask = kvm_pmu_valid_counter_mask(vcpu);
905 if (p->is_write) {
906 val = p->regval & mask;
907 if (r->Op2 & 0x1) {
908 /* accessing PMCNTENSET_EL0 */
8d404c4c 909 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
418e5ca8 910 kvm_pmu_enable_counter_mask(vcpu, val);
435e53fb 911 kvm_vcpu_pmu_restore_guest(vcpu);
96b0eebc
SZ		 912 } else {
913 /* accessing PMCNTENCLR_EL0 */
8d404c4c 914 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
418e5ca8 915 kvm_pmu_disable_counter_mask(vcpu, val);
96b0eebc
SZ		 916 }
917 } else {
8d404c4c 918 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
96b0eebc
SZ		 919 }
920
921 return true;
922}
923
9db52c78
SZ		 924static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
925 const struct sys_reg_desc *r)
926{
927 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
928
929 if (!kvm_arm_pmu_v3_ready(vcpu))
930 return trap_raz_wi(vcpu, p, r);
931
9008c235
MZ		 932 if (!vcpu_mode_priv(vcpu)) {
933 kvm_inject_undefined(vcpu);
d692b8ad 934 return false;
9008c235 935 }
d692b8ad 936
9db52c78
SZ		 937 if (p->is_write) {
938 u64 val = p->regval & mask;
939
940 if (r->Op2 & 0x1)
941 /* accessing PMINTENSET_EL1 */
8d404c4c 942 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
9db52c78
SZ		 943 else
944 /* accessing PMINTENCLR_EL1 */
8d404c4c 945 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
9db52c78 946 } else {
8d404c4c 947 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask;
9db52c78
SZ		 948 }
949
950 return true;
951}
952
76d883c4
SZ		 953static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
954 const struct sys_reg_desc *r)
955{
956 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
957
958 if (!kvm_arm_pmu_v3_ready(vcpu))
959 return trap_raz_wi(vcpu, p, r);
960
d692b8ad
SZ		 961 if (pmu_access_el0_disabled(vcpu))
962 return false;
963
76d883c4
SZ		 964 if (p->is_write) {
965 if (r->CRm & 0x2)
966 /* accessing PMOVSSET_EL0 */
8d404c4c 967 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);
76d883c4
SZ		 968 else
969 /* accessing PMOVSCLR_EL0 */
8d404c4c 970 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
76d883c4 971 } else {
8d404c4c 972 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask;
76d883c4
SZ		 973 }
974
975 return true;
976}
977
7a0adc70
SZ		 978static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
979 const struct sys_reg_desc *r)
980{
981 u64 mask;
982
983 if (!kvm_arm_pmu_v3_ready(vcpu))
984 return trap_raz_wi(vcpu, p, r);
985
e0443230 986 if (!p->is_write)
e7f1d1ee 987 return read_from_write_only(vcpu, p, r);
e0443230 988
d692b8ad
SZ		 989 if (pmu_write_swinc_el0_disabled(vcpu))
990 return false;
991
e0443230
MZ		 992 mask = kvm_pmu_valid_counter_mask(vcpu);
993 kvm_pmu_software_increment(vcpu, p->regval & mask);
994 return true;
7a0adc70
SZ		 995}
996
d692b8ad
SZ		 997static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
998 const struct sys_reg_desc *r)
999{
1000 if (!kvm_arm_pmu_v3_ready(vcpu))
1001 return trap_raz_wi(vcpu, p, r);
1002
1003 if (p->is_write) {
9008c235
MZ		 1004 if (!vcpu_mode_priv(vcpu)) {
1005 kvm_inject_undefined(vcpu);
d692b8ad 1006 return false;
9008c235 1007 }
d692b8ad 1008
8d404c4c
CD		 1009 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) =
1010 p->regval & ARMV8_PMU_USERENR_MASK;
d692b8ad 1011 } else {
8d404c4c 1012 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0)
d692b8ad
SZ		 1013 & ARMV8_PMU_USERENR_MASK;
1014 }
1015
1016 return true;
1017}
1018
09838de9
MZ		 1019#define reg_to_encoding(x) \
1020 sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \
1021 (u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2);
1022
0c557ed4
MZ		 1023/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
1024#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
ee1b64e6 1025 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \
03fdfb26 1026 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \
ee1b64e6 1027 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \
03fdfb26 1028 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \
ee1b64e6 1029 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \
03fdfb26 1030 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \
ee1b64e6 1031 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \
03fdfb26 1032 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr }
0c557ed4 1033
051ff581
SZ		 1034/* Macro to expand the PMEVCNTRn_EL0 register */
1035#define PMU_PMEVCNTR_EL0(n) \
174ed3e4 1036 { SYS_DESC(SYS_PMEVCNTRn_EL0(n)), \
051ff581
SZ		 1037 access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), }
1038
9feb21ac
SZ		 1039/* Macro to expand the PMEVTYPERn_EL0 register */
1040#define PMU_PMEVTYPER_EL0(n) \
174ed3e4 1041 { SYS_DESC(SYS_PMEVTYPERn_EL0(n)), \
9feb21ac
SZ		 1042 access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
1043
4fcdf106
IV		 1044static bool access_amu(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1045 const struct sys_reg_desc *r)
1046{
1047 kvm_inject_undefined(vcpu);
1048
1049 return false;
1050}
1051
1052/* Macro to expand the AMU counter and type registers*/
1053#define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), access_amu }
493cf9b7 1054#define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), access_amu }
4fcdf106 1055#define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), access_amu }
493cf9b7 1056#define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), access_amu }
4fcdf106 1057
384b40ca
MR		 1058static bool trap_ptrauth(struct kvm_vcpu *vcpu,
1059 struct sys_reg_params *p,
1060 const struct sys_reg_desc *rd)
1061{
384b40ca 1062 /*
29eb5a3c
MZ		 1063 * If we land here, that is because we didn't fixup the access on exit
1064 * by allowing the PtrAuth sysregs. The only way this happens is when
1065 * the guest does not have PtrAuth support enabled.
384b40ca 1066 */
29eb5a3c
MZ		 1067 kvm_inject_undefined(vcpu);
1068
384b40ca
MR		 1069 return false;
1070}
1071
1072static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu,
1073 const struct sys_reg_desc *rd)
1074{
1075 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN_USER | REG_HIDDEN_GUEST;
1076}
1077
1078#define __PTRAUTH_KEY(k) \
1079 { SYS_DESC(SYS_## k), trap_ptrauth, reset_unknown, k, \
1080 .visibility = ptrauth_visibility}
1081
1082#define PTRAUTH_KEY(k) \
1083 __PTRAUTH_KEY(k ## KEYLO_EL1), \
1084 __PTRAUTH_KEY(k ## KEYHI_EL1)
1085
84135d3d
AP		 1086static bool access_arch_timer(struct kvm_vcpu *vcpu,
1087 struct sys_reg_params *p,
1088 const struct sys_reg_desc *r)
c9a3c58f 1089{
84135d3d
AP		 1090 enum kvm_arch_timers tmr;
1091 enum kvm_arch_timer_regs treg;
1092 u64 reg = reg_to_encoding(r);
7b6b4631 1093
84135d3d
AP		 1094 switch (reg) {
1095 case SYS_CNTP_TVAL_EL0:
1096 case SYS_AARCH32_CNTP_TVAL:
1097 tmr = TIMER_PTIMER;
1098 treg = TIMER_REG_TVAL;
1099 break;
1100 case SYS_CNTP_CTL_EL0:
1101 case SYS_AARCH32_CNTP_CTL:
1102 tmr = TIMER_PTIMER;
1103 treg = TIMER_REG_CTL;
1104 break;
1105 case SYS_CNTP_CVAL_EL0:
1106 case SYS_AARCH32_CNTP_CVAL:
1107 tmr = TIMER_PTIMER;
1108 treg = TIMER_REG_CVAL;
1109 break;
1110 default:
1111 BUG();
c1b135af 1112 }
7b6b4631 1113
7b6b4631 1114 if (p->is_write)
84135d3d 1115 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval);
7b6b4631 1116 else
84135d3d 1117 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg);
7b6b4631 1118
c9a3c58f
JL		 1119 return true;
1120}
1121
93390c0a 1122/* Read a sanitised cpufeature ID register by sys_reg_desc */
1c199913
DM		 1123static u64 read_id_reg(const struct kvm_vcpu *vcpu,
1124 struct sys_reg_desc const *r, bool raz)
93390c0a
DM		 1125{
1126 u32 id = sys_reg((u32)r->Op0, (u32)r->Op1,
1127 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
07d79fe7 1128 u64 val = raz ? 0 : read_sanitised_ftr_reg(id);
93390c0a 1129
4fcdf106
IV		 1130 if (id == SYS_ID_AA64PFR0_EL1) {
1131 if (!vcpu_has_sve(vcpu))
1132 val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);
1133 val &= ~(0xfUL << ID_AA64PFR0_AMU_SHIFT);
e1026237
MZ		 1134 if (!(val & (0xfUL << ID_AA64PFR0_CSV2_SHIFT)) &&
1135 arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED)
1136 val |= (1UL << ID_AA64PFR0_CSV2_SHIFT);
384b40ca 1137 } else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) {
9eecfc22
KM		 1138 val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) |
1139 (0xfUL << ID_AA64ISAR1_API_SHIFT) |
1140 (0xfUL << ID_AA64ISAR1_GPA_SHIFT) |
1141 (0xfUL << ID_AA64ISAR1_GPI_SHIFT));
c854188e
AM		 1142 } else if (id == SYS_ID_AA64DFR0_EL1) {
1143 /* Limit guests to PMUv3 for ARMv8.1 */
1144 val = cpuid_feature_cap_perfmon_field(val,
1145 ID_AA64DFR0_PMUVER_SHIFT,
1146 ID_AA64DFR0_PMUVER_8_1);
1147 } else if (id == SYS_ID_DFR0_EL1) {
1148 /* Limit guests to PMUv3 for ARMv8.1 */
1149 val = cpuid_feature_cap_perfmon_field(val,
1150 ID_DFR0_PERFMON_SHIFT,
1151 ID_DFR0_PERFMON_8_1);
07d79fe7
DM		 1152 }
1153
1154 return val;
93390c0a
DM		 1155}
1156
1157/* cpufeature ID register access trap handlers */
1158
1159static bool __access_id_reg(struct kvm_vcpu *vcpu,
1160 struct sys_reg_params *p,
1161 const struct sys_reg_desc *r,
1162 bool raz)
1163{
1164 if (p->is_write)
1165 return write_to_read_only(vcpu, p, r);
1166
1c199913 1167 p->regval = read_id_reg(vcpu, r, raz);
93390c0a
DM		 1168 return true;
1169}
1170
1171static bool access_id_reg(struct kvm_vcpu *vcpu,
1172 struct sys_reg_params *p,
1173 const struct sys_reg_desc *r)
1174{
1175 return __access_id_reg(vcpu, p, r, false);
1176}
1177
1178static bool access_raz_id_reg(struct kvm_vcpu *vcpu,
1179 struct sys_reg_params *p,
1180 const struct sys_reg_desc *r)
1181{
1182 return __access_id_reg(vcpu, p, r, true);
1183}
1184
1185static int reg_from_user(u64 *val, const void __user *uaddr, u64 id);
1186static int reg_to_user(void __user *uaddr, const u64 *val, u64 id);
1187static u64 sys_reg_to_index(const struct sys_reg_desc *reg);
1188
73433762
DM		 1189/* Visibility overrides for SVE-specific control registers */
1190static unsigned int sve_visibility(const struct kvm_vcpu *vcpu,
1191 const struct sys_reg_desc *rd)
1192{
1193 if (vcpu_has_sve(vcpu))
1194 return 0;
1195
1196 return REG_HIDDEN_USER | REG_HIDDEN_GUEST;
1197}
1198
1199/* Visibility overrides for SVE-specific ID registers */
1200static unsigned int sve_id_visibility(const struct kvm_vcpu *vcpu,
1201 const struct sys_reg_desc *rd)
1202{
1203 if (vcpu_has_sve(vcpu))
1204 return 0;
1205
1206 return REG_HIDDEN_USER;
1207}
1208
1209/* Generate the emulated ID_AA64ZFR0_EL1 value exposed to the guest */
1210static u64 guest_id_aa64zfr0_el1(const struct kvm_vcpu *vcpu)
1211{
1212 if (!vcpu_has_sve(vcpu))
1213 return 0;
1214
1215 return read_sanitised_ftr_reg(SYS_ID_AA64ZFR0_EL1);
1216}
1217
1218static bool access_id_aa64zfr0_el1(struct kvm_vcpu *vcpu,
1219 struct sys_reg_params *p,
1220 const struct sys_reg_desc *rd)
1221{
1222 if (p->is_write)
1223 return write_to_read_only(vcpu, p, rd);
1224
1225 p->regval = guest_id_aa64zfr0_el1(vcpu);
1226 return true;
1227}
1228
1229static int get_id_aa64zfr0_el1(struct kvm_vcpu *vcpu,
1230 const struct sys_reg_desc *rd,
1231 const struct kvm_one_reg *reg, void __user *uaddr)
1232{
1233 u64 val;
1234
700698a8 1235 if (WARN_ON(!vcpu_has_sve(vcpu)))
73433762
DM		 1236 return -ENOENT;
1237
1238 val = guest_id_aa64zfr0_el1(vcpu);
1239 return reg_to_user(uaddr, &val, reg->id);
1240}
1241
1242static int set_id_aa64zfr0_el1(struct kvm_vcpu *vcpu,
1243 const struct sys_reg_desc *rd,
1244 const struct kvm_one_reg *reg, void __user *uaddr)
1245{
1246 const u64 id = sys_reg_to_index(rd);
1247 int err;
1248 u64 val;
1249
700698a8 1250 if (WARN_ON(!vcpu_has_sve(vcpu)))
73433762
DM		 1251 return -ENOENT;
1252
1253 err = reg_from_user(&val, uaddr, id);
1254 if (err)
1255 return err;
1256
1257 /* This is what we mean by invariant: you can't change it. */
1258 if (val != guest_id_aa64zfr0_el1(vcpu))
1259 return -EINVAL;
1260
1261 return 0;
1262}
1263
93390c0a
DM		 1264/*
1265 * cpufeature ID register user accessors
1266 *
1267 * For now, these registers are immutable for userspace, so no values
1268 * are stored, and for set_id_reg() we don't allow the effective value
1269 * to be changed.
1270 */
1c199913
DM		 1271static int __get_id_reg(const struct kvm_vcpu *vcpu,
1272 const struct sys_reg_desc *rd, void __user *uaddr,
93390c0a
DM		 1273 bool raz)
1274{
1275 const u64 id = sys_reg_to_index(rd);
1c199913 1276 const u64 val = read_id_reg(vcpu, rd, raz);
93390c0a
DM		 1277
1278 return reg_to_user(uaddr, &val, id);
1279}
1280
1c199913
DM		 1281static int __set_id_reg(const struct kvm_vcpu *vcpu,
1282 const struct sys_reg_desc *rd, void __user *uaddr,
93390c0a
DM		 1283 bool raz)
1284{
1285 const u64 id = sys_reg_to_index(rd);
1286 int err;
1287 u64 val;
1288
1289 err = reg_from_user(&val, uaddr, id);
1290 if (err)
1291 return err;
1292
1293 /* This is what we mean by invariant: you can't change it. */
1c199913 1294 if (val != read_id_reg(vcpu, rd, raz))
93390c0a
DM		 1295 return -EINVAL;
1296
1297 return 0;
1298}
1299
1300static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1301 const struct kvm_one_reg *reg, void __user *uaddr)
1302{
1c199913 1303 return __get_id_reg(vcpu, rd, uaddr, false);
93390c0a
DM		 1304}
1305
1306static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1307 const struct kvm_one_reg *reg, void __user *uaddr)
1308{
1c199913 1309 return __set_id_reg(vcpu, rd, uaddr, false);
93390c0a
DM		 1310}
1311
1312static int get_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1313 const struct kvm_one_reg *reg, void __user *uaddr)
1314{
1c199913 1315 return __get_id_reg(vcpu, rd, uaddr, true);
93390c0a
DM		 1316}
1317
1318static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1319 const struct kvm_one_reg *reg, void __user *uaddr)
1320{
1c199913 1321 return __set_id_reg(vcpu, rd, uaddr, true);
93390c0a
DM		 1322}
1323
f7f2b15c
AB		 1324static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1325 const struct sys_reg_desc *r)
1326{
1327 if (p->is_write)
1328 return write_to_read_only(vcpu, p, r);
1329
1330 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0);
1331 return true;
1332}
1333
1334static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1335 const struct sys_reg_desc *r)
1336{
1337 if (p->is_write)
1338 return write_to_read_only(vcpu, p, r);
1339
1340 p->regval = read_sysreg(clidr_el1);
1341 return true;
1342}
1343
1344static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1345 const struct sys_reg_desc *r)
1346{
7c582bf4
JM		 1347 int reg = r->reg;
1348
1349 /* See the 32bit mapping in kvm_host.h */
1350 if (p->is_aarch32)
1351 reg = r->reg / 2;
1352
f7f2b15c 1353 if (p->is_write)
7c582bf4 1354 vcpu_write_sys_reg(vcpu, p->regval, reg);
f7f2b15c 1355 else
7c582bf4 1356 p->regval = vcpu_read_sys_reg(vcpu, reg);
f7f2b15c
AB		 1357 return true;
1358}
1359
1360static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1361 const struct sys_reg_desc *r)
1362{
1363 u32 csselr;
1364
1365 if (p->is_write)
1366 return write_to_read_only(vcpu, p, r);
1367
1368 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1);
1369 p->regval = get_ccsidr(csselr);
793acf87
AB		 1370
1371 /*
1372 * Guests should not be doing cache operations by set/way at all, and
1373 * for this reason, we trap them and attempt to infer the intent, so
1374 * that we can flush the entire guest's address space at the appropriate
1375 * time.
1376 * To prevent this trapping from causing performance problems, let's
1377 * expose the geometry of all data and unified caches (which are
1378 * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way.
1379 * [If guests should attempt to infer aliasing properties from the
1380 * geometry (which is not permitted by the architecture), they would
1381 * only do so for virtually indexed caches.]
1382 */
1383 if (!(csselr & 1)) // data or unified cache
1384 p->regval &= ~GENMASK(27, 3);
f7f2b15c
AB		 1385 return true;
1386}
1387
93390c0a
DM		 1388/* sys_reg_desc initialiser for known cpufeature ID registers */
1389#define ID_SANITISED(name) { \
1390 SYS_DESC(SYS_##name), \
1391 .access = access_id_reg, \
1392 .get_user = get_id_reg, \
1393 .set_user = set_id_reg, \
1394}
1395
1396/*
1397 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID
1398 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
1399 * (1 <= crm < 8, 0 <= Op2 < 8).
1400 */
1401#define ID_UNALLOCATED(crm, op2) { \
1402 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
1403 .access = access_raz_id_reg, \
1404 .get_user = get_raz_id_reg, \
1405 .set_user = set_raz_id_reg, \
1406}
1407
1408/*
1409 * sys_reg_desc initialiser for known ID registers that we hide from guests.
1410 * For now, these are exposed just like unallocated ID regs: they appear
1411 * RAZ for the guest.
1412 */
1413#define ID_HIDDEN(name) { \
1414 SYS_DESC(SYS_##name), \
1415 .access = access_raz_id_reg, \
1416 .get_user = get_raz_id_reg, \
1417 .set_user = set_raz_id_reg, \
1418}
1419
7c8c5e6a
MZ		 1420/*
1421 * Architected system registers.
1422 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
7609c125 1423 *
0c557ed4
MZ		 1424 * Debug handling: We do trap most, if not all debug related system
1425 * registers. The implementation is good enough to ensure that a guest
1426 * can use these with minimal performance degradation. The drawback is
1427 * that we don't implement any of the external debug, none of the
1428 * OSlock protocol. This should be revisited if we ever encounter a
1429 * more demanding guest...
7c8c5e6a
MZ		 1430 */
1431static const struct sys_reg_desc sys_reg_descs[] = {
7606e078
MR		 1432 { SYS_DESC(SYS_DC_ISW), access_dcsw },
1433 { SYS_DESC(SYS_DC_CSW), access_dcsw },
1434 { SYS_DESC(SYS_DC_CISW), access_dcsw },
7c8c5e6a 1435
0c557ed4
MZ		 1436 DBG_BCR_BVR_WCR_WVR_EL1(0),
1437 DBG_BCR_BVR_WCR_WVR_EL1(1),
ee1b64e6
MR		 1438 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
1439 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
0c557ed4
MZ		 1440 DBG_BCR_BVR_WCR_WVR_EL1(2),
1441 DBG_BCR_BVR_WCR_WVR_EL1(3),
1442 DBG_BCR_BVR_WCR_WVR_EL1(4),
1443 DBG_BCR_BVR_WCR_WVR_EL1(5),
1444 DBG_BCR_BVR_WCR_WVR_EL1(6),
1445 DBG_BCR_BVR_WCR_WVR_EL1(7),
1446 DBG_BCR_BVR_WCR_WVR_EL1(8),
1447 DBG_BCR_BVR_WCR_WVR_EL1(9),
1448 DBG_BCR_BVR_WCR_WVR_EL1(10),
1449 DBG_BCR_BVR_WCR_WVR_EL1(11),
1450 DBG_BCR_BVR_WCR_WVR_EL1(12),
1451 DBG_BCR_BVR_WCR_WVR_EL1(13),
1452 DBG_BCR_BVR_WCR_WVR_EL1(14),
1453 DBG_BCR_BVR_WCR_WVR_EL1(15),
1454
ee1b64e6
MR		 1455 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },
1456 { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi },
1457 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 },
1458 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },
1459 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },
1460 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },
1461 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
1462 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
1463
1464 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
1465 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
1466 // DBGDTR[TR]X_EL0 share the same encoding
1467 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
1468
1469 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
62a89c44 1470
851050a5 1471 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
93390c0a
DM		 1472
1473 /*
1474 * ID regs: all ID_SANITISED() entries here must have corresponding
1475 * entries in arm64_ftr_regs[].
1476 */
1477
1478 /* AArch64 mappings of the AArch32 ID registers */
1479 /* CRm=1 */
1480 ID_SANITISED(ID_PFR0_EL1),
1481 ID_SANITISED(ID_PFR1_EL1),
1482 ID_SANITISED(ID_DFR0_EL1),
1483 ID_HIDDEN(ID_AFR0_EL1),
1484 ID_SANITISED(ID_MMFR0_EL1),
1485 ID_SANITISED(ID_MMFR1_EL1),
1486 ID_SANITISED(ID_MMFR2_EL1),
1487 ID_SANITISED(ID_MMFR3_EL1),
1488
1489 /* CRm=2 */
1490 ID_SANITISED(ID_ISAR0_EL1),
1491 ID_SANITISED(ID_ISAR1_EL1),
1492 ID_SANITISED(ID_ISAR2_EL1),
1493 ID_SANITISED(ID_ISAR3_EL1),
1494 ID_SANITISED(ID_ISAR4_EL1),
1495 ID_SANITISED(ID_ISAR5_EL1),
1496 ID_SANITISED(ID_MMFR4_EL1),
8e3747be 1497 ID_SANITISED(ID_ISAR6_EL1),
93390c0a
DM		 1498
1499 /* CRm=3 */
1500 ID_SANITISED(MVFR0_EL1),
1501 ID_SANITISED(MVFR1_EL1),
1502 ID_SANITISED(MVFR2_EL1),
1503 ID_UNALLOCATED(3,3),
16824085 1504 ID_SANITISED(ID_PFR2_EL1),
dd35ec07 1505 ID_HIDDEN(ID_DFR1_EL1),
152accf8 1506 ID_SANITISED(ID_MMFR5_EL1),
93390c0a
DM		 1507 ID_UNALLOCATED(3,7),
1508
1509 /* AArch64 ID registers */
1510 /* CRm=4 */
1511 ID_SANITISED(ID_AA64PFR0_EL1),
1512 ID_SANITISED(ID_AA64PFR1_EL1),
1513 ID_UNALLOCATED(4,2),
1514 ID_UNALLOCATED(4,3),
73433762 1515 { SYS_DESC(SYS_ID_AA64ZFR0_EL1), access_id_aa64zfr0_el1, .get_user = get_id_aa64zfr0_el1, .set_user = set_id_aa64zfr0_el1, .visibility = sve_id_visibility },
93390c0a
DM		 1516 ID_UNALLOCATED(4,5),
1517 ID_UNALLOCATED(4,6),
1518 ID_UNALLOCATED(4,7),
1519
1520 /* CRm=5 */
1521 ID_SANITISED(ID_AA64DFR0_EL1),
1522 ID_SANITISED(ID_AA64DFR1_EL1),
1523 ID_UNALLOCATED(5,2),
1524 ID_UNALLOCATED(5,3),
1525 ID_HIDDEN(ID_AA64AFR0_EL1),
1526 ID_HIDDEN(ID_AA64AFR1_EL1),
1527 ID_UNALLOCATED(5,6),
1528 ID_UNALLOCATED(5,7),
1529
1530 /* CRm=6 */
1531 ID_SANITISED(ID_AA64ISAR0_EL1),
1532 ID_SANITISED(ID_AA64ISAR1_EL1),
1533 ID_UNALLOCATED(6,2),
1534 ID_UNALLOCATED(6,3),
1535 ID_UNALLOCATED(6,4),
1536 ID_UNALLOCATED(6,5),
1537 ID_UNALLOCATED(6,6),
1538 ID_UNALLOCATED(6,7),
1539
1540 /* CRm=7 */
1541 ID_SANITISED(ID_AA64MMFR0_EL1),
1542 ID_SANITISED(ID_AA64MMFR1_EL1),
1543 ID_SANITISED(ID_AA64MMFR2_EL1),
1544 ID_UNALLOCATED(7,3),
1545 ID_UNALLOCATED(7,4),
1546 ID_UNALLOCATED(7,5),
1547 ID_UNALLOCATED(7,6),
1548 ID_UNALLOCATED(7,7),
1549
851050a5 1550 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
af473829 1551 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 },
851050a5 1552 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
73433762 1553 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
851050a5
MR		 1554 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
1555 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
1556 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
1557
384b40ca
MR		 1558 PTRAUTH_KEY(APIA),
1559 PTRAUTH_KEY(APIB),
1560 PTRAUTH_KEY(APDA),
1561 PTRAUTH_KEY(APDB),
1562 PTRAUTH_KEY(APGA),
1563
851050a5
MR		 1564 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },
1565 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },
1566 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },
558daf69
DG		 1567
1568 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi },
1569 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi },
1570 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi },
1571 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi },
1572 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi },
1573 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi },
1574 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi },
1575 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi },
1576
851050a5
MR		 1577 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
1578 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
7c8c5e6a 1579
174ed3e4 1580 { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 },
7ccadf23 1581 { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 },
7c8c5e6a 1582
851050a5
MR		 1583 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
1584 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
7c8c5e6a 1585
22925521
MZ		 1586 { SYS_DESC(SYS_LORSA_EL1), trap_loregion },
1587 { SYS_DESC(SYS_LOREA_EL1), trap_loregion },
1588 { SYS_DESC(SYS_LORN_EL1), trap_loregion },
1589 { SYS_DESC(SYS_LORC_EL1), trap_loregion },
1590 { SYS_DESC(SYS_LORID_EL1), trap_loregion },
cc33c4e2 1591
851050a5 1592 { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
c773ae2b 1593 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
db7dedd0 1594
7b1dba1f 1595 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only },
e7f1d1ee 1596 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only },
7b1dba1f 1597 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only },
e7f1d1ee 1598 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only },
7b1dba1f 1599 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only },
e804d208 1600 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
03bd646d
MZ		 1601 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi },
1602 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi },
7b1dba1f 1603 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only },
e7f1d1ee 1604 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only },
7b1dba1f 1605 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only },
e804d208 1606 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
db7dedd0 1607
851050a5
MR		 1608 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
1609 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },
7c8c5e6a 1610
851050a5 1611 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
7c8c5e6a 1612
f7f2b15c
AB		 1613 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr },
1614 { SYS_DESC(SYS_CLIDR_EL1), access_clidr },
1615 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },
1616 { SYS_DESC(SYS_CTR_EL0), access_ctr },
7c8c5e6a 1617
03fdfb26 1618 { SYS_DESC(SYS_PMCR_EL0), access_pmcr, reset_pmcr, PMCR_EL0 },
174ed3e4 1619 { SYS_DESC(SYS_PMCNTENSET_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
7ccadf23
MZ		 1620 { SYS_DESC(SYS_PMCNTENCLR_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
1621 { SYS_DESC(SYS_PMOVSCLR_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 },
174ed3e4
MR		 1622 { SYS_DESC(SYS_PMSWINC_EL0), access_pmswinc, reset_unknown, PMSWINC_EL0 },
1623 { SYS_DESC(SYS_PMSELR_EL0), access_pmselr, reset_unknown, PMSELR_EL0 },
1624 { SYS_DESC(SYS_PMCEID0_EL0), access_pmceid },
1625 { SYS_DESC(SYS_PMCEID1_EL0), access_pmceid },
1626 { SYS_DESC(SYS_PMCCNTR_EL0), access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 },
1627 { SYS_DESC(SYS_PMXEVTYPER_EL0), access_pmu_evtyper },
1628 { SYS_DESC(SYS_PMXEVCNTR_EL0), access_pmu_evcntr },
1629 /*
1630 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
d692b8ad
SZ		 1631 * in 32bit mode. Here we choose to reset it as zero for consistency.
1632 */
174ed3e4
MR		 1633 { SYS_DESC(SYS_PMUSERENR_EL0), access_pmuserenr, reset_val, PMUSERENR_EL0, 0 },
1634 { SYS_DESC(SYS_PMOVSSET_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 },
7c8c5e6a 1635
851050a5
MR		 1636 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
1637 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
4fcdf106
IV		 1638
1639 { SYS_DESC(SYS_AMCR_EL0), access_amu },
1640 { SYS_DESC(SYS_AMCFGR_EL0), access_amu },
1641 { SYS_DESC(SYS_AMCGCR_EL0), access_amu },
1642 { SYS_DESC(SYS_AMUSERENR_EL0), access_amu },
1643 { SYS_DESC(SYS_AMCNTENCLR0_EL0), access_amu },
1644 { SYS_DESC(SYS_AMCNTENSET0_EL0), access_amu },
1645 { SYS_DESC(SYS_AMCNTENCLR1_EL0), access_amu },
1646 { SYS_DESC(SYS_AMCNTENSET1_EL0), access_amu },
1647 AMU_AMEVCNTR0_EL0(0),
1648 AMU_AMEVCNTR0_EL0(1),
1649 AMU_AMEVCNTR0_EL0(2),
1650 AMU_AMEVCNTR0_EL0(3),
1651 AMU_AMEVCNTR0_EL0(4),
1652 AMU_AMEVCNTR0_EL0(5),
1653 AMU_AMEVCNTR0_EL0(6),
1654 AMU_AMEVCNTR0_EL0(7),
1655 AMU_AMEVCNTR0_EL0(8),
1656 AMU_AMEVCNTR0_EL0(9),
1657 AMU_AMEVCNTR0_EL0(10),
1658 AMU_AMEVCNTR0_EL0(11),
1659 AMU_AMEVCNTR0_EL0(12),
1660 AMU_AMEVCNTR0_EL0(13),
1661 AMU_AMEVCNTR0_EL0(14),
1662 AMU_AMEVCNTR0_EL0(15),
493cf9b7
VM		 1663 AMU_AMEVTYPER0_EL0(0),
1664 AMU_AMEVTYPER0_EL0(1),
1665 AMU_AMEVTYPER0_EL0(2),
1666 AMU_AMEVTYPER0_EL0(3),
1667 AMU_AMEVTYPER0_EL0(4),
1668 AMU_AMEVTYPER0_EL0(5),
1669 AMU_AMEVTYPER0_EL0(6),
1670 AMU_AMEVTYPER0_EL0(7),
1671 AMU_AMEVTYPER0_EL0(8),
1672 AMU_AMEVTYPER0_EL0(9),
1673 AMU_AMEVTYPER0_EL0(10),
1674 AMU_AMEVTYPER0_EL0(11),
1675 AMU_AMEVTYPER0_EL0(12),
1676 AMU_AMEVTYPER0_EL0(13),
1677 AMU_AMEVTYPER0_EL0(14),
1678 AMU_AMEVTYPER0_EL0(15),
4fcdf106
IV		 1679 AMU_AMEVCNTR1_EL0(0),
1680 AMU_AMEVCNTR1_EL0(1),
1681 AMU_AMEVCNTR1_EL0(2),
1682 AMU_AMEVCNTR1_EL0(3),
1683 AMU_AMEVCNTR1_EL0(4),
1684 AMU_AMEVCNTR1_EL0(5),
1685 AMU_AMEVCNTR1_EL0(6),
1686 AMU_AMEVCNTR1_EL0(7),
1687 AMU_AMEVCNTR1_EL0(8),
1688 AMU_AMEVCNTR1_EL0(9),
1689 AMU_AMEVCNTR1_EL0(10),
1690 AMU_AMEVCNTR1_EL0(11),
1691 AMU_AMEVCNTR1_EL0(12),
1692 AMU_AMEVCNTR1_EL0(13),
1693 AMU_AMEVCNTR1_EL0(14),
1694 AMU_AMEVCNTR1_EL0(15),
493cf9b7
VM		 1695 AMU_AMEVTYPER1_EL0(0),
1696 AMU_AMEVTYPER1_EL0(1),
1697 AMU_AMEVTYPER1_EL0(2),
1698 AMU_AMEVTYPER1_EL0(3),
1699 AMU_AMEVTYPER1_EL0(4),
1700 AMU_AMEVTYPER1_EL0(5),
1701 AMU_AMEVTYPER1_EL0(6),
1702 AMU_AMEVTYPER1_EL0(7),
1703 AMU_AMEVTYPER1_EL0(8),
1704 AMU_AMEVTYPER1_EL0(9),
1705 AMU_AMEVTYPER1_EL0(10),
1706 AMU_AMEVTYPER1_EL0(11),
1707 AMU_AMEVTYPER1_EL0(12),
1708 AMU_AMEVTYPER1_EL0(13),
1709 AMU_AMEVTYPER1_EL0(14),
1710 AMU_AMEVTYPER1_EL0(15),
62a89c44 1711
84135d3d
AP		 1712 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer },
1713 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer },
1714 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer },
c9a3c58f 1715
051ff581
SZ		 1716 /* PMEVCNTRn_EL0 */
1717 PMU_PMEVCNTR_EL0(0),
1718 PMU_PMEVCNTR_EL0(1),
1719 PMU_PMEVCNTR_EL0(2),
1720 PMU_PMEVCNTR_EL0(3),
1721 PMU_PMEVCNTR_EL0(4),
1722 PMU_PMEVCNTR_EL0(5),
1723 PMU_PMEVCNTR_EL0(6),
1724 PMU_PMEVCNTR_EL0(7),
1725 PMU_PMEVCNTR_EL0(8),
1726 PMU_PMEVCNTR_EL0(9),
1727 PMU_PMEVCNTR_EL0(10),
1728 PMU_PMEVCNTR_EL0(11),
1729 PMU_PMEVCNTR_EL0(12),
1730 PMU_PMEVCNTR_EL0(13),
1731 PMU_PMEVCNTR_EL0(14),
1732 PMU_PMEVCNTR_EL0(15),
1733 PMU_PMEVCNTR_EL0(16),
1734 PMU_PMEVCNTR_EL0(17),
1735 PMU_PMEVCNTR_EL0(18),
1736 PMU_PMEVCNTR_EL0(19),
1737 PMU_PMEVCNTR_EL0(20),
1738 PMU_PMEVCNTR_EL0(21),
1739 PMU_PMEVCNTR_EL0(22),
1740 PMU_PMEVCNTR_EL0(23),
1741 PMU_PMEVCNTR_EL0(24),
1742 PMU_PMEVCNTR_EL0(25),
1743 PMU_PMEVCNTR_EL0(26),
1744 PMU_PMEVCNTR_EL0(27),
1745 PMU_PMEVCNTR_EL0(28),
1746 PMU_PMEVCNTR_EL0(29),
1747 PMU_PMEVCNTR_EL0(30),
9feb21ac
SZ		 1748 /* PMEVTYPERn_EL0 */
1749 PMU_PMEVTYPER_EL0(0),
1750 PMU_PMEVTYPER_EL0(1),
1751 PMU_PMEVTYPER_EL0(2),
1752 PMU_PMEVTYPER_EL0(3),
1753 PMU_PMEVTYPER_EL0(4),
1754 PMU_PMEVTYPER_EL0(5),
1755 PMU_PMEVTYPER_EL0(6),
1756 PMU_PMEVTYPER_EL0(7),
1757 PMU_PMEVTYPER_EL0(8),
1758 PMU_PMEVTYPER_EL0(9),
1759 PMU_PMEVTYPER_EL0(10),
1760 PMU_PMEVTYPER_EL0(11),
1761 PMU_PMEVTYPER_EL0(12),
1762 PMU_PMEVTYPER_EL0(13),
1763 PMU_PMEVTYPER_EL0(14),
1764 PMU_PMEVTYPER_EL0(15),
1765 PMU_PMEVTYPER_EL0(16),
1766 PMU_PMEVTYPER_EL0(17),
1767 PMU_PMEVTYPER_EL0(18),
1768 PMU_PMEVTYPER_EL0(19),
1769 PMU_PMEVTYPER_EL0(20),
1770 PMU_PMEVTYPER_EL0(21),
1771 PMU_PMEVTYPER_EL0(22),
1772 PMU_PMEVTYPER_EL0(23),
1773 PMU_PMEVTYPER_EL0(24),
1774 PMU_PMEVTYPER_EL0(25),
1775 PMU_PMEVTYPER_EL0(26),
1776 PMU_PMEVTYPER_EL0(27),
1777 PMU_PMEVTYPER_EL0(28),
1778 PMU_PMEVTYPER_EL0(29),
1779 PMU_PMEVTYPER_EL0(30),
174ed3e4
MR		 1780 /*
1781 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero
9feb21ac
SZ		 1782 * in 32bit mode. Here we choose to reset it as zero for consistency.
1783 */
174ed3e4 1784 { SYS_DESC(SYS_PMCCFILTR_EL0), access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 },
051ff581 1785
851050a5
MR		 1786 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 },
1787 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 },
c88b0936 1788 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
62a89c44
MZ		 1789};
1790
bdfb4b38 1791static bool trap_dbgidr(struct kvm_vcpu *vcpu,
3fec037d 1792 struct sys_reg_params *p,
bdfb4b38
MZ		 1793 const struct sys_reg_desc *r)
1794{
1795 if (p->is_write) {
1796 return ignore_write(vcpu, p);
1797 } else {
46823dd1
DM		 1798 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
1799 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
28c5dcb2 1800 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
bdfb4b38 1801
2ec5be3d
PF		 1802 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
1803 (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
1804 (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20)
1805 | (6 << 16) | (el3 << 14) | (el3 << 12));
bdfb4b38
MZ		 1806 return true;
1807 }
1808}
1809
1810static bool trap_debug32(struct kvm_vcpu *vcpu,
3fec037d 1811 struct sys_reg_params *p,
bdfb4b38
MZ		 1812 const struct sys_reg_desc *r)
1813{
1814 if (p->is_write) {
2ec5be3d 1815 vcpu_cp14(vcpu, r->reg) = p->regval;
fa89d31c 1816 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
bdfb4b38 1817 } else {
2ec5be3d 1818 p->regval = vcpu_cp14(vcpu, r->reg);
bdfb4b38
MZ		 1819 }
1820
1821 return true;
1822}
1823
84e690bf
AB		 1824/* AArch32 debug register mappings
1825 *
1826 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
1827 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
1828 *
1829 * All control registers and watchpoint value registers are mapped to
1830 * the lower 32 bits of their AArch64 equivalents. We share the trap
1831 * handlers with the above AArch64 code which checks what mode the
1832 * system is in.
1833 */
1834
281243cb
MZ		 1835static bool trap_xvr(struct kvm_vcpu *vcpu,
1836 struct sys_reg_params *p,
1837 const struct sys_reg_desc *rd)
84e690bf
AB		 1838{
1839 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
1840
1841 if (p->is_write) {
1842 u64 val = *dbg_reg;
1843
1844 val &= 0xffffffffUL;
2ec5be3d 1845 val |= p->regval << 32;
84e690bf
AB		 1846 *dbg_reg = val;
1847
fa89d31c 1848 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
84e690bf 1849 } else {
2ec5be3d 1850 p->regval = *dbg_reg >> 32;
84e690bf
AB		 1851 }
1852
eef8c85a
AB		 1853 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
1854
84e690bf
AB		 1855 return true;
1856}
1857
1858#define DBG_BCR_BVR_WCR_WVR(n) \
1859 /* DBGBVRn */ \
1860 { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
1861 /* DBGBCRn */ \
1862 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
1863 /* DBGWVRn */ \
1864 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
1865 /* DBGWCRn */ \
1866 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1867
1868#define DBGBXVR(n) \
1869 { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n }
bdfb4b38
MZ		 1870
1871/*
1872 * Trapped cp14 registers. We generally ignore most of the external
1873 * debug, on the principle that they don't really make sense to a
84e690bf 1874 * guest. Revisit this one day, would this principle change.
bdfb4b38 1875 */
72564016 1876static const struct sys_reg_desc cp14_regs[] = {
bdfb4b38
MZ		 1877 /* DBGIDR */
1878 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
1879 /* DBGDTRRXext */
1880 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1881
1882 DBG_BCR_BVR_WCR_WVR(0),
1883 /* DBGDSCRint */
1884 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1885 DBG_BCR_BVR_WCR_WVR(1),
1886 /* DBGDCCINT */
1887 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 },
1888 /* DBGDSCRext */
1889 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 },
1890 DBG_BCR_BVR_WCR_WVR(2),
1891 /* DBGDTR[RT]Xint */
1892 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1893 /* DBGDTR[RT]Xext */
1894 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1895 DBG_BCR_BVR_WCR_WVR(3),
1896 DBG_BCR_BVR_WCR_WVR(4),
1897 DBG_BCR_BVR_WCR_WVR(5),
1898 /* DBGWFAR */
1899 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1900 /* DBGOSECCR */
1901 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1902 DBG_BCR_BVR_WCR_WVR(6),
1903 /* DBGVCR */
1904 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 },
1905 DBG_BCR_BVR_WCR_WVR(7),
1906 DBG_BCR_BVR_WCR_WVR(8),
1907 DBG_BCR_BVR_WCR_WVR(9),
1908 DBG_BCR_BVR_WCR_WVR(10),
1909 DBG_BCR_BVR_WCR_WVR(11),
1910 DBG_BCR_BVR_WCR_WVR(12),
1911 DBG_BCR_BVR_WCR_WVR(13),
1912 DBG_BCR_BVR_WCR_WVR(14),
1913 DBG_BCR_BVR_WCR_WVR(15),
1914
1915 /* DBGDRAR (32bit) */
1916 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1917
1918 DBGBXVR(0),
1919 /* DBGOSLAR */
1920 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
1921 DBGBXVR(1),
1922 /* DBGOSLSR */
1923 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
1924 DBGBXVR(2),
1925 DBGBXVR(3),
1926 /* DBGOSDLR */
1927 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1928 DBGBXVR(4),
1929 /* DBGPRCR */
1930 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1931 DBGBXVR(5),
1932 DBGBXVR(6),
1933 DBGBXVR(7),
1934 DBGBXVR(8),
1935 DBGBXVR(9),
1936 DBGBXVR(10),
1937 DBGBXVR(11),
1938 DBGBXVR(12),
1939 DBGBXVR(13),
1940 DBGBXVR(14),
1941 DBGBXVR(15),
1942
1943 /* DBGDSAR (32bit) */
1944 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1945
1946 /* DBGDEVID2 */
1947 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1948 /* DBGDEVID1 */
1949 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1950 /* DBGDEVID */
1951 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1952 /* DBGCLAIMSET */
1953 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1954 /* DBGCLAIMCLR */
1955 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1956 /* DBGAUTHSTATUS */
1957 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
72564016
MZ		 1958};
1959
a9866ba0
MZ		 1960/* Trapped cp14 64bit registers */
1961static const struct sys_reg_desc cp14_64_regs[] = {
bdfb4b38
MZ		 1962 /* DBGDRAR (64bit) */
1963 { Op1( 0), CRm( 1), .access = trap_raz_wi },
1964
1965 /* DBGDSAR (64bit) */
1966 { Op1( 0), CRm( 2), .access = trap_raz_wi },
a9866ba0
MZ		 1967};
1968
051ff581
SZ		 1969/* Macro to expand the PMEVCNTRn register */
1970#define PMU_PMEVCNTR(n) \
1971 /* PMEVCNTRn */ \
1972 { Op1(0), CRn(0b1110), \
1973 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1974 access_pmu_evcntr }
1975
9feb21ac
SZ		 1976/* Macro to expand the PMEVTYPERn register */
1977#define PMU_PMEVTYPER(n) \
1978 /* PMEVTYPERn */ \
1979 { Op1(0), CRn(0b1110), \
1980 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1981 access_pmu_evtyper }
1982
4d44923b
MZ		 1983/*
1984 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
1985 * depending on the way they are accessed (as a 32bit or a 64bit
1986 * register).
1987 */
62a89c44 1988static const struct sys_reg_desc cp15_regs[] = {
f7f2b15c 1989 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },
3c1e7165 1990 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
af473829
JM		 1991 { Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr },
1992 { Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr },
4d44923b
MZ		 1993 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1994 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
1995 { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
1996 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
1997 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
1998 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
1999 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
2000 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
2001 { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
2002 { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
2003
62a89c44
MZ		 2004 /*
2005 * DC{C,I,CI}SW operations:
2006 */
2007 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
2008 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
2009 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
4d44923b 2010
7609c125 2011 /* PMU */
ab946834 2012 { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
96b0eebc
SZ		 2013 { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
2014 { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
76d883c4 2015 { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
7a0adc70 2016 { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
3965c3ce 2017 { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
a86b5505
SZ		 2018 { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
2019 { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
051ff581 2020 { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
9feb21ac 2021 { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
051ff581 2022 { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
d692b8ad 2023 { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr },
9db52c78
SZ		 2024 { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
2025 { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
76d883c4 2026 { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
4d44923b
MZ		 2027
2028 { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
2029 { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
2030 { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
2031 { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
db7dedd0
CD		 2032
2033 /* ICC_SRE */
f7f6f2d9 2034 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
db7dedd0 2035
4d44923b 2036 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
051ff581 2037
84135d3d
AP		 2038 /* Arch Tmers */
2039 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer },
2040 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer },
eac137b4 2041
051ff581
SZ		 2042 /* PMEVCNTRn */
2043 PMU_PMEVCNTR(0),
2044 PMU_PMEVCNTR(1),
2045 PMU_PMEVCNTR(2),
2046 PMU_PMEVCNTR(3),
2047 PMU_PMEVCNTR(4),
2048 PMU_PMEVCNTR(5),
2049 PMU_PMEVCNTR(6),
2050 PMU_PMEVCNTR(7),
2051 PMU_PMEVCNTR(8),
2052 PMU_PMEVCNTR(9),
2053 PMU_PMEVCNTR(10),
2054 PMU_PMEVCNTR(11),
2055 PMU_PMEVCNTR(12),
2056 PMU_PMEVCNTR(13),
2057 PMU_PMEVCNTR(14),
2058 PMU_PMEVCNTR(15),
2059 PMU_PMEVCNTR(16),
2060 PMU_PMEVCNTR(17),
2061 PMU_PMEVCNTR(18),
2062 PMU_PMEVCNTR(19),
2063 PMU_PMEVCNTR(20),
2064 PMU_PMEVCNTR(21),
2065 PMU_PMEVCNTR(22),
2066 PMU_PMEVCNTR(23),
2067 PMU_PMEVCNTR(24),
2068 PMU_PMEVCNTR(25),
2069 PMU_PMEVCNTR(26),
2070 PMU_PMEVCNTR(27),
2071 PMU_PMEVCNTR(28),
2072 PMU_PMEVCNTR(29),
2073 PMU_PMEVCNTR(30),
9feb21ac
SZ		 2074 /* PMEVTYPERn */
2075 PMU_PMEVTYPER(0),
2076 PMU_PMEVTYPER(1),
2077 PMU_PMEVTYPER(2),
2078 PMU_PMEVTYPER(3),
2079 PMU_PMEVTYPER(4),
2080 PMU_PMEVTYPER(5),
2081 PMU_PMEVTYPER(6),
2082 PMU_PMEVTYPER(7),
2083 PMU_PMEVTYPER(8),
2084 PMU_PMEVTYPER(9),
2085 PMU_PMEVTYPER(10),
2086 PMU_PMEVTYPER(11),
2087 PMU_PMEVTYPER(12),
2088 PMU_PMEVTYPER(13),
2089 PMU_PMEVTYPER(14),
2090 PMU_PMEVTYPER(15),
2091 PMU_PMEVTYPER(16),
2092 PMU_PMEVTYPER(17),
2093 PMU_PMEVTYPER(18),
2094 PMU_PMEVTYPER(19),
2095 PMU_PMEVTYPER(20),
2096 PMU_PMEVTYPER(21),
2097 PMU_PMEVTYPER(22),
2098 PMU_PMEVTYPER(23),
2099 PMU_PMEVTYPER(24),
2100 PMU_PMEVTYPER(25),
2101 PMU_PMEVTYPER(26),
2102 PMU_PMEVTYPER(27),
2103 PMU_PMEVTYPER(28),
2104 PMU_PMEVTYPER(29),
2105 PMU_PMEVTYPER(30),
2106 /* PMCCFILTR */
2107 { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
f7f2b15c
AB		 2108
2109 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
2110 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
2111 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, c0_CSSELR },
a9866ba0
MZ		 2112};
2113
2114static const struct sys_reg_desc cp15_64_regs[] = {
2115 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
051ff581 2116 { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
03bd646d 2117 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
4d44923b 2118 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
03bd646d
MZ		 2119 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
2120 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
84135d3d 2121 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer },
7c8c5e6a
MZ		 2122};
2123
bb44a8db
MZ		 2124static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n,
2125 bool is_32)
2126{
2127 unsigned int i;
2128
2129 for (i = 0; i < n; i++) {
2130 if (!is_32 && table[i].reg && !table[i].reset) {
2131 kvm_err("sys_reg table %p entry %d has lacks reset\n",
2132 table, i);
2133 return 1;
2134 }
2135
2136 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2137 kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
2138 return 1;
2139 }
2140 }
2141
2142 return 0;
2143}
2144
623eefa8
MZ		 2145static int match_sys_reg(const void *key, const void *elt)
2146{
2147 const unsigned long pval = (unsigned long)key;
2148 const struct sys_reg_desc *r = elt;
2149
09838de9 2150 return pval - reg_to_encoding(r);
623eefa8
MZ		 2151}
2152
7c8c5e6a
MZ		 2153static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
2154 const struct sys_reg_desc table[],
2155 unsigned int num)
2156{
09838de9 2157 unsigned long pval = reg_to_encoding(params);
623eefa8
MZ		 2158
2159 return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
7c8c5e6a
MZ		 2160}
2161
74cc7e0c 2162int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu)
62a89c44
MZ		 2163{
2164 kvm_inject_undefined(vcpu);
2165 return 1;
2166}
2167
e70b9522
MZ		 2168static void perform_access(struct kvm_vcpu *vcpu,
2169 struct sys_reg_params *params,
2170 const struct sys_reg_desc *r)
2171{
599d79dc
MZ		 2172 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r);
2173
7f34e409
DM		 2174 /* Check for regs disabled by runtime config */
2175 if (sysreg_hidden_from_guest(vcpu, r)) {
2176 kvm_inject_undefined(vcpu);
2177 return;
2178 }
2179
e70b9522
MZ		 2180 /*
2181 * Not having an accessor means that we have configured a trap
2182 * that we don't know how to handle. This certainly qualifies
2183 * as a gross bug that should be fixed right away.
2184 */
2185 BUG_ON(!r->access);
2186
2187 /* Skip instruction if instructed so */
2188 if (likely(r->access(vcpu, params, r)))
2189 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
2190}
2191
72564016
MZ		 2192/*
2193 * emulate_cp -- tries to match a sys_reg access in a handling table, and
2194 * call the corresponding trap handler.
2195 *
2196 * @params: pointer to the descriptor of the access
2197 * @table: array of trap descriptors
2198 * @num: size of the trap descriptor array
2199 *
2200 * Return 0 if the access has been handled, and -1 if not.
2201 */
2202static int emulate_cp(struct kvm_vcpu *vcpu,
3fec037d 2203 struct sys_reg_params *params,
72564016
MZ		 2204 const struct sys_reg_desc *table,
2205 size_t num)
62a89c44 2206{
72564016 2207 const struct sys_reg_desc *r;
62a89c44 2208
72564016
MZ		 2209 if (!table)
2210 return -1; /* Not handled */
62a89c44 2211
62a89c44 2212 r = find_reg(params, table, num);
62a89c44 2213
72564016 2214 if (r) {
e70b9522
MZ		 2215 perform_access(vcpu, params, r);
2216 return 0;
72564016
MZ		 2217 }
2218
2219 /* Not handled */
2220 return -1;
2221}
2222
2223static void unhandled_cp_access(struct kvm_vcpu *vcpu,
2224 struct sys_reg_params *params)
2225{
3a949f4c 2226 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
40c4f8d2 2227 int cp = -1;
72564016 2228
3a949f4c 2229 switch (esr_ec) {
c6d01a94
MR		 2230 case ESR_ELx_EC_CP15_32:
2231 case ESR_ELx_EC_CP15_64:
72564016
MZ		 2232 cp = 15;
2233 break;
c6d01a94
MR		 2234 case ESR_ELx_EC_CP14_MR:
2235 case ESR_ELx_EC_CP14_64:
72564016
MZ		 2236 cp = 14;
2237 break;
2238 default:
40c4f8d2 2239 WARN_ON(1);
62a89c44
MZ		 2240 }
2241
bf4b96bb
MR		 2242 print_sys_reg_msg(params,
2243 "Unsupported guest CP%d access at: %08lx [%08lx]\n",
2244 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
62a89c44
MZ		 2245 kvm_inject_undefined(vcpu);
2246}
2247
2248/**
7769db90 2249 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
62a89c44
MZ		 2250 * @vcpu: The VCPU pointer
2251 * @run: The kvm_run struct
2252 */
72564016
MZ		 2253static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
2254 const struct sys_reg_desc *global,
dcaffa7b 2255 size_t nr_global)
62a89c44
MZ		 2256{
2257 struct sys_reg_params params;
3a949f4c 2258 u32 esr = kvm_vcpu_get_esr(vcpu);
c667186f 2259 int Rt = kvm_vcpu_sys_get_rt(vcpu);
3a949f4c 2260 int Rt2 = (esr >> 10) & 0x1f;
62a89c44 2261
2072d29c
MZ		 2262 params.is_aarch32 = true;
2263 params.is_32bit = false;
3a949f4c
GS		 2264 params.CRm = (esr >> 1) & 0xf;
2265 params.is_write = ((esr & 1) == 0);
62a89c44
MZ		 2266
2267 params.Op0 = 0;
3a949f4c 2268 params.Op1 = (esr >> 16) & 0xf;
62a89c44
MZ		 2269 params.Op2 = 0;
2270 params.CRn = 0;
2271
2272 /*
2ec5be3d 2273 * Make a 64-bit value out of Rt and Rt2. As we use the same trap
62a89c44
MZ		 2274 * backends between AArch32 and AArch64, we get away with it.
2275 */
2276 if (params.is_write) {
2ec5be3d
PF		 2277 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
2278 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
62a89c44
MZ		 2279 }
2280
b6b7a806 2281 /*
dcaffa7b 2282 * If the table contains a handler, handle the
b6b7a806
MZ		 2283 * potential register operation in the case of a read and return
2284 * with success.
2285 */
dcaffa7b 2286 if (!emulate_cp(vcpu, &params, global, nr_global)) {
b6b7a806
MZ		 2287 /* Split up the value between registers for the read side */
2288 if (!params.is_write) {
2289 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
2290 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
2291 }
62a89c44 2292
b6b7a806 2293 return 1;
62a89c44
MZ		 2294 }
2295
b6b7a806 2296 unhandled_cp_access(vcpu, &params);
62a89c44
MZ		 2297 return 1;
2298}
2299
2300/**
7769db90 2301 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
62a89c44
MZ		 2302 * @vcpu: The VCPU pointer
2303 * @run: The kvm_run struct
2304 */
72564016
MZ		 2305static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
2306 const struct sys_reg_desc *global,
dcaffa7b 2307 size_t nr_global)
62a89c44
MZ		 2308{
2309 struct sys_reg_params params;
3a949f4c 2310 u32 esr = kvm_vcpu_get_esr(vcpu);
c667186f 2311 int Rt = kvm_vcpu_sys_get_rt(vcpu);
62a89c44 2312
2072d29c
MZ		 2313 params.is_aarch32 = true;
2314 params.is_32bit = true;
3a949f4c 2315 params.CRm = (esr >> 1) & 0xf;
2ec5be3d 2316 params.regval = vcpu_get_reg(vcpu, Rt);
3a949f4c
GS		 2317 params.is_write = ((esr & 1) == 0);
2318 params.CRn = (esr >> 10) & 0xf;
62a89c44 2319 params.Op0 = 0;
3a949f4c
GS		 2320 params.Op1 = (esr >> 14) & 0x7;
2321 params.Op2 = (esr >> 17) & 0x7;
62a89c44 2322
dcaffa7b 2323 if (!emulate_cp(vcpu, &params, global, nr_global)) {
2ec5be3d
PF		 2324 if (!params.is_write)
2325 vcpu_set_reg(vcpu, Rt, params.regval);
72564016 2326 return 1;
2ec5be3d 2327 }
72564016
MZ		 2328
2329 unhandled_cp_access(vcpu, &params);
62a89c44
MZ		 2330 return 1;
2331}
2332
74cc7e0c 2333int kvm_handle_cp15_64(struct kvm_vcpu *vcpu)
72564016 2334{
dcaffa7b 2335 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs));
72564016
MZ		 2336}
2337
74cc7e0c 2338int kvm_handle_cp15_32(struct kvm_vcpu *vcpu)
72564016 2339{
dcaffa7b 2340 return kvm_handle_cp_32(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs));
72564016
MZ		 2341}
2342
74cc7e0c 2343int kvm_handle_cp14_64(struct kvm_vcpu *vcpu)
72564016 2344{
dcaffa7b 2345 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs));
72564016
MZ		 2346}
2347
74cc7e0c 2348int kvm_handle_cp14_32(struct kvm_vcpu *vcpu)
72564016 2349{
dcaffa7b 2350 return kvm_handle_cp_32(vcpu, cp14_regs, ARRAY_SIZE(cp14_regs));
72564016
MZ		 2351}
2352
54ad68b7
MR		 2353static bool is_imp_def_sys_reg(struct sys_reg_params *params)
2354{
2355 // See ARM DDI 0487E.a, section D12.3.2
2356 return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011;
2357}
2358
7c8c5e6a 2359static int emulate_sys_reg(struct kvm_vcpu *vcpu,
3fec037d 2360 struct sys_reg_params *params)
7c8c5e6a 2361{
dcaffa7b 2362 const struct sys_reg_desc *r;
7c8c5e6a 2363
dcaffa7b 2364 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
7c8c5e6a
MZ		 2365
2366 if (likely(r)) {
e70b9522 2367 perform_access(vcpu, params, r);
54ad68b7
MR		 2368 } else if (is_imp_def_sys_reg(params)) {
2369 kvm_inject_undefined(vcpu);
7c8c5e6a 2370 } else {
bf4b96bb
MR		 2371 print_sys_reg_msg(params,
2372 "Unsupported guest sys_reg access at: %lx [%08lx]\n",
2373 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
e70b9522 2374 kvm_inject_undefined(vcpu);
7c8c5e6a 2375 }
7c8c5e6a
MZ		 2376 return 1;
2377}
2378
750ed566
JM		 2379/**
2380 * kvm_reset_sys_regs - sets system registers to reset value
2381 * @vcpu: The VCPU pointer
2382 *
2383 * This function finds the right table above and sets the registers on the
2384 * virtual CPU struct to their architecturally defined reset values.
2385 */
2386void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
7c8c5e6a
MZ		 2387{
2388 unsigned long i;
2389
750ed566
JM		 2390 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++)
2391 if (sys_reg_descs[i].reset)
2392 sys_reg_descs[i].reset(vcpu, &sys_reg_descs[i]);
7c8c5e6a
MZ		 2393}
2394
2395/**
2396 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
2397 * @vcpu: The VCPU pointer
7c8c5e6a 2398 */
74cc7e0c 2399int kvm_handle_sys_reg(struct kvm_vcpu *vcpu)
7c8c5e6a
MZ		 2400{
2401 struct sys_reg_params params;
3a949f4c 2402 unsigned long esr = kvm_vcpu_get_esr(vcpu);
c667186f 2403 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2ec5be3d 2404 int ret;
7c8c5e6a 2405
eef8c85a
AB		 2406 trace_kvm_handle_sys_reg(esr);
2407
2072d29c
MZ		 2408 params.is_aarch32 = false;
2409 params.is_32bit = false;
7c8c5e6a
MZ		 2410 params.Op0 = (esr >> 20) & 3;
2411 params.Op1 = (esr >> 14) & 0x7;
2412 params.CRn = (esr >> 10) & 0xf;
2413 params.CRm = (esr >> 1) & 0xf;
2414 params.Op2 = (esr >> 17) & 0x7;
2ec5be3d 2415 params.regval = vcpu_get_reg(vcpu, Rt);
7c8c5e6a
MZ		 2416 params.is_write = !(esr & 1);
2417
2ec5be3d
PF		 2418 ret = emulate_sys_reg(vcpu, &params);
2419
2420 if (!params.is_write)
2421 vcpu_set_reg(vcpu, Rt, params.regval);
2422 return ret;
7c8c5e6a
MZ		 2423}
2424
2425/******************************************************************************
2426 * Userspace API
2427 *****************************************************************************/
2428
2429static bool index_to_params(u64 id, struct sys_reg_params *params)
2430{
2431 switch (id & KVM_REG_SIZE_MASK) {
2432 case KVM_REG_SIZE_U64:
2433 /* Any unused index bits means it's not valid. */
2434 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
2435 | KVM_REG_ARM_COPROC_MASK
2436 | KVM_REG_ARM64_SYSREG_OP0_MASK
2437 | KVM_REG_ARM64_SYSREG_OP1_MASK
2438 | KVM_REG_ARM64_SYSREG_CRN_MASK
2439 | KVM_REG_ARM64_SYSREG_CRM_MASK
2440 | KVM_REG_ARM64_SYSREG_OP2_MASK))
2441 return false;
2442 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
2443 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
2444 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
2445 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
2446 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
2447 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
2448 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
2449 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
2450 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
2451 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
2452 return true;
2453 default:
2454 return false;
2455 }
2456}
2457
4b927b94
VK		 2458const struct sys_reg_desc *find_reg_by_id(u64 id,
2459 struct sys_reg_params *params,
2460 const struct sys_reg_desc table[],
2461 unsigned int num)
2462{
2463 if (!index_to_params(id, params))
2464 return NULL;
2465
2466 return find_reg(params, table, num);
2467}
2468
7c8c5e6a
MZ		 2469/* Decode an index value, and find the sys_reg_desc entry. */
2470static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
2471 u64 id)
2472{
dcaffa7b 2473 const struct sys_reg_desc *r;
7c8c5e6a
MZ		 2474 struct sys_reg_params params;
2475
2476 /* We only do sys_reg for now. */
2477 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
2478 return NULL;
2479
1ce74e96
WD		 2480 if (!index_to_params(id, &params))
2481 return NULL;
2482
dcaffa7b 2483 r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
7c8c5e6a 2484
93390c0a
DM		 2485 /* Not saved in the sys_reg array and not otherwise accessible? */
2486 if (r && !(r->reg || r->get_user))
7c8c5e6a
MZ		 2487 r = NULL;
2488
2489 return r;
2490}
2491
2492/*
2493 * These are the invariant sys_reg registers: we let the guest see the
2494 * host versions of these, so they're part of the guest state.
2495 *
2496 * A future CPU may provide a mechanism to present different values to
2497 * the guest, or a future kvm may trap them.
2498 */
2499
2500#define FUNCTION_INVARIANT(reg) \
2501 static void get_##reg(struct kvm_vcpu *v, \
2502 const struct sys_reg_desc *r) \
2503 { \
1f3d8699 2504 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \
7c8c5e6a
MZ		 2505 }
2506
2507FUNCTION_INVARIANT(midr_el1)
7c8c5e6a 2508FUNCTION_INVARIANT(revidr_el1)
7c8c5e6a
MZ		 2509FUNCTION_INVARIANT(clidr_el1)
2510FUNCTION_INVARIANT(aidr_el1)
2511
f7f2b15c
AB		 2512static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r)
2513{
2514 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0);
2515}
2516
7c8c5e6a
MZ		 2517/* ->val is filled in by kvm_sys_reg_table_init() */
2518static struct sys_reg_desc invariant_sys_regs[] = {
0d449541
MR		 2519 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 },
2520 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 },
0d449541
MR		 2521 { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 },
2522 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 },
2523 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 },
7c8c5e6a
MZ		 2524};
2525
26c99af1 2526static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
7c8c5e6a 2527{
7c8c5e6a
MZ		 2528 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
2529 return -EFAULT;
2530 return 0;
2531}
2532
26c99af1 2533static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
7c8c5e6a 2534{
7c8c5e6a
MZ		 2535 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
2536 return -EFAULT;
2537 return 0;
2538}
2539
2540static int get_invariant_sys_reg(u64 id, void __user *uaddr)
2541{
2542 struct sys_reg_params params;
2543 const struct sys_reg_desc *r;
2544
4b927b94
VK		 2545 r = find_reg_by_id(id, &params, invariant_sys_regs,
2546 ARRAY_SIZE(invariant_sys_regs));
7c8c5e6a
MZ		 2547 if (!r)
2548 return -ENOENT;
2549
2550 return reg_to_user(uaddr, &r->val, id);
2551}
2552
2553static int set_invariant_sys_reg(u64 id, void __user *uaddr)
2554{
2555 struct sys_reg_params params;
2556 const struct sys_reg_desc *r;
2557 int err;
2558 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
2559
4b927b94
VK		 2560 r = find_reg_by_id(id, &params, invariant_sys_regs,
2561 ARRAY_SIZE(invariant_sys_regs));
7c8c5e6a
MZ		 2562 if (!r)
2563 return -ENOENT;
2564
2565 err = reg_from_user(&val, uaddr, id);
2566 if (err)
2567 return err;
2568
2569 /* This is what we mean by invariant: you can't change it. */
2570 if (r->val != val)
2571 return -EINVAL;
2572
2573 return 0;
2574}
2575
2576static bool is_valid_cache(u32 val)
2577{
2578 u32 level, ctype;
2579
2580 if (val >= CSSELR_MAX)
18d45766 2581 return false;
7c8c5e6a
MZ		 2582
2583 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
2584 level = (val >> 1);
2585 ctype = (cache_levels >> (level * 3)) & 7;
2586
2587 switch (ctype) {
2588 case 0: /* No cache */
2589 return false;
2590 case 1: /* Instruction cache only */
2591 return (val & 1);
2592 case 2: /* Data cache only */
2593 case 4: /* Unified cache */
2594 return !(val & 1);
2595 case 3: /* Separate instruction and data caches */
2596 return true;
2597 default: /* Reserved: we can't know instruction or data. */
2598 return false;
2599 }
2600}
2601
2602static int demux_c15_get(u64 id, void __user *uaddr)
2603{
2604 u32 val;
2605 u32 __user *uval = uaddr;
2606
2607 /* Fail if we have unknown bits set. */
2608 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2609 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2610 return -ENOENT;
2611
2612 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2613 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2614 if (KVM_REG_SIZE(id) != 4)
2615 return -ENOENT;
2616 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2617 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2618 if (!is_valid_cache(val))
2619 return -ENOENT;
2620
2621 return put_user(get_ccsidr(val), uval);
2622 default:
2623 return -ENOENT;
2624 }
2625}
2626
2627static int demux_c15_set(u64 id, void __user *uaddr)
2628{
2629 u32 val, newval;
2630 u32 __user *uval = uaddr;
2631
2632 /* Fail if we have unknown bits set. */
2633 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2634 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2635 return -ENOENT;
2636
2637 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2638 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2639 if (KVM_REG_SIZE(id) != 4)
2640 return -ENOENT;
2641 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2642 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2643 if (!is_valid_cache(val))
2644 return -ENOENT;
2645
2646 if (get_user(newval, uval))
2647 return -EFAULT;
2648
2649 /* This is also invariant: you can't change it. */
2650 if (newval != get_ccsidr(val))
2651 return -EINVAL;
2652 return 0;
2653 default:
2654 return -ENOENT;
2655 }
2656}
2657
2658int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2659{
2660 const struct sys_reg_desc *r;
2661 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2662
2663 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2664 return demux_c15_get(reg->id, uaddr);
2665
2666 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2667 return -ENOENT;
2668
2669 r = index_to_sys_reg_desc(vcpu, reg->id);
2670 if (!r)
2671 return get_invariant_sys_reg(reg->id, uaddr);
2672
7f34e409
DM		 2673 /* Check for regs disabled by runtime config */
2674 if (sysreg_hidden_from_user(vcpu, r))
2675 return -ENOENT;
2676
84e690bf
AB		 2677 if (r->get_user)
2678 return (r->get_user)(vcpu, r, reg, uaddr);
2679
8d404c4c 2680 return reg_to_user(uaddr, &__vcpu_sys_reg(vcpu, r->reg), reg->id);
7c8c5e6a
MZ		 2681}
2682
2683int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2684{
2685 const struct sys_reg_desc *r;
2686 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2687
2688 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2689 return demux_c15_set(reg->id, uaddr);
2690
2691 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2692 return -ENOENT;
2693
2694 r = index_to_sys_reg_desc(vcpu, reg->id);
2695 if (!r)
2696 return set_invariant_sys_reg(reg->id, uaddr);
2697
7f34e409
DM		 2698 /* Check for regs disabled by runtime config */
2699 if (sysreg_hidden_from_user(vcpu, r))
2700 return -ENOENT;
2701
84e690bf
AB		 2702 if (r->set_user)
2703 return (r->set_user)(vcpu, r, reg, uaddr);
2704
8d404c4c 2705 return reg_from_user(&__vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
7c8c5e6a
MZ		 2706}
2707
2708static unsigned int num_demux_regs(void)
2709{
2710 unsigned int i, count = 0;
2711
2712 for (i = 0; i < CSSELR_MAX; i++)
2713 if (is_valid_cache(i))
2714 count++;
2715
2716 return count;
2717}
2718
2719static int write_demux_regids(u64 __user *uindices)
2720{
efd48cea 2721 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
7c8c5e6a
MZ		 2722 unsigned int i;
2723
2724 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
2725 for (i = 0; i < CSSELR_MAX; i++) {
2726 if (!is_valid_cache(i))
2727 continue;
2728 if (put_user(val | i, uindices))
2729 return -EFAULT;
2730 uindices++;
2731 }
2732 return 0;
2733}
2734
2735static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
2736{
2737 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
2738 KVM_REG_ARM64_SYSREG |
2739 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
2740 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
2741 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
2742 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
2743 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
2744}
2745
2746static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
2747{
2748 if (!*uind)
2749 return true;
2750
2751 if (put_user(sys_reg_to_index(reg), *uind))
2752 return false;
2753
2754 (*uind)++;
2755 return true;
2756}
2757
7f34e409
DM		 2758static int walk_one_sys_reg(const struct kvm_vcpu *vcpu,
2759 const struct sys_reg_desc *rd,
93390c0a
DM		 2760 u64 __user **uind,
2761 unsigned int *total)
2762{
2763 /*
2764 * Ignore registers we trap but don't save,
2765 * and for which no custom user accessor is provided.
2766 */
2767 if (!(rd->reg || rd->get_user))
2768 return 0;
2769
7f34e409
DM		 2770 if (sysreg_hidden_from_user(vcpu, rd))
2771 return 0;
2772
93390c0a
DM		 2773 if (!copy_reg_to_user(rd, uind))
2774 return -EFAULT;
2775
2776 (*total)++;
2777 return 0;
2778}
2779
7c8c5e6a
MZ		 2780/* Assumed ordered tables, see kvm_sys_reg_table_init. */
2781static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
2782{
dcaffa7b 2783 const struct sys_reg_desc *i2, *end2;
7c8c5e6a 2784 unsigned int total = 0;
93390c0a 2785 int err;
7c8c5e6a 2786
7c8c5e6a
MZ		 2787 i2 = sys_reg_descs;
2788 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
2789
dcaffa7b
JM		 2790 while (i2 != end2) {
2791 err = walk_one_sys_reg(vcpu, i2++, &uind, &total);
93390c0a
DM		 2792 if (err)
2793 return err;
7c8c5e6a
MZ		 2794 }
2795 return total;
2796}
2797
2798unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
2799{
2800 return ARRAY_SIZE(invariant_sys_regs)
2801 + num_demux_regs()
2802 + walk_sys_regs(vcpu, (u64 __user *)NULL);
2803}
2804
2805int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
2806{
2807 unsigned int i;
2808 int err;
2809
2810 /* Then give them all the invariant registers' indices. */
2811 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
2812 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
2813 return -EFAULT;
2814 uindices++;
2815 }
2816
2817 err = walk_sys_regs(vcpu, uindices);
2818 if (err < 0)
2819 return err;
2820 uindices += err;
2821
2822 return write_demux_regids(uindices);
2823}
2824
2825void kvm_sys_reg_table_init(void)
2826{
2827 unsigned int i;
2828 struct sys_reg_desc clidr;
2829
2830 /* Make sure tables are unique and in order. */
bb44a8db
MZ		 2831 BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false));
2832 BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true));
2833 BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true));
2834 BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true));
2835 BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true));
2836 BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false));
7c8c5e6a
MZ		 2837
2838 /* We abuse the reset function to overwrite the table itself. */
2839 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
2840 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
2841
2842 /*
2843 * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
2844 *
2845 * If software reads the Cache Type fields from Ctype1
2846 * upwards, once it has seen a value of 0b000, no caches
2847 * exist at further-out levels of the hierarchy. So, for
2848 * example, if Ctype3 is the first Cache Type field with a
2849 * value of 0b000, the values of Ctype4 to Ctype7 must be
2850 * ignored.
2851 */
2852 get_clidr_el1(NULL, &clidr); /* Ugly... */
2853 cache_levels = clidr.val;
2854 for (i = 0; i < 7; i++)
2855 if (((cache_levels >> (i*3)) & 7) == 0)
2856 break;
2857 /* Clear all higher bits. */
2858 cache_levels &= (1 << (i*3))-1;
2859}
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